mirror of
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synced 2026-09-02 01:58:36 +08:00
Beaglebone: Update PWM driver imported from BBBIO
This patch adapts the previously added Beaglebone PWM code from BBBIO to RTEMS. This work was done in the context of the Google Summer of Code 2016, and further patches will follow to improve the code quality and documentation.
This commit is contained in:
Punit Vara
committed by
Martin Galvan
Martin Galvan
parent
6dc5c03fad
commit
5e3096db5a
@@ -41,6 +41,7 @@ include_bsp_HEADERS += include/irq.h
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include_bsp_HEADERS += include/i2c.h
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include_bsp_HEADERS += include/beagleboneblack.h
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include_bsp_HEADERS += include/bbb-gpio.h
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include_bsp_HEADERS += include/bbb-pwm.h
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include_libcpu_HEADERS =
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include_libcpu_HEADERS += ../../../libcpu/arm/shared/include/arm-cp15.h
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@@ -117,6 +118,9 @@ libbsp_a_SOURCES += misc/i2c.c
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# GPIO
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libbsp_a_SOURCES += gpio/bbb-gpio.c
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#pwm
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libbsp_a_SOURCES += pwm/pwm.c
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#RTC
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libbsp_a_SOURCES += rtc.c
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libbsp_a_SOURCES += ../../shared/tod.c
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@@ -1,3 +1,23 @@
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/**
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* @file
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*
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* @ingroup arm_beagle
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*
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* @brief BeagleBone Black BSP definitions.
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*/
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/**
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* Copyright (c) 2016 Punit Vara <punitvara at gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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/** Some constants are taken from
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* https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.h
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*/
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#ifndef LIBBSP_ARM_BEAGLE_BBB_PWM_H
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#define LIBBSP_ARM_BEAGLE_BBB_PWM_H
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@@ -8,31 +28,125 @@ extern "C" {
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/**
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* @brief BeagleBone Black PWM Macros.
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*/
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#define BBBIO_PWMSS_COUNT 3
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#define BBBIO_PWMSS0 0
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#define BBBIO_PWMSS1 1
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#define BBBIO_PWMSS2 2
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#define BBB_CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4))
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#define BBB_CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4))
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#define MUXMODE0 0
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#define MUXMODE1 1
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#define MUXMODE2 2
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#define MUXMODE3 3
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#define MUXMODE4 4
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#define MUXMODE5 5
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#define MUXMODE6 6
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#define MUXMODE7 7
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#define BBB_PWMSS_COUNT 3
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#define BBB_PWMSS0 0
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#define BBB_PWMSS1 1
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#define BBB_PWMSS2 2
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#define EPWM_GROUP1 1
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#define EPWM_GROUP2 2
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#define EPWM_GROUP0 0
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#define BBB_P8_13_2B 3
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#define BBB_P8_19_2A 4
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#define BBB_P8_45_2A 5
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#define BBB_P8_46_2B 6
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#define BBB_P8_34_1B 7
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#define BBB_P8_36_1A 8
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#define BBB_P9_14_1A 9
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#define BBB_P9_16_1B 10
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#define BBB_P9_21_0B 11
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#define BBB_P9_22_0A 12
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#define BBB_P9_29_0B 13
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#define BBB_P9_31_0A 14
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int BBBIO_PWMSS_Setting(unsigned int PWMID , float HZ ,float dutyA ,float dutyB);
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int BBBIO_PWM_Init();
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void BBBIO_PWM_Release();
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int BBBIO_PWMSS_Status(unsigned int PWMID);
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void BBBIO_ehrPWM_Enable(unsigned int PWMSS_ID);
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void BBBIO_ehrPWM_Disable(unsigned int PWMSS_ID);
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#define BBB_MUX0 0
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#define BBB_MUX1 1
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#define BBB_MUX2 2
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#define BBB_MUX3 3
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#define BBB_MUX4 4
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#define BBB_MUX5 5
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#define BBB_MUX6 6
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#define BBB_MUX7 7
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#define BBB_EPWM1 1
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#define BBB_EPWM2 2
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#define BBB_EPWM0 0
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/**
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* @brief BeagleBone Black PWM API.
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*/
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/**
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* @brief This function intilize clock and pinmuxing for pwm sub system.
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*
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* @param PWMSS_ID It is the instance number of EPWM of pwm sub system.
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*
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* @return true if successful
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* @return false if not successful
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*
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**/
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bool beagle_pwm_init(uint32_t pwmss_id);
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/* PWMSS setting
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* set pulse argument of epwm module
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*
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* @param pwm_id : EPWMSS number , 0~2
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* @param pwm_freq : frequency to be generated
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* @param dutyA : Duty Cycle in ePWM A
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* @param dutyB : Duty Cycle in ePWM B
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*
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* @return : 1 for success
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* @return : 0 for failed
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*
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* @example : PWMSS_Setting(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 ,
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* // duty cycle is 50% for ePWM0A , 25% for ePWM0B
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*
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* @Note :
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* find an number nearst 65535 for TBPRD , to improve duty precision,
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*
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* Using big TBPRD can increase the range of CMPA and CMPB ,
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* and it means we can get better precision on duty cycle.
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*
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* EX : 20.25% duty cycle
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* on TBPRD = 62500 , CMPA = 12656.25 ( .25 rejection) , real duty : 20.2496% (12656 /62500)
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* on TBPRD = 6250 , CMPA = 1265.625 ( .625 rejection), real duty : 20.24% (1265 6250)
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* on TBPRD = 500 , CMPA = 101.25 ( .25 rejection) , real duty : 20.2% (101/500)
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*
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* Divisor = CLKDIV * HSPCLKDIV
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* 1 TBPRD : 10 ns (default)
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* 65535 TBPRD : 655350 ns
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* 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cyclens
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*
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* accrooding to that , we must find a Divisor value , let X nearest 65535 .
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* so , Divisor must Nearest Cyclens/655350
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*/
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int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB);
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/**
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* @brief This API enables the particular PWM module.
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*
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* @param pwmid It is the instance number of EPWM of pwm sub system.
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*
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* @return true if successful
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* @return false if fail
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*
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**/
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bool beagle_ehrpwm_enable(uint32_t pwmid);
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/**
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* @brief This API disables the HR sub-module.
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*
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* @param pwmid It is the instance number of EPWM of pwm sub system.
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*
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* @return true if successful
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* @return false if fail
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*
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**/
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bool beagle_ehrpwm_disable(uint32_t pwmid);
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/**
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* @brief This function Enables pinmuxing for PWM module.
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*
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* @param pin_no It is individual pin at which freuqency need to be generated.
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* It should be according to pwm sub system.
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*
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* @param pwm_id It is the instance number of EPWM of pwmsubsystem.
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*
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* @return true if successful
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* @return false if fail
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*
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**/
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bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id);
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#ifdef __cplusplus
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}
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File diff suppressed because it is too large
Load Diff
@@ -467,4 +467,99 @@
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#define AM335X_CONF_EXT_WAKEUP 0xA00
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#define AM335X_CONF_RTC_KALDO_ENN 0xA04
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#define AM335X_CONF_USB0_DRVVBUS 0xA1C
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#define AM335X_CONF_USB1_DRVVBUS 0xA34
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#define AM335X_CONF_USB1_DRVVBUS 0xA34
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/* Registers for PWM Subsystem */
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#define AM335X_PWMSS_CTRL (0x664)
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#define AM335X_CM_PER_EPWMSS0_CLKCTRL (0xD4)
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#define AM335X_CM_PER_EPWMSS1_CLKCTRL (0xCC)
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#define AM335X_CM_PER_EPWMSS2_CLKCTRL (0xD8)
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#define AM335X_CONTROL_MODULE (0x44e10000)
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#define AM335X_CM_PER_ADDR (0x44e00000)
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#define AM335X_PWMSS_CLKSTATUS (0xC)
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#define AM335X_PWMSS0_MMAP_ADDR 0x48300000
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#define AM335X_PWMSS1_MMAP_ADDR 0x48302000
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#define AM335X_PWMSS2_MMAP_ADDR 0x48304000
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#define AM335X_PWMSS_MMAP_LEN 0x1000
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#define AM335X_PWMSS_IDVER 0x0
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#define AM335X_PWMSS_SYSCONFIG 0x4
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#define AM335X_PWMSS_CLKCONFIG 0x8
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#define AM335X_PWMSS_CLK_EN_ACK 0x100
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#define AM335X_PWMSS_CLKSTATUS 0xC
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#define AM335X_EPWM_TBCTL 0x0
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#define AM335X_EPWM_TBSTS 0x2
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#define AM335X_EPWM_TBPHSHR 0x4
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#define AM335X_EPWM_TBPHS 0x6
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#define AM335X_EPWM_TBCNT 0x8
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#define AM335X_EPWM_TBPRD 0xA
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#define AM335X_EPWM_CMPCTL 0xE
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#define AM335X_EPWM_CMPAHR 0x10
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#define AM335X_EPWM_CMPA 0x12
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#define AM335X_EPWM_CMPB 0x14
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#define AM335X_EPWM_AQCTLA 0x16
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#define AM335X_EPWM_AQCTLB 0x18
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#define AM335X_EPWM_AQSFRC 0x1A
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#define AM335X_EPWM_AQCSFRC 0x1C
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#define AM335X_EPWM_DBCTL 0x1E
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#define AM335X_EPWM_DBRED 0x20
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#define AM335X_EPWM_DBFED 0x22
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#define AM335X_TBCTL_CTRMODE_UP 0x0
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#define AM335X_TBCTL_CTRMODE_DOWN 0x1
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#define AM335X_TBCTL_CTRMODE_UPDOWN 0x2
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#define AM335X_TBCTL_CTRMODE_FREEZE 0x3
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#define AM335X_EPWM_AQCTLA_ZRO_XALOW (0x0001u)
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#define AM335X_EPWM_AQCTLA_ZRO_XAHIGH (0x0002u)
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#define AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE (0x0003u)
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#define AM335X_EPWM_AQCTLA_CAU_SHIFT (0x0004u)
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#define AM335X_EPWM_AQCTLA_ZRO_XBLOW (0x0001u)
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#define AM335X_EPWM_AQCTLB_ZRO_XBHIGH (0x0002u)
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#define AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE (0x0003u)
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#define AM335X_EPWM_AQCTLB_CBU_SHIFT (0x0008u)
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#define AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE (0x0003u)
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#define AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u)
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#define AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN (0x00000002u)
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#define AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u)
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#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
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#define AM335X_TBCTL_CLKDIV_MASK (3 << 10)
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#define AM335X_TBCTL_HSPCLKDIV_MASK (3 << 7)
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#define AM335X_EPWM_TBCTL_CLKDIV (0x1C00u)
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#define AM335X_EPWM_TBCTL_CLKDIV_SHIFT (0x000Au)
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#define AM335X_EPWM_TBCTL_HSPCLKDIV (0x0380u)
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#define AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT (0x0007u)
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#define AM335X_EPWM_TBCTL_PRDLD (0x0008u)
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#define AM335X_EPWM_PRD_LOAD_SHADOW_MASK AM335X_EPWM_TBCTL_PRDLD
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#define AM335X_EPWM_SHADOW_WRITE_ENABLE 0x0
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#define AM335X_EPWM_SHADOW_WRITE_DISABLE 0x1
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#define AM335X_EPWM_TBCTL_PRDLD_SHIFT (0x0003u)
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#define AM335X_EPWM_TBCTL_CTRMODE (0x0003u)
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#define AM335X_EPWM_COUNTER_MODE_MASK AM335X_EPWM_TBCTL_CTRMODE
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#define AM335X_TBCTL_FREERUN (2 << 14)
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#define AM335X_TBCTL_CTRMODE_UP (0x0000u)
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#define AM335X_TBCTL_CTRMODE_SHIFT (0x0000u)
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#define AM335X_EPWM_COUNT_UP (AM335X_TBCTL_CTRMODE_UP << \
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AM335X_TBCTL_CTRMODE_SHIFT)
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#define AM335X_EPWM_REGS (0x00000200)
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#define AM335X_EPWM_0_REGS (AM335X_PWMSS0_MMAP_ADDR + AM335X_EPWM_REGS)
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#define AM335X_EPWM_1_REGS (AM335X_PWMSS1_MMAP_ADDR + AM335X_EPWM_REGS)
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#define AM335X_EPWM_2_REGS (AM335X_PWMSS2_MMAP_ADDR + AM335X_EPWM_REGS)
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#define AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE (0x00000003u)
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#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u)
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#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
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#define AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u)
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#define AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u)
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#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u)
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#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u)
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#define AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
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#define AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE (0x00000003u)
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#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC (0x0u)
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#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
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#define AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST (0x00030000u)
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