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This commit is contained in:
Ralf Corsepius
2009-12-04 05:25:30 +00:00
parent 42e243eeef
commit 5bb38e1566
37 changed files with 298 additions and 298 deletions
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cpukit/score/cpu/arm/arm_exc_handler_high.c
+16 -16
View File
@@ -44,18 +44,18 @@ static void _defaultExcHandler (CPU_Exception_frame *ctx)
printk("----------------------------------------------------------\n\r");
#if 0
printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r",
ctx->register_r0, ctx->register_r1,
ctx->register_r0, ctx->register_r1,
ctx->register_r2, ctx->register_r3);
printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r",
ctx->register_r4, ctx->register_r5,
ctx->register_r4, ctx->register_r5,
ctx->register_r6, ctx->register_r7);
printk(" r8 = %8x r9 = %8x r10 = %8x\n\r",
ctx->register_r8, ctx->register_r9, ctx->register_r10);
printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r",
ctx->register_fp, ctx->register_ip,
ctx->register_fp, ctx->register_ip,
ctx->register_sp, ctx->register_lr - 4);
printk("----------------------------------------------------------\n\r");
#endif
#endif
if (_ISR_Nest_level > 0) {
/*
* In this case we shall not delete the task interrupted as
@@ -75,9 +75,9 @@ typedef void (*cpuExcHandlerType) (CPU_Exception_frame*);
cpuExcHandlerType _currentExcHandler = _defaultExcHandler;
extern void _Exception_Handler_Undef_Swi(void);
extern void _Exception_Handler_Abort(void);
extern void _exc_data_abort(void);
extern void _Exception_Handler_Undef_Swi(void);
extern void _Exception_Handler_Abort(void);
extern void _exc_data_abort(void);
@@ -85,31 +85,31 @@ extern void _exc_data_abort(void);
void rtems_exception_init_mngt(void)
{
ISR_Level level;
_CPU_ISR_Disable(level);
_CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,
_Exception_Handler_Undef_Swi,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_SWI,
_Exception_Handler_Undef_Swi,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
_exc_data_abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,
_CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ,
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_Enable(level);
}
cpukit/score/cpu/arm/arm_exc_handler_low.S
+1 -1
View File
@@ -63,7 +63,7 @@ _go_back_1:
ldr sp, [r13, #REG_SP]
ldr lr, [r13, #REG_LR]
add r13,r13,#SIZE_REGS
movs pc,r14 /* return */
movs pc,r14 /* return */
/* FIXME: _Exception_Handler_Abort is untested */
DEFINE_FUNCTION_ARM(_Exception_Handler_Abort)
cpukit/score/cpu/arm/cpu.c
+2 -2
View File
@@ -93,10 +93,10 @@ void _CPU_ISR_install_vector(
)
{
/* Redirection table starts at the end of the vector table */
volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4);
volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4);
uint32_t current_handler = table [vector];
/* The current handler is now the old one */
if (old_handler != NULL) {
*old_handler = (proc_ptr) current_handler;
cpukit/score/cpu/arm/cpu_asm.S
+3 -3
View File
@@ -37,9 +37,9 @@
*
* Using the ldm/stm opcodes save 2-3 us on 100 MHz ARM9TDMI with
* a 16 bit data bus.
*
*
*/
DEFINE_FUNCTION_ARM(_CPU_Context_switch)
/* Start saving context */
mrs r2, cpsr
@@ -47,7 +47,7 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch)
/* Start restoring context */
_restore:
_restore:
ldmia r1, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
msr cpsr, r2
#ifdef __thumb__
cpukit/score/cpu/arm/rtems/asm.h
+2 -2
View File
@@ -11,7 +11,7 @@
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*/
/*
* COPYRIGHT:
*
@@ -96,7 +96,7 @@
#define NUM_IRQ_VECTOR 6 // IRQ number
#define NUM_FIQ_VECTOR 7 // IRQ number
// //
// //
#define CPSR_IRQ_DISABLE 0x80 // FIQ disabled when =1
#define CPSR_FIQ_DISABLE 0x40 // FIQ disabled when =1
#define CPSR_THUMB_ENABLE 0x20 // Thumb mode when =1
cpukit/score/cpu/arm/rtems/score/arm.h
+1 -1
View File
@@ -2,7 +2,7 @@
* @file rtems/score/arm.h
*/
/*
/*
* $Id$
*
* COPYRIGHT (c) 2000 Canon Research Centre France SA.
cpukit/score/cpu/h8300/cpu.c
+2 -2
View File
@@ -41,7 +41,7 @@ void _CPU_Initialize(void)
*
* This routine returns the current interrupt level.
*/
uint32_t _CPU_ISR_Get_level( void )
{
unsigned int _ccr;
@@ -61,7 +61,7 @@ uint32_t _CPU_ISR_Get_level( void )
*
* _CPU_ISR_install_raw_handler
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
cpukit/score/cpu/h8300/cpu_asm.S
+8 -8
View File
@@ -3,14 +3,14 @@
* Copyright Comnet Technologies Ltd 1999
*
* Based on example code and other ports with this copyright:
*
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/
@@ -18,18 +18,18 @@
;.equ RUNCONTEXT_ARG, er0
;.equ HEIRCONTEXT_ARG, er1
/*
/*
* Make sure we tell the assembler what type of CPU model we are
* being compiled for.
*/
*/
#if defined(__H8300H__)
.h8300h
#endif
#if defined(__H8300S__)
#if defined(__H8300S__)
.h8300s
#endif
#if defined(__H8300SX__)
#if defined(__H8300SX__)
.h8300sx
#endif
.text
@@ -121,7 +121,7 @@ __ISR_Handler:
nested:
mov.l er6,@-er7 ; save sp so pop regardless of nest level
;; Inc system counters
;; Inc system counters
mov.l @__ISR_Nest_level,er1
inc.l #1,er1
mov.l er1,@__ISR_Nest_level
cpukit/score/cpu/h8300/rtems/asm.h
+3 -3
View File
@@ -19,14 +19,14 @@
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
*
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/
cpukit/score/cpu/h8300/rtems/score/cpu.h
+13 -13
View File
@@ -274,7 +274,7 @@ extern "C" {
* H8300 Specific Information:
*
* XXX
* The port initially called a BSP dependent routine called
* The port initially called a BSP dependent routine called
* IDLE_Monitor. The idle task body can be overridden by
* the BSP in newer versions of RTEMS.
*/
@@ -484,7 +484,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
* It is highly unlikely the H8300 will get used in a multiprocessor system.
*/
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
/*
* This defines the number of entries in the ISR_Vector_table managed
@@ -642,7 +642,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
*
* H8300 Specific Information:
*
* XXX
* XXX
*/
#if defined(__H8300H__) || defined(__H8300S__)
@@ -652,7 +652,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
asm volatile( "stc ccr, %0 ; orc #0x80,ccr " \
: "=m" (__ccr) /* : "0" (__ccr) */ ); \
(_isr_cookie) = __ccr; \
} while (0)
} while (0)
#else
#define _CPU_ISR_Disable( _isr_cookie ) (_isr_cookie) = 0
#endif
@@ -673,7 +673,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
asm volatile( "ldc %0, ccr" : : "m" (__ccr) ); \
} while (0)
} while (0)
#else
#define _CPU_ISR_Enable( _isr_cookie )
#endif
@@ -694,7 +694,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
do { \
unsigned char __ccr = (unsigned char) (_isr_cookie); \
asm volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \
} while (0)
} while (0)
#else
#define _CPU_ISR_Flash( _isr_cookie )
#endif
@@ -852,8 +852,8 @@ uint32_t _CPU_ISR_Get_level( void );
#define _CPU_Fatal_halt( _error ) \
printk("Fatal Error %d Halted\n",_error); \
for(;;)
for(;;)
/* end of Fatal Error manager macros */
@@ -986,14 +986,14 @@ void _CPU_Initialize(void);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*
* H8300 Specific Information:
*
* XXX
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
@@ -1129,18 +1129,18 @@ void _CPU_Context_restore_fp(
*
* This is the generic implementation.
*/
static inline uint32_t CPU_swap_u32(
uint32_t value
)
{
uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return( swapped );
}
cpukit/score/cpu/h8300/rtems/score/h8300.h
+1 -1
View File
@@ -40,4 +40,4 @@ extern "C" {
}
#endif
#endif
#endif
cpukit/score/cpu/m32c/varvects.S
+9 -9
View File
@@ -3,30 +3,30 @@
Copyright (c) 2008 Red Hat Incorporated.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright
Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
The name of Red Hat Incorporated may not be used to endorse
or promote products derived from this software without specific
prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
cpukit/score/cpu/m32r/cpu.c
+2 -2
View File
@@ -36,7 +36,7 @@ void _CPU_Initialize(void)
*
* XXX document implementation including references if appropriate
*/
uint32_t _CPU_ISR_Get_level( void )
{
return 0;
@@ -50,7 +50,7 @@ uint32_t _CPU_ISR_Get_level( void )
*
* XXX document implementation including references if appropriate
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
cpukit/score/cpu/m32r/cpu_asm.c
+1 -1
View File
@@ -84,7 +84,7 @@ void _ISR_Handler(void)
*
* LABEL "exit interrupt (simple case):
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
* if outermost interrupt
* if outermost interrupt
* restore stack
* #endif
* prepare to get out of interrupt
cpukit/score/cpu/m32r/rtems/score/cpu.h
+17 -17
View File
@@ -13,7 +13,7 @@
*
* + Anywhere there is an XXX, it should be replaced
* with information about the CPU family being ported to.
*
*
* + At the end of each comment section, there is a heading which
* says "Port Specific Information:". When porting to RTEMS,
* add CPU family specific information in this section
@@ -168,7 +168,7 @@ extern "C" {
/**
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*
* Port Specific Information:
@@ -195,7 +195,7 @@ extern "C" {
* an i387 and wish to leave floating point support out of RTEMS.
*/
/**
/**
* @def CPU_SOFTWARE_FP
*
* Does the CPU have no hardware floating point and GCC provides a
@@ -203,7 +203,7 @@ extern "C" {
* switched?
*
* This feature conditional is used to indicate whether or not there
* is software implemented floating point that must be context
* is software implemented floating point that must be context
* switched. The determination of whether or not this applies
* is very tool specific and the state saved/restored is also
* compiler specific.
@@ -494,7 +494,7 @@ typedef struct {
* This macro returns the stack pointer associated with @a _context.
*
* @param[in] _context is the thread context area to access
*
*
* @return This method returns the stack pointer.
*/
#define _CPU_Context_Get_SP( _context ) \
@@ -517,7 +517,7 @@ typedef struct {
* in @ref Context_Control.
*/
typedef struct {
/** This field is a hint that a port will have a number of integer
/** This field is a hint that a port will have a number of integer
* registers that need to be saved when an interrupt occurs or
* when a context switch occurs at the end of an ISR.
*/
@@ -557,14 +557,14 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/**
* @ingroup CPUInterrupt
* This variable points to the lowest physical address of the interrupt
* This variable points to the lowest physical address of the interrupt
* stack.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
/**
* @ingroup CPUInterrupt
* This variable points to the lowest physical address of the interrupt
* This variable points to the lowest physical address of the interrupt
* stack.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
@@ -658,7 +658,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
*
* @note This does not have to be a power of 2 although it should be
* a multiple of 2 greater than or equal to 2. The requirement
* to be a multiple of 2 is because the heap uses the least
* to be a multiple of 2 is because the heap uses the least
* significant field of the front and back flags to indicate
* that a block is in use or free. So you do not want any odd
* length blocks really putting length data in that bit.
@@ -939,7 +939,7 @@ void _CPU_Context_Restart_self(
/**
* @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
*
* This set of routines are used to implement fast searches for
* This set of routines are used to implement fast searches for
* the most important ready task.
*/
@@ -964,7 +964,7 @@ void _CPU_Context_Restart_self(
/**
* @ingroup CPUBitfield
* This routine sets @a _output to the bit number of the first bit
* set in @a _value. @a _value is of CPU dependent type
* set in @a _value. @a _value is of CPU dependent type
* @a Priority_Bit_map_control. This type may be either 16 or 32 bits
* wide although only the 16 least significant bits will be used.
*
@@ -1007,14 +1007,14 @@ void _CPU_Context_Restart_self(
if _value > 0x00ff
_value >>=8
_number = 8;
if _value > 0x0000f
_value >=8
_number += 4
_number += bit_set_table[ _value ]
@endverbatim
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*
@@ -1086,7 +1086,7 @@ void _CPU_Initialize(void);
/**
* @ingroup CPUInterrupt
* This routine installs a "raw" interrupt handler directly into the
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*
* @param[in] vector is the vector number
@@ -1236,12 +1236,12 @@ static inline uint32_t CPU_swap_u32(
)
{
uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return swapped;
}
cpukit/score/cpu/m32r/rtems/score/m32r.h
+8 -8
View File
@@ -1,5 +1,5 @@
/*
* This file sets up basic CPU dependency settings based on
* This file sets up basic CPU dependency settings based on
* compiler settings. For example, it can determine if
* floating point is available. This particular implementation
* is specified to the NO CPU port.
@@ -32,25 +32,25 @@ extern "C" {
* that this port supports and which RTEMS CPU model they correspond
* to.
*/
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define NOCPU_HAS_FPU 1
#elif defined(__m32r__)
#define CPU_MODEL_NAME "m32r"
#define NOCPU_HAS_FPU 1
#else
#error "Unsupported CPU Model"
#endif
/*
cpukit/score/cpu/m68k/cpu.c
+3 -3
View File
@@ -49,7 +49,7 @@ void _CPU_Initialize(void)
*
* _CPU_ISR_Get_level
*/
uint32_t _CPU_ISR_Get_level( void )
{
uint32_t level;
@@ -63,7 +63,7 @@ uint32_t _CPU_ISR_Get_level( void )
*
* _CPU_ISR_install_raw_handler
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
@@ -88,7 +88,7 @@ void _CPU_ISR_install_raw_handler(
/*
* On CPU models without a VBR, it is necessary for there to be some
* header code for each ISR which saves a register, loads the vector
* number, and jumps to _ISR_Handler.
* number, and jumps to _ISR_Handler.
*/
m68k_get_vbr( interrupt_table );
cpukit/score/cpu/m68k/rtems/m68k/m68302.h
+2 -2
View File
@@ -227,7 +227,7 @@ enum m68302_ivec_e {
* The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7
* structures in the parameter RAM.
*
* Access to the DRAM registers can be accomplished by
* Access to the DRAM registers can be accomplished by
* the following approach:
*
* volatile m302_DRAM_refresh_t *dram;
@@ -599,7 +599,7 @@ typedef struct {
} m302_dualPortRAM_t;
/* some useful defines the some of the registers above */
/* ----
MC68302 Chip Select Registers
cpukit/score/cpu/m68k/rtems/m68k/qsm.h
+3 -3
View File
@@ -14,10 +14,10 @@
*
* For more information, refer to Motorola's "Modular Microcontroller
* Family Queued Serial Module Reference Manual" (Motorola document
* QSMRM/AD).
* QSMRM/AD).
*
* This file was created by John S. Gwynne to support Motorola's 68332 MCU.
*
*
* Redistribution and use in source and binary forms are permitted
* provided that the following conditions are met:
* 1. Redistribution of source code and documentation must retain
@@ -53,7 +53,7 @@
#undef SIM_MM
#define SIM_MM 1
#define QSM_CRB 0xfffc00
#endif
#endif
#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB)
cpukit/score/cpu/m68k/rtems/m68k/sim.h
+4 -4
View File
@@ -12,7 +12,7 @@
* () Clock signal generation for other intermodule bus (IMB) members
* and external devices.
*
* () The generation of chip-select signals that simplify external
* () The generation of chip-select signals that simplify external
* circuitry interface.
*
* () Data ports that are available for general purpose input and
@@ -22,10 +22,10 @@
*
* For more information, refer to Motorola's "Modular Microcontroller
* Family System Integration Module Reference Manual" (Motorola document
* SIMRM/AD).
* SIMRM/AD).
*
* This file was created by John S. Gwynne to support Motorola's 68332 MCU.
*
*
* Redistribution and use in source and binary forms are permitted
* provided that the following conditions are met:
* 1. Redistribution of source code and documentation must retain
@@ -215,7 +215,7 @@
used. These bits always read zero; write have no effect. CSPAR0 bit
1 always reads one; writes to CSPAR0 bit 1 have no effect. */
#define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB)
/* Chip Select Pin Assignment
/* Chip Select Pin Assignment
Register 1 */
/* CSPAR1 contains five two-bit fields that determine the finctions of
corresponding chip-select pins. CSPAR1[15:10] are not used. These
cpukit/score/cpu/m68k/rtems/score/cpu.h
+6 -6
View File
@@ -66,7 +66,7 @@ extern "C" {
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
@@ -311,7 +311,7 @@ typedef struct {
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
extern void* _VBR;
extern void* _VBR;
#if ( M68K_HAS_VBR == 0 )
@@ -336,7 +336,7 @@ typedef struct {
#define M68K_JMP 0x4EF9
/* points to jsr-exception-table in targets wo/ VBR register */
SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
#endif /* M68K_HAS_VBR */
@@ -659,10 +659,10 @@ void _CPU_Initialize(void);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
@@ -724,7 +724,7 @@ void _CPU_Context_restore_fp(
/*
* Hooks for the Floating Point Support Package (FPSP) provided by Motorola
*
* NOTES:
* NOTES:
*
* Motorola 68k family CPU's before the 68040 used a coprocessor
* (68881 or 68882) to handle floating point. The 68040 has internal
cpukit/score/cpu/m68k/rtems/score/m68k.h
+24 -24
View File
@@ -71,9 +71,9 @@ extern "C" {
* implement the output buffer impedance selection mode of operation."
*
* M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
* which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
* which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
* 68010, 68302, 68306, 68307). This instruction is available on the 68020
* up and the cpu32 based models.
* up and the cpu32 based models.
*
* M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
* data access (68020, 68030, 68040, 68060, CPU32+).
@@ -91,7 +91,7 @@ extern "C" {
# define CPU_NAME "Motorola ColdFire"
# if defined(__mcfisaa__)
/* Motorola ColdFire ISA A */
/* Motorola ColdFire ISA A */
# define CPU_MODEL_NAME "mcfisaa"
# define M68K_HAS_VBR 1
# define M68K_HAS_BFFFO 0
@@ -101,7 +101,7 @@ extern "C" {
# define M68K_HAS_MISALIGNED 1
# elif defined(__mcfisaaplus__)
/* Motorola ColdFire ISA A+ */
/* Motorola ColdFire ISA A+ */
# define CPU_MODEL_NAME "mcfisaaplus"
# define M68K_HAS_VBR 1
# define M68K_HAS_BFFFO 0
@@ -111,7 +111,7 @@ extern "C" {
# define M68K_HAS_MISALIGNED 1
# elif defined(__mcfisab__)
/* Motorola ColdFire ISA B */
/* Motorola ColdFire ISA B */
# define CPU_MODEL_NAME "mcfisab"
# define M68K_HAS_VBR 1
# define M68K_HAS_BFFFO 0
@@ -169,8 +169,8 @@ extern "C" {
#else
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines. Notice the only exception to this is that
* Figure out all CPU Model Feature Flags based upon compiler
* predefines. Notice the only exception to this is that
* gcc does not distinguish between CPU32 and CPU32+. This
* feature selection logic is setup such that if RTEMS__mcpu32p__
* is defined, then CPU32+ rules are used. Otherwise, the safe
@@ -181,7 +181,7 @@ extern "C" {
/*
* One stack size fits all 68000 processors.
*/
*/
# define M68K_CPU_STACK_MINIMUM_SIZE 4096
# if (defined(__mc68020__) && !defined(__mcpu32__))
@@ -200,9 +200,9 @@ extern "C" {
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
# elif defined(__mc68030__)
# define CPU_MODEL_NAME "m68030"
# define M68K_HAS_VBR 1
# define M68K_HAS_SEPARATE_STACKS 1
@@ -217,7 +217,7 @@ extern "C" {
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
# elif defined(__mc68040__)
# define CPU_MODEL_NAME "m68040"
@@ -234,7 +234,7 @@ extern "C" {
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
# elif defined(__mc68060__)
# define CPU_MODEL_NAME "m68060"
@@ -251,7 +251,7 @@ extern "C" {
# define M68K_HAS_FPU 0
# define M68K_HAS_FPSP_PACKAGE 0
# endif
# elif defined(__mc68302__)
# define CPU_MODEL_NAME "m68302"
@@ -266,7 +266,7 @@ extern "C" {
/* gcc and egcs do not distinguish between CPU32 and CPU32+ */
# elif defined(RTEMS__mcpu32p__)
# define CPU_MODEL_NAME "mcpu32+"
# define M68K_HAS_VBR 1
# define M68K_HAS_SEPARATE_STACKS 0
@@ -278,7 +278,7 @@ extern "C" {
# define M68K_HAS_FPSP_PACKAGE 0
# elif defined(__mcpu32__)
# define CPU_MODEL_NAME "mcpu32"
# define M68K_HAS_VBR 1
# define M68K_HAS_SEPARATE_STACKS 0
@@ -290,7 +290,7 @@ extern "C" {
# define M68K_HAS_FPSP_PACKAGE 0
# elif defined(__mc68000__)
# define CPU_MODEL_NAME "m68000"
# define M68K_HAS_VBR 0
# define M68K_HAS_SEPARATE_STACKS 0
@@ -376,7 +376,7 @@ extern "C" {
asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
_level = (_tmpsr & 0x0700) >> 8; \
} while (0)
#define m68k_set_interrupt_level( _newlevel ) \
do { \
register uint32_t _tmpsr; \
@@ -394,7 +394,7 @@ extern "C" {
asm volatile ( "movec %0,%%vbr " : : "r" (vbr))
#elif ( defined(__mcoldfire__) )
extern void* _VBR;
extern void* _VBR;
#define m68k_get_vbr( _vbr ) _vbr = &_VBR
#define m68k_set_vbr( _vbr ) \
@@ -402,7 +402,7 @@ extern void* _VBR;
asm volatile ( "movec %0,%%vbr " : : "r" (_vbr)); \
_VBR = (void *)_vbr; \
} while(0)
#else
#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
#define m68k_set_vbr( _vbr )
@@ -429,23 +429,23 @@ static inline uint32_t m68k_swap_u32(
)
{
uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return( swapped );
}
static inline uint16_t m68k_swap_u16(
uint16_t value
)
{
return (((value & 0xff) << 8) | ((value >> 8) & 0xff));
}
#else
static inline uint32_t m68k_swap_u32(
@@ -484,7 +484,7 @@ static inline uint16_t m68k_swap_u16(
*
* This function is used to map virtual addresses to physical
* addresses.
*
*
* FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE
* PHYSICAL ADDRESSES
*/
cpukit/score/cpu/mips/cpu.c
+11 -11
View File
@@ -8,7 +8,7 @@
* should still work OK.
*
* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
* Joel Sherrill <joel@OARcorp.com>.
* Joel Sherrill <joel@OARcorp.com>.
*
* These changes made the code conditional on standard cpp predefines,
* merged the mips1 and mips3 code sequences as much as possible,
@@ -29,7 +29,7 @@
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the
* Transition Networks makes no representations about the
* suitability of this software for any purpose.
*
* COPYRIGHT (c) 1989-2001.
@@ -49,19 +49,19 @@
/*
** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
/*
** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
** address to the context switch code.
*/
#if (__mips == 1) || (__mips == 32)
typedef uint32_t ESF_PTR_TYPE;
#elif (__mips == 3)
#elif (__mips == 3)
typedef uint64_t ESF_PTR_TYPE;
#else
#error "unknown MIPS ISA"
#endif
ESF_PTR_TYPE __exceptionStackFrame = 0;
ESF_PTR_TYPE __exceptionStackFrame = 0;
@@ -124,12 +124,12 @@ void _CPU_ISR_Set_level( uint32_t new_level )
{
unsigned int sr, srbits;
/*
** mask off the int level bits only so we can
/*
** mask off the int level bits only so we can
** preserve software int settings and FP enable
** for this thread. Note we don't force software ints
** enabled when changing level, they were turned on
** when this task was created, but may have been turned
** when this task was created, but may have been turned
** off since, so we'll just leave them alone.
*/
@@ -158,7 +158,7 @@ void _CPU_ISR_Set_level( uint32_t new_level )
mips_set_sr(sr); * first disable ie bit (recommended) *
}
*/
#elif __mips == 1
mips_set_sr( (sr & ~SR_IEC) );
srbits = sr & ~(0xfc00 | SR_IEC);
@@ -184,7 +184,7 @@ void _CPU_ISR_Set_level( uint32_t new_level )
* Output parameters: NONE
*
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
cpukit/score/cpu/mips/cpu_asm.S
+76 -76
View File
@@ -19,7 +19,7 @@
* Networks makes no representations about the suitability
* of this software for any purpose.
* 2000: Reworked by Alan Cudmore <alanc@linuxstart.com> to become
* the baseline of the more general MIPS port.
* the baseline of the more general MIPS port.
* 2001: Joel Sherrill <joel@OARcorp.com> continued this rework,
* rewriting as much as possible in C and added the JMR3904 BSP
* so testing could be performed on a simulator.
@@ -39,7 +39,7 @@
* support for R4000 processors running 32 bit code. Fixed #define
* problems that caused fpu code to always be included even when no
* fpu is present.
*
*
* COPYRIGHT (c) 1989-2002.
* On-Line Applications Research Corporation (OAR).
*
@@ -160,38 +160,38 @@
#define C0_EPC_OFFSET 12
/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */
#define FP0_OFFSET 0
#define FP1_OFFSET 1
#define FP2_OFFSET 2
#define FP3_OFFSET 3
#define FP4_OFFSET 4
#define FP5_OFFSET 5
#define FP6_OFFSET 6
#define FP7_OFFSET 7
#define FP8_OFFSET 8
#define FP9_OFFSET 9
#define FP10_OFFSET 10
#define FP11_OFFSET 11
#define FP12_OFFSET 12
#define FP13_OFFSET 13
#define FP14_OFFSET 14
#define FP15_OFFSET 15
#define FP16_OFFSET 16
#define FP17_OFFSET 17
#define FP18_OFFSET 18
#define FP19_OFFSET 19
#define FP20_OFFSET 20
#define FP21_OFFSET 21
#define FP22_OFFSET 22
#define FP23_OFFSET 23
#define FP24_OFFSET 24
#define FP25_OFFSET 25
#define FP26_OFFSET 26
#define FP27_OFFSET 27
#define FP28_OFFSET 28
#define FP29_OFFSET 29
#define FP30_OFFSET 30
#define FP31_OFFSET 31
#define FP0_OFFSET 0
#define FP1_OFFSET 1
#define FP2_OFFSET 2
#define FP3_OFFSET 3
#define FP4_OFFSET 4
#define FP5_OFFSET 5
#define FP6_OFFSET 6
#define FP7_OFFSET 7
#define FP8_OFFSET 8
#define FP9_OFFSET 9
#define FP10_OFFSET 10
#define FP11_OFFSET 11
#define FP12_OFFSET 12
#define FP13_OFFSET 13
#define FP14_OFFSET 14
#define FP15_OFFSET 15
#define FP16_OFFSET 16
#define FP17_OFFSET 17
#define FP18_OFFSET 18
#define FP19_OFFSET 19
#define FP20_OFFSET 20
#define FP21_OFFSET 21
#define FP22_OFFSET 22
#define FP23_OFFSET 23
#define FP24_OFFSET 24
#define FP25_OFFSET 25
#define FP26_OFFSET 26
#define FP27_OFFSET 27
#define FP28_OFFSET 28
#define FP29_OFFSET 29
#define FP30_OFFSET 30
#define FP31_OFFSET 31
#define FPCS_OFFSET 32
@@ -222,9 +222,9 @@ FRAME(_CPU_Context_save_fp,sp,0,ra)
.set noreorder
.set noat
/*
** Make sure the FPU is on before we save state. This code
** is here because the FPU context switch might occur when an
/*
** Make sure the FPU is on before we save state. This code
** is here because the FPU context switch might occur when an
** integer task is switching out with a FP task switching in.
*/
mfc0 t0,C0_SR
@@ -245,7 +245,7 @@ FRAME(_CPU_Context_save_fp,sp,0,ra)
jal _CPU_Context_save_fp_from_exception
NOP
/*
/*
** Reassert the task's state because we've not saved it yet.
*/
mtc0 t1,C0_SR
@@ -321,9 +321,9 @@ FRAME(_CPU_Context_restore_fp,sp,0,ra)
.set noat
.set noreorder
/*
** Make sure the FPU is on before we retrieve state. This code
** is here because the FPU context switch might occur when an
/*
** Make sure the FPU is on before we retrieve state. This code
** is here because the FPU context switch might occur when an
** integer task is switching out with a FP task switching in.
*/
mfc0 t0,C0_SR
@@ -344,7 +344,7 @@ FRAME(_CPU_Context_restore_fp,sp,0,ra)
jal _CPU_Context_restore_fp_from_exception
NOP
/*
/*
** Reassert the old task's state because we've not restored the
** new one yet.
*/
@@ -439,14 +439,14 @@ FRAME(_CPU_Context_switch,sp,0,ra)
STREG s7,S7_OFFSET*R_SZ(a0)
/*
/*
** this code grabs the userspace EPC if we're dispatching from
** an interrupt frame or supplies the address of the dispatch
** routines if not. This is entirely for the gdbstub's benefit so
** routines if not. This is entirely for the gdbstub's benefit so
** it can know where each task is running.
**
** Its value is only set when calling threadDispatch from
** the interrupt handler and is cleared immediately when this
** the interrupt handler and is cleared immediately when this
** routine gets it.
*/
@@ -504,14 +504,14 @@ _CPU_Context_switch_restore:
/*
** Incorporate the incoming task's FP coprocessor state and interrupt mask/enable
** into the status register. We jump thru the requisite hoops to ensure we
** into the status register. We jump thru the requisite hoops to ensure we
** maintain all other SR bits as global values.
**
** Get the task's FPU enable, int mask & int enable bits. Although we keep the
** Get the task's FPU enable, int mask & int enable bits. Although we keep the
** software int enables on a per-task basis, the rtems_task_create
** Interrupt Level & int level manipulation functions cannot enable/disable them,
** so they are automatically enabled for all tasks. To turn them off, a task
** must itself manipulate the SR register.
** Interrupt Level & int level manipulation functions cannot enable/disable them,
** so they are automatically enabled for all tasks. To turn them off, a task
** must itself manipulate the SR register.
**
** Although something of a hack on this processor, we treat the SR register
** int enables as the RTEMS interrupt level. We use the int level
@@ -523,7 +523,7 @@ _CPU_Context_switch_restore:
** interrupt enable state is recorded. The task swapping in will apply its
** specific SR bits, including interrupt enable. If further task-specific
** SR bits are arranged, it is this code, the cpu.c interrupt level stuff and
** cpu.h task initialization code that will be affected.
** cpu.h task initialization code that will be affected.
*/
li t2,SR_CU1
@@ -531,12 +531,12 @@ _CPU_Context_switch_restore:
/* int enable bits */
#if (__mips == 3) || (__mips == 32)
/*
/*
** Save IE
*/
or t2,SR_IE
#elif __mips == 1
/*
/*
** Save current, previous & old int enables. This is key because
** we can dispatch from within the stack frame used by an
** interrupt service. The int enables nest, but not beyond
@@ -623,7 +623,7 @@ ENDFRAME(_DBG_Handler)
* This routine provides the RTEMS interrupt management.
*
* void _ISR_Handler()
*
*
*
* This discussion ignores a lot of the ugly details in a real
* implementation such as saving enough registers/state to be
@@ -654,7 +654,7 @@ FRAME(_ISR_Handler,sp,0,ra)
/* wastes a lot of stack space for context?? */
ADDIU sp,sp,-EXCP_STACK_SIZE
STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
STREG v0, R_V0*R_SZ(sp)
STREG v1, R_V1*R_SZ(sp)
STREG a0, R_A0*R_SZ(sp)
@@ -671,11 +671,11 @@ FRAME(_ISR_Handler,sp,0,ra)
STREG t7, R_T7*R_SZ(sp)
mflo t0
STREG t8, R_T8*R_SZ(sp)
STREG t0, R_MDLO*R_SZ(sp)
STREG t0, R_MDLO*R_SZ(sp)
STREG t9, R_T9*R_SZ(sp)
mfhi t0
STREG gp, R_GP*R_SZ(sp)
STREG t0, R_MDHI*R_SZ(sp)
STREG t0, R_MDHI*R_SZ(sp)
STREG fp, R_FP*R_SZ(sp)
.set noat
@@ -747,16 +747,16 @@ _ISR_Handler_Exception:
andi t0,t0,(SR_CU1 >> 16)
beqz t0, 1f
NOP
la a1,R_F0*R_SZ(sp)
jal _CPU_Context_save_fp_from_exception
jal _CPU_Context_save_fp_from_exception
NOP
mfc1 t0,C1_REVISION
mfc1 t1,C1_STATUS
STREG t0,R_FEIR*R_SZ(sp)
STREG t1,R_FCSR*R_SZ(sp)
1:
1:
#endif
move a0,sp
@@ -764,10 +764,10 @@ _ISR_Handler_Exception:
NOP
/*
/*
** Note, if the exception vector returns, rely on it to have
** adjusted EPC so we will return to some correct address. If
** this is not done, we might get stuck in an infinite loop because
** this is not done, we might get stuck in an infinite loop because
** we'll return to the instruction where the exception occured and
** it could throw again.
**
@@ -839,7 +839,7 @@ excreturn:
andi t0,t0,(SR_CU1 >> 16)
beqz t0, 2f
NOP
la a1,R_F0*R_SZ(sp)
jal _CPU_Context_restore_fp_from_exception
NOP
@@ -861,9 +861,9 @@ excreturn:
/* do NOT restore the sp as this could mess up the world */
/* do NOT restore the cause as this could mess up the world */
/*
/*
** Jump all the way out. If theres a pending interrupt, just
** let it be serviced later. Since we're probably using the
** let it be serviced later. Since we're probably using the
** gdb stub, we've already disrupted the ISR service timing
** anyhow. We oughtn't mix exception and interrupt processing
** in the same exception call in case the exception stuff
@@ -960,7 +960,7 @@ _ISR_Handler_1:
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
* restore stack
* #endif
*
*
* if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
* goto the label "exit interrupt (simple case)"
*/
@@ -994,7 +994,7 @@ _ISR_Handler_1:
#elif (__mips == 3) || (__mips == 32)
/*
/*
** clear XL and set IE so we can get interrupts.
*/
li t1, SR_EXL
@@ -1013,22 +1013,22 @@ _ISR_Handler_1:
jal _Thread_Dispatch
NOP
/*
/*
** And make sure its clear in case we didn't dispatch. if we did, its
** already cleared
** already cleared
*/
la t0,__exceptionStackFrame
STREG zero,(t0)
NOP
/*
/*
** turn interrupts back off while we restore context so
** a badly timed interrupt won't mess things up
*/
mfc0 t0, C0_SR
#if __mips == 1
/* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
li t1,SR_IEC | SR_KUP | SR_KUC
not t1
@@ -1038,10 +1038,10 @@ _ISR_Handler_1:
#elif (__mips == 3) || (__mips == 32)
/* make sure EXL and IE are set so ints are disabled & we can update EPC for the return */
/* make sure EXL and IE are set so ints are disabled & we can update EPC for the return */
li t1,SR_IE /* Clear IE first (recommended) */
not t1
and t0,t1
not t1
and t0,t1
mtc0 t0,C0_SR
NOP
@@ -1097,7 +1097,7 @@ _ISR_Handler_exit:
LDREG t8, R_MDLO*R_SZ(sp)
LDREG t0, R_T0*R_SZ(sp)
mtlo t8
LDREG t8, R_MDHI*R_SZ(sp)
LDREG t8, R_MDHI*R_SZ(sp)
LDREG t1, R_T1*R_SZ(sp)
mthi t8
LDREG t2, R_T2*R_SZ(sp)
cpukit/score/cpu/mips/rtems/mips/idtcpu.h
+4 -4
View File
@@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
$Id$
*/
*/
/*
** idtcpu.h -- cpu related defines
@@ -70,7 +70,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */
#define C_VEC (K0BASE+0x100) /* cache error vector */
#define E_VEC (K0BASE+0x180) /* exception vector */
#else
#else
#error "EXCEPTION VECTORS: unknown ISA level"
#endif
#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
@@ -184,7 +184,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#endif
*/
/* Disabled by joel -- horrible overload of common word.
#ifndef wait
#ifndef wait
#define wait .word 0x42000020
#endif wait
*/
@@ -279,7 +279,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#endif
*/
/* Disabled by joel -- horrible overload of common word.
#ifndef wait
#ifndef wait
#define wait .word 0x42000020
#endif wait
*/
cpukit/score/cpu/mips/rtems/mips/iregdef.h
+2 -2
View File
@@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
$Id$
*/
*/
/*
** iregdef.h - IDT R3000 register structure header file
@@ -39,7 +39,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
* Look towards end of this file.
*/
/*
** register names
** register names
*/
#define r0 $0
#define r1 $1
cpukit/score/cpu/mips/rtems/score/cpu.h
+14 -14
View File
@@ -391,11 +391,11 @@ extern "C" {
/* WARNING: If this structure is modified, the constants in cpu.h must be updated. */
#if (__mips == 1) || (__mips == 32)
#define __MIPS_REGISTER_TYPE uint32_t
#define __MIPS_FPU_REGISTER_TYPE uint32_t
#define __MIPS_REGISTER_TYPE uint32_t
#define __MIPS_FPU_REGISTER_TYPE uint32_t
#elif __mips == 3
#define __MIPS_REGISTER_TYPE uint64_t
#define __MIPS_FPU_REGISTER_TYPE uint64_t
#define __MIPS_REGISTER_TYPE uint64_t
#define __MIPS_FPU_REGISTER_TYPE uint64_t
#else
#error "mips register size: unknown architecture level!!"
#endif
@@ -464,13 +464,13 @@ typedef struct {
* This struct reflects the stack frame employed in ISR_Handler. Note
* that the ISR routine save some of the registers to this frame for
* all interrupts and exceptions. Other registers are saved only on
* exceptions, while others are not touched at all. The untouched
* registers are not normally disturbed by high-level language
* exceptions, while others are not touched at all. The untouched
* registers are not normally disturbed by high-level language
* programs so they can be accessed when required.
*
* The registers and their ordering in this struct must directly
* correspond to the layout and ordering of * shown in iregdef.h,
* as cpu_asm.S uses those definitions to fill the stack frame.
* as cpu_asm.S uses those definitions to fill the stack frame.
* This struct provides access to the stack frame for C code.
*
* Similarly, this structure is used by debugger stubs and exception
@@ -820,17 +820,17 @@ void _CPU_ISR_Set_level( uint32_t ); /* in cpu.c */
* The per-thread status register holds the interrupt enable, FP enable
* and global interrupt enable for that thread. It means each thread can
* enable its own set of interrupts. If interrupts are disabled, RTEMS
* can still dispatch via blocking calls. This is the function of the
* "Interrupt Level", and on the MIPS, it controls the IEC bit and all
* can still dispatch via blocking calls. This is the function of the
* "Interrupt Level", and on the MIPS, it controls the IEC bit and all
* the hardware interrupts as defined in the SR. Software ints
* are automatically enabled for all threads, as they will only occur under
* program control anyhow. Besides, the interrupt level parm is only 8 bits,
* are automatically enabled for all threads, as they will only occur under
* program control anyhow. Besides, the interrupt level parm is only 8 bits,
* and controlling the software ints plus the others would require 9.
*
* If the Interrupt Level is 0, all ints are on. Otherwise, the
* Interrupt Level should supply a bit pattern to impose on the SR
* If the Interrupt Level is 0, all ints are on. Otherwise, the
* Interrupt Level should supply a bit pattern to impose on the SR
* interrupt bits; bit 0 applies to the mips1 IEC bit/mips3 EXL&IE, bits 1 thru 6
* apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of
* apply to the SR register Intr bits from bit 10 thru bit 15. Bit 7 of
* the Interrupt Level parameter is unused at this time.
*
* These are the only per-thread SR bits, the others are maintained
cpukit/score/cpu/mips/rtems/score/mips.h
+6 -6
View File
@@ -52,12 +52,12 @@ extern "C" {
* dependent features are present in a particular member
* of the family.
*/
#if defined(__mips_soft_float)
#define MIPS_HAS_FPU 0
#else
#define MIPS_HAS_FPU 1
#endif
#endif
#if (__mips == 1)
@@ -165,7 +165,7 @@ extern "C" {
/*
* Access the Breakpoint Program Counter & Mask registers
* Access the Breakpoint Program Counter & Mask registers
* (_x for BPC, _y for mask)
*/
@@ -190,7 +190,7 @@ extern "C" {
/*
* Access the Breakpoint Data Address & Mask registers
* Access the Breakpoint Data Address & Mask registers
* (_x for BDA, _y for mask)
*/
@@ -241,9 +241,9 @@ extern "C" {
#endif
/*
* Manipulate interrupt mask
* Manipulate interrupt mask
*
* mips_unmask_interrupt( _mask)
* mips_unmask_interrupt( _mask)
* enables interrupts - mask is positioned so it only needs to be or'ed
* into the status reg. This also does some other things !!!! Caution
* should be used if invoking this while in the middle of a debugging
cpukit/score/cpu/powerpc/rtems/asm.h
+3 -3
View File
@@ -49,7 +49,7 @@
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__
#endif
#ifndef __REGISTER_PREFIX__
@@ -210,8 +210,8 @@
/* The following registers are for the MPC5xx */
#define eie 0x050 /* External Interrupt Enable Register */
#define eid 0x051 /* External Interrupt Disable Register */
#define nri 0x052 /* Non-Recoverable Interrupt Register */
#define nri 0x052 /* Non-Recoverable Interrupt Register */
#elif defined(mpc860) || defined(mpc821)
/* The following registers are for the MPC8x0 */
#define der 0x095 /* Debug Enable Register */
cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
+5 -5
View File
@@ -104,7 +104,7 @@ extern "C" {
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
@@ -153,7 +153,7 @@ extern "C" {
*/
#ifndef ASM
/*
* This variable is optional. It is used on CPUs on which it is difficult
* to generate an "uninitialized" FP context. It is filled in by
@@ -194,7 +194,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
*/
#ifndef ASM
SCORE_EXTERN struct {
uint32_t *Disable_level;
void *Stack;
@@ -259,7 +259,7 @@ SCORE_EXTERN struct {
*/
#ifndef ASM
static inline uint32_t _CPU_ISR_Get_level( void )
{
register unsigned int msr;
@@ -280,7 +280,7 @@ static inline void _CPU_ISR_Set_level( uint32_t level )
}
_CPU_MSR_SET(msr);
}
void BSP_panic(char *);
/* Fatal Error manager macros */
cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
+1 -1
View File
@@ -43,7 +43,7 @@
/* Bit encodings for Hardware Implementation Register (HID0)
on PowerPC 603, 604, etc. processors (not 601). */
/* WARNING: HID0/HID1 are *truely* implementation dependent!
/* WARNING: HID0/HID1 are *truely* implementation dependent!
* you *cannot* rely on the same bits to be present,
* at the same place or even in the same register
* on different CPU familys.
cpukit/score/cpu/powerpc/rtems/score/cpu.h
+3 -3
View File
@@ -12,7 +12,7 @@
*
* $Id$
*/
#ifndef _RTEMS_SCORE_CPU_H
#define _RTEMS_SCORE_CPU_H
@@ -394,13 +394,13 @@ typedef struct CPU_Interrupt_frame {
* endianness for ALL fetches -- both code and data -- so the code
* will be fetched incorrectly.
*/
static inline uint32_t CPU_swap_u32(
uint32_t value
)
{
uint32_t swapped;
asm volatile("rlwimi %0,%1,8,24,31;"
"rlwimi %0,%1,24,16,23;"
"rlwimi %0,%1,8,8,15;"
cpukit/score/cpu/powerpc/rtems/score/powerpc.h
+3 -3
View File
@@ -61,7 +61,7 @@ extern "C" {
* This file contains the information required to build
* RTEMS for the PowerPC family.
*/
/* Generic ppc */
#ifdef _SOFT_FLOAT
@@ -72,7 +72,7 @@ extern "C" {
#define CPU_MODEL_NAME "Generic (classic FPU)"
#endif
#define PPC_ALIGNMENT 8
#define PPC_ALIGNMENT 8
#define PPC_STRUCTURE_ALIGNMENT 32
/*
@@ -132,7 +132,7 @@ extern "C" {
* support doubles (8-byte floating point numbers).
*
* If the model does NOT have FP support, then the model does
* NOT have double length FP registers.
* NOT have double length FP registers.
*/
#if (PPC_HAS_FPU)
cpukit/score/cpu/sh/cpu.c
+10 -10
View File
@@ -10,7 +10,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998-2001.
* On-Line Applications Research Corporation (OAR).
@@ -21,7 +21,7 @@
*
* $Id$
*/
#include <rtems/system.h>
#include <rtems/score/isr.h>
#include <rtems/score/sh_io.h>
@@ -71,7 +71,7 @@ void _CPU_Initialize(void)
*
* _CPU_ISR_Get_level
*/
uint32_t _CPU_ISR_Get_level( void )
{
/*
@@ -79,9 +79,9 @@ uint32_t _CPU_ISR_Get_level( void )
*/
register uint32_t _mask ;
sh_get_interrupt_level( _mask );
return ( _mask);
}
@@ -89,7 +89,7 @@ uint32_t _CPU_ISR_Get_level( void )
*
* _CPU_ISR_install_raw_handler
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
@@ -102,11 +102,11 @@ void _CPU_ISR_install_raw_handler(
*/
volatile proc_ptr *vbr ;
#if SH_PARANOID_ISR
#if SH_PARANOID_ISR
uint32_t level ;
sh_disable_interrupts( level );
#endif
#endif
/* get vbr */
asm ( "stc vbr,%0" : "=r" (vbr) );
@@ -155,7 +155,7 @@ void _CPU_ISR_install_vector(
#endif
/*
* We put the actual user ISR address in '_ISR_Vector_table'.
* We put the actual user ISR address in '_ISR_Vector_table'.
* This will be used by __ISR_Handler so the user gets control.
*/
@@ -193,7 +193,7 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
uint8_t _bit_set_table[16] =
uint8_t _bit_set_table[16] =
{ 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
cpukit/score/cpu/sh/rtems/score/cpu.h
+10 -10
View File
@@ -14,7 +14,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998-2006.
* On-Line Applications Research Corporation (OAR).
@@ -125,11 +125,11 @@ extern "C" {
/*
* We define the interrupt stack in the linker script
*/
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
@@ -293,7 +293,7 @@ extern "C" {
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
#endif
/*
* The following defines the number of bits actually used in the
* interrupt field of the task mode. How those bits map to the
@@ -374,7 +374,7 @@ typedef struct {
uint32_t *r0; /* arg return */
uint32_t gbr;
uint32_t sr;
uint32_t sr;
} Context_Control;
@@ -536,9 +536,9 @@ SCORE_EXTERN void CPU_delay( uint32_t microseconds );
*
* SH Specific Information: NONE
*/
#define _CPU_Initialize_vectors()
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _level.
@@ -607,7 +607,7 @@ uint32_t _CPU_ISR_Get_level( void );
* where the PSR contains an enable FPU bit.
*/
/*
/*
* FIXME: defined as a function for debugging - should be a macro
*/
SCORE_EXTERN void _CPU_Context_Initialize(
@@ -818,10 +818,10 @@ void _CPU_Initialize(void);
/*
* _CPU_ISR_install_raw_handler
*
* This routine installs a "raw" interrupt handler directly into the
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
cpukit/score/cpu/sh/rtems/score/sh.h
+17 -17
View File
@@ -14,7 +14,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
*
* COPYRIGHT (c) 1998-2001.
* On-Line Applications Research Corporation (OAR).
@@ -36,14 +36,14 @@ extern "C" {
/*
* This file contains the information required to build
* RTEMS for a particular member of the "SH" family.
*
*
* It does this by setting variables to indicate which implementation
* dependent features are present in a particular member of the family.
*/
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#if defined(__SH2E__) || defined(__SH3E__)
@@ -53,7 +53,7 @@ extern "C" {
#elif defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
/*
/*
* Define this if you want to use XD-registers.
* Then this registers will be saved/restored on context switch.
* ! They will not be saved/restored on interrupts!
@@ -68,7 +68,7 @@ extern "C" {
#define SH_HAS_FPU 0
#endif
#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
#define SH_HAS_FPU 0
#else
#warning Cannot detect FPU support, assuming no FPU
@@ -108,7 +108,7 @@ extern "C" {
"stc sr,%0\n\t" \
"ldc %1,sr\n\t"\
: "=&r" (_level ) \
: "r" (SH_IRQDIS_VALUE) );
: "r" (SH_IRQDIS_VALUE) );
#define sh_enable_interrupts( _level ) \
asm volatile( "ldc %0,sr\n\t" \
@@ -121,7 +121,7 @@ extern "C" {
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define sh_flash_interrupts( _level ) \
asm volatile( \
"ldc %1,sr\n\t" \
@@ -142,7 +142,7 @@ extern "C" {
"ldc r5,sr\n\t"\
: "=&r" (_level ) \
: "r" (SH_IRQDIS_MASK) \
: "r5" );
: "r5" );
#define sh_enable_interrupts( _level ) \
asm volatile( "ldc %0,sr\n\t" \
@@ -155,7 +155,7 @@ extern "C" {
* sections into two or more parts. The parameter _level is not
* modified.
*/
#define sh_flash_interrupts( _level ) \
asm volatile( \
"stc sr,r5\n\t" \
@@ -189,18 +189,18 @@ extern "C" {
* The following routine swaps the endian format of an unsigned int.
* It must be static because it is referenced indirectly.
*/
static inline uint32_t sh_swap_u32(
uint32_t value
)
{
register uint32_t swapped;
asm volatile (
asm volatile (
"swap.b %1,%0; "
"swap.w %0,%0; "
"swap.b %0,%0"
: "=r" (swapped)
"swap.b %0,%0"
: "=r" (swapped)
: "r" (value) );
return( swapped );
@@ -220,8 +220,8 @@ static inline uint16_t sh_swap_u16(
#define CPU_swap_u32( value ) sh_swap_u32( value )
#define CPU_swap_u16( value ) sh_swap_u16( value )
extern unsigned int sh_set_irq_priority(
unsigned int irq,
extern unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio );
#endif /* !ASM */
cpukit/score/cpu/sh/rtems/score/sh_io.h
+2 -2
View File
@@ -16,7 +16,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998-2001.
* On-Line Applications Research Corporation (OAR).
@@ -30,7 +30,7 @@
#ifndef _RTEMS_SCORE_SH_IO_H
#define _RTEMS_SCORE_SH_IO_H
#define readb(addr) (*(volatile unsigned char *) (addr))
#define readw(addr) (*(volatile unsigned short *) (addr))
#define readl(addr) (*(volatile unsigned int *) (addr))