mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-22 13:56:45 +08:00
2010-05-13 Joel Sherrill <joel.sherrill@oarcorp.com>
* Makefile.am, preinstall.am: Many files were duplicated across MIPS BSPs. Now those which were directly copied are shared. * liblnk/lnklib.S, liblnk/pmon.S, liblnk/regs.h, startup/idtmem.S: Removed.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,10 @@
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2010-05-13 Joel Sherrill <joel.sherrill@oarcorp.com>
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* Makefile.am, preinstall.am: Many files were duplicated across MIPS
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BSPs. Now those which were directly copied are shared.
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* liblnk/lnklib.S, liblnk/pmon.S, liblnk/regs.h, startup/idtmem.S:
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Removed.
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2010-05-13 Joel Sherrill <joel.sherrill@oarcorp.com>
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* configure.ac: rbtx4925, rbtx4938, and hurricane had very similar
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@@ -12,6 +12,7 @@ dist_project_lib_DATA = bsp_specs
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include_HEADERS = include/bsp.h
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include_HEADERS += ../../shared/include/tm27.h
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include_bsp_HEADERS = ../shared/liblnk/regs.h
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nodist_include_HEADERS = include/bspopts.h
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nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
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@@ -36,8 +37,8 @@ libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsppredriverhook.c \
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../../shared/bsplibc.c ../../shared/bsppost.c startup/bspstart.c \
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../../shared/bootcard.c ../../shared/sbrk.c \
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../../shared/gnatinstallhandler.c ../../shared/setvec.c \
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startup/inittlb.c \
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startup/idtmem.S startup/idttlb.S ../shared/irq/exception.S
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startup/inittlb.c ../shared/startup/idttlb.S \
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../shared/startup/idtmem.S ../shared/irq/exception.S
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# clock
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noinst_PROGRAMS += clock.rel
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@@ -49,7 +50,8 @@ clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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libbsp_a_SOURCES += console/console-io.c
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# liblnk
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libbsp_a_SOURCES += liblnk/lnklib.S liblnk/pmon.S liblnk/regs.h
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libbsp_a_SOURCES += ../shared/liblnk/lnklib.S ../shared/liblnk/pmon.S \
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../shared/liblnk/regs.h
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libbsp_a_LIBADD = \
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clock.rel \
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@@ -1,62 +0,0 @@
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/*
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* lnklib.S,v 1.4 1999/03/31 23:21:19 joel Exp
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*/
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#include <rtems/mips/iregdef.h>
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#include <rtems/mips/idtcpu.h>
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#define FRAME(name,frm_reg,offset,ret_reg) \
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.globl name; \
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.ent name; \
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name:; \
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.frame frm_reg,offset,ret_reg
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#define ENDFRAME(name) \
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.end name
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#define PROM_LINK(name,entry) \
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.globl name; \
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.ent name; \
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name: la $2,+entry; \
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j $2; \
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.end name
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#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
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#define PROM_RESET PROM_ENTRY(0)
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#define PROM_NOT_IMP PROM_ENTRY(1)
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#define PROM_RESTART PROM_ENTRY(2)
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#define PROM_REINIT PROM_ENTRY(3)
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#define PROM_GETCHAR PROM_ENTRY(11)
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#define PROM_PUTCHAR PROM_ENTRY(12)
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#define PROM_SHOWCHAR PROM_ENTRY(13)
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#define PROM_PRINTF PROM_ENTRY(16)
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#define PROM_RETURN PROM_ENTRY(17)
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#define PROM_RGETS PROM_ENTRY(25)
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#define PROM_FLUSHCACHE PROM_ENTRY(28)
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#define PROM_CLEARCACHE PROM_ENTRY(29)
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#define PROM_SETJMP PROM_ENTRY(30)
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#define PROM_LONGJMP PROM_ENTRY(31)
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.text
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PROM_LINK(idtsim_putchar, PROM_PUTCHAR)
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PROM_LINK(idtsim_getchar, PROM_GETCHAR)
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PROM_LINK(idtsim_showchar, PROM_SHOWCHAR)
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PROM_LINK(idtsim__exit, PROM_RETURN)
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PROM_LINK(idtsim_reinit, PROM_REINIT)
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PROM_LINK(idtsim_restart, PROM_RESTART)
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PROM_LINK(idtsim_reset, PROM_RESET)
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PROM_LINK(idtsim_promexit, PROM_RETURN)
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PROM_LINK(idtsim_setjmp, PROM_SETJMP)
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PROM_LINK(idtsim_longjmp, PROM_LONGJMP)
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FRAME(idtsim_init_sbrk,sp,0,ra)
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j ra
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ENDFRAME(idtsim_init_sbrk)
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FRAME(idtsim_init_file,sp,0,ra)
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j ra
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ENDFRAME(idtsim_init_file)
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@@ -1,180 +0,0 @@
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/*
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* pmon.S -- low-level entry points into PMON monitor.
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*
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* Copyright (c) 1996, 1997 Cygnus Support
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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#ifdef __mips16
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/* This file contains 32 bit assembly code. */
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.set nomips16
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#endif
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#if __mips < 3
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/* This machine does not support 64-bit operations. */
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#define ADDU addu
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#define SUBU subu
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#else
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/* This machine supports 64-bit operations. */
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#define ADDU daddu
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#define SUBU dsubu
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#endif
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#include "regs.h"
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.text
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.align 2
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#ifdef LSI
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#define PMON_VECTOR 0xbfc00200
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#else
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#define PMON_VECTOR 0xbfc00500
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#endif
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#ifndef __mips_eabi
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/* Provide named functions for entry into the monitor: */
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#define INDIRECT(name,index) \
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.globl name; \
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.ent name; \
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.set noreorder; \
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name: la $2,+(PMON_VECTOR+((index)*4)); \
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lw $2,0($2); \
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j $2; \
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nop; \
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.set reorder; \
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.end name
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#else
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#define INDIRECT(name,index) \
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.globl name; \
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.ent name; \
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.set noreorder; \
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name: la $2,+(PMON_VECTOR+((index)*4)); \
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lw $2,0($2); \
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SUBU sp,sp,0x40; \
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sd ra,0x38(sp); \
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sd fp,0x30(sp); \
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jal $2; \
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move fp,sp; \
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ld ra,0x38(sp); \
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ld fp,0x30(sp); \
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j ra; \
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ADDU sp,sp,0x40; \
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.set reorder; \
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.end name
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#endif
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/* The following magic numbers are for the slots into the PMON monitor */
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/* The first are used as the lo-level library run-time: */
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INDIRECT(mon_read,0)
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INDIRECT(mon_write,1)
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INDIRECT(mon_open,2)
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INDIRECT(mon_close,3)
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/* The following are useful monitor routines: */
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INDIRECT(mon_ioctl,4)
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INDIRECT(mon_printf,5)
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INDIRECT(mon_vsprintf,6)
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INDIRECT(mon_ttctl,7)
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INDIRECT(mon_cliexit,8)
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INDIRECT(mon_getenv,9)
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INDIRECT(mon_onintr,10)
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INDIRECT(mon_flush_cache,11)
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INDIRECT(mon_exception,12)
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INDIRECT(mon_fpgaconfig,21)
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#if 0
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/* The following routine is required by the "print()" function: */
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.globl pmon_outbyte
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.ent pmon_outbyte
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.set noreorder
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pmon_outbyte:
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subu sp,sp,0x20 /* allocate stack space for string */
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sd ra,0x18(sp) /* stack return address */
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sd fp,0x10(sp) /* stack frame-pointer */
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move fp,sp /* take a copy of the stack pointer */
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/* We leave so much space on the stack for the string (16
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characters), since the call to mon_printf seems to corrupt
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the 8bytes at offset 8 into the string/stack. */
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sb a0,0x00(sp) /* character to print */
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sb z0,0x01(sp) /* NUL terminator */
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jal mon_printf /* and output the string */
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move a0,sp /* take a copy of the string pointer {DELAY SLOT} */
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move sp,fp /* recover stack pointer */
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ld ra,0x18(sp) /* recover return address */
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ld fp,0x10(sp) /* recover frame-pointer */
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j ra /* return to the caller */
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addu sp,sp,0x20 /* dump the stack space {DELAY SLOT} */
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.set reorder
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.end pmon_outbyte
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/* The following routine is required by the "sbrk()" function: */
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.globl get_mem_info
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.ent get_mem_info
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.set noreorder
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get_mem_info:
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# in: a0 = pointer to 3 word structure
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# out: void
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subu sp,sp,0x18 /* create some stack space */
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sd ra,0x00(sp) /* stack return address */
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sd fp,0x08(sp) /* stack frame-pointer */
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sd a0,0x10(sp) /* stack structure pointer */
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move fp,sp /* take a copy of the stack pointer */
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# The monitor has already sized memory, but unfortunately we
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# do not have access to the data location containing the
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# memory size.
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jal __sizemem
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nop
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ld a0,0x10(sp) # recover structure pointer
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sw v0,0(a0) # amount of memory available
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# Deal with getting the cache size information:
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mfc0 a1, C0_CONFIG
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nop
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nop
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andi a2,a1,0x7 << 9 # bits 11..9 for instruction cache size
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sll a2,a2,12 - 8
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sw a2,4(a0)
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andi a2,a1,0x7 << 6 # bits 8..6 for data cache size
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sll a2,a2,12 - 5
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sw a2,8(a0) # data cache size
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#
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move sp,fp /* recover stack pointer */
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ld ra,0x00(sp) /* recover return address */
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ld fp,0x08(sp) /* recover frame-pointer */
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j ra /* return to the caller */
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addu sp,sp,0x18 /* restore stack pointer {DELAY SLOT} */
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.set reorder
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.end get_mem_info
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#ifdef LSI
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# For the LSI MiniRISC board, we can safely assume that we have
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# at least one megabyte of RAM.
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.globl __sizemem
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.ent __sizemem
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__sizemem:
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li v0,0x100000
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j ra
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.end __sizemem
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#else
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#endif
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#endif
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/* EOF pmon.S */
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@@ -1,137 +0,0 @@
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/*
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* regs.S -- standard MIPS register names.
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*
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* Copyright (c) 1995 Cygnus Support
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*
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||||
* The authors hereby grant permission to use, copy, modify, distribute,
|
||||
* and license this software and its documentation for any purpose, provided
|
||||
* that existing copyright notices are retained in all copies and that this
|
||||
* notice is included verbatim in any distributions. No written agreement,
|
||||
* license, or royalty fee is required for any of the authorized uses.
|
||||
* Modifications to this software may be copyrighted by their authors
|
||||
* and need not follow the licensing terms described here, provided that
|
||||
* the new terms are clearly indicated on the first page of each file where
|
||||
* they apply.
|
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*/
|
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/* Standard MIPS register names: */
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#define zero $0
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#define z0 $0
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#define v0 $2
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#define v1 $3
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#define a0 $4
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#define a1 $5
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#define a2 $6
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#define a3 $7
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#define t0 $8
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#define t1 $9
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#define s0 $16
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#define s1 $17
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#define s2 $18
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#define s3 $19
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#define s4 $20
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#define s5 $21
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#define s6 $22
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#define s7 $23
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#define t8 $24
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#define t9 $25
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#define k0 $26 /* kernel private register 0 */
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#define k1 $27 /* kernel private register 1 */
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#define gp $28 /* global data pointer */
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#define sp $29 /* stack-pointer */
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#define fp $30 /* frame-pointer */
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#define ra $31 /* return address */
|
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#define pc $pc /* pc, used on mips16 */
|
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|
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#define fp0 $f0
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#define fp1 $f1
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|
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/* Useful memory constants: */
|
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#define K0BASE 0x80000000
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#ifndef __mips64
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#define K1BASE 0xA0000000
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#else
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#define K1BASE 0xFFFFFFFFA0000000LL
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#endif
|
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|
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#define PHYS_TO_K1(a) ((unsigned)(a) | K1BASE)
|
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|
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/* Standard Co-Processor 0 register numbers: */
|
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#define C0_COUNT $9 /* Count Register */
|
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#define C0_SR $12 /* Status Register */
|
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#define C0_CAUSE $13 /* last exception description */
|
||||
#define C0_EPC $14 /* Exception error address */
|
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#define C0_CONFIG $16 /* CPU configuration */
|
||||
|
||||
/* Standard Status Register bitmasks: */
|
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#define SR_CU1 0x20000000 /* Mark CP1 as usable */
|
||||
#define SR_FR 0x04000000 /* Enable MIPS III FP registers */
|
||||
#define SR_BEV 0x00400000 /* Controls location of exception vectors */
|
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#define SR_PE 0x00100000 /* Mark soft reset (clear parity error) */
|
||||
|
||||
#define SR_KX 0x00000080 /* Kernel extended addressing enabled */
|
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#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */
|
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#define SR_UX 0x00000020 /* User extended addressing enabled */
|
||||
|
||||
/* Standard (R4000) cache operations. Taken from "MIPS R4000
|
||||
Microprocessor User's Manual" 2nd edition: */
|
||||
|
||||
#define CACHE_I (0) /* primary instruction */
|
||||
#define CACHE_D (1) /* primary data */
|
||||
#define CACHE_SI (2) /* secondary instruction */
|
||||
#define CACHE_SD (3) /* secondary data (or combined instruction/data) */
|
||||
|
||||
#define INDEX_INVALIDATE (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
|
||||
#define INDEX_LOAD_TAG (1)
|
||||
#define INDEX_STORE_TAG (2)
|
||||
#define CREATE_DIRTY_EXCLUSIVE (3) /* CACHE_D and CACHE_SD only */
|
||||
#define HIT_INVALIDATE (4)
|
||||
#define CACHE_FILL (5) /* CACHE_I only */
|
||||
#define HIT_WRITEBACK_INVALIDATE (5) /* CACHE_D and CACHE_SD only */
|
||||
#define HIT_WRITEBACK (6) /* CACHE_I, CACHE_D and CACHE_SD only */
|
||||
#define HIT_SET_VIRTUAL (7) /* CACHE_SI and CACHE_SD only */
|
||||
|
||||
#define BUILD_CACHE_OP(o,c) (((o) << 2) | (c))
|
||||
|
||||
/* Individual cache operations: */
|
||||
#define INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
|
||||
#define INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
|
||||
#define INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
|
||||
#define INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
|
||||
|
||||
#define INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
|
||||
#define INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
|
||||
#define INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
|
||||
#define INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
|
||||
|
||||
#define INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
|
||||
#define INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
|
||||
#define INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
|
||||
#define INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
|
||||
|
||||
#define CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
|
||||
#define CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
|
||||
|
||||
#define HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
|
||||
#define HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
|
||||
#define HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
|
||||
#define HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
|
||||
|
||||
#define CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
|
||||
#define HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
|
||||
#define HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
|
||||
|
||||
#define HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
|
||||
#define HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
|
||||
#define HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
|
||||
|
||||
#define HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
|
||||
#define HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
|
||||
|
||||
/*> EOF regs.S <*/
|
||||
@@ -45,6 +45,10 @@ $(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirs
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/regs.h: ../shared/liblnk/regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/regs.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/regs.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user