mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-02 00:49:46 +08:00
beagle: pwm polishing
. added a README to pwm . added select_pwmss() to select pwmss-generic registers, as opposed to PWM-specific registers . added pwmss_clock_en_status(), beagle_pwmss_is_running() and pwmss_tb_clock_check() . other API improvements . style improvements
This commit is contained in:
Punit Vara
Ben Gras
@@ -3,11 +3,11 @@
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*
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* @ingroup arm_beagle
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*
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* @brief BeagleBone Black BSP definitions.
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* @brief BeagleBone Black PWM support definitions.
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*/
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/**
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* Copyright (c) 2016 Punit Vara <punitvara at gmail.com>
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* Copyright (c) 2016 Punit Vara <punitvara@gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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@@ -31,43 +31,53 @@ extern "C" {
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#define BBB_CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4))
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#define BBB_CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4))
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#define BBB_PWMSS_COUNT 3
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#define BBB_PWMSS0 0
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#define BBB_PWMSS1 1
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#define BBB_PWMSS2 2
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/**
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* @brief The set of possible PWM subsystem module
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*
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* Enumerated type to define various instance of pwm module.
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*/
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typedef enum{
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BBB_PWMSS0 = 0,
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BBB_PWMSS1,
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BBB_PWMSS2,
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BBB_PWMSS_COUNT
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}BBB_PWMSS;
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#define BBB_P8_13_2B 3
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#define BBB_P8_19_2A 4
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#define BBB_P8_45_2A 5
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#define BBB_P8_46_2B 6
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#define BBB_P8_34_1B 7
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#define BBB_P8_36_1A 8
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#define BBB_P9_14_1A 9
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#define BBB_P9_16_1B 10
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#define BBB_P9_21_0B 11
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#define BBB_P9_22_0A 12
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#define BBB_P9_29_0B 13
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#define BBB_P9_31_0A 14
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typedef enum{
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BBB_P8_13_2B = 3,
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BBB_P8_19_2A,
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BBB_P8_45_2A,
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BBB_P8_46_2B,
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BBB_P8_34_1B,
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BBB_P8_36_1A,
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BBB_P9_14_1A,
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BBB_P9_16_1B,
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BBB_P9_21_0B,
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BBB_P9_22_0A,
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BBB_P9_29_0B,
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BBB_P9_31_0A
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}bbb_pwm_pin_t;
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#define BBB_MUX0 0
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#define BBB_MUX1 1
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#define BBB_MUX2 2
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#define BBB_MUX3 3
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#define BBB_MUX4 4
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#define BBB_MUX5 5
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#define BBB_MUX6 6
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#define BBB_MUX7 7
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#define BBB_EPWM1 1
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#define BBB_EPWM2 2
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#define BBB_EPWM0 0
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#define BBB_P8_13_MUX_PWM 4
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#define BBB_P8_19_MUX_PWM 4
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#define BBB_P8_45_MUX_PWM 3
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#define BBB_P8_46_MUX_PWM 3
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#define BBB_P8_34_MUX_PWM 2
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#define BBB_P8_36_MUX_PWM 2
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#define BBB_P9_14_MUX_PWM 6
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#define BBB_P9_16_MUX_PWM 6
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#define BBB_P9_21_MUX_PWM 3
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#define BBB_P9_22_MUX_PWM 3
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#define BBB_P9_29_MUX_PWM 1
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#define BBB_P9_31_MUX_PWM 1
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#define BBB_PWM_FREQ_THRESHOLD 0.5f
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/**
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* @brief BeagleBone Black PWM API.
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*/
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/**
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* @brief This function intilize clock and pinmuxing for pwm sub system.
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* @brief This function intilizes clock for pwm sub system.
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*
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* @param PWMSS_ID It is the instance number of EPWM of pwm sub system.
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*
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@@ -75,20 +85,20 @@ extern "C" {
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* @return false if not successful
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*
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**/
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bool beagle_pwm_init(uint32_t pwmss_id);
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bool beagle_pwm_init(BBB_PWMSS pwmss_id);
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/* PWMSS setting
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* set pulse argument of epwm module
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*
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* @param pwm_id : EPWMSS number , 0~2
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* @param pwm_freq : frequency to be generated
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* @param dutyA : Duty Cycle in ePWM A
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* @param dutyB : Duty Cycle in ePWM B
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* @param dutyA : Duty Cycle(in percentage) in PWM channel A
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* @param dutyB : Duty Cycle(in percentage) in PWM channel B
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*
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* @return : 1 for success
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* @return : 0 for failed
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*
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* @example : PWMSS_Setting(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 ,
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* @example : beagle_pwm_configure(0 , 50.0f , 50.0f , 25.0f); // Generate 50HZ pwm in PWM0 ,
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* // duty cycle is 50% for ePWM0A , 25% for ePWM0B
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*
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* @Note :
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@@ -105,12 +115,12 @@ bool beagle_pwm_init(uint32_t pwmss_id);
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* Divisor = CLKDIV * HSPCLKDIV
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* 1 TBPRD : 10 ns (default)
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* 65535 TBPRD : 655350 ns
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* 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cyclens
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* 65535 TBPRD : 655350 * Divisor ns = X TBPRD : Cycle
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*
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* accrooding to that , we must find a Divisor value , let X nearest 65535 .
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* so , Divisor must Nearest Cyclens/655350
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* so , Divisor must Nearest Cycle/655350
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*/
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int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB);
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int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b);
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/**
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* @brief This API enables the particular PWM module.
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@@ -121,10 +131,10 @@ int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dut
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* @return false if fail
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*
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**/
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bool beagle_ehrpwm_enable(uint32_t pwmid);
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bool beagle_pwm_enable(BBB_PWMSS pwmid);
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/**
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* @brief This API disables the HR sub-module.
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* @brief This API disables the particular PWM module.
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*
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* @param pwmid It is the instance number of EPWM of pwm sub system.
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*
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@@ -132,10 +142,10 @@ bool beagle_ehrpwm_enable(uint32_t pwmid);
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* @return false if fail
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*
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**/
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bool beagle_ehrpwm_disable(uint32_t pwmid);
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bool beagle_pwm_disable(BBB_PWMSS pwmid);
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/**
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* @brief This function Enables pinmuxing for PWM module.
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* @brief This function enables pinmuxing for PWM module.
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*
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* @param pin_no It is individual pin at which freuqency need to be generated.
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* It should be according to pwm sub system.
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@@ -146,7 +156,20 @@ bool beagle_ehrpwm_disable(uint32_t pwmid);
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* @return false if fail
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*
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**/
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bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id);
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bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id);
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/**
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* @brief This function determines whether PWMSS-wide clocks enabled or not.
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*
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* @param pwmss_id It is the instance number of PWMSS which clocks need to be
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* checked.
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*
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* @return true if successful
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* @return false if fail
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*
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**/
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bool beagle_pwmss_is_running(unsigned int pwmss_id);
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#ifdef __cplusplus
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}
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@@ -118,6 +118,10 @@ $(PROJECT_INCLUDE)/bsp/bbb-gpio.h: include/bbb-gpio.h $(PROJECT_INCLUDE)/bsp/$(d
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bbb-gpio.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bbb-gpio.h
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$(PROJECT_INCLUDE)/bsp/bbb-pwm.h: include/bbb-pwm.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bbb-pwm.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bbb-pwm.h
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$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
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@@ -0,0 +1,197 @@
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Pulse Width Modulation subsystem includes EPWM, ECAP , EQEP. There are
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different instances available for each one. For PWM there are three
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different individual EPWM module 0 , 1 and 2. So wherever pwmss word is
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used that affects whole PWM sub system such as EPWM, ECAP and EQEP. This code
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has only implementation Non high resolution PWM module. APIs for high
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resolution PWM has been yet to develop.
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For Each EPWM instance, has two PWM channels, e.g. EPWM0 has two channel
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EPWM0A and EPWM0B. If you configure two PWM outputs(e.g. EPWM0A , EPWM0B)
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in the same device, then they *must* be configured with the same frequency.
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Changing frequency on one channel (e.g EPWMxA) will automatically change
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frequency on another channel(e.g. EPWMxB). However, it is possible to set
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different pulse-width/duty cycle to different channel at a time. So always
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set the frequency first and then pulse-width/duty cycle.
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For more you can refer :
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http://www.ofitselfso.com/BBBCSIO/Source/PWMPortEnum.cs.html
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Pulse Width Modulation uses the system frequency of Beagle Bone Black.
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System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT(By Default)
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SYCLKOUT = 100 MHz
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Please visit following link to check why SYSCLKDIV = 100MHz:
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https://groups.google.com/forum/#!topic/beagleboard/Ed2J9Txe_E4
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(Refer Technical Reference Manual (TRM) Table 15-41 as well)
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To generate different frequencies with the help of PWM module , SYSCLKOUT
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need to be scaled down, which will act as TBCLK and TBCLK will be base clock
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for the pwm subsystem.
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TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV)
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|----------------|
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| clock |
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SYSCLKOUT---> | |---> TBCLK
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| prescale |
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|----------------|
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^ ^
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| |
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TBCTL[CLKDIV]----- ------TBCTL[HSPCLKDIV]
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CLKDIV and HSPCLKDIV bits are part of the TBCTL register (Refer TRM).
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CLKDIV - These bits determine part of the time-base clock prescale value.
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Please use the following values of CLKDIV to scale down sysclk respectively.
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0h (R/W) = /1
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1h (R/W) = /2
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2h (R/W) = /4
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3h (R/W) = /8
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4h (R/W) = /16
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5h (R/W) = /32
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6h (R/W) = /64
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7h (R/W) = /128
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These bits determine part of the time-base clock prescale value.
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Please use following value of HSPCLKDIV to scale down sysclk respectively
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0h (R/W) = /1
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1h (R/W) = /2
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2h (R/W) = /4
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3h (R/W) = /6
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4h (R/W) = /8
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5h (R/W) = /10
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6h (R/W) = /12
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7h (R/W) = /14
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For example, if you set CLKDIV = 3h and HSPCLKDIV= 2h Then
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SYSCLKOUT will be divided by (1/8)(1/4). It means SYSCLKOUT/32
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How to generate frequency ?
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freq = 1/Period
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TBPRD register is responsible to generate the frequency. These bits determine
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the period of the time-base counter.
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By default TBCLK = SYSCLKOUT = 100 MHz
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Here by default period is 1/100MHz = 10 nsec
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Following example shows value to be loaded into TBPRD
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e.g. TBPRD = 1 = 1 count
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count x Period = 1 x 1ns = 1ns
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freq = 1/Period = 1 / 1ns = 100 MHz
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For duty cycle CMPA and CMPB are the responsible registers.
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To generate single with 50% Duty cycle & 100MHz freq.
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CMPA = count x Duty Cycle
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= TBPRD x Duty Cycle
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= 1 x 50/100
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= 0.2
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The value in the active CMPA register is continuously compared to
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the time-base counter (TBCNT). When the values are equal, the
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counter-compare module generates a "time-base counter equal to
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counter compare A" event. This event is sent to the action-qualifier
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where it is qualified and converted it into one or more actions.
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These actions can be applied to either the EPWMxA or the
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EPWMxB output depending on the configuration of the AQCTLA and
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AQCTLB registers.
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List of pins for that can be used for different PWM instance :
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------------------------------------------------
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| EPWM2 | EPWM1 | EPWM0 |
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------------------------------------------------
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| BBB_P8_13_2B | BBB_P8_34_1B | BBB_P9_21_0B |
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| BBB_P8_19_2A | BBB_P8_36_1A | BBB_P9_22_0A |
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| BBB_P8_45_2A | BBB_P9_14_1A | BBB_P9_29_0B |
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| BBB_P8_46_2B | BBB_P9_16_1B | BBB_P9_31_0A |
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------------------------------------------------
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BBB_P8_13_2B represents P8 Header , pin number 13 , 2nd PWM instance and B channel.
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Following sample program can be used to generate 7 Hz frequency.
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/test.h>
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#include <bsp.h>
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#include <bsp/gpio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <bsp/bbb-pwm.h>
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const char rtems_test_name[] = "Testing PWM driver";
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rtems_printer rtems_test_printer;
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static void inline delay_sec(int sec)
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{
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rtems_task_wake_after(sec*rtems_clock_get_ticks_per_second());
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}
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rtems_task Init(rtems_task_argument argument);
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rtems_task Init(
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rtems_task_argument ignored
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)
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{
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rtems_test_begin();
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printf("Starting PWM Testing");
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/*Initialize GPIO pins in BBB*/
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rtems_gpio_initialize();
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/* Set P9 Header , 21 Pin number , PWM B channel and 0 PWM instance to generate frequency*/
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beagle_epwm_pinmux_setup(BBB_P9_21_0B,BBB_PWMSS0);
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/** Initialize clock for PWM sub system
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* Turn on time base clock for PWM o instance
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*/
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beagle_pwm_init(BBB_PWMSS0);
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float PWM_HZ = 7.0f ; /* 7 Hz */
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float duty_A = 20.0f ; /* 20% Duty cycle for PWM 0_A output */
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const float duty_B = 50.0f ; /* 50% Duty cycle for PWM 0_B output*/
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/*Note: Always check whether pwmss clocks are enabled or not before configuring PWM*/
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bool is_running = beagle_pwmss_is_running(BBB_PWMSS2);
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if(is_running) {
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/*To analyse the two different duty cycle Output should be observed at P8_45 and P8_46 pin number */
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beagle_pwm_configure(BBB_PWMSS0, PWM_HZ ,duty_A , duty_B);
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printf("PWM enable for 10s ....\n");
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/*Set Up counter and enable pwm module */
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beagle_pwm_enable(BBB_PWMSS0);
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delay_sec(10);
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/*freeze the counter and disable pwm module*/
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beagle_epwm_disable(BBB_PWMSS0);
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}
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}
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/* NOTICE: the clock driver is enabled */
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#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
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#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
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#define CONFIGURE_MAXIMUM_TASKS 1
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#define CONFIGURE_USE_DEVFS_AS_BASE_FILESYSTEM
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#define CONFIGURE_MAXIMUM_SEMAPHORES 1
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#define CONFIGURE_RTEMS_INIT_TASKS_TABLE
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#define CONFIGURE_EXTRA_TASK_STACKS (2 * RTEMS_MINIMUM_STACK_SIZE)
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#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION
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#define CONFIGURE_INIT
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#include <rtems/confdefs.h>
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