mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-23 05:56:18 +08:00
Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>.
As part of this effort, the mpc750 libcpu code is now shared with the ppc6xx.
This commit is contained in:
Joel Sherrill
@@ -1,90 +0,0 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
@SET_MAKE@
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||||
srcdir = @srcdir@
|
||||
top_srcdir = @top_srcdir@
|
||||
top_builddir = ../..
|
||||
subdir = powerpc/other_cpu
|
||||
|
||||
RTEMS_ROOT = @RTEMS_ROOT@
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||||
PROJECT_ROOT = @PROJECT_ROOT@
|
||||
|
||||
VPATH = @srcdir@
|
||||
|
||||
RELS = ../$(ARCH)/rtems-cpu.rel
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||||
|
||||
# C source names, if any, go here -- minus the .c
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C_PIECES = cpu ppccache
|
||||
C_FILES = $(C_PIECES:%=%.c)
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C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
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||||
|
||||
ROOT_H_PIECES =
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ROOT_H_FILES = $(ROOT_H_PIECES:%=$(srcdir)/%)
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RTEMS_SCORE_H_PIECES = cpu.h
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RTEMS_SCORE_H_FILES = $(RTEMS_SCORE_H_PIECES:%=$(srcdir)/%)
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H_PIECES = $(ROOT_H_PIECES) $(RTEMS_SCORE_H_PIECES)
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H_FILES = $(H_PIECES%=$(srcdir)/%)
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I_PIECES = c_isr
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||||
I_FILES = $(I_PIECES:%=$(srcdir)/%.inl)
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||||
# Assembly source names, if any, go here -- minus the .S
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S_PIECES = cpu_asm rtems # irq_stub
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S_FILES = $(S_PIECES:%=%.S)
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S_O_FILES = $(S_FILES:%.S=${ARCH}/%.o)
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|
||||
SRCS = $(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) $(EXTERNAL_H_FILES) \
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$(I_FILES)
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OBJS = $(C_O_FILES) $(CC_O_FILES) $(S_O_FILES)
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|
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include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
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include $(RTEMS_ROOT)/make/leaf.cfg
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||||
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||||
INSTALL_CHANGE = @INSTALL_CHANGE@
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mkinstalldirs = $(SHELL) $(top_srcdir)/@RTEMS_TOPdir@/mkinstalldirs
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||||
|
||||
INSTALLDIRS = $(PROJECT_INCLUDE)/rtems/score $(PROJECT_INCLUDE)
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$(INSTALLDIRS):
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@$(mkinstalldirs) $(INSTALLDIRS)
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||||
#
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# (OPTIONAL) Add local stuff here using +=
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#
|
||||
|
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DEFINES +=
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CPPFLAGS +=
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CFLAGS += $(CFLAGS_OS_V)
|
||||
|
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LD_PATHS +=
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LD_LIBS +=
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LDFLAGS +=
|
||||
|
||||
#
|
||||
# Add your list of files to delete here. The config files
|
||||
# already know how to delete some stuff, so you may want
|
||||
# to just run 'make clean' first to see what gets missed.
|
||||
# 'make clobber' already includes 'make clean'
|
||||
#
|
||||
|
||||
CLEAN_ADDITIONS +=
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||||
CLOBBER_ADDITIONS +=
|
||||
|
||||
../$(ARCH)/rtems-cpu.rel: $(OBJS)
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||||
test -d ../$(ARCH) || mkdir ../$(ARCH)
|
||||
$(make-rel)
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||||
|
||||
all: ${ARCH} $(SRCS) preinstall $(OBJS) $(RELS)
|
||||
|
||||
# Install the program(s), appending _g or _p as appropriate.
|
||||
# for include files, just use $(INSTALL_CHANGE)
|
||||
install: all
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||||
|
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preinstall: ${ARCH}
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@$(INSTALL_CHANGE) -m 644 $(RTEMS_SCORE_H_FILES) $(I_FILES) $(PROJECT_INCLUDE)/rtems/score
|
||||
@$(INSTALL_CHANGE) -m 644 $(ROOT_H_FILES) $(PROJECT_INCLUDE)
|
||||
|
||||
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
|
||||
cd $(top_builddir) \
|
||||
&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
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||||
@@ -1,78 +0,0 @@
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||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
There are various issues regarding this port:
|
||||
|
||||
|
||||
|
||||
1) Legal
|
||||
|
||||
This port is written by Andrew Bray <andy@i-cubed.co.uk>, and
|
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is copyright 1995 i-cubed ltd.
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||||
|
||||
This port was later updated by Joel Sherrill <joel@OARcorp.com>
|
||||
to test the support for the PPC603, PPC603e, and PPC604. This
|
||||
was tested on the PowerPC simulator PSIM and a VMEbus single board
|
||||
computer.
|
||||
|
||||
2) CPU support.
|
||||
|
||||
This release fully supports the PPC403GA, PPC403GB, PPC603, PPC603e,
|
||||
and PPC604 processors. A good faith attempt has been made to include
|
||||
support other models based upon available documentation.
|
||||
|
||||
This port was originally written and tested on the PPC403GA (using
|
||||
software floating point). Current ports are tested on 60x CPUs
|
||||
using the PowerPC simulator PSIM.
|
||||
|
||||
Andrew Bray received assistance during the initial porting effort
|
||||
from IBM and Blue Micro and we would like to gratefully acknowledge
|
||||
that help.
|
||||
|
||||
The support for the PPC602 processor is incomplete as only sketchy
|
||||
data is currently available. Perhaps this model has been dropped.
|
||||
|
||||
|
||||
|
||||
3) Application Binary INterface
|
||||
|
||||
In the context of RTEMS, the ABI is of interest for the following
|
||||
aspects:
|
||||
|
||||
a) Register usage. Which registers are used to provide static variable
|
||||
linkage, stack pointer etc.
|
||||
|
||||
b) Function calling convention. How parameters are passed, how function
|
||||
variables should be invoked, how values are returned, etc.
|
||||
|
||||
c) Stack frame layout.
|
||||
|
||||
I am aware of a number of ABIs for the PowerPC:
|
||||
|
||||
a) The PowerOpen ABI. This is the original Power ABI used on the RS/6000.
|
||||
This is the only ABI supported by versions of GCC before 2.7.0.
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||||
|
||||
b) The SVR4 ABI. This is the ABI defined by SunSoft for the Solaris port
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to the PowerPC.
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||||
|
||||
c) The Embedded ABI. This is an embedded ABI for PowerPC use, which has no
|
||||
operating system interface defined. It is promoted by SunSoft, Motorola,
|
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and Cygnus Support. Cygnus are porting the GNU toolchain to this ABI.
|
||||
|
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d) GCC 2.7.0. This compiler is partway along the road to supporting the EABI,
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but is currently halfway in between.
|
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|
||||
This port was built and tested using the PowerOpen ABI, with the following
|
||||
caveat: we used an ELF assembler and linker. So some attention may be
|
||||
required on the assembler files to get them through a traditional (XCOFF)
|
||||
PowerOpen assembler.
|
||||
|
||||
This port contains support for the other ABIs, but this may prove to be
|
||||
incomplete as it is untested.
|
||||
|
||||
The RTEMS PowerPC port supports EABI as the primary ABI. The powerpc-rtems
|
||||
GNU toolset configuration is EABI and .
|
||||
|
||||
Andrew Bray, 4 December 1995
|
||||
Joel Sherrill, 16 July 1997
|
||||
@@ -1,8 +0,0 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
Todo list:
|
||||
|
||||
Maybe decode external interrupts like the HPPA does.
|
||||
See c/src/lib/libcpu/powerpc/ppc403/ictrl/* for implementation on ppc403
|
||||
@@ -1,4 +0,0 @@
|
||||
RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void )
|
||||
{
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||||
return (_ISR_Nest_level != 0);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,268 +0,0 @@
|
||||
/*
|
||||
* This file contains the interrupt handler assembly code for the PowerPC
|
||||
* implementation of RTEMS. It is #included from cpu_asm.s.
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
/* void __ISR_Handler()
|
||||
*
|
||||
* This routine provides the RTEMS interrupt management.
|
||||
* The vector number is in r0. R0 has already been stacked.
|
||||
*
|
||||
*/
|
||||
PUBLIC_VAR (_CPU_IRQ_info )
|
||||
|
||||
/* Finish off the interrupt frame */
|
||||
stw r2, IP_2(r1)
|
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stw r3, IP_3(r1)
|
||||
stw r4, IP_4(r1)
|
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stw r5, IP_5(r1)
|
||||
stw r6, IP_6(r1)
|
||||
stw r7, IP_7(r1)
|
||||
stw r8, IP_8(r1)
|
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stw r9, IP_9(r1)
|
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stw r10, IP_10(r1)
|
||||
stw r11, IP_11(r1)
|
||||
stw r12, IP_12(r1)
|
||||
stw r13, IP_13(r1)
|
||||
stmw r28, IP_28(r1)
|
||||
mfcr r5
|
||||
mfctr r6
|
||||
mfxer r7
|
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mflr r8
|
||||
MFPC (r9)
|
||||
MFMSR (r10)
|
||||
/* Establish addressing */
|
||||
#if (PPC_USE_SPRG)
|
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mfspr r11, sprg3
|
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#else
|
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lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
#endif
|
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dcbt r0, r11
|
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stw r5, IP_CR(r1)
|
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stw r6, IP_CTR(r1)
|
||||
stw r7, IP_XER(r1)
|
||||
stw r8, IP_LR(r1)
|
||||
stw r9, IP_PC(r1)
|
||||
stw r10, IP_MSR(r1)
|
||||
|
||||
lwz r30, Vector_table(r11)
|
||||
slwi r4,r0,2
|
||||
lwz r28, Nest_level(r11)
|
||||
add r4, r4, r30
|
||||
|
||||
lwz r30, 0(r28)
|
||||
mr r3, r0
|
||||
lwz r31, Stack(r11)
|
||||
/*
|
||||
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
|
||||
* if ( _ISR_Nest_level == 0 )
|
||||
* switch to software interrupt stack
|
||||
* #endif
|
||||
*/
|
||||
/* Switch stacks, here we must prevent ALL interrupts */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfmsr r5
|
||||
mfspr r6, sprg2
|
||||
#else
|
||||
lwz r6,msr_initial(r11)
|
||||
lis r5,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
|
||||
and r6,r6,r5
|
||||
mfmsr r5
|
||||
#endif
|
||||
mtmsr r6
|
||||
cmpwi r30, 0
|
||||
lwz r29, Disable_level(r11)
|
||||
subf r31,r1,r31
|
||||
bne LABEL (nested)
|
||||
stwux r1,r1,r31
|
||||
LABEL (nested):
|
||||
/*
|
||||
* _ISR_Nest_level++;
|
||||
*/
|
||||
lwz r31, 0(r29)
|
||||
addi r30,r30,1
|
||||
stw r30,0(r28)
|
||||
/* From here on out, interrupts can be re-enabled. RTEMS
|
||||
* convention says not.
|
||||
*/
|
||||
lwz r4,0(r4)
|
||||
/*
|
||||
* _Thread_Dispatch_disable_level++;
|
||||
*/
|
||||
addi r31,r31,1
|
||||
stw r31, 0(r29)
|
||||
/* SCE 980217
|
||||
*
|
||||
* We need address translation ON when we call our ISR routine
|
||||
|
||||
mtmsr r5
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* (*_ISR_Vector_table[ vector ])( vector );
|
||||
*/
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
lwz r6,0(r4)
|
||||
lwz r2,4(r4)
|
||||
mtlr r6
|
||||
lwz r11,8(r4)
|
||||
#endif
|
||||
#if (PPC_ABI == PPC_ABI_GCC27)
|
||||
lwz r2, Default_r2(r11)
|
||||
mtlr r4
|
||||
#lwz r2, 0(r2)
|
||||
#endif
|
||||
#if (PPC_ABI == PPC_ABI_SVR4 || PPC_ABI == PPC_ABI_EABI)
|
||||
mtlr r4
|
||||
lwz r2, Default_r2(r11)
|
||||
lwz r13, Default_r13(r11)
|
||||
#lwz r2, 0(r2)
|
||||
#lwz r13, 0(r13)
|
||||
#endif
|
||||
mr r4,r1
|
||||
blrl
|
||||
/* NOP marker for debuggers */
|
||||
or r6,r6,r6
|
||||
|
||||
/* We must re-disable the interrupts */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfspr r11, sprg3
|
||||
mfspr r0, sprg2
|
||||
#else
|
||||
lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
lwz r0,msr_initial(r11)
|
||||
lis r30,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r30,r30,~PPC_MSR_DISABLE_MASK@l
|
||||
and r0,r0,r30
|
||||
#endif
|
||||
mtmsr r0
|
||||
lwz r30, 0(r28)
|
||||
lwz r31, 0(r29)
|
||||
|
||||
/*
|
||||
* if (--Thread_Dispatch_disable,--_ISR_Nest_level)
|
||||
* goto easy_exit;
|
||||
*/
|
||||
addi r30, r30, -1
|
||||
cmpwi r30, 0
|
||||
addi r31, r31, -1
|
||||
stw r30, 0(r28)
|
||||
stw r31, 0(r29)
|
||||
bne LABEL (easy_exit)
|
||||
cmpwi r31, 0
|
||||
|
||||
lwz r30, Switch_necessary(r11)
|
||||
|
||||
/*
|
||||
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
|
||||
* restore stack
|
||||
* #endif
|
||||
*/
|
||||
lwz r1,0(r1)
|
||||
bne LABEL (easy_exit)
|
||||
lwz r30, 0(r30)
|
||||
lwz r31, Signal(r11)
|
||||
|
||||
/*
|
||||
* if ( _Context_Switch_necessary )
|
||||
* goto switch
|
||||
*/
|
||||
cmpwi r30, 0
|
||||
lwz r28, 0(r31)
|
||||
li r6,0
|
||||
bne LABEL (switch)
|
||||
/*
|
||||
* if ( !_ISR_Signals_to_thread_executing )
|
||||
* goto easy_exit
|
||||
* _ISR_Signals_to_thread_executing = 0;
|
||||
*/
|
||||
cmpwi r28, 0
|
||||
beq LABEL (easy_exit)
|
||||
|
||||
/*
|
||||
* switch:
|
||||
* call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
|
||||
*/
|
||||
LABEL (switch):
|
||||
stw r6, 0(r31)
|
||||
/* Re-enable interrupts */
|
||||
lwz r0, IP_MSR(r1)
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
lwz r2, Dispatch_r2(r11)
|
||||
#else
|
||||
/* R2 and R13 still hold their values from the last call */
|
||||
#endif
|
||||
mtmsr r0
|
||||
bl SYM (_Thread_Dispatch)
|
||||
/* NOP marker for debuggers */
|
||||
or r6,r6,r6
|
||||
/*
|
||||
* prepare to get out of interrupt
|
||||
*/
|
||||
/* Re-disable IRQs */
|
||||
#if (PPC_USE_SPRG)
|
||||
mfspr r0, sprg2
|
||||
#else
|
||||
lis r11,_CPU_IRQ_info@ha
|
||||
addi r11,r11,_CPU_IRQ_info@l
|
||||
lwz r0,msr_initial(r11)
|
||||
lis r5,~PPC_MSR_DISABLE_MASK@ha
|
||||
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
|
||||
and r0,r0,r5
|
||||
#endif
|
||||
mtmsr r0
|
||||
|
||||
/*
|
||||
* easy_exit:
|
||||
* prepare to get out of interrupt
|
||||
* return from interrupt
|
||||
*/
|
||||
LABEL (easy_exit):
|
||||
lwz r5, IP_CR(r1)
|
||||
lwz r6, IP_CTR(r1)
|
||||
lwz r7, IP_XER(r1)
|
||||
lwz r8, IP_LR(r1)
|
||||
lwz r9, IP_PC(r1)
|
||||
lwz r10, IP_MSR(r1)
|
||||
mtcrf 255,r5
|
||||
mtctr r6
|
||||
mtxer r7
|
||||
mtlr r8
|
||||
MTPC (r9)
|
||||
MTMSR (r10)
|
||||
lwz r0, IP_0(r1)
|
||||
lwz r2, IP_2(r1)
|
||||
lwz r3, IP_3(r1)
|
||||
lwz r4, IP_4(r1)
|
||||
lwz r5, IP_5(r1)
|
||||
lwz r6, IP_6(r1)
|
||||
lwz r7, IP_7(r1)
|
||||
lwz r8, IP_8(r1)
|
||||
lwz r9, IP_9(r1)
|
||||
lwz r10, IP_10(r1)
|
||||
lwz r11, IP_11(r1)
|
||||
lwz r12, IP_12(r1)
|
||||
lwz r13, IP_13(r1)
|
||||
lmw r28, IP_28(r1)
|
||||
lwz r1, 0(r1)
|
||||
@@ -1,61 +0,0 @@
|
||||
/*
|
||||
* PowerPC Cache enable routines
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems/system.h>
|
||||
|
||||
#define PPC_Get_HID0( _value ) \
|
||||
do { \
|
||||
_value = 0; /* to avoid warnings */ \
|
||||
asm volatile( \
|
||||
"mfspr %0, 0x3f0;" /* get HID0 */ \
|
||||
"isync" \
|
||||
: "=r" (_value) \
|
||||
: "0" (_value) \
|
||||
); \
|
||||
} while (0)
|
||||
|
||||
#define PPC_Set_HID0( _value ) \
|
||||
do { \
|
||||
asm volatile( \
|
||||
"isync;" \
|
||||
"mtspr 0x3f0, %0;" /* load HID0 */ \
|
||||
"isync" \
|
||||
: "=r" (_value) \
|
||||
: "0" (_value) \
|
||||
); \
|
||||
} while (0)
|
||||
|
||||
|
||||
void powerpc_instruction_cache_enable ()
|
||||
{
|
||||
unsigned32 value;
|
||||
|
||||
/*
|
||||
* Enable the instruction cache
|
||||
*/
|
||||
|
||||
PPC_Get_HID0( value );
|
||||
|
||||
value |= 0x00008000; /* Set ICE bit */
|
||||
|
||||
PPC_Set_HID0( value );
|
||||
}
|
||||
|
||||
void powerpc_data_cache_enable ()
|
||||
{
|
||||
unsigned32 value;
|
||||
|
||||
/*
|
||||
* enable data cache
|
||||
*/
|
||||
|
||||
PPC_Get_HID0( value );
|
||||
|
||||
value |= 0x00004000; /* set DCE bit */
|
||||
|
||||
PPC_Set_HID0( value );
|
||||
}
|
||||
|
||||
@@ -1,132 +0,0 @@
|
||||
/* rtems.s
|
||||
*
|
||||
* This file contains the single entry point code for
|
||||
* the PowerPC implementation of RTEMS.
|
||||
*
|
||||
* Author: Andrew Bray <andy@i-cubed.co.uk>
|
||||
*
|
||||
* COPYRIGHT (c) 1995 by i-cubed ltd.
|
||||
*
|
||||
* To anyone who acknowledges that this file is provided "AS IS"
|
||||
* without any express or implied warranty:
|
||||
* permission to use, copy, modify, and distribute this file
|
||||
* for any purpose is hereby granted without fee, provided that
|
||||
* the above copyright notice and this notice appears in all
|
||||
* copies, and that the name of i-cubed limited not be used in
|
||||
* advertising or publicity pertaining to distribution of the
|
||||
* software without specific, written prior permission.
|
||||
* i-cubed limited makes no representations about the suitability
|
||||
* of this software for any purpose.
|
||||
*
|
||||
* Derived from c/src/exec/cpu/no_cpu/rtems.c:
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1997.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* Copyright assigned to U.S. Government, 1994.
|
||||
*
|
||||
* The license and distribution terms for this file may in
|
||||
* the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <asm.h>
|
||||
|
||||
BEGIN_CODE
|
||||
/*
|
||||
* RTEMS
|
||||
*
|
||||
* This routine jumps to the directive indicated in r11.
|
||||
* This routine is used when RTEMS is linked by itself and placed
|
||||
* in ROM. This routine is the first address in the ROM space for
|
||||
* RTEMS. The user "calls" this address with the directive arguments
|
||||
* in the normal place.
|
||||
* This routine then jumps indirectly to the correct directive
|
||||
* preserving the arguments. The directive should not realize
|
||||
* it has been "wrapped" in this way. The table "_Entry_points"
|
||||
* is used to look up the directive.
|
||||
*/
|
||||
|
||||
ALIGN (4, 2)
|
||||
PUBLIC_PROC (RTEMS)
|
||||
PROC (RTEMS):
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
mflr r0
|
||||
stw r0, 8(r1)
|
||||
stwu r1, -64(r1)
|
||||
|
||||
/* Establish addressing */
|
||||
bl base
|
||||
base:
|
||||
mflr r12
|
||||
addi r12, r12, tabaddr - base
|
||||
|
||||
lwz r12, Entry_points-abase(r12)
|
||||
slwi r11, r11, 2
|
||||
lwzx r12, r12, r11
|
||||
|
||||
stw r2, 56(r1)
|
||||
lwz r0, 0(r12)
|
||||
mtlr r0
|
||||
lwz r2, 4(r12)
|
||||
lwz r11, 8(r12)
|
||||
blrl
|
||||
lwz r2, 56(r1)
|
||||
addi r1, r1, 64
|
||||
lwz r0, 8(r1)
|
||||
mtlr r0
|
||||
#else
|
||||
mflr r0
|
||||
stw r0, 4(r1)
|
||||
stwu r1, -16(r1)
|
||||
|
||||
/* Establish addressing */
|
||||
bl base
|
||||
base:
|
||||
mflr r12
|
||||
addi r12, r12, tabaddr - base
|
||||
|
||||
lwz r12, Entry_points-abase(r12)
|
||||
slwi r11, r11, 2
|
||||
lwzx r11, r12, r11
|
||||
|
||||
stw r2, 8(r1)
|
||||
#if (PPC_ABI != PPC_ABI_GCC27)
|
||||
stw r13, 12(r1)
|
||||
#endif
|
||||
mtlr r11
|
||||
lwz r11, irqinfo-abase(r12)
|
||||
lwz r2, 0(r11)
|
||||
#if (PPC_ABI != PPC_ABI_GCC27)
|
||||
lwz r13, 4(r11)
|
||||
#endif
|
||||
blrl
|
||||
lwz r2, 8(r1)
|
||||
#if (PPC_ABI != PPC_ABI_GCC27)
|
||||
lwz r13, 12(r1)
|
||||
#endif
|
||||
addi r1, r1, 16
|
||||
lwz r0, 4(r1)
|
||||
mtlr r0
|
||||
#endif
|
||||
blr
|
||||
|
||||
|
||||
/* Addressability stuff */
|
||||
tabaddr:
|
||||
abase:
|
||||
EXTERN_VAR (_Entry_points)
|
||||
Entry_points:
|
||||
EXT_SYM_REF (_Entry_points)
|
||||
#if (PPC_ABI != PPC_ABI_POWEROPEN)
|
||||
EXTERN_VAR (_CPU_IRQ_info)
|
||||
irqinfo:
|
||||
EXT_SYM_REF (_CPU_IRQ_info)
|
||||
#endif
|
||||
|
||||
#if (PPC_ABI == PPC_ABI_POWEROPEN)
|
||||
DESCRIPTOR (RTEMS)
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user