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bsps: Add gicv3_trigger_sgi()

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This commit is contained in:
Sebastian Huber
2022-04-06 09:48:52 +02:00
parent f10c551f54
commit 518330069d
2 changed files with 22 additions and 14 deletions
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bsps/include/dev/irq/arm-gicv3.h
+21
View File
@@ -166,6 +166,27 @@ static inline bool gicv3_sgi_ppi_is_pending(
return (sgi_ppi->icspispendr[0] & (1U << vector)) != 0;
}
static inline void gicv3_trigger_sgi(
rtems_vector_number vector,
uint32_t targets
)
{
#ifndef ARM_MULTILIB_ARCH_V4
uint64_t mpidr;
#else
uint32_t mpidr;
#endif
mpidr = READ_SR(MPIDR);
uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
| ICC_SGIR_INTID(vector)
| ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
| ICC_SGIR_CPU_TARGET_LIST(targets);
#ifndef ARM_MULTILIB_ARCH_V4
value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
#endif
WRITE64_SR(ICC_SGI1, value);
}
#ifdef __cplusplus
}
#endif
bsps/shared/dev/irq/arm-gicv3.c
+1 -14
View File
@@ -385,20 +385,7 @@ rtems_status_code bsp_interrupt_get_affinity(
void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets)
{
#ifndef ARM_MULTILIB_ARCH_V4
uint64_t mpidr;
#else
uint32_t mpidr;
#endif
mpidr = READ_SR(MPIDR);
uint64_t value = ICC_SGIR_AFFINITY2(MPIDR_AFFINITY2_GET(mpidr))
| ICC_SGIR_INTID(vector)
| ICC_SGIR_AFFINITY1(MPIDR_AFFINITY1_GET(mpidr))
| ICC_SGIR_CPU_TARGET_LIST(targets);
#ifndef ARM_MULTILIB_ARCH_V4
value |= ICC_SGIR_AFFINITY3(MPIDR_AFFINITY3_GET(mpidr));
#endif
WRITE64_SR(ICC_SGI1, value);
gicv3_trigger_sgi(vector, targets);
}
uint32_t arm_gic_irq_processor_count(void)