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fix sdram timing for MPC5200B chips

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Thomas Doerfler
2010-04-07 14:20:21 +00:00
parent 88919d021e
commit 456d9b2b48
2 changed files with 20 additions and 4 deletions
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c/src/lib/libbsp/powerpc/gen5200/ChangeLog
+4
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@@ -1,3 +1,7 @@
2010-04-07 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* start/start.S: fix sdram timing for MPC5200B chips
2010-03-27 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* bestcomm/task_api/tasksetup_general.h,
c/src/lib/libbsp/powerpc/gen5200/start/start.S
+16 -4
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@@ -460,11 +460,23 @@ SDRAM_init:
#endif
/* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */
/* set 5 delays to their maximum to support two banks */
LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
#if 0
LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
#else
/* EB 04.12.08:
* on MPC5200B, Erratum342 is no longer applicable.
* on MPC5200_, Single Write2Read/Prec is only 3 bits,
* therefore the MSB of the set value (1100) was ignored
* in the MPC5200B, this bit is implemented in results in
* SSSLLLOOOWWW access to SDRAM. To make the mem ctrl settings compatible with the MPC5200_,
* we use a 4 for now.
*/
LWI r30, 0xC4222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
#endif
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
/* Refr.2No-Read delay=0x06, Write latency=0x0 */
LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
#ifdef BRS5L