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Remove stray white spaces.

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This commit is contained in:
Ralf Corsepius
2004-04-16 21:29:43 +00:00
parent aed742c9a0
commit 3906b3eaa1
33 changed files with 501 additions and 501 deletions
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c/src/lib/libcpu/sh/sh7032/clock/ckinit.c
+24 -24
View File
@@ -9,7 +9,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -40,11 +40,11 @@
#define I_CLK_PHI_4 2
#define I_CLK_PHI_8 3
/*
/*
* Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
* a PHI/X clock rate.
*/
#define I_CLK_PHI I_CLK_PHI_4
#define CLOCK_SCALE (1<<I_CLK_PHI)
@@ -62,12 +62,12 @@
* clicks_per_tick := clicks_per_sec * usec_per_tick
*
* This is a very expensive function ;-)
*
*
* Below are two variants:
* 1. A variant applying integer arithmetics, only.
* 2. A variant applying floating point arithmetics
*
* The floating point variant pulls in the fmath routines when linking,
* The floating point variant pulls in the fmath routines when linking,
* resulting in slightly larger executables for applications that do not
* apply fmath otherwise. However, the imath variant is significantly slower
* than the fmath variant and more complex.
@@ -78,13 +78,13 @@
* To the sake of simplicity, we might abandon one of both variants in
* future.
*/
static unsigned int sh_clicks_per_tick(
static unsigned int sh_clicks_per_tick(
unsigned int clicks_per_sec,
unsigned int usec_per_tick )
{
#if 1
unsigned int clicks_per_tick = 0 ;
unsigned int b = clicks_per_sec ;
unsigned int c = 1000000 ;
unsigned int d = 1 ;
@@ -98,10 +98,10 @@ static unsigned int sh_clicks_per_tick(
d *= 10 ;
a = ( ( b / c ) * usec_per_tick ) / d ;
clicks_per_tick += a ;
}
}
return clicks_per_tick ;
#else
double fclicks_per_tick =
double fclicks_per_tick =
((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ;
return (uint32_t) fclicks_per_tick ;
#endif
@@ -138,7 +138,7 @@ static uint32_t Clock_isrs_const; /* only calculated once */
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
@@ -198,26 +198,26 @@ void Install_clock(
uint32_t microseconds_per_tick ;
uint32_t cclicks_per_tick ;
uint16_t Clock_limit ;
/*
* Initialize the clock tick device driver variables
*/
Clock_driver_ticks = 0;
if ( rtems_configuration_get_microseconds_per_tick() != 0 )
microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ;
else
microseconds_per_tick = 10000 ; /* 10000 us */
/* clock clicks per tick */
cclicks_per_tick =
cclicks_per_tick =
sh_clicks_per_tick(
rtems_cpu_configuration_get_clicks_per_second() / CLOCK_SCALE,
microseconds_per_tick );
Clock_isrs_const = cclicks_per_tick >> 16 ;
if ( ( cclicks_per_tick | 0xffff ) > 0 )
if ( ( cclicks_per_tick | 0xffff ) > 0 )
Clock_isrs_const++ ;
Clock_limit = cclicks_per_tick / Clock_isrs_const ;
Clock_isrs = Clock_isrs_const;
@@ -226,7 +226,7 @@ void Install_clock(
/*
* Hardware specific initialize goes here
*/
/* stop Timer 0 */
temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
write8( temp8, ITU_TSTR);
@@ -246,8 +246,8 @@ void Install_clock(
write8( ITU0_TCRMASK , ITU_TCR0);
/* use GRA without I/O - pins */
write8( ITU0_TIORVAL, ITU_TIOR0);
write8( ITU0_TIORVAL, ITU_TIOR0);
/* reset flags of the status register */
temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
write8( temp8, ITU_TSR0);
@@ -262,7 +262,7 @@ void Install_clock(
/* set counter limits */
write16( Clock_limit, ITU_GRA0);
/* start counter */
temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
write8( temp8, ITU_TSTR);
@@ -312,14 +312,14 @@ rtems_device_driver Clock_initialize(
)
{
Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
@@ -331,14 +331,14 @@ rtems_device_driver Clock_control(
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args != 0)
{
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr(CLOCK_VECTOR);
@@ -348,7 +348,7 @@ rtems_device_driver Clock_control(
rtems_isr_entry ignored ;
rtems_interrupt_disable( isrlevel );
rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
rtems_interrupt_enable( isrlevel );
}
}
c/src/lib/libcpu/sh/sh7032/delay/delay.c
+4 -4
View File
@@ -1,4 +1,4 @@
/*
/*
* This routine is a simple spin delay
*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
@@ -37,10 +37,10 @@
*/
void CPU_delay( uint32_t microseconds )
{
register uint32_t clicks_per_usec =
{
register uint32_t clicks_per_usec =
rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
register uint32_t _delay =
register uint32_t _delay =
(microseconds) * (clicks_per_usec);
asm volatile (
"0: add #-4,%0\n\
c/src/lib/libcpu/sh/sh7032/include/iosh7032.h
+3 -3
View File
@@ -7,7 +7,7 @@
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
@@ -15,7 +15,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -32,7 +32,7 @@
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h
+1 -1
View File
@@ -10,7 +10,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
c/src/lib/libcpu/sh/sh7032/include/sci.h
+4 -4
View File
@@ -9,7 +9,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -30,12 +30,12 @@ extern "C" {
/*
* Devices are set to 9600 bps, 8 databits, 1 stopbit, no
* parity and asynchronous mode by default.
* parity and asynchronous mode by default.
*
* NOTE:
* The onboard serial devices of the SH do not support hardware
* The onboard serial devices of the SH do not support hardware
* handshake.
*/
*/
#define DEVSCI_DRIVER_TABLE_ENTRY \
{ sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h
+1 -1
View File
@@ -104,7 +104,7 @@
#define PB1MD0 0x0004
#define PB0MD1 0x0002
#define PB0MD0 0x0001
#define PB7MD PB7MD1|PB7MD0
#define PB6MD PB6MD1|PB6MD0
#define PB5MD PB5MD1|PB5MD0
c/src/lib/libcpu/sh/sh7032/sci/sci.c
+25 -25
View File
@@ -8,7 +8,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -36,9 +36,9 @@
/*
* NOTE: Some SH variants have 3 sci devices
*/
#define SCI_MINOR_DEVICES 2
#define SH_SCI_BASE_0 SCI0_SMR
#define SH_SCI_BASE_1 SCI1_SMR
@@ -67,13 +67,13 @@ static int _sci_set_cflags(
{
uint8_t smr ;
uint8_t brr ;
if ( c_cflag & CBAUD )
{
if ( _sci_get_brparms( c_cflag, &smr, &brr ) != 0 )
return -1 ;
}
if ( c_cflag & CSIZE )
{
if ( c_cflag & CS8 )
@@ -98,26 +98,26 @@ static int _sci_set_cflags(
smr |= SCI_ODD_PARITY ;
else
smr &= ~SCI_ODD_PARITY;
write8( smr, sci_dev->addr + SCI_SMR );
write8( brr, sci_dev->addr + SCI_BRR );
return 0 ;
}
static void _sci_init(
static void _sci_init(
rtems_device_minor_number minor )
{
uint16_t temp16 ;
/* Pin function controller initialisation for asynchronous mode */
/* Pin function controller initialisation for asynchronous mode */
if( minor == 0)
{
temp16 = read16( PFC_PBCR1);
temp16 &= ~( PB8MD | PB9MD );
temp16 |= (PB_TXD0 | PB_RXD0);
write16( temp16, PFC_PBCR1);
}
}
else
{
temp16 = read16( PFC_PBCR1);
@@ -147,7 +147,7 @@ static void _sci_tx_polled(
{
struct scidev_t *scidev = &sci_device[minor] ;
int8_t ssr ;
while ( !inb((scidev->addr + SCI_SSR) & SCI_TDRE ))
;
write8(buf,scidev->addr+SCI_TDR);
@@ -155,13 +155,13 @@ static void _sci_tx_polled(
ssr = inb(scidev->addr+SCI_SSR);
ssr &= ~SCI_TDRE ;
write8(ssr,scidev->addr+SCI_SSR);
}
}
static int _sci_rx_polled (
int minor)
{
struct scidev_t *scidev = &sci_device[minor] ;
unsigned char c;
char ssr ;
ssr = read8(scidev->addr + SCI_SSR) ;
@@ -171,9 +171,9 @@ static int _sci_rx_polled (
if ( !(ssr & SCI_RDRF) )
return -1;
c = read8(scidev->addr + SCI_RDR) ;
write8(ssr & ~SCI_RDRF,scidev->addr + SCI_SSR);
return c;
}
@@ -189,7 +189,7 @@ rtems_device_driver sh_sci_initialize(
{
rtems_device_driver status ;
rtems_device_minor_number i;
/*
* register all possible devices.
* the initialization of the hardware is done by sci_open
@@ -206,7 +206,7 @@ rtems_device_driver sh_sci_initialize(
}
/* default hardware setup */
return RTEMS_SUCCESSFUL;
}
@@ -221,20 +221,20 @@ rtems_device_driver sh_sci_open(
void * arg )
{
uint8_t temp8;
/* check for valid minor number */
if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
{
return RTEMS_INVALID_NUMBER;
}
/* device already opened */
if ( sci_device[minor].opened > 0 )
{
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
_sci_init( minor );
if (minor == 0) {
@@ -256,16 +256,16 @@ rtems_device_driver sh_sci_open(
/* FIXME: Should be one bit delay */
CPU_delay(50000); /* microseconds */
temp8 |= SCI_RE | SCI_TE;
write8(temp8, sci_device[minor].addr + SCI_SCR); /* Enable clock output */
}
}
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
/*
* Close entry point
*/
@@ -282,7 +282,7 @@ rtems_device_driver sh_sci_close(
}
sci_device[minor].opened-- ;
return RTEMS_SUCCESSFUL ;
}
@@ -297,7 +297,7 @@ rtems_device_driver sh_sci_read(
)
{
int count = 0;
rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg;
char * buffer = rw_args->buffer;
int maximum = rw_args->count;
c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
+13 -13
View File
@@ -13,7 +13,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -49,23 +49,23 @@ extern proc_ptr _Hardware_isr_Table[];
unsigned long *_old_stack_ptr;
#endif
register unsigned long *stack_ptr asm("r15");
register unsigned long *stack_ptr asm("r15");
/*
/*
* sh_set_irq_priority
*
*
* this function sets the interrupt level of the specified interrupt
*
* parameters:
* - irq : interrupt number
* - irq : interrupt number
* - prio: priority to set for this interrupt number
*
* returns: 0 if ok
* -1 on error
*/
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
uint32_t shiftcount;
@@ -91,7 +91,7 @@ unsigned int sh_set_irq_priority(
{
irq = irq - 72;
shiftcount = 12 - ((irq & ~0x03) % 16);
switch( irq / 16)
{
case 0: { prioreg = INTC_IPRC; break;}
@@ -183,7 +183,7 @@ void _CPU_Context_restore_fp(
*/
/*
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* the offset each time Context_Control is changed
*/
void __CPU_Context_switch(
@@ -197,7 +197,7 @@ asm volatile(
"__CPU_Context_switch:\n"
" add %0,r4\n"
" stc.l sr,@-r4\n"
" stc.l gbr,@-r4\n"
" mov.l r0,@-r4\n"
@@ -251,10 +251,10 @@ asm volatile(
" nop\n" );
}
/*
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( uint32_t vector)
{
register uint32_t level;
@@ -291,7 +291,7 @@ void __ISR_Handler( uint32_t vector)
if( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
stack_ptr = _old_stack_ptr;
#endif
_CPU_ISR_Enable( level );
c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c
+48 -48
View File
@@ -3,8 +3,8 @@
* From these procedures __ISR_Handler is called with the vector number
* as argument.
*
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* file contains both isrs and normal functions.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
@@ -15,7 +15,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -38,37 +38,37 @@
*/
proc_ptr _Hardware_isr_Table[256]={
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
_nmi_isp, _usb_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
_nmi_isp, _usb_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
/* irq 64 ... */
_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
_wdt_isp,
_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
_wdt_isp,
/* 113 */ _dref_isp
};
@@ -76,7 +76,7 @@ _wdt_isp,
/*
* Some versions of gcc and all version of egcs at least until egcs-1.1b
* are not able to handle #pragma interrupt correctly if more than 1 isr is
* are not able to handle #pragma interrupt correctly if more than 1 isr is
* contained in a file and when optimizing.
* We try to work around this problem by using the macro below.
*/
@@ -119,8 +119,8 @@ asm (".global _"Str(name)"\n\t" \
".long "Str(func));
/************************************************
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
asm(" .section .text\n\
.global __dummy_isp\n\
@@ -133,17 +133,17 @@ __dummy_isp:\n\
nop");
/*****************************
* Non maskable interrupt
* Non maskable interrupt
*****************************/
isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
/*****************************
* User break controller
/*****************************
* User break controller
*****************************/
isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
/*****************************
* External interrupts 0-7
* External interrupts 0-7
*****************************/
isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
@@ -155,7 +155,7 @@ isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
/*****************************
* DMA - controller
* DMA - controller
*****************************/
isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
@@ -163,12 +163,12 @@ isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
/*****************************
* Interrupt timer unit
/*****************************
* Interrupt timer unit
*****************************/
/*****************************
* Timer 0
* Timer 0
*****************************/
isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
@@ -204,7 +204,7 @@ isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler);
/*****************************
* Serial interfaces
* Serial interfaces
*****************************/
/*****************************
@@ -225,27 +225,27 @@ isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
/*****************************
* Parity control unit of
* the bus state controller
* Parity control unit of
* the bus state controller
*****************************/
isp( _prt_isp, PRT_ISP_V, ___ISR_Handler);
/******************************
/******************************
* Analog digital converter
* ADC
* ADC
******************************/
isp( _adu_isp, ADU_ISP_V, ___ISR_Handler);
/******************************
* Watchdog timer
* Watchdog timer
******************************/
isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
/******************************
* DRAM refresh control unit
* of bus state controller
* DRAM refresh control unit
* of bus state controller
******************************/
isp( _dref_isp, DREF_ISP_V, ___ISR_Handler);
c/src/lib/libcpu/sh/sh7032/timer/timer.c
+6 -6
View File
@@ -1,5 +1,5 @@
/*
* timer for the Hitachi SH 703X
* timer for the Hitachi SH 703X
*
* This file manages the benchmark timer used by the RTEMS Timing Test
* Suite. Each measured time period is demarcated by calls to
@@ -41,9 +41,9 @@
/*
* Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
* a PHI/X clock rate.
* a PHI/X clock rate.
*/
#define I_CLK_PHI I_CLK_PHI_4
#define CLOCK_SCALE (1<<I_CLK_PHI)
@@ -154,10 +154,10 @@ int Read_timer( void )
/*
* Read the timer and see how many clicks it has been since we started.
*/
cclicks = read16( ITU_TCNT1); /* XXX: read some HW here */
/*
* Total is calculated by taking into account the number of timer overflow
* interrupts since the timer was initialized and clicks since the last
@@ -168,7 +168,7 @@ int Read_timer( void )
if ( Timer_driver_Find_average_overhead )
return total / CLOCK_SCALE; /* in XXX microsecond units */
else
else
{
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
c/src/lib/libcpu/sh/sh7045/clock/ckinit.c
+15 -15
View File
@@ -9,7 +9,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -91,7 +91,7 @@ static uint32_t Clock_isrs_const; /* only calculated once */
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
@@ -150,8 +150,8 @@ void Install_clock(
{
uint8_t temp8 = 0;
uint32_t factor = 1000000;
/*
* Initialize the clock tick device driver variables
*/
@@ -159,7 +159,7 @@ void Install_clock(
Clock_driver_ticks = 0;
Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000;
Clock_isrs = Clock_isrs_const;
factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */
Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / factor ;
@@ -168,7 +168,7 @@ void Install_clock(
/*
* Hardware specific initialize goes here
*/
/* stop Timer 0 */
temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
write8( temp8, MTU_TSTR);
@@ -188,8 +188,8 @@ void Install_clock(
write8( MTU0_TCRMASK , MTU_TCR0);
/* use GRA without I/O - pins */
write8( MTU0_TIORVAL, MTU_TIORL0);
write8( MTU0_TIORVAL, MTU_TIORL0);
/* reset flags of the status register */
temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
write8( temp8, MTU_TSR0);
@@ -204,7 +204,7 @@ void Install_clock(
/* set counter limits */
write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A);
/* start counter */
temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
write8( temp8, MTU_TSTR);
@@ -254,14 +254,14 @@ rtems_device_driver Clock_initialize(
)
{
Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
@@ -273,14 +273,14 @@ rtems_device_driver Clock_control(
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args != 0)
{
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr(CLOCK_VECTOR);
@@ -290,7 +290,7 @@ rtems_device_driver Clock_control(
rtems_isr_entry ignored ;
rtems_interrupt_disable( isrlevel );
rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
rtems_interrupt_enable( isrlevel );
}
}
c/src/lib/libcpu/sh/sh7045/include/io_types.h
+3 -3
View File
@@ -30,10 +30,10 @@
*
*
************************************************************************/
#ifndef _sh_io_types_h
#define _sh_io_types_h
#include <rtems/score/iosh7045.h>
#include <termios.h>
@@ -46,7 +46,7 @@ typedef struct {
portNo line;
int speed_ix;
dataBits dBits;
int parEn;
int parEn;
parity par;
int mulPro;
stopBits sBits;
c/src/lib/libcpu/sh/sh7045/include/iosh7045.h
+5 -5
View File
@@ -7,7 +7,7 @@
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
@@ -15,7 +15,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -24,8 +24,8 @@
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* Modified to reflect on-chip registers for sh7045 processor, based on
* "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
* Modified to reflect on-chip registers for sh7045 processor, based on
* "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
* contained no copyright notice:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
@@ -46,7 +46,7 @@
/*
* After each line is explained whether the access is char short or long.
* The functions read/writeb, w, l, 8, 16, 32 can be found
* The functions read/writeb, w, l, 8, 16, 32 can be found
* in exec/score/cpu/sh/sh_io.h
*
* 8 bit == char ( readb, writeb, read8, write8)
c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h
+2 -2
View File
@@ -10,7 +10,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -24,7 +24,7 @@
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
c/src/lib/libcpu/sh/sh7045/include/sci.h
+8 -8
View File
@@ -9,7 +9,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -32,12 +32,12 @@ extern "C" {
/*
* Devices are set to 9600 bps, 8 databits, 1 stopbit, no
* parity and asynchronous mode by default.
* parity and asynchronous mode by default.
*
* NOTE:
* The onboard serial devices of the SH do not support hardware
* The onboard serial devices of the SH do not support hardware
* handshake.
*/
*/
#define DEVSCI_DRIVER_TABLE_ENTRY \
{ sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
@@ -78,11 +78,11 @@ extern rtems_device_driver sh_sci_control(
rtems_device_minor_number,
void *
);
extern const rtems_termios_callbacks * sh_sci_get_termios_handlers(
rtems_boolean poll
extern const rtems_termios_callbacks * sh_sci_get_termios_handlers(
rtems_boolean poll
);
#ifdef __cplusplus
}
c/src/lib/libcpu/sh/sh7045/include/sci_termios.h
+8 -8
View File
@@ -18,7 +18,7 @@ extern "C"{
#endif
int sh_sci_set_attributes(
int sh_sci_set_attributes(
int minor,
const struct termios *t
);
@@ -26,31 +26,31 @@ int sh_sci_set_attributes(
void sh_sci_initialize_interrupts(int minor);
void sh_sci_init(int minor);
int sh_sci_write_support_int(
int minor,
const char *buf,
int minor,
const char *buf,
int len
);
int sh_sci_write_support_polled(
int minor,
const char *buf,
int len
);
void sh_sci_write_polled(
int minor,
char c
);
int sh_sci_inbyte_nonblocking_polled(int minor);
int sh_sci_first_open(
int major,
int minor,
void *arg
void *arg
);
int sh_sci_last_close(
c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h
+1 -1
View File
@@ -191,7 +191,7 @@
#define PB1MD0 0x0004
#define PB0MD1 0x0002
#define PB0MD0 0x0001
#define PB7MD PB7MD1|PB7MD0
#define PB6MD PB6MD1|PB6MD0
#define PB5MD PB5MD1|PB5MD0
c/src/lib/libcpu/sh/sh7045/sci/sci.c
+31 -31
View File
@@ -1,12 +1,12 @@
/*
* /dev/sci[0|1] for Hitachi SH 704X
*
* The SH doesn't have a designated console device. Therefore we "alias"
* another device as /dev/console and revector all calls to /dev/console
* The SH doesn't have a designated console device. Therefore we "alias"
* another device as /dev/console and revector all calls to /dev/console
* to this device.
*
* This approach is similar to installing a sym-link from one device to
* another device. If rtems once will support sym-links for devices files,
* This approach is similar to installing a sym-link from one device to
* another device. If rtems once will support sym-links for devices files,
* this implementation could be dropped.
*
* Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
@@ -16,7 +16,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -61,9 +61,9 @@
/*
* NOTE: Some SH variants have 3 sci devices
*/
#define SCI_MINOR_DEVICES 2
/*
* FIXME: sh7045 register names match Hitachi data book,
* but conflict with RTEMS sh7032 usage.
@@ -106,13 +106,13 @@ static int _sci_set_cflags(
{
uint8_t smr ;
uint8_t brr ;
if ( c_cflag & CBAUD )
{
if ( _sci_get_brparms( c_cflag, &smr, &brr ) != 0 )
return -1 ;
}
if ( c_cflag & CSIZE )
{
if ( c_cflag & CS8 )
@@ -137,10 +137,10 @@ static int _sci_set_cflags(
smr |= SCI_ODD_PARITY ;
else
smr &= ~SCI_ODD_PARITY;
write8( smr, sci_dev->addr + SCI_SMR );
write8( brr, sci_dev->addr + SCI_BRR );
return 0 ;
}
@@ -255,7 +255,7 @@ char sh_sci_inbyte_polled(
rtems_device_minor_number minor )
{
char ch;
if (minor == 0) /* blocks until char.ready */
while (rdSCI0(&ch) != TRUE); /* SCI0 */
else
@@ -296,8 +296,8 @@ rtems_device_driver sh_sci_initialize(
rtems_device_driver status;
rtems_device_minor_number i;
rtems_driver_name_t driver;
/*
* register all possible devices.
* the initialization of the hardware is done by sci_open
@@ -341,22 +341,22 @@ rtems_device_driver sh_sci_open(
{
uint8_t temp8;
uint16_t temp16;
unsigned a ;
/* check for valid minor number */
if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
{
return RTEMS_INVALID_NUMBER;
}
/* device already opened */
if ( sci_device[minor].opened > 0 )
{
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
/* set PFC registers to enable I/O pins */
if ((minor == 0)) {
@@ -364,8 +364,8 @@ rtems_device_driver sh_sci_open(
temp16 &= ~(PA2MD1 | PA2MD0);
temp16 |= (PA_TXD0 | PA_RXD0); /* enable pins for Tx0, Rx0 */
write16(temp16, PFC_PACRL2);
} else if (minor == 1) {
} else if (minor == 1) {
temp16 = read16(PFC_PACRL2); /* disable SCK1, DMA, IRQ */
temp16 &= ~(PA5MD1 | PA5MD0);
temp16 |= (PA_TXD1 | PA_RXD1); /* enable pins for Tx1, Rx1 */
@@ -390,24 +390,24 @@ rtems_device_driver sh_sci_open(
while(temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER)){
temp8 = read8(sci_device[minor].addr + SCI_RDR); /* flush input */
temp8 = read8(sci_device[minor].addr + SCI_SSR); /* clear some flags */
write8(temp8 & ~(SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER),
write8(temp8 & ~(SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER),
sci_device[minor].addr + SCI_SSR);
temp8 = read8(sci_device[minor].addr + SCI_SSR); /* check if everything is OK */
}
}
/* Clear RDRF flag */
write8(0x00, sci_device[minor].addr + SCI_TDR); /* force output */
/* Clear the TDRE bit */
temp8 = read8(sci_device[minor].addr + SCI_SSR) & ~SCI_TDRE;
write8(temp8, sci_device[minor].addr + SCI_SSR);
/* add interrupt setup if required */
sci_device[minor].opened++ ;
return RTEMS_SUCCESSFUL ;
}
/*
* Close entry point
*/
@@ -423,7 +423,7 @@ rtems_device_driver sh_sci_close(
sci_device[minor].opened-- ;
else
return RTEMS_INVALID_NUMBER ;
return RTEMS_SUCCESSFUL ;
}
@@ -441,7 +441,7 @@ rtems_device_driver sh_sci_read(
char *buffer;
int maximum;
int count = 0;
rw_args = (rtems_libio_rw_args_t *) arg;
buffer = rw_args->buffer;
@@ -460,7 +460,7 @@ rtems_device_driver sh_sci_read(
}
/*
* write bytes to the serial port. Stdout and stderr are the same.
* write bytes to the serial port. Stdout and stderr are the same.
*/
rtems_device_driver sh_sci_write(
@@ -527,7 +527,7 @@ static int _sh_sci_poll_read(int minor)
{
int value = -1;
char ch;
if( minor == 0 ){
if( rdSCI0( &ch ) )
value = (int) ch;
@@ -539,12 +539,12 @@ static int _sh_sci_poll_read(int minor)
}
/*
* Termios polled write
* Termios polled write
*/
static int _sh_sci_poll_write(int minor, const char *buf, int len)
{
int count;
for(count = 0; count < len; count++)
outbyte( minor, buf[count] );
return count;
c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c
+77 -77
View File
@@ -34,7 +34,7 @@
#include <sh/sci_termios.h>
/*
/*
* Some handy macros
*/
#define SH_SCI_REG_DATA(_data, _minor, _register) \
@@ -51,22 +51,22 @@
/*
* NOTE: Some SH variants have 3 sci devices
*/
#define SCI_MINOR_DEVICES 2
/*
* Automatically generated function imported from scitab.rel
/*
* Automatically generated function imported from scitab.rel
*/
extern int _sci_get_brparms(
tcflag_t cflag,
unsigned char *smr,
unsigned char *brr );
/*
/*
* Translate termios flags into SCI settings
*/
int sh_sci_set_attributes(
int sh_sci_set_attributes(
int minor,
const struct termios *t
)
@@ -74,7 +74,7 @@ int sh_sci_set_attributes(
uint8_t smr ;
uint8_t brr ;
int a;
tcflag_t c_cflag = t->c_cflag;
if ( c_cflag & CBAUD )
@@ -82,7 +82,7 @@ int sh_sci_set_attributes(
if ( _sci_get_brparms( c_cflag, &smr, &brr ) != 0 )
return -1 ;
}
if ( c_cflag & CSIZE )
{
if ( c_cflag & CS8 )
@@ -109,34 +109,34 @@ int sh_sci_set_attributes(
smr &= ~SCI_ODD_PARITY;
SH_SCI_REG_MASK((SCI_RE | SCI_TE), minor, SCI_SCR);
SH_SCI_REG_DATA(smr, minor, SCI_SMR);
SH_SCI_REG_DATA(brr, minor, SCI_BRR);
for(a=0; a < 10000L; a++) { /* Delay one bit */
asm volatile ("nop");
}
SH_SCI_REG_FLAG((SCI_RE | SCI_TE), minor, SCI_SCR);
return 0;
}
/*
/*
* Receive-data-full ISR
*
* The same routine for all interrupt sources of the same type.
* The same routine for all interrupt sources of the same type.
*/
rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
{
int minor;
for(minor = 0; minor < Console_Port_Count; minor++)
{
if(Console_Port_Tbl[minor].ulIntVector == vector)
{
{
uint8_t temp8;
/*
* FIXME: error handling should be added
*/
@@ -152,7 +152,7 @@ rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
}
}
/*
/*
* Transmit-data-empty ISR
*
* The same routine for all interrupt sources of the same type.
@@ -165,11 +165,11 @@ rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
{
if(Console_Port_Tbl[minor].ulDataPort == vector)
{
/*
/*
* FIXME: Error handling should be added
*/
/*
/*
* Mask end-of-transmission interrupt
*/
SH_SCI_REG_MASK(SCI_TIE, minor, SCI_SCR);
@@ -177,7 +177,7 @@ rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
if(rtems_termios_dequeue_characters(
Console_Port_Data[minor].termios_data, 1))
{
/*
/*
* More characters to be received - interrupt must be enabled
*/
SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR);
@@ -188,38 +188,38 @@ rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
}
/*
/*
* Initialization of serial port
*/
void sh_sci_init(int minor)
{
uint16_t temp16;
/*
* set PFC registers to enable I/O pins
/*
* set PFC registers to enable I/O pins
*/
if ((minor == 0))
if ((minor == 0))
{
temp16 = read16(PFC_PACRL2); /* disable SCK0, DMA, IRQ */
temp16 &= ~(PA2MD1 | PA2MD0);
temp16 |= (PA_TXD0 | PA_RXD0); /* enable pins for Tx0, Rx0 */
write16(temp16, PFC_PACRL2);
}
else if (minor == 1)
{
}
else if (minor == 1)
{
temp16 = read16(PFC_PACRL2); /* disable SCK1, DMA, IRQ */
temp16 &= ~(PA5MD1 | PA5MD0);
temp16 |= (PA_TXD1 | PA_RXD1); /* enable pins for Tx1, Rx1 */
write16(temp16, PFC_PACRL2);
}
}
/*
/*
* Non-default hardware setup occurs in sh_sci_first_open
*/
}
/*
/*
* Initialization of interrupts
*
* Interrupts can be started only after opening a device, so interrupt
@@ -231,22 +231,22 @@ void sh_sci_initialize_interrupts(int minor)
rtems_status_code status;
sh_sci_init(minor);
/*
/*
* Disable IRQ of SCIx
*/
status = sh_set_irq_priority(
Console_Port_Tbl[minor].ulIntVector, 0);
Console_Port_Tbl[minor].ulIntVector, 0);
if(status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
SH_SCI_REG_MASK(SCI_RIE, minor, SCI_SCR);
/*
/*
* Catch apropriate vectors
*/
status = rtems_interrupt_catch(
sh_sci_rx_isr,
sh_sci_rx_isr,
Console_Port_Tbl[minor].ulIntVector,
&old_isr);
@@ -260,14 +260,14 @@ void sh_sci_initialize_interrupts(int minor)
if(status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
/*
* Enable IRQ of SCIx
/*
* Enable IRQ of SCIx
*/
SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
status = sh_set_irq_priority(
Console_Port_Tbl[minor].ulIntVector,
Console_Port_Tbl[minor].ulIntVector,
Console_Port_Tbl[minor].ulCtrlPort2);
if(status != RTEMS_SUCCESSFUL)
@@ -287,21 +287,21 @@ int sh_sci_first_open(
{
uint8_t temp8;
unsigned int a ;
/*
* check for valid minor number
/*
* check for valid minor number
*/
if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
{
return RTEMS_INVALID_NUMBER;
}
/*
* set up SCI registers
/*
* set up SCI registers
*/
/* Clear SCR - disable Tx and Rx */
SH_SCI_REG_DATA(0x00, minor, SCI_SCR);
/* set SMR and BRR - baudrate and format */
sh_sci_set_attributes(minor, Console_Port_Tbl[minor].pDeviceParams);
@@ -312,8 +312,8 @@ int sh_sci_first_open(
write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */
Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SCR);
/*
* clear error flags
/*
* clear error flags
*/
temp8 = read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR);
while(temp8 & (SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER))
@@ -323,25 +323,25 @@ int sh_sci_first_open(
/* clear some flags */
SH_SCI_REG_FLAG((SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER), minor, SCI_SSR);
/* check if everything is OK */
temp8 = read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR);
}
}
/* Clear RDRF flag */
SH_SCI_REG_DATA(0x00, minor, SCI_TDR); /* force output */
/* Clear the TDRE bit */
SH_SCI_REG_FLAG(SCI_TDRE, minor, SCI_SSR);
/*
* Interrupt setup
/*
* Interrupt setup
*/
if(Console_Port_Tbl[minor].pDeviceFns->deviceOutputUsesInterrupts)
{
SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
}
return RTEMS_SUCCESSFUL ;
}
@@ -365,12 +365,12 @@ int sh_sci_last_close(
return RTEMS_SUCCESSFUL ;
}
/*
/*
* Interrupt aware write routine
*/
int sh_sci_write_support_int(
int minor,
const char *buf,
int minor,
const char *buf,
int len
)
{
@@ -381,15 +381,15 @@ int sh_sci_write_support_int(
*/
SH_SCI_REG_DATA(*buf, minor, SCI_TDR);
SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR);
/*
/*
* Enable interrupt
*/
SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR);
return 1;
}
/*
/*
* Polled write method
*/
int sh_sci_write_support_polled(
@@ -399,19 +399,19 @@ int sh_sci_write_support_polled(
)
{
int count = 0;
while(count < len)
{
sh_sci_write_polled(minor, buf[count]);
count++;
}
/*
/*
* Return number of bytes written
*/
return count;
}
/*
/*
* Polled write of one character at a time
*/
void sh_sci_write_polled(
@@ -419,45 +419,45 @@ void sh_sci_write_polled(
char c
)
{
/*
/*
* Wait for end of previous character
*/
while(!(read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR) & SCI_TDRE));
/*
/*
* Send the character
*/
SH_SCI_REG_DATA(c, minor, SCI_TDR);
/*
/*
* Clear TDRE flag
*/
SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR);
}
/*
* Non-blocking read
/*
* Non-blocking read
*/
int sh_sci_inbyte_nonblocking_polled(int minor)
{
uint8_t inbyte;
/*
/*
* Check if input buffer is full
*/
if(read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR) & SCI_RDRF)
{
inbyte = read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_RDR);
SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR);
/*
/*
* Check for errors
*/
if(read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR) &
if(read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR) &
(SCI_ORER | SCI_FER | SCI_PER))
{
SH_SCI_REG_MASK((SCI_ORER | SCI_FER | SCI_PER), minor, SCI_SSR);
return -1;
}
}
return (int)inbyte;
}
return -1;
c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
+12 -12
View File
@@ -13,7 +13,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -48,23 +48,23 @@ extern proc_ptr _Hardware_isr_Table[];
unsigned long *_old_stack_ptr;
#endif
register unsigned long *stack_ptr asm("r15");
register unsigned long *stack_ptr asm("r15");
/*
/*
* sh_set_irq_priority
*
*
* this function sets the interrupt level of the specified interrupt
*
* parameters:
* - irq : interrupt number
* - irq : interrupt number
* - prio: priority to set for this interrupt number
*
* returns: 0 if ok
* -1 on error
*/
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
uint32_t shiftcount;
@@ -90,7 +90,7 @@ unsigned int sh_set_irq_priority(
{
irq = irq - 72;
shiftcount = 12 - ((irq & ~0x03) % 16);
switch( irq / 16)
{
case 0: { prioreg = INTC_IPRC; break;}
@@ -185,7 +185,7 @@ void _CPU_Context_restore_fp(
*/
/*
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* the offset each time Context_Control is changed
*/
void __CPU_Context_switch(
@@ -253,10 +253,10 @@ __CPU_Context_restore:\n\
nop" );
}
/*
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( uint32_t vector)
{
register uint32_t level;
@@ -293,7 +293,7 @@ void __ISR_Handler( uint32_t vector)
if( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
stack_ptr = _old_stack_ptr;
#endif
_CPU_ISR_Enable( level );
c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c
+43 -43
View File
@@ -3,8 +3,8 @@
* From these procedures __ISR_Handler is called with the vector number
* as argument.
*
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
* some releases of gcc doesn't properly handle #pragma interrupt, if a
* file contains both isrs and normal functions.
*
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
@@ -15,7 +15,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -54,23 +54,23 @@
proc_ptr _Hardware_isr_Table[256]={
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
_nmi_isp, _usb_isp, /* irq 11, 12*/
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp,
/* trapa 0 -31 */
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */
_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
@@ -78,15 +78,15 @@ _dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
@@ -102,7 +102,7 @@ _oei_isp, /* I/O Port: irq 156*/
/*
* Some versions of gcc and all version of egcs at least until egcs-1.1b
* are not able to handle #pragma interrupt correctly if more than 1 isr is
* are not able to handle #pragma interrupt correctly if more than 1 isr is
* contained in a file and when optimizing.
* We try to work around this problem by using the macro below.
*/
@@ -148,8 +148,8 @@ asm (".global _"Str(name)"\n\t"\
".long "Str(number));
/************************************************
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 34
************************************************/
asm(" .section .text\n\
.global __dummy_isp\n\
@@ -167,17 +167,17 @@ __dummy_isp:\n\
/*****************************
* Non maskable interrupt
* Non maskable interrupt
*****************************/
isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
/*****************************
* User break controller
/*****************************
* User break controller
*****************************/
isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
/*****************************
* External interrupts 0-7
* External interrupts 0-7
*****************************/
isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
@@ -189,7 +189,7 @@ isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
/*****************************
* DMA - controller
* DMA - controller
*****************************/
isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
@@ -197,12 +197,12 @@ isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
/*****************************
* Match timer unit
/*****************************
* Match timer unit
*****************************/
/*****************************
* Timer 0
* Timer 0
*****************************/
isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
@@ -246,7 +246,7 @@ isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
/*****************************
* Serial interfaces
* Serial interfaces
*****************************/
/*****************************
@@ -266,36 +266,36 @@ isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
/******************************
/******************************
* A/D converters
* ADC0-1
* ADC0-1
******************************/
isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler);
isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler);
/******************************
* Data transfer controller
* Data transfer controller
******************************/
isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler);
/******************************
* Counter match timer
* Counter match timer
******************************/
isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler);
isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler);
/******************************
* Watchdog timer
* Watchdog timer
******************************/
isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
/******************************
* DRAM refresh control unit
* of bus state controller
* DRAM refresh control unit
* of bus state controller
******************************/
isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler);
@@ -306,8 +306,8 @@ isp( _oei_isp, OEI_ISP_V, ___ISR_Handler);
/*****************************
* Parity control unit of
* the bus state controller
* Parity control unit of
* the bus state controller
* NOT PROVIDED IN SH-2
*****************************/
/* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */
c/src/lib/libcpu/sh/sh7045/timer/timer.c
+5 -5
View File
@@ -1,5 +1,5 @@
/*
* timer for the Hitachi SH 704X
* timer for the Hitachi SH 704X
*
* This file manages the benchmark timer used by the RTEMS Timing Test
* Suite. Each measured time period is demarcated by calls to
@@ -69,7 +69,7 @@ void Timer_initialize( void )
rtems_isr *ignored;
Timer_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
/*
* Timer has never overflowed. This may not be necessary on some
* implemenations of timer but ....
@@ -150,10 +150,10 @@ int Read_timer( void )
/*
* Read the timer and see how many clicks it has been since we started.
*/
clicks = read16( MTU_TCNT1); /* XXX: read some HW here */
/*
* Total is calculated by taking into account the number of timer overflow
* interrupts since the timer was initialized and clicks since the last
@@ -164,7 +164,7 @@ int Read_timer( void )
if ( Timer_driver_Find_average_overhead )
return total / SCALE; /* in XXX microsecond units */
else
else
{
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
c/src/lib/libcpu/sh/sh7750/clock/ckinit.c
+28 -28
View File
@@ -70,11 +70,11 @@ rtems_isr_entry Old_ticker;
*
* PARAMETERS:
* vector - interrupt vector number
*
*
* RETURNS:
* none
*/
rtems_isr
rtems_isr
Clock_isr(rtems_vector_number vector)
{
uint16_t tcr;
@@ -103,7 +103,7 @@ Clock_isr(rtems_vector_number vector)
* SIDE EFFECTS:
* Establish clock interrupt handler, configure Timer 0 hardware
*/
void
void
Install_clock(rtems_isr_entry clock_isr)
{
int cpudiv = 1; /* CPU frequency divider */
@@ -111,7 +111,7 @@ Install_clock(rtems_isr_entry clock_isr)
uint32_t timer_divider; /* Calculated Timer Divider value */
uint8_t temp8;
uint16_t temp16;
/*
* Initialize the clock tick device driver variables
*/
@@ -124,27 +124,27 @@ Install_clock(rtems_isr_entry clock_isr)
case SH7750_FRQCR_IFCDIV1:
cpudiv = 1;
break;
case SH7750_FRQCR_IFCDIV2:
cpudiv = 2;
break;
case SH7750_FRQCR_IFCDIV3:
cpudiv = 3;
break;
case SH7750_FRQCR_IFCDIV4:
cpudiv = 4;
break;
case SH7750_FRQCR_IFCDIV6:
cpudiv = 6;
break;
case SH7750_FRQCR_IFCDIV8:
cpudiv = 8;
break;
default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
}
@@ -155,35 +155,35 @@ Install_clock(rtems_isr_entry clock_isr)
case SH7750_FRQCR_PFCDIV2:
tidiv = 2 * CLOCK_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV3:
tidiv = 3 * CLOCK_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV4:
tidiv = 4 * CLOCK_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV6:
tidiv = 6 * CLOCK_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV8:
tidiv = 8 * CLOCK_PRESCALER;
break;
default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
}
timer_divider =
(rtems_cpu_configuration_get_clicks_per_second() *
timer_divider =
(rtems_cpu_configuration_get_clicks_per_second() *
cpudiv / (tidiv*1000000)) *
rtems_configuration_get_microseconds_per_tick();
/*
* Hardware specific initialization
*/
/* Stop the Timer 0 */
temp8 = read8(SH7750_TSTR);
temp8 &= ~SH7750_TSTR_STR0;
@@ -197,7 +197,7 @@ Install_clock(rtems_isr_entry clock_isr)
/* Load divider */
write32(timer_divider, SH7750_TCOR0);
write16(
SH7750_TCR_UNIE | /* Enable Underflow Interrupt */
SH7750_TCR_CKEG_RAISE | /* Count on rising edge */
@@ -233,7 +233,7 @@ Install_clock(rtems_isr_entry clock_isr)
* SIDE EFFECTS:
* Stop Timer 0 counting, set timer 0 interrupt priority level to 0.
*/
void
void
Clock_exit(void)
{
uint8_t temp8 = 0;
@@ -264,19 +264,19 @@ Clock_exit(void)
* RETURNS:
* RTEMS_SUCCESSFUL
*/
rtems_device_driver
Clock_initialize(rtems_device_major_number major,
rtems_device_driver
Clock_initialize(rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp)
{
Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}
@@ -291,21 +291,21 @@ Clock_initialize(rtems_device_major_number major,
* RETURNS:
* RTEMS_SUCCESSFUL
*/
rtems_device_driver
rtems_device_driver
Clock_control(rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp)
{
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args != 0)
{
/*
* This is hokey, but until we get a defined interface
* to do this, it will just be this simple...
*/
if (args->command == rtems_build_name('I', 'S', 'R', ' '))
{
Clock_isr(CLOCK_VECTOR);
@@ -315,7 +315,7 @@ Clock_control(rtems_device_major_number major,
rtems_isr_entry ignored ;
rtems_interrupt_disable( isrlevel );
rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
rtems_interrupt_enable( isrlevel );
}
}
c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h
+4 -4
View File
@@ -7,7 +7,7 @@
* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
* Bernd Becker (becker@faw.uni-ulm.de)
*
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
* contained no copyright notice.
*
* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
@@ -15,7 +15,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -24,8 +24,8 @@
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* Modified to reflect on-chip registers for sh7045 processor, based on
* "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
* Modified to reflect on-chip registers for sh7045 processor, based on
* "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
* contained no copyright notice:
* John M. Mills (jmills@tga.com)
* TGA Technologies, Inc.
c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h
+2 -2
View File
@@ -27,8 +27,8 @@ extern "C" {
#define IPL_DRIVER_TABLE_ENTRY \
{ ipl_console_initialize, ipl_console_open, ipl_console_close, \
ipl_console_read, ipl_console_write, ipl_console_control }
#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL
rtems_device_driver ipl_console_initialize(
c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h
+2 -2
View File
@@ -14,7 +14,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -28,7 +28,7 @@
* TGA Technologies, Inc.
* 100 Pinnacle Way, Suite 140
* Norcross, GA 30071 U.S.A.
*
*
*
* This modified file may be copied and distributed in accordance
* the above-referenced license. It is provided for critique and
c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h
+5 -5
View File
@@ -8,7 +8,7 @@
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*
* @(#) $Id$
*/
@@ -20,14 +20,14 @@
#define SH4_SR_RB 0x20000000 /* General register bank specifier */
#define SH4_SR_BL 0x10000000 /* Exeption/interrupt masking bit */
#define SH4_SR_FD 0x00008000 /* FPU disable bit */
#define SH4_SR_M 0x00000200 /* For signed division:
#define SH4_SR_M 0x00000200 /* For signed division:
divisor (module) is negative */
#define SH4_SR_Q 0x00000100 /* For signed division:
#define SH4_SR_Q 0x00000100 /* For signed division:
dividend (and quotient) is negative */
#define SH4_SR_IMASK 0x000000f0 /* Interrupt mask level */
#define SH4_SR_IMASK_S 4
#define SH4_SR_S 0x00000002 /* Saturation for MAC instruction:
if set, data in MACH/L register
if set, data in MACH/L register
is restricted to 48/32 bits
for MAC.W/L instructions */
#define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */
@@ -36,7 +36,7 @@
/* FPSCR -- FPU Starus/Control Register */
#define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */
#define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */
#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point
#define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point
operations flag */
/* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
#define SH4_FPSCR_DN 0x00040000 /* Treat denormalized number as zero */
c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h
+29 -29
View File
@@ -12,26 +12,26 @@
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*
* @(#) $Id$
*/
#ifndef __SH7750_REGS_H__
#define __SH7750_REGS_H__
/*
* All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
/*
* All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
* in 0x1f000000 - 0x1fffffff (area 7 address)
*/
#define SH7750_P4_BASE 0xff000000 /* Accessable only in
#define SH7750_P4_BASE 0xff000000 /* Accessable only in
priveleged mode */
#define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */
#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
/*
* MMU Registers
/*
* MMU Registers
*/
/* Page Table Entry High register - PTEH */
@@ -61,9 +61,9 @@
#define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */
#define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode*/
#define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode*/
#define SH7750_PTEL_C 0x00000008 /* Cacheability
#define SH7750_PTEL_C 0x00000008 /* Cacheability
(0 - page not cacheable) */
#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been
#define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been
performed to a page) */
#define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are
shared by processes) */
@@ -130,12 +130,12 @@
#define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS)
#define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */
#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit:
#define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit:
set it to clear IC */
#define SH7750_CCR_ICE 0x00000100 /* IC enable bit */
#define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */
#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit
if you set OCE = 0,
#define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit
if you set OCE = 0,
you should set ORA = 0 */
#define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */
#define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */
@@ -166,7 +166,7 @@
#define SH7750_TRA_IMM_S 2
/* Exeption event register - EXPEVT */
#define SH7750_EXPEVT_REGOFS 0x000024
#define SH7750_EXPEVT_REGOFS 0x000024
#define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
#define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
@@ -174,7 +174,7 @@
#define SH7750_EXPEVT_EX_S 0
/* Interrupt event register */
#define SH7750_INTEVT_REGOFS 0x000028
#define SH7750_INTEVT_REGOFS 0x000028
#define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
#define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
#define SH7750_INTEVT_EX 0x00000fff /* Exeption code */
@@ -254,7 +254,7 @@
/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
#define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */
#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow
#define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow
interrupt */
/* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
@@ -292,7 +292,7 @@
standby mode:
0 - normal state
1 - high-impendance state */
#define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls*/
#define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */
#define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4
@@ -331,7 +331,7 @@
#define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
#define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable
#define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable
0 - CKIO pin goes to HiZ/pullup
1 - Clock is output from CKIO */
#define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */
@@ -364,7 +364,7 @@
/*
* Watchdog Timer (WDT)
*/
/* Watchdog Timer Counter register - WTCNT */
#define SH7750_WTCNT_REGOFS 0xC00008 /* offset */
#define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS)
@@ -621,7 +621,7 @@
#define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS)
#define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */
#define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */
#define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/
#define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/
#define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control:
0 - pull-up resistor is on for
control input pins
@@ -643,7 +643,7 @@
#define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable:
0 - External requests are not
accepted
1 - External requests are
1 - External requests are
accepted */
#define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit:
0 - Master Mode
@@ -877,14 +877,14 @@
#define SH7750_MCR_TCAS_1 0x00000000 /* 1 */
#define SH7750_MCR_TCAS_2 0x00800000 /* 2 */
#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period
#define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period
SDRAM: minimum number of cycles
until the next bank active cmd
is output after precharging */
#define SH7750_MCR_TPC_S 19
#define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */
#define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */
#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */
#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */
#define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */
#define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */
#define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */
@@ -1148,7 +1148,7 @@
#define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */
#define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control
Select, specifies CS5 or CS6
Select, specifies CS5 or CS6
space wait control for PCMCIA
access */
@@ -1186,8 +1186,8 @@
Address Mode (External Addr
Space -> External Device) */
#define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single
Address Mode, (External
Device -> External Addr
Address Mode, (External
Device -> External Addr
Space)*/
#define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr
Space -> External Addr Space)*/
@@ -1195,7 +1195,7 @@
#define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr
Space -> On-chip Peripheral
Module) */
#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip
#define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip
Peripheral Module ->
External Addr Space */
#define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr
@@ -1206,7 +1206,7 @@
External Addr Space) */
#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF Transmit-Data-Empty intr
transfer request (external
address space -> SCFTDR1) */
address space -> SCFTDR1) */
#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr
transfer request (SCFRDR2 ->
External Addr Space) */
@@ -1341,7 +1341,7 @@
#define SH7750_SCSSR1_TDRE 0x80 /* Transmit Data Register Empty */
#define SH7750_SCSSR1_RDRF 0x40 /* Receive Data Register Full */
#define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */
#define SH7750_SCSSR1_ORER 0x20 /* Overrun Error */
#define SH7750_SCSSR1_FER 0x10 /* Framing Error */
#define SH7750_SCSSR1_PER 0x08 /* Parity Error */
#define SH7750_SCSSR1_TEND 0x04 /* Transmit End */
@@ -1569,7 +1569,7 @@
#define SH7750_IPRA_RTC_S 0
/* Interrupt Priority Register B - IPRB (half) */
#define SH7750_IPRB_REGOFS 0xD00008 /* offset */
#define SH7750_IPRB_REGOFS 0xD00008 /* offset */
#define SH7750_IPRB SH7750_P4_REG32(SH7750_IPRB_REGOFS)
#define SH7750_IPRB_A7 SH7750_A7_REG32(SH7750_IPRB_REGOFS)
@@ -1596,7 +1596,7 @@
#define SH7750_IPRC_HUDI_S 0
/*
/*
* User Break Controller registers
*/
#define SH7750_BARA 0x200000 /* Break address regiser A */
c/src/lib/libcpu/sh/sh7750/sci/console.c
+7 -7
View File
@@ -157,10 +157,10 @@ console_first_open(int major, int minor, void *arg)
args->iop->data1, /* tty */
minor+1, /* channel */
(console_mode == CONSOLE_MODE_INT));
if (sc == RTEMS_SUCCESSFUL)
sc = sh4uart_reset(&sh4_uarts[minor]);
return sc;
}
@@ -193,7 +193,7 @@ console_last_close(int major, int minor, void *arg)
void
console_reserve_resources(rtems_configuration_table *configuration)
{
if ((console_mode != CONSOLE_MODE_RAW) &&
if ((console_mode != CONSOLE_MODE_RAW) &&
(console_mode != CONSOLE_MODE_IPL))
rtems_termios_reserve_resources (configuration, 2);
}
@@ -233,7 +233,7 @@ console_initialize(rtems_device_major_number major,
if ((console_mode != CONSOLE_MODE_RAW) &&
(console_mode != CONSOLE_MODE_IPL))
rtems_termios_initialize ();
/*
* Register the devices
*/
@@ -265,7 +265,7 @@ console_initialize(rtems_device_major_number major,
sc = sh4uart_reset(&sh4_uarts[1]);
return sc;
}
}
return RTEMS_SUCCESSFUL;
}
@@ -348,7 +348,7 @@ console_close(rtems_device_major_number major,
return rtems_termios_close (arg);
else
return RTEMS_SUCCESSFUL;
}
}
/* console_read --
* Read from the console device
@@ -425,7 +425,7 @@ console_write(rtems_device_major_number major,
char *buf = argp->buffer;
int count = argp->count;
int i;
for (i = 0; i < count; i++)
{
if (*buf == '\n')
c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
+39 -39
View File
@@ -72,15 +72,15 @@ sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven)
/*
* sh4uart_get_Pph --
* Get current peripheral module clock.
*
*
* PARAMETERS: none;
* Cpu clock is get from CPU_CLOCK_RATE_HZ marco
* Cpu clock is get from CPU_CLOCK_RATE_HZ marco
* (defined in bspopts.h, included from bsp.h)
*
* RETURNS:
* peripheral module clock in Hz.
*/
uint32_t
uint32_t
sh4uart_get_Pph(void)
{
uint16_t frqcr = *(volatile uint16_t*)SH7750_FRQCR;
@@ -114,7 +114,7 @@ sh4uart_get_Pph(void)
default: /* unreachable */
break;
}
switch (frqcr & SH7750_FRQCR_PFC)
{
case SH7750_FRQCR_PFCDIV2:
@@ -202,7 +202,7 @@ sh4uart_set_baudrate(sh4uart *uart, speed_t baud)
/* Set default baudrate if specified baudrate is impossible */
if (n >= 4)
sh4uart_set_baudrate(uart, B9600);
SCSMR(uart->chn) &= ~SH7750_SCSMR_CKS;
SCSMR(uart->chn) |= n << SH7750_SCSMR_CKS_S;
SCBRR(uart->chn) = div;
@@ -240,7 +240,7 @@ sh4uart_reset(sh4uart *uart)
SCSMR(chn) = 0x0; /* 8-bit, non-parity, 1 stop bit, pf/1 clock */
if (chn == SH4_SCIF)
SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST |
SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST |
SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4;
if (chn == SH4_SCI)
@@ -259,13 +259,13 @@ sh4uart_reset(sh4uart *uart)
ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRB_SCI1_S;
IPRB = ipr;
rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit,
SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI),
rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit,
SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI),
&uart->old_handler_transmit);
if (rc != RTEMS_SUCCESSFUL)
return rc;
rc = rtems_interrupt_catch(sh4uart1_interrupt_receive,
SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI),
rc = rtems_interrupt_catch(sh4uart1_interrupt_receive,
SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI),
&uart->old_handler_receive);
if (rc != RTEMS_SUCCESSFUL)
return rc;
@@ -277,13 +277,13 @@ sh4uart_reset(sh4uart *uart)
ipr |= SH4_UART_INTERRUPT_LEVEL << SH7750_IPRC_SCIF_S;
IPRC = ipr;
rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit,
SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI),
rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit,
SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI),
&uart->old_handler_transmit);
if (rc != RTEMS_SUCCESSFUL)
return rc;
rc = rtems_interrupt_catch(sh4uart2_interrupt_receive,
SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI),
rc = rtems_interrupt_catch(sh4uart2_interrupt_receive,
SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI),
&uart->old_handler_receive);
if (rc != RTEMS_SUCCESSFUL)
return rc;
@@ -295,10 +295,10 @@ sh4uart_reset(sh4uart *uart)
sh4uart_set_baudrate(uart, B38400); /* debug defaults (unfortunately,
it is differ to termios default */
SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE |
(chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) |
SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE |
(chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) |
(int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0);
return RTEMS_SUCCESSFUL;
}
@@ -324,15 +324,15 @@ sh4uart_disable(sh4uart *uart, int disable_port)
if (uart->int_driven)
{
rc = rtems_interrupt_catch(uart->old_handler_transmit,
uart->chn == SH4_SCI ?
SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI,
rc = rtems_interrupt_catch(uart->old_handler_transmit,
uart->chn == SH4_SCI ?
SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI,
NULL);
if (rc != RTEMS_SUCCESSFUL)
return rc;
rc = rtems_interrupt_catch(uart->old_handler_receive,
uart->chn == SH4_SCI ?
SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI,
rc = rtems_interrupt_catch(uart->old_handler_receive,
uart->chn == SH4_SCI ?
SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI,
NULL);
if (rc != RTEMS_SUCCESSFUL)
return rc;
@@ -359,7 +359,7 @@ sh4uart_set_attributes(sh4uart *uart, const struct termios *t)
int level;
speed_t baud;
uint16_t smr;
smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn));
baud = cfgetospeed(t);
@@ -473,7 +473,7 @@ sh4uart_poll_read(sh4uart *uart)
if (chn == SH4_SCI)
{
if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
SH7750_SCSSR1_ORER)) != 0)
{
error_occured = 1;
@@ -487,7 +487,7 @@ sh4uart_poll_read(sh4uart *uart)
else
{
if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
SH7750_SCSSR2_BRK)) != 0 ||
SH7750_SCSSR2_BRK)) != 0 ||
(SCLSR2 & SH7750_SCLSR2_ORER) != 0)
{
error_occured = 1;
@@ -560,15 +560,15 @@ sh4uart_poll_write(sh4uart *uart, const char *buf, int len)
while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0)
{
int i;
for (i = 0;
i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
SH7750_SCFCR2_TTRG);
for (i = 0;
i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
SH7750_SCFCR2_TTRG);
i++)
{
SCTDR2 = *buf++;
len--;
}
while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 ||
while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 ||
(SCSSR2 & SH7750_SCSSR2_TEND) == 0);
SCSSR2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND);
}
@@ -604,7 +604,7 @@ sh4uart1_interrupt_receive(rtems_vector_number vec)
if ((bp < sizeof(buf) - 1) && ((SCSSR1 & SH7750_SCSSR1_RDRF) != 0))
{
/* Receive character and handle frame/parity errors */
if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
SH7750_SCSSR1_ORER)) != 0)
{
if (SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER))
@@ -661,7 +661,7 @@ sh4uart2_interrupt_receive(rtems_vector_number vec)
if ((bp < sizeof(buf) - 1) && ((SCSSR2 & SH7750_SCSSR2_RDF) != 0))
{
if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
SH7750_SCSSR2_BRK)) != 0 ||
SH7750_SCSSR2_BRK)) != 0 ||
(SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0)
{
if (SCSSR2 & SH7750_SCSSR2_ER)
@@ -687,7 +687,7 @@ sh4uart2_interrupt_receive(rtems_vector_number vec)
else
buf[bp++] = 0x00; /* XXX -- SIGINT */
}
sh4uart_handle_error(uart);
}
else
@@ -722,7 +722,7 @@ sh4uart1_interrupt_transmit(rtems_vector_number vec)
if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len)
{
while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 &&
while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 &&
uart->tx_ptr < uart->tx_buf_len)
{
SCTDR1 = uart->tx_buf[uart->tx_ptr++];
@@ -764,9 +764,9 @@ sh4uart2_interrupt_transmit(rtems_vector_number vec)
while ((SCSSR2 & SH7750_SCSSR2_TDFE) != 0)
{
int i;
for (i = 0;
i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
SH7750_SCFCR2_TTRG);
for (i = 0;
i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
SH7750_SCFCR2_TTRG);
i++)
SCTDR2 = uart->tx_buf[uart->tx_ptr++];
while ((SCSSR1 & SH7750_SCSSR1_TDRE) == 0 ||
@@ -807,7 +807,7 @@ sh4uart_interrupt_write(sh4uart *uart, const char *buf, int len)
while ((SCSSR1 & SH7750_SCSSR1_TEND) == 0);
rtems_interrupt_disable(level);
uart->tx_buf = buf;
uart->tx_buf_len = len;
uart->tx_ptr = 0;
@@ -932,7 +932,7 @@ int
ipl_console_poll_write(int minor, const char *buf, int len)
{
int c;
while (len > 0)
while (len > 0)
{
c = (len < 64 ? len : 64);
ipl_serial_output(buf, c);
c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
+11 -11
View File
@@ -13,7 +13,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -48,7 +48,7 @@ extern proc_ptr _Hardware_isr_Table[];
unsigned long *_old_stack_ptr;
#endif
register unsigned long *stack_ptr asm("r15");
register unsigned long *stack_ptr asm("r15");
/*
* _CPU_Context_save_fp_context
@@ -68,7 +68,7 @@ void _CPU_Context_save_fp(
)
{
#if SH_HAS_FPU
asm volatile("\n\
mov.l @%0,r4 \n\
add %1,r4\n\
@@ -95,12 +95,12 @@ asm volatile("\n\
fmov xd4,@-r4\n\
fmov xd2,@-r4\n\
fmov xd0,@-r4\n\
"
"
#endif
"lds %4,fpscr\n\
"
:
: "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)),
:
: "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)),
"r"(SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR)
: "r4", "r0");
@@ -154,7 +154,7 @@ asm volatile("\n\
fmov @r4+,dr14\n\
lds.l @r4+,fpul\n\
lds.l @r4+,fpscr\n\
" :
" :
: "r"(fp_context_ptr), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_SZ)
: "r4", "r0");
@@ -182,7 +182,7 @@ asm volatile("\n\
*/
/*
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* FIXME: This is an ugly hack, but we wanted to avoid recalculating
* the offset each time Context_Control is changed
*/
void __CPU_Context_switch(
@@ -250,10 +250,10 @@ __CPU_Context_restore:\n\
nop" );
}
/*
/*
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( uint32_t vector)
{
register uint32_t level;
@@ -290,7 +290,7 @@ void __ISR_Handler( uint32_t vector)
if( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
stack_ptr = _old_stack_ptr;
#endif
_CPU_ISR_Enable( level );
c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c
+11 -11
View File
@@ -13,7 +13,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
*
*
*
* COPYRIGHT (c) 1998.
* On-Line Applications Research Corporation (OAR).
@@ -117,7 +117,7 @@ asm (" .text\n"
" .long __VBR_Saved\n"
"offset100_k:\n"
" .long 0x100\n"
" .org __vbr_base + 0x400\n"
"vbr_400:\n"
" mov.l r0,@-r15\n"
@@ -155,7 +155,7 @@ asm (" .text\n"
" mov.l r5,@-r15 \n"
" mov.l r6,@-r15 \n"
" mov.l r7,@-r15 \n"
#if 0
#if 0
" mov.l r8,@-r15 \n"
" mov.l r9,@-r15 \n"
" mov.l r10,@-r15 \n"
@@ -184,7 +184,7 @@ asm (" .text\n"
" fmov fr13,@-r15 \n"
" fmov fr14,@-r15 \n"
" fmov fr15,@-r15 \n"
" sts.l pr,@-r15 \n"
" sts.l mach,@-r15 \n"
" sts.l macl,@-r15 \n"
@@ -200,7 +200,7 @@ asm (" .text\n"
" mov.l @r4,r4 \n"
" shlr2 r4 \n"
" shlr r4 \n"
" mov.l _ISR_Table_k,r0\n"
" mov.l @r0,r0 \n"
" add r4,r0 \n"
@@ -247,7 +247,7 @@ asm (" .text\n"
" mov.l @r15+,r9 \n"
" mov.l @r15+,r8 \n"
#endif
" mov.l @r15+,r7 \n"
" mov.l @r15+,r6 \n"
" mov.l @r15+,r5 \n"
@@ -298,15 +298,15 @@ asm (" .text\n"
" lds.l @r15+,fpul \n"
" lds.l @r15+,fpscr\n"
" mov.l @r15+,r14 \n"
" mov.l @r15+,r13 \n"
" mov.l @r15+,r12 \n"
" mov.l @r15+,r11 \n"
" mov.l @r15+,r10 \n"
" mov.l @r15+,r9 \n"
" mov.l @r15+,r8 \n"
" mov.l @r15+,r7 \n"
" mov.l @r15+,r6 \n"
" mov.l @r15+,r5 \n"
@@ -329,10 +329,10 @@ asm (" .text\n"
" .long 0x600\n"
);
/************************************************
* Dummy interrupt service procedure for
* Dummy interrupt service procedure for
* interrupts being not allowed --> Trap 2
************************************************/
asm(" .section .text\n\
c/src/lib/libcpu/sh/sh7750/timer/timer.c
+24 -24
View File
@@ -62,7 +62,7 @@ rtems_boolean Timer_driver_Find_average_overhead;
* RETURNS:
* none
*/
void
void
Timer_initialize(void)
{
uint8_t temp8;
@@ -81,27 +81,27 @@ Timer_initialize(void)
case SH7750_FRQCR_IFCDIV1:
cpudiv = 1;
break;
case SH7750_FRQCR_IFCDIV2:
cpudiv = 2;
break;
case SH7750_FRQCR_IFCDIV3:
cpudiv = 3;
break;
case SH7750_FRQCR_IFCDIV4:
cpudiv = 4;
break;
case SH7750_FRQCR_IFCDIV6:
cpudiv = 6;
break;
case SH7750_FRQCR_IFCDIV8:
cpudiv = 8;
break;
default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
}
@@ -112,29 +112,29 @@ Timer_initialize(void)
case SH7750_FRQCR_PFCDIV2:
tidiv = 2 * TIMER_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV3:
tidiv = 3 * TIMER_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV4:
tidiv = 4 * TIMER_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV6:
tidiv = 6 * TIMER_PRESCALER;
break;
case SH7750_FRQCR_PFCDIV8:
tidiv = 8 * TIMER_PRESCALER;
break;
default:
rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
}
microseconds_divider =
rtems_cpu_configuration_get_clicks_per_second() * cpudiv /
microseconds_divider =
rtems_cpu_configuration_get_clicks_per_second() * cpudiv /
(tidiv * 1000000);
microseconds_per_int = 0xFFFFFFFF / microseconds_divider;
@@ -153,7 +153,7 @@ Timer_initialize(void)
/* Reset timer constant and counter */
write32(0xFFFFFFFF, SH7750_TCOR1);
write32(0xFFFFFFFF, SH7750_TCNT1);
/* Select timer mode */
write16(
SH7750_TCR_UNIE | /* Enable Underflow Interrupt */
@@ -200,7 +200,7 @@ Timer_initialize(void)
* RETURNS:
* number of microseconds since timer has been started
*/
int
int
Read_timer(void)
{
uint32_t clicks;
@@ -208,16 +208,16 @@ Read_timer(void)
uint32_t total ;
rtems_interrupt_level level;
uint32_t tcr;
_CPU_ISR_Disable(level);
clicks = 0xFFFFFFFF - read32(SH7750_TCNT1);
tcr = read32(SH7750_TCR1);
ints = Timer_interrupts;
_CPU_ISR_Enable(level);
/* Handle the case when timer overflowed but interrupt was not processed */
if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0))
{
@@ -228,7 +228,7 @@ Read_timer(void)
if ( Timer_driver_Find_average_overhead )
return total; /* in microsecond units */
else
else
{
if ( total < LEAST_VALID )
return 0; /* below timer resolution */
@@ -249,7 +249,7 @@ Read_timer(void)
* RETURNS:
* RTEMS_SUCCESSFUL
*/
rtems_status_code
rtems_status_code
Empty_function( void )
{
return RTEMS_SUCCESSFUL;
@@ -267,18 +267,18 @@ Empty_function( void )
* RETURNS:
* none
*/
void
void
Set_find_average_overhead(rtems_boolean find_flag)
{
Timer_driver_Find_average_overhead = find_flag;
}
/* timerisr --
* Timer interrupt handler routine. This function invoked on timer
* Timer interrupt handler routine. This function invoked on timer
* underflow event; once per 2^32 clocks. It should reset the timer
* event and increment timer interrupts counter.
*/
void
void
timerisr(void)
{
uint8_t temp8;