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mips: Remove the GDB stub
bsps/mips/shared/gdbstub/ holds a GDB stub of 2001 in five files. No build item names any of them, so no BSP compiles the stub and mips_gdb_stub_install() has no caller. The stub could not link in any case. It installed its handler with rtems_interrupt_catch(), a simple vectored directive which the tree does not have. It calls rtems_gdb_stub_get_current_thread() and two more functions which gdb_if.h declares and no source defines. It declares mips_register_t for __mips 1 and __mips 3 alone, so the preprocessor raises an error for the malta and the csb350 BSP. Its README names the MongooseV BSP, which the tree dropped. cpu_asm.S carries the support of the stub. mips_break() is the breakpoint trampoline and the exception return steps over the break of it. Nothing else calls either one. A commented-out block of the R3000 return logic states that the stub does that work instead. Five comments name the stub. Remove the directory and that support. A back end of cpukit/libdebugger/ will serve the MIPS port. The library carries one for aarch64, arm, i386, microblaze and powerpc today. Update #5752. Assisted-by: Claude:claude-opus-5 claude-code Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
This commit is contained in:
Sebastian Huber
committed by
Kinsey Moore
Kinsey Moore
parent
710d341453
commit
382be2ca57
@@ -1,151 +0,0 @@
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GDB stub
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========
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Debugged this stub against the MongooseV bsp. Relies on putting break
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instructions on breakpoints and step targets- normal stuff, and does not
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employ hardware breakpoint support at this time. As written, a single
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breakpoint in a loop will not be reasserted unless the user steps or has
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a 2nd one, since breakpoints are only reset when the gdb stub is
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re-entered. A useful enhancement would be to fix the break instruction
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management so the stub could invisibly put a 2nd break after the 1st
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"official" one so it can silently reset breakpoints. Shouldn't be too
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hard, mostly a matter of working it out.
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This was tested only against an R3000 MIPS. It should work OK on a
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R4000. Needs to be tested at some point.
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This stub supports threads as implemented by gdb 5 and doesn't have any
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bugs I'm aware of.
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Greg Menke
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3/5/2002
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The contents of this directory are based upon the "r46kstub.tar.gz" package
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released to the net by
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C. M. Heard
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VVNET, Inc. phone: +1 408 247 9376
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4040 Moorpark Ave. Suite 206 fax: +1 408 244 3651
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San Jose, CA 95117 USA e-mail: heard@vvnet.com
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This package was released in the September 1996 time frame for use
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with gdb 4.16 and an IDT R4600 Orion. The stub was modified to support
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R3000 class CPUs and to work within the mips-rtems exeception processing
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framework.
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The file memlimits.h could end up being target board dependent. If
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this is the case, copy it to your BSP directory and modify as necessary.
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Original README
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---------------
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The r46kstub directory and its compressed archive (r46kstub.tar.gz) contain
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the 9/29/96 source code snapshot for a ROM-resident gdb-4.16 debug agent
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(aka stub) for the IDT R4600 Orion processor. It is based on the stub for
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the Hitachi SH processor written by Ben Lee and Steve Chamberlain and
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supplied with the gdb-4.16 distribution; that stub in turn was "originally
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based on an m68k software stub written by Glenn Engel at HP, but has changed
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quite a bit". The modifications for the R4600 were contributed by C. M.
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Heard of VVNET, Inc. and were based in part on the Algorithmics R4000 version
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of Phil Bunce's PMON program.
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The distribution consists of the following files:
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```
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-rw-r--r-- 1 1178 Sep 29 16:34 ChangeLog
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-rw-r--r-- 1 748 Jul 26 01:18 Makefile
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-rw-r--r-- 1 6652 Sep 29 16:34 README
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-rw-r--r-- 1 1829 May 21 02:02 gdb_if.h
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-rw-r--r-- 1 3745 Sep 29 14:03 ioaddr.h
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-rw-r--r-- 1 2906 Sep 29 14:39 limits.h
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-rw-r--r-- 1 6552 May 23 00:17 mips_opcode.h
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-rw-r--r-- 1 14017 May 21 02:04 r4600.h
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-rw-r--r-- 1 23874 Jul 21 20:31 r46kstub.c
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-rw-r--r-- 1 1064 Jul 3 12:35 r46kstub.ld
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-rw-r--r-- 1 13299 Sep 29 16:24 stubinit.S
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```
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With the exception of mips_opcode.h, which is a slightly modified version
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of a header file contributed by Ralph Campbell to 4.4 BSD and is therefore
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copyrighted by the UC Regents, all of the source files have been dedicated
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by their authors to the public domain. Use them as you wish, but do so
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at your own risk! The authors accept _no_ responsibility for any errors.
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The debug agent contained herein is at this writing in active use at VVNET
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supporting initial hardware debug and board bring-up of an OC-12 ATM probe
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board. It uses polled I/O on a 16C450 UART. We had originally intended to
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add support for interrupts to allow gdb to break in on a running program,
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but we have found that this is not really necessary since the reset button
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will accomplish the same purpose (thanks to the MIPS feature of saving the
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program counter in the ErrorEPC register when a reset exception occurs).
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Be aware that this stub handles ALL interrupts and exceptions except for
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reset (or NMI) in the same way -- by passing control to the debug command
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loop. It of course uses the ROM exception vectors to do so. In order to
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support code that actally needs to use interrupts we use use a more elaborate
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stub that is linked with the downloaded program. It hooks the RAM exception
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vectors and clears the BEV status bit to gain control. The ROM-based stub
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is still used in this case for initial program loading.
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In order to port this stub to a different platform you will at a minimum
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need to customize the macros in limits.h (which define the limits of readable,
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writeable, and steppable address space) and the I/O addresses in ioaddr.h
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(which define the 16C450 MMIO addresses). If you use something other than
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a 16C450 UART you will probably also need to modify the portions of stubinit.S
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which deal with the serial port. I've tried to be careful to respect all the
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architecturally-defined hazards as described in Appendix F of Kane and
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Heinrich, MIPS RISC Architecture, in order to minimize the work in porting
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to 4000-series processors other than the R4600, but no guarantees are offered.
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Support is presently restricted to big-endian addressing, and I've not even
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considered what changes would be needed for little-endian support.
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When this stub is built with gcc-2.7.2 and binutils-2.6 you will see a few
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warning messages from the single-step support routine where a cast is used
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to sign-extend a pointer (the next instruction address) into a long long
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(the PC image). Those warnings are expected; I've checked the generated
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code and it is doing what I had intended. But you should not see any other
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warnings or errors. Here is a log of the build:
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```shell
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mips64orion-idt-elf-gcc -g -Wa,-ahld -Wall -membedded-data \
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-O3 -c r46kstub.c >r46kstub.L
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r46kstub.c: In function `doSStep':
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r46kstub.c:537: warning: cast to pointer from integer of different size
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r46kstub.c:539: warning: cast to pointer from integer of different size
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r46kstub.c:547: warning: cast to pointer from integer of different size
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r46kstub.c:561: warning: cast to pointer from integer of different size
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r46kstub.c:563: warning: cast to pointer from integer of different size
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r46kstub.c:572: warning: cast to pointer from integer of different size
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r46kstub.c:574: warning: cast to pointer from integer of different size
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r46kstub.c:582: warning: cast to pointer from integer of different size
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r46kstub.c:589: warning: cast to pointer from integer of different size
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r46kstub.c:591: warning: cast to pointer from integer of different size
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r46kstub.c:597: warning: cast to pointer from integer of different size
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r46kstub.c:599: warning: cast to pointer from integer of different size
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r46kstub.c:605: warning: cast to pointer from integer of different size
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r46kstub.c:607: warning: cast to pointer from integer of different size
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r46kstub.c:613: warning: cast to pointer from integer of different size
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r46kstub.c:615: warning: cast to pointer from integer of different size
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r46kstub.c:624: warning: cast to pointer from integer of different size
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r46kstub.c:628: warning: cast to pointer from integer of different size
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r46kstub.c:635: warning: cast to pointer from integer of different size
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r46kstub.c:637: warning: cast to pointer from integer of different size
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mips64orion-idt-elf-gcc -g -Wa,-ahld -Wall -membedded-data \
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-O3 -c stubinit.S >stubinit.L
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mips64orion-idt-elf-ld -t -s -T r46kstub.ld -Map r46kstub.map -o r46kstub.out
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mips64orion-idt-elf-ld: mode elf32bmip
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stubinit.o
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r46kstub.o
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mips64orion-idt-elf-objcopy -S -R .bss -R .data -R .reginfo \
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-O srec r46kstub.out r46kstub.hex
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```
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Limitations: stubinit.S deliberately forces the PC (which is a 64-bit
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register) to contain a legitimate sign-extended 32-bit value. This was
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done to cope with a bug in gdb-4.16, which does _not_ properly sign-extend
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the initial PC when it loads a program. This means that you cannot use
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the "set" command to load an unmapped sixty-four bit virtual address into
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the PC, as you can for all other registers.
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Please send bug reports, comments, or suggestions for improvement to:
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@@ -1,194 +0,0 @@
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/**
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* @file
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* @ingroup mips_gdb
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* @brief Definition of the interface between stub and gdb
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*/
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/*
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* gdb_if.h - definition of the interface between the stub and gdb
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*
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* THIS SOFTWARE IS NOT COPYRIGHTED
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*
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* The following software is offered for use in the public domain.
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* There is no warranty with regard to this software or its performance
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* and the user must accept the software "AS IS" with all faults.
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*
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* THE CONTRIBUTORS DISCLAIM ANY WARRANTIES, EXPRESS OR IMPLIED, WITH
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* REGARD TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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/**
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* @defgroup mips_gdb GDB Interface
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* @ingroup RTEMSBSPsMIPSShared
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* @brief GDB Interface
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* @{
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*/
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#ifndef _GDB_IF_H
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#define _GDB_IF_H
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/** @brief Max number of threads in qM response */
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#define QM_MAX_THREADS (20)
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struct rtems_gdb_stub_thread_info {
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char display[256];
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char name[256];
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char more_display[256];
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};
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/**
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* @name Prototypes
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* @{
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*/
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int parse_zbreak(const char *in, int *type, unsigned char **addr, int *len);
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char* mem2hstr(char *buf, const unsigned char *mem, int count);
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int hstr2mem(unsigned char *mem, const char *buf, int count);
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void set_mem_err(void);
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unsigned char get_byte(const unsigned char *ptr);
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void set_byte(unsigned char *ptr, int val);
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char* thread2vhstr(char *buf, int thread);
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char* thread2fhstr(char *buf, int thread);
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const char* fhstr2thread(const char *buf, int *thread);
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const char* vhstr2thread(const char *buf, int *thread);
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char* int2fhstr(char *buf, int val);
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char* int2vhstr(char *buf, int vali);
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const char* fhstr2int(const char *buf, int *ival);
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const char* vhstr2int(const char *buf, int *ival);
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int hstr2byte(const char *buf, int *bval);
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int hstr2nibble(const char *buf, int *nibble);
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Thread_Control *rtems_gdb_index_to_stub_id(int);
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int rtems_gdb_stub_thread_support_ok(void);
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int rtems_gdb_stub_get_current_thread(void);
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int rtems_gdb_stub_get_next_thread(int);
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int rtems_gdb_stub_get_offsets(
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unsigned char **text_addr,
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unsigned char **data_addr,
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unsigned char **bss_addr
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);
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int rtems_gdb_stub_get_thread_regs(
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int thread,
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unsigned int *registers
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);
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int rtems_gdb_stub_set_thread_regs(
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int thread,
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unsigned int *registers
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);
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void rtems_gdb_process_query(
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char *inbuffer,
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char *outbuffer,
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int do_threads,
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int thread
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);
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/** @} */
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/**
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* @name MIPS registers
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* @brief Numbered in the order in which gdb expects to see them.
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* @{
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*/
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#define ZERO 0
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#define AT 1
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#define V0 2
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#define V1 3
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#define A0 4
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#define A1 5
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#define A2 6
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#define A3 7
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#define T0 8
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#define T1 9
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#define T2 10
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#define T3 11
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#define T4 12
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#define T5 13
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#define T6 14
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#define T7 15
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#define S0 16
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#define S1 17
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#define S2 18
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#define S3 19
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#define S4 20
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#define S5 21
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#define S6 22
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#define S7 23
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#define T8 24
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#define T9 25
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#define K0 26
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#define K1 27
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#define GP 28
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#define SP 29
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#define S8 30
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#define RA 31
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#define SR 32
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#define LO 33
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#define HI 34
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#define BAD_VA 35
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#define CAUSE 36
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#define PC 37
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#define F0 38
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#define F1 39
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#define F2 40
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#define F3 41
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#define F4 42
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#define F5 43
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#define F6 44
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#define F7 45
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#define F8 46
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#define F9 47
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#define F10 48
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#define F11 49
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#define F12 50
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#define F13 51
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#define F14 52
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#define F15 53
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#define F16 54
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#define F17 55
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#define F18 56
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#define F19 57
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#define F20 58
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#define F21 59
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#define F22 60
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#define F23 61
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#define F24 62
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#define F25 63
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#define F26 64
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#define F27 65
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#define F28 66
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#define F29 67
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#define F30 68
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#define F31 69
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#define FCSR 70
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#define FIRR 71
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#define NUM_REGS 72
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/** @} */
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void mips_gdb_stub_install(int enableThreads) ;
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#define MEMOPT_READABLE 1
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#define MEMOPT_WRITEABLE 2
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#ifndef NUM_MEMSEGS
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#define NUM_MEMSEGS 10
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#endif
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int gdbstub_add_memsegment(unsigned,unsigned,int);
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/** @} */
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#endif /* _GDB_IF_H */
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@@ -1,100 +0,0 @@
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/**
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* @file
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* @ingroup mips_limits
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* @brief Definition of machine and system dependent address limits.
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*/
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/*
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* limits.h - definition of machine & system dependent address limits
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*
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* THIS SOFTWARE IS NOT COPYRIGHTED
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*
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* The following software is offered for use in the public domain.
|
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* There is no warranty with regard to this software or its performance
|
||||
* and the user must accept the software "AS IS" with all faults.
|
||||
*
|
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* THE CONTRIBUTORS DISCLAIM ANY WARRANTIES, EXPRESS OR IMPLIED, WITH
|
||||
* REGARD TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
|
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*/
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#ifndef _MEMLIMITS_H_
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#define _MEMLIMITS_H_
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/*
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* The macros in this file are specific to a given implementation.
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* The general rules for their construction are as follows:
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*
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* 1.) is_readable(addr,length) should be true if and only if the
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* region starting at the given virtual address can be read
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* _without_ causing an exception or other fatal error. Note
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* that the stub will use the strictest alignment satisfied
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* by _both_ addr and length (e.g., if both are divisible by
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* 8 then the region will be read in double-word chunks).
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*
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* 2.) is_writeable(addr,length) should be true if and only if the
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* region starting at the given virtual address can be written
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* _without_ causing an exception or other fatal error. Note
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* that the stub will use the strictest alignment satisfied
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* by _both_ addr and length (e.g., if both are divisible by
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* 8 then the region will be written in double-word chunks).
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*
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* 3.) is-steppable(ptr) whould be true if and only if ptr is the
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* address of a writeable region of memory which may contain
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* an executable instruction. At a minimum this requires that
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* ptr be word-aligned (divisible by 4) and not point to EPROM
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* or memory-mapped I/O.
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*
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* Note: in order to satisfy constraints related to cacheability
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* of certain memory subsystems it may be necessary for regions
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* of kseg0 and kseg1 which map to the same physical addresses
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* to have different readability and/or writeability attributes.
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*/
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/**
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* @defgroup mips_limits Address Limits
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* @ingroup RTEMSBSPsMIPSShared
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* @brief Address Limits
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*/
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/*
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#define K0_LIMIT_FOR_READ (K0BASE+0x18000000)
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#define K1_LIMIT_FOR_READ (K1BASE+K1SIZE)
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#define is_readable(addr,length) \
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(((K0BASE <= addr) && ((addr + length) <= K0_LIMIT_FOR_READ)) \
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|| ((K1BASE <= addr) && ((addr + length) <= K1_LIMIT_FOR_READ)))
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#define K0_LIMIT_FOR_WRITE (K0BASE+0x08000000)
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#define K1_LIMIT_FOR_WRITE (K1BASE+0x1e000000)
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#define is_writeable(addr,length) \
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(((K0BASE <= addr) && ((addr + length) <= K0_LIMIT_FOR_WRITE)) \
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|| ((K1BASE <= addr) && ((addr + length) <= K1_LIMIT_FOR_WRITE)))
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|
||||
#define K0_LIMIT_FOR_STEP (K0BASE+0x08000000)
|
||||
#define K1_LIMIT_FOR_STEP (K1BASE+0x08000000)
|
||||
|
||||
#define is_steppable(ptr) \
|
||||
((((int)ptr & 0x3) == 0) \
|
||||
&& (((K0BASE <= (int)ptr) && ((int)ptr < K0_LIMIT_FOR_STEP)) \
|
||||
|| ((K1BASE <= (int)ptr) && ((int)ptr < K1_LIMIT_FOR_STEP))))
|
||||
|
||||
struct memseg
|
||||
{
|
||||
unsigned begin, end, opts;
|
||||
};
|
||||
|
||||
#define MEMOPT_READABLE 1
|
||||
#define MEMOPT_WRITEABLE 2
|
||||
|
||||
#define NUM_MEMSEGS 10
|
||||
|
||||
int add_memsegment(unsigned,unsigned,int);
|
||||
int is_readable(unsigned,unsigned);
|
||||
int is_writeable(unsigned,unsigned);
|
||||
int is_steppable(unsigned);
|
||||
*/
|
||||
|
||||
#endif /* _MEMLIMITS_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -115,7 +115,6 @@
|
||||
/* #define INSTRUMENT_EXECUTING_THREAD */
|
||||
|
||||
|
||||
|
||||
/* Ifdefs prevent the duplication of code for MIPS ISA Level 3 ( R4xxx )
|
||||
* and MIPS ISA Level 1 (R3xxx).
|
||||
*/
|
||||
@@ -471,8 +470,7 @@ FRAME(_CPU_Context_switch,sp,0,ra)
|
||||
/*
|
||||
** this code grabs the userspace EPC if we're dispatching from
|
||||
** an interrupt frame or supplies the address of the dispatch
|
||||
** routines if not. This is entirely for the gdbstub's benefit so
|
||||
** it can know where each task is running.
|
||||
** routines if not, so the context records where each task runs.
|
||||
**
|
||||
** Its value is only set when calling threadDispatch from
|
||||
** the interrupt handler and is cleared immediately when this
|
||||
@@ -716,8 +714,6 @@ _ISR_Handler_Exception:
|
||||
* bad is going on and we can continue to run normally.
|
||||
* But we want to save the entire CPU context so exception
|
||||
* handlers can look at it and change it.
|
||||
*
|
||||
* NOTE: This is the path the debugger stub will take.
|
||||
*/
|
||||
|
||||
/* already got t0 = cause in the interrupt test above */
|
||||
@@ -778,67 +774,8 @@ _ISR_Handler_Exception:
|
||||
** this is not done, we might get stuck in an infinite loop because
|
||||
** we'll return to the instruction where the exception occurred and
|
||||
** it could throw again.
|
||||
**
|
||||
** It is expected the only code using the exception processing is
|
||||
** either the gdb stub or some user code which is either going to
|
||||
** panic or do something useful. Regardless, it is up to each
|
||||
** exception routine to properly adjust EPC, so the code below
|
||||
** may be helpful for doing just that.
|
||||
*/
|
||||
|
||||
/* *********************************************************************
|
||||
** this code follows the R3000's exception return logic, but is not
|
||||
** needed because the gdb stub does it for us. It might be useful
|
||||
** for something else at some point...
|
||||
**
|
||||
* compute the address of the instruction we'll return to *
|
||||
|
||||
LDREG t1, R_CAUSE*R_SZ(sp)
|
||||
LDREG t0, R_EPC*R_SZ(sp)
|
||||
|
||||
* first see if the exception happened in the delay slot *
|
||||
li t3,CAUSE_BD
|
||||
AND t4,t1,t3
|
||||
beqz t4,excnodelay
|
||||
NOP
|
||||
|
||||
* it did, now see if the branch occurred or not *
|
||||
li t3,CAUSE_BT
|
||||
AND t4,t1,t3
|
||||
beqz t4,excnobranch
|
||||
NOP
|
||||
|
||||
* branch was taken, we resume at the branch target *
|
||||
LDREG t0, R_TAR*R_SZ(sp)
|
||||
j excreturn
|
||||
NOP
|
||||
|
||||
excnobranch:
|
||||
ADDU t0,R_SZ
|
||||
|
||||
excnodelay:
|
||||
ADDU t0,R_SZ
|
||||
|
||||
excreturn:
|
||||
STREG t0, R_EPC*R_SZ(sp)
|
||||
NOP
|
||||
********************************************************************* */
|
||||
|
||||
|
||||
/* if we're returning into mips_break, move to the next instruction */
|
||||
|
||||
LDREG t0,R_EPC*R_SZ(sp)
|
||||
la t1,mips_break
|
||||
xor t2,t0,t1
|
||||
bnez t2,3f
|
||||
|
||||
addu t0,R_SZ
|
||||
STREG t0,R_EPC*R_SZ(sp)
|
||||
NOP
|
||||
3:
|
||||
|
||||
|
||||
|
||||
|
||||
#if ( CPU_HARDWARE_FP == TRUE )
|
||||
mfc0 t0,C0_SR /* FPU is enabled, restore state */
|
||||
@@ -871,11 +808,11 @@ excreturn:
|
||||
|
||||
/*
|
||||
** Jump all the way out. If theres a pending interrupt, just
|
||||
** let it be serviced later. Since we're probably using the
|
||||
** gdb stub, we've already disrupted the ISR service timing
|
||||
** anyhow. We oughtn't mix exception and interrupt processing
|
||||
** in the same exception call in case the exception stuff
|
||||
** might interfere with the dispatching & timer ticks.
|
||||
** let it be serviced later. An exception handler has already
|
||||
** disrupted the ISR service timing anyhow. We oughtn't mix
|
||||
** exception and interrupt processing in the same exception call
|
||||
** in case the exception stuff might interfere with the
|
||||
** dispatching & timer ticks.
|
||||
*/
|
||||
j _ISR_Handler_exit
|
||||
NOP
|
||||
@@ -975,7 +912,6 @@ _ISR_Handler_1:
|
||||
NOP
|
||||
|
||||
|
||||
|
||||
#ifdef INSTRUMENT_EXECUTING_THREAD
|
||||
lw t0,THREAD_EXECUTING
|
||||
NOP
|
||||
@@ -1062,10 +998,6 @@ _ISR_Handler_1:
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef INSTRUMENT_EXECUTING_THREAD
|
||||
lw t0,THREAD_EXECUTING
|
||||
NOP
|
||||
@@ -1143,12 +1075,3 @@ _ISR_Handler_exit:
|
||||
ENDFRAME(_ISR_Handler)
|
||||
|
||||
|
||||
FRAME(mips_break,sp,0,ra)
|
||||
.set noreorder
|
||||
break 0x0 /* this statement must be first in this function, assumed so by mips-stub.c */
|
||||
NOP
|
||||
j ra
|
||||
NOP
|
||||
.set reorder
|
||||
ENDFRAME(mips_break)
|
||||
|
||||
|
||||
@@ -744,7 +744,6 @@ void _CPU_Context_Initialize(
|
||||
|
||||
/* end of Context handler macros */
|
||||
|
||||
extern void mips_break( int error );
|
||||
|
||||
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
|
||||
|
||||
|
||||
Reference in New Issue
Block a user