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LEON: updated shared drivers to Driver Manger framework

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Some bugfixes at the same time. After this patch the drivers
may be used on RASTA systems having a big-endian PCI layout.

Removed not up to date changelogs, rely on git log instead.
This commit is contained in:
Daniel Hellstrom
2015-04-17 01:10:17 +02:00
parent e67b2b8d05
commit 3681925508
10 changed files with 4330 additions and 3782 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/lib/libbsp/sparc/shared/1553/b1553brm.c
+1080 -919
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c/src/lib/libbsp/sparc/shared/can/grcan.c
+837 -840
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c/src/lib/libbsp/sparc/shared/can/occan.c
+679 -554
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c/src/lib/libbsp/sparc/shared/i2c/i2cmst.c
+212 -157
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c/src/lib/libbsp/sparc/shared/include/b1553brm.h
+6 -19
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@@ -3,24 +3,21 @@
* @ingroup sparc_bsp
* @defgroup 1553 B1553BRM
* @ingroup 1553
* @brief Macros used for brm controller
* @brief B1553BRM device driver
*/
/*
* COPYRIGHT (c) 2006.
* Gaisler Research
* Cobham Gaisler AB.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#ifndef __B1553BRM_H__
#define __B1553BRM_H__
#include <ambapp.h>
#ifdef __cplusplus
extern "C" {
#endif
@@ -102,6 +99,7 @@ struct bc_msg {
#define BC_RTRT 0x0002
#define BC_BUSA 0x0004
#define BC_EOL 0x0020
#define BC_SKIP 0x0040
#define BC_BAME 0x8000
#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */
@@ -114,7 +112,7 @@ struct bc_msg {
#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */
#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */
#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */
#define BRM_MERR_IRQ 4096 /* Message Error irq */
#define BRM_MERR_IRQ 2048 /* Message Error irq */
#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */
#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */
#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */
@@ -144,13 +142,6 @@ struct bc_msg {
#define BRM_MODE_BM 0x2
#define BRM_MODE_BM_RT 0x3 /* both RT and BM */
/* Register RAMON FPGA BRM driver, calls brm_register */
int brm_register_leon3_ramon_fpga(void);
/* Register RAMON ASIC BRM driver, calls brm_register */
int brm_register_leon3_ramon_asic(void);
#define BRM_FREQ_12MHZ 0
#define BRM_FREQ_16MHZ 1
#define BRM_FREQ_20MHZ 2
@@ -161,15 +152,11 @@ int brm_register_leon3_ramon_asic(void);
#define CLKSEL_MASK 0x7
/* Register BRM driver
* See (struct brm_reg).w_ctrl for clksel and clkdiv.
* See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq
* bus = &ambapp_plb for LEON3. (LEON2 not yet supported for this driver)
*/
int b1553brm_register(struct ambapp_bus *bus, unsigned int clksel, unsigned int clkdiv, unsigned int brm_freq);
void b1553brm_register_drv(void);
#ifdef __cplusplus
}
#endif
#endif /* __BRM_H__ */
c/src/lib/libbsp/sparc/shared/include/grcan.h
+2 -18
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@@ -8,19 +8,16 @@
/*
* COPYRIGHT (c) 2007.
* Gaisler Research
* Cobham Gaisler AB.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#ifndef __GRCAN_H__
#define __GRCAN_H__
#include <ambapp.h>
#ifdef __cplusplus
extern "C" {
#endif
@@ -187,21 +184,8 @@ typedef struct {
#define GRCAN_IOC_SET_SFILTER 40 /* Set Sync Messages RX/TX filters, NULL disables the IRQ completely */
#define GRCAN_IOC_GET_STATUS 41 /* Get status register of GRCAN core */
struct grcan_device_info {
unsigned int base_address;
int irq;
};
/* Use hard coded addresses and IRQs to find hardware */
int grcan_rasta_register_abs(struct grcan_device_info *devices, int dev_cnt);
/* Use prescanned AMBA Plug&Play information to find all GRFIFO cores */
int grcan_rasta_register(struct ambapp_bus *abus);
int grcan_register(struct ambapp_bus *abus);
#if 0
void grcan_register(unsigned int baseaddr, unsigned int ram_base);
void grcan_interrupt_handler(rtems_vector_number v);
#endif
void grcan_register_drv(void);
#ifdef __cplusplus
}
c/src/lib/libbsp/sparc/shared/include/grspw.h
+40 -17
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@@ -3,12 +3,12 @@
* @ingroup sparc_bsp
* @defgroup spw SpaceWire
* @ingroup spw
* @brief Macros used for Spacewire bus
* @brief GRSPW Device Driver
*/
/*
* COPYRIGHT (c) 2007.
* Gaisler Research
* Cobham Gaisler AB.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -32,12 +32,18 @@ typedef struct {
unsigned int txhsize;
} spw_ioctl_packetsize;
#define GRSPW_PKTSEND_OPTION_HDR_CRC 0x1
#define GRSPW_PKTSEND_OPTION_DATA_CRC 0x2
#define GRSPW_PKTSEND_OPTION_NOCRCLEN(len) ((len & 0xf) << 8)
#define GRSPW_PKTSEND_OPTION_NOCRCLEN_MASK 0xf00
typedef struct {
unsigned int hlen;
char *hdr;
unsigned int dlen;
char *data;
unsigned int sent;
unsigned int options;
} spw_ioctl_pkt_send;
typedef struct {
@@ -84,6 +90,11 @@ typedef struct {
unsigned int is_rmapcrc;
unsigned int nodemask;
unsigned int keep_source; /* copy source address to user-buffer in read() operations
* Note that rm_prot_id has no effect when keep_source is
* set.
*/
unsigned int rtimeout; /* Read timeout if != 0 */
} spw_config;
#define SPACEWIRE_IOCTRL_SET_NODEADDR 1
@@ -113,30 +124,42 @@ typedef struct {
#define SPACEWIRE_IOCTRL_SET_COREFREQ 32
#define SPACEWIRE_IOCTRL_SET_CLKDIVSTART 33
#define SPACEWIRE_IOCTRL_SET_NODEMASK 34
#define SPACEWIRE_IOCTRL_SET_KEEP_SOURCE 35
#define SPACEWIRE_IOCTRL_SET_TCODE_CTRL 36
#define SPACEWIRE_IOCTRL_SET_TCODE 37
#define SPACEWIRE_IOCTRL_GET_TCODE 38
#define SPACEWIRE_IOCTRL_SET_READ_TIMEOUT 39
#define SPACEWIRE_IOCTRL_START 64
#define SPACEWIRE_IOCTRL_STOP 65
int grspw_register(struct ambapp_bus *bus);
/* Defines what register bits that will be touched
* for SPACEWIRE_IOCTRL_SET_TCODE_CTRL
*/
#define SPACEWIRE_TCODE_CTRL_IE_MSK 0x001
#define SPACEWIRE_TCODE_CTRL_TT_MSK 0x004
#define SPACEWIRE_TCODE_CTRL_TR_MSK 0x008
/* Defines what register bits that should be set
* for SPACEWIRE_IOCTRL_SET_TCODE_CTRL
*/
#define SPACEWIRE_TCODE_CTRL_IE 0x100
#define SPACEWIRE_TCODE_CTRL_TT 0x400
#define SPACEWIRE_TCODE_CTRL_TR 0x800
#if 0
struct grspw_buf;
/* SPACEWIRE_IOCTRL_SET_TCODE argument mask */
#define SPACEWIRE_TCODE_TCODE 0x0ff
#define SPACEWIRE_TCODE_SET 0x100 /* Set Timecode register */
#define SPACEWIRE_TCODE_TX 0x400
struct grspw_buf {
grspw_buf *next; /* next packet in chain */
void grspw_register_drv (void);
/* Always used */
unsigned int dlen; /* data length of '*data' */
unsigned int max_dlen; /* allocated length of '*data' */
void *data; /* pointer to beginning of cargo data */
void grspw_print(int options);
/* Global GRSPW Function pointer called upon timecode receive interrupt */
extern void (*grspw_timecode_callback)
(void *pDev, void *regs, int minor, unsigned int tc);
/* Only used when transmitting */
unsigned int hlen; /* length of header '*header' */
unsigned int max_hlen; /* allocated length of '*header' */
void *header; /* pointer to beginning of header data */
};
#endif
#ifdef __cplusplus
}
c/src/lib/libbsp/sparc/shared/include/i2cmst.h
+1 -22
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@@ -7,13 +7,12 @@
*/
/*
* COPYRIGHT (c) 2007 Gaisler Research
* COPYRIGHT (c) 2007 Cobham Gaisler AB
* with parts from the RTEMS MPC83xx I2C driver (c) 2007 Embedded Brains GmbH.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
*/
#ifndef _I2CMST_H
@@ -56,26 +55,6 @@ typedef struct gr_i2cmst_regs {
#define GRI2C_STATUS_IDLE 0x00000000
/* The OC I2C core will perform a write after a start unless the RD bit
in the command register has been set. Since the rtems framework has
a send_start function we buffer that command and use it when the first
data is written. The START is buffered in the sendstart member below */
typedef struct gr_i2cmst_prv {
gr_i2cmst_regs_t *reg_ptr;
unsigned int sysfreq; /* System clock frequency in kHz */
unsigned char sendstart; /* START events are buffered here */
/* rtems_irq_number irq_number; */
/* rtems_id irq_sema_id; */
} gr_i2cmst_prv_t;
typedef struct gr_i2cmst_desc {
rtems_libi2c_bus_t bus_desc;
gr_i2cmst_prv_t prv;
} gr_i2cmst_desc_t;
/* Scans for I2CMST core and initalizes i2c library */
rtems_status_code leon_register_i2c(struct ambapp_bus *abus);
#ifdef __cplusplus
}
#endif
c/src/lib/libbsp/sparc/shared/include/occan.h
+4 -9
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@@ -6,20 +6,15 @@
/*
* COPYRIGHT (c) 2007.
* Gaisler Research.
* Cobham Gaisler AB.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Author: Daniel Hellström, Gaisler Research AB, www.gaisler.com
*/
#ifndef __OCCAN_H__
#define __OCCAN_H__
#include <ambapp.h>
#ifndef __OCCAN_DRIVER_H__
#define __OCCAN_DRIVER_H__
#ifdef __cplusplus
extern "C" {
@@ -152,7 +147,7 @@ struct occan_afilter {
#define OCCAN_BLK_MODE_RX 0x1
#define OCCAN_BLK_MODE_TX 0x2
int occan_register(struct ambapp_bus *bus);
void occan_register_drv (void);
#define OCCAN_SPEED_500K 500000
c/src/lib/libbsp/sparc/shared/spw/grspw.c
+1469 -1227
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