mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-08-22 23:19:55 +08:00
Update from "erik.ivanenko" <erik.ivanenko@utoronto.ca>.
Also removed bsp_postdriver_hook() from every bsp possible and moved to shared version.
This commit is contained in:
Joel Sherrill
@@ -16,4 +16,4 @@ include $(RTEMS_ROOT)/make/directory.cfg
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#was:
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#SUB_DIRS=include startup clock console shmsupp timer wrapup
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#is
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SUB_DIRS=include startup clock console timer wrapup
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SUB_DIRS=include start startup clock console timer wrapup
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@@ -19,5 +19,5 @@
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%{qrtems_debug: start_g.o%s}}
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*link:
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%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e start}
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%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e reset}
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@@ -19,7 +19,7 @@
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#include <stdlib.h>
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#include "../startup/80386ex.h"
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#include "../start/80386ex.h"
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/* console_cleanup
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*
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@@ -0,0 +1,254 @@
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/*
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* Submitted by:
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*
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* Erik Ivanenko
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* University of Toronto
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* erik.ivanenko@utoronto.ca
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*/
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/* REMAP ADDRESSING Registers */
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#define REMAPCFGH 0x0023
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#define REMAPCFGL 0x0022
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#define REMAPCFG 0x0022
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/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */
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#define ICW1M 0xF020
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#define ICW1S 0xF0A0
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#define ICW2M 0xF021
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#define ICW2S 0xF0A1
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#define ICW3M 0xF021
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#define ICW3S 0xF0A1
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#define ICW4M 0xF021
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#define ICW4S 0xF0A1
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#define OCW1M 0xF021
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#define OCW1S 0xF0A1
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#define OCW2M 0xF020
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#define OCW2S 0xF0A0
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#define OCW3M 0xF020
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#define OCW3S 0xF0A0
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/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */
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#define ICW1MDOS 0x0020
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#define ICW1SDOS 0x00A0
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#define ICW2MDOS 0x0021
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#define ICW2SDOS 0x00A1
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#define ICW3MDOS 0x0021
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#define ICW3SDOS 0x00A1
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#define ICW4MDOS 0x0021
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#define ICW4SDOS 0x00A1
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#define OCW1MDOS 0x0021
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#define OCW1SDOS 0x00A1
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#define OCW2MDOS 0x0020
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#define OCW2SDOS 0x00A0
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#define OCW3MDOS 0x0020
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#define OCW3SDOS 0x00A0
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/* CONFIGURATION Registers */
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#define DMACFG 0xF830
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#define INTCFG 0xF832
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#define TMRCFG 0xF834
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#define SIOCFG 0xF836
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#define P1CFG 0xF820
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#define P2CFG 0xF822
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#define P3CFG 0xF824
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#define PINCFG 0xF826
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/* WATCHDOG TIMER Registers */
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#define WDTRLDH 0xF4C0
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#define WDTRLDL 0xF4C2
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#define WDTCNTH 0xF4C4
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#define WDTCNTL 0xF4C6
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#define WDTCLR 0xF4C8
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#define WDTSTATUS 0xF4CA
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/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */
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#define TMR0 0xF040
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#define TMR1 0xF041
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#define TMR2 0xF042
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#define TMRCON 0xF043
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/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */
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#define TMR0DOS 0x0040
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#define TMR1DOS 0x0041
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#define TMR2DOS 0x0042
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#define TMRCONDOS 0x0043
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/* INPUT/OUTPUT PORT UNIT Registers */
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#define P1PIN 0xF860
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#define P1LTC 0xF862
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#define P1DIR 0xF864
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#define P2PIN 0xF868
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#define P2LTC 0xF86A
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#define P2DIR 0xF86C
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#define P3PIN 0xF870
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#define P3LTC 0xF872
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#define P3DIR 0xF874
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/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */
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#define RBR0 0xF4F8
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#define THR0 0xF4F8
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#define TBR0 0xF4F8
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#define DLL0 0xF4F8
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#define IER0 0xF4F9
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#define DLH0 0xF4F9
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#define IIR0 0xF4FA
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#define LCR0 0xF4FB
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#define MCR0 0xF4FC
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#define LSR0 0xF4FD
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#define MSR0 0xF4FE
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#define SCR0 0xF4FF
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/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */
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#define RBR0DOS 0x03F8
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#define THR0DOS 0x03F8
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#define TBR0DOS 0x03F8
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#define DLL0DOS 0x03F8
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#define IER0DOS 0x03F9
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#define DLH0DOS 0x03F9
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#define IIR0DOS 0x03FA
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#define LCR0DOS 0x03FB
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#define MCR0DOS 0x03FC
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#define LSR0DOS 0x03FD
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#define MSR0DOS 0x03FE
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#define SCR0DOS 0x03FF
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/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */
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#define RBR1 0xF8F8
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#define THR1 0xF8F8
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#define TBR1 0XF8F8
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#define DLL1 0xF8F8
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#define IER1 0xF8F9
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#define DLH1 0xF8F9
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#define IIR1 0xF8FA
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#define LCR1 0xF8FB
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#define MCR1 0xF8FC
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#define LSR1 0xF8FD
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#define MSR1 0xF8FE
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#define SCR1 0xF8FF
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/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */
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#define RBR1DOS 0x02F8
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#define THR1DOS 0x02F8
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#define TBR1DOS 0x02F8
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#define DLL1DOS 0x02F8
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#define IER1DOS 0x02F9
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#define DLH1DOS 0x02F9
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#define IIR1DOS 0x02FA
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#define LCR1DOS 0x02FB
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#define MCR1DOS 0x02FC
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#define LSR1DOS 0x02FD
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#define MSR1DOS 0x02FE
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#define SCR1DOS 0x02FF
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/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */
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#define SSIOTBUF 0xF480
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#define SSIORBUF 0xF482
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#define SSIOBAUD 0xF484
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#define SSIOCON1 0xF486
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#define SSIOCON2 0xF488
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#define SSIOCTR 0xF48A
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/* CHIP SELECT UNIT Registers */
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#define CS0ADL 0xF400
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#define CS0ADH 0xF402
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#define CS0MSKL 0xF404
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#define CS0MSKH 0xF406
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#define CS1ADL 0xF408
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#define CS1ADH 0xF40A
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#define CS1MSKL 0xF40C
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#define CS1MSKH 0xF40E
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#define CS2ADL 0xF410
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#define CS2ADH 0xF412
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#define CS2MSKL 0xF414
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#define CS2MSKH 0xF416
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#define CS3ADL 0xF418
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#define CS3ADH 0xF41A
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#define CS3MSKL 0xF41C
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#define CS3MSKH 0xF41E
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#define CS4ADL 0xF420
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#define CS4ADH 0xF422
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#define CS4MSKL 0xF424
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#define CS4MSKH 0xF426
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#define CS5ADL 0xF428
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#define CS5ADH 0xF42A
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#define CS5MSKL 0xF42C
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#define CS5MSKH 0xF42E
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#define CS6ADL 0xF430
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#define CS6ADH 0xF432
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#define CS6MSKL 0xF434
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#define CS6MSKH 0xF436
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#define UCSADL 0xF438
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#define UCSADH 0xF43A
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#define UCSMSKL 0xF43C
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#define UCSMSKH 0xF43E
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/* REFRESH CONTROL UNIT Registers */
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#define RFSBAD 0xF4A0
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#define RFSCIR 0xF4A2
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#define RFSCON 0xF4A4
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#define RFSADD 0xF4A6
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/* POWER MANAGEMENT CONTROL Registers */
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#define PWRCON 0xF800
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#define CLKPRS 0xF804
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/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */
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#define DMA0TAR 0xF000
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#define DMA0BYC 0xF001
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#define DMA1TAR 0xF002
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#define DMA1BYC 0xF003
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#define DMACMD1 0xF008
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#define DMASTS 0xF008
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#define DMASRR 0xF009
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#define DMAMSK 0xF00A
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#define DMAMOD1 0xF00B
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#define DMACLRBP 0xF00C
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#define DMACLR 0xF00D
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#define DMACLRMSK 0xF00E
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#define DMAGRPMSK 0xF00F
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#define DMA0REQL 0xF010
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#define DMA0REQH 0xF011
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#define DMA1REQL 0xF012
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#define DMA1REQH 0xF013
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#define DMABSR 0xF018
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#define DMACHR 0xF019
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#define DMAIS 0xF019
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#define DMACMD2 0xF01A
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#define DMAMOD2 0xF01B
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#define DMAIEN 0xF01C
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#define DMAOVFE 0xF01D
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#define DMACLRTC 0xF01E
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#define DMA1TARPL 0xF083
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#define DMA1TARPH 0xF085
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#define DMA0TARPH 0xF086
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#define DMA0TARPL 0xF087
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#define DMA0BYCH 0xF098
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#define DMA1BYCH 0xF099
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/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */
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#define DMA0TARDOS 0x0000
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#define DMA0BYCDOS 0x0001
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#define DMA1TARDOS 0x0002
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#define DMA1BYCDOS 0x0003
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#define DMACMD1DOS 0x0008
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#define DMASTSDOS 0x0008
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#define DMASRRDOS 0x0009
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#define DMAMSKDOS 0x000A
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#define DMAMOD1DOS 0x000B
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#define DMACLRBPDOS 0x000C
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#define DMACLRDOS 0x000D
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#define DMACLRMSKDOS 0x000E
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#define DMAGRPMSKDOS 0x000F
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#define DMA1TARPLDOS 0x0083
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#define DMA0TARPLDOS 0x0087
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/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */
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#define PORT92 0xF092
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/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */
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#define PORT92DOS 0x0092
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/* end of include file */
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@@ -0,0 +1,252 @@
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/*
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* Submitted by:
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*
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||||
* Erik Ivanenko
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||||
* University of Toronto
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||||
* erik.ivanenko@utoronto.ca
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
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/* REMAP ADDRESSING Registers */
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.set REMAPCFGH , 0x0023
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.set REMAPCFGL , 0x0022
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.set REMAPCFG , 0x0022
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/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */
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.set ICW1M , 0xF020
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.set ICW1S , 0xF0A0
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.set ICW2M , 0xF021
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.set ICW2S , 0xF0A1
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.set ICW3M , 0xF021
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.set ICW3S , 0xF0A1
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.set ICW4M , 0xF021
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.set ICW4S , 0xF0A1
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||||
.set OCW1M , 0xF021
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||||
.set OCW1S , 0xF0A1
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||||
.set OCW2M , 0xF020
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.set OCW2S , 0xF0A0
|
||||
.set OCW3M , 0xF020
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||||
.set OCW3S , 0xF0A0
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||||
/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */
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||||
.set ICW1MDOS , 0x0020
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||||
.set ICW1SDOS , 0x00A0
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||||
.set ICW2MDOS , 0x0021
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||||
.set ICW2SDOS , 0x00A1
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.set ICW3MDOS , 0x0021
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||||
.set ICW3SDOS , 0x00A1
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||||
.set ICW4MDOS , 0x0021
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||||
.set ICW4SDOS , 0x00A1
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.set OCW1MDOS , 0x0021
|
||||
.set OCW1SDOS , 0x00A1
|
||||
.set OCW2MDOS , 0x0020
|
||||
.set OCW2SDOS , 0x00A0
|
||||
.set OCW3MDOS , 0x0020
|
||||
.set OCW3SDOS , 0x00A0
|
||||
|
||||
|
||||
/* CONFIGURATION Registers */
|
||||
.set DMACFG , 0xF830
|
||||
.set INTCFG , 0xF832
|
||||
.set TMRCFG , 0xF834
|
||||
.set SIOCFG , 0xF836
|
||||
.set P1CFG , 0xF820
|
||||
.set P2CFG , 0xF822
|
||||
.set P3CFG , 0xF824
|
||||
.set PINCFG , 0xF826
|
||||
|
||||
/* WATCHDOG TIMER Registers */
|
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.set WDTRLDH , 0xF4C0
|
||||
.set WDTRLDL , 0xF4C2
|
||||
.set WDTCNTH , 0xF4C4
|
||||
.set WDTCNTL , 0xF4C6
|
||||
.set WDTCLR , 0xF4C8
|
||||
.set WDTSTATUS , 0xF4CA
|
||||
|
||||
/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */
|
||||
.set TMR0 , 0xF040
|
||||
.set TMR1 , 0xF041
|
||||
.set TMR2 , 0xF042
|
||||
.set TMRCON , 0xF043
|
||||
/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */
|
||||
.set TMR0DOS , 0x0040
|
||||
.set TMR1DOS , 0x0041
|
||||
.set TMR2DOS , 0x0042
|
||||
.set TMRCONDOS , 0x0043
|
||||
|
||||
/* INPUT/OUTPUT PORT UNIT Registers */
|
||||
.set P1PIN , 0xF860
|
||||
.set P1LTC , 0xF862
|
||||
.set P1DIR , 0xF864
|
||||
.set P2PIN , 0xF868
|
||||
.set P2LTC , 0xF86A
|
||||
.set P2DIR , 0xF86C
|
||||
.set P3PIN , 0xF870
|
||||
.set P3LTC , 0xF872
|
||||
.set P3DIR , 0xF874
|
||||
|
||||
/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */
|
||||
.set RBR0 , 0xF4F8
|
||||
.set THR0 , 0xF4F8
|
||||
.set TBR0 , 0xF4F8
|
||||
.set DLL0 , 0xF4F8
|
||||
.set IER0 , 0xF4F9
|
||||
.set DLH0 , 0xF4F9
|
||||
.set IIR0 , 0xF4FA
|
||||
.set LCR0 , 0xF4FB
|
||||
.set MCR0 , 0xF4FC
|
||||
.set LSR0 , 0xF4FD
|
||||
.set MSR0 , 0xF4FE
|
||||
.set SCR0 , 0xF4FF
|
||||
/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */
|
||||
.set RBR0DOS , 0x03F8
|
||||
.set THR0DOS , 0x03F8
|
||||
.set TBR0DOS , 0x03F8
|
||||
.set DLL0DOS , 0x03F8
|
||||
.set IER0DOS , 0x03F9
|
||||
.set DLH0DOS , 0x03F9
|
||||
.set IIR0DOS , 0x03FA
|
||||
.set LCR0DOS , 0x03FB
|
||||
.set MCR0DOS , 0x03FC
|
||||
.set LSR0DOS , 0x03FD
|
||||
.set MSR0DOS , 0x03FE
|
||||
.set SCR0DOS , 0x03FF
|
||||
|
||||
/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */
|
||||
.set RBR1 , 0xF8F8
|
||||
.set THR1 , 0xF8F8
|
||||
.set TBR1 , 0XF8F8
|
||||
.set DLL1 , 0xF8F8
|
||||
.set IER1 , 0xF8F9
|
||||
.set DLH1 , 0xF8F9
|
||||
.set IIR1 , 0xF8FA
|
||||
.set LCR1 , 0xF8FB
|
||||
.set MCR1 , 0xF8FC
|
||||
.set LSR1 , 0xF8FD
|
||||
.set MSR1 , 0xF8FE
|
||||
.set SCR1 , 0xF8FF
|
||||
/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */
|
||||
.set RBR1DOS , 0x02F8
|
||||
.set THR1DOS , 0x02F8
|
||||
.set TBR1DOS , 0x02F8
|
||||
.set DLL1DOS , 0x02F8
|
||||
.set IER1DOS , 0x02F9
|
||||
.set DLH1DOS , 0x02F9
|
||||
.set IIR1DOS , 0x02FA
|
||||
.set LCR1DOS , 0x02FB
|
||||
.set MCR1DOS , 0x02FC
|
||||
.set LSR1DOS , 0x02FD
|
||||
.set MSR1DOS , 0x02FE
|
||||
.set SCR1DOS , 0x02FF
|
||||
|
||||
/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */
|
||||
.set SSIOTBUF , 0xF480
|
||||
.set SSIORBUF , 0xF482
|
||||
.set SSIOBAUD , 0xF484
|
||||
.set SSIOCON1 , 0xF486
|
||||
.set SSIOCON2 , 0xF488
|
||||
.set SSIOCTR , 0xF48A
|
||||
|
||||
/* CHIP SELECT UNIT Registers */
|
||||
.set CS0ADL , 0xF400
|
||||
.set CS0ADH , 0xF402
|
||||
.set CS0MSKL , 0xF404
|
||||
.set CS0MSKH , 0xF406
|
||||
.set CS1ADL , 0xF408
|
||||
.set CS1ADH , 0xF40A
|
||||
.set CS1MSKL , 0xF40C
|
||||
.set CS1MSKH , 0xF40E
|
||||
.set CS2ADL , 0xF410
|
||||
.set CS2ADH , 0xF412
|
||||
.set CS2MSKL , 0xF414
|
||||
.set CS2MSKH , 0xF416
|
||||
.set CS3ADL , 0xF418
|
||||
.set CS3ADH , 0xF41A
|
||||
.set CS3MSKL , 0xF41C
|
||||
.set CS3MSKH , 0xF41E
|
||||
.set CS4ADL , 0xF420
|
||||
.set CS4ADH , 0xF422
|
||||
.set CS4MSKL , 0xF424
|
||||
.set CS4MSKH , 0xF426
|
||||
.set CS5ADL , 0xF428
|
||||
.set CS5ADH , 0xF42A
|
||||
.set CS5MSKL , 0xF42C
|
||||
.set CS5MSKH , 0xF42E
|
||||
.set CS6ADL , 0xF430
|
||||
.set CS6ADH , 0xF432
|
||||
.set CS6MSKL , 0xF434
|
||||
.set CS6MSKH , 0xF436
|
||||
.set UCSADL , 0xF438
|
||||
.set UCSADH , 0xF43A
|
||||
.set UCSMSKL , 0xF43C
|
||||
.set UCSMSKH , 0xF43E
|
||||
|
||||
/* REFRESH CONTROL UNIT Registers */
|
||||
|
||||
.set RFSBAD , 0xF4A0
|
||||
.set RFSCIR , 0xF4A2
|
||||
.set RFSCON , 0xF4A4
|
||||
.set RFSADD , 0xF4A6
|
||||
|
||||
/* POWER MANAGEMENT CONTROL Registers */
|
||||
|
||||
.set PWRCON , 0xF800
|
||||
.set CLKPRS , 0xF804
|
||||
|
||||
/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */
|
||||
.set DMA0TAR , 0xF000
|
||||
.set DMA0BYC , 0xF001
|
||||
.set DMA1TAR , 0xF002
|
||||
.set DMA1BYC , 0xF003
|
||||
.set DMACMD1 , 0xF008
|
||||
.set DMASTS , 0xF008
|
||||
.set DMASRR , 0xF009
|
||||
.set DMAMSK , 0xF00A
|
||||
.set DMAMOD1 , 0xF00B
|
||||
.set DMACLRBP , 0xF00C
|
||||
.set DMACLR , 0xF00D
|
||||
.set DMACLRMSK , 0xF00E
|
||||
.set DMAGRPMSK , 0xF00F
|
||||
.set DMA0REQL , 0xF010
|
||||
.set DMA0REQH , 0xF011
|
||||
.set DMA1REQL , 0xF012
|
||||
.set DMA1REQH , 0xF013
|
||||
.set DMABSR , 0xF018
|
||||
.set DMACHR , 0xF019
|
||||
.set DMAIS , 0xF019
|
||||
.set DMACMD2 , 0xF01A
|
||||
.set DMAMOD2 , 0xF01B
|
||||
.set DMAIEN , 0xF01C
|
||||
.set DMAOVFE , 0xF01D
|
||||
.set DMACLRTC , 0xF01E
|
||||
.set DMA1TARPL , 0xF083
|
||||
.set DMA1TARPH , 0xF085
|
||||
.set DMA0TARPH , 0xF086
|
||||
.set DMA0TARPL , 0xF087
|
||||
.set DMA0BYCH , 0xF098
|
||||
.set DMA1BYCH , 0xF099
|
||||
|
||||
/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */
|
||||
.set DMA0TARDOS , 0x0000
|
||||
.set DMA0BYCDOS , 0x0001
|
||||
.set DMA1TARDOS , 0x0002
|
||||
.set DMA1BYCDOS , 0x0003
|
||||
.set DMACMD1DOS , 0x0008
|
||||
.set DMASTSDOS , 0x0008
|
||||
.set DMASRRDOS , 0x0009
|
||||
.set DMAMSKDOS , 0x000A
|
||||
.set DMAMOD1DOS , 0x000B
|
||||
.set DMACLRBPDOS , 0x000C
|
||||
.set DMACLRDOS , 0x000D
|
||||
.set DMACLRMSKDOS , 0x000E
|
||||
.set DMAGRPMSKDOS , 0x000F
|
||||
.set DMA1TARPLDOS , 0x0083
|
||||
.set DMA0TARPLDOS , 0x0087
|
||||
|
||||
/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */
|
||||
.set PORT92 , 0xF092
|
||||
/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */
|
||||
.set PORT92DOS , 0x0092
|
||||
@@ -0,0 +1,57 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
@SET_MAKE@
|
||||
srcdir = @srcdir@
|
||||
VPATH = @srcdir@
|
||||
RTEMS_ROOT = @top_srcdir@
|
||||
PROJECT_ROOT = @PROJECT_ROOT@
|
||||
|
||||
PGMS=${ARCH}/start.o
|
||||
|
||||
# C source names, if any, go here -- minus the .c
|
||||
C_PIECES=
|
||||
C_FILES=$(C_PIECES:%=%.c)
|
||||
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
|
||||
|
||||
H_FILES=
|
||||
|
||||
# Assembly source names, if any, go here -- minus the .s
|
||||
S_PIECES=start
|
||||
S_FILES=$(S_PIECES:%=%.s)
|
||||
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
|
||||
|
||||
SRCS=$(C_FILES) $(H_FILES) $(S_FILES)
|
||||
OBJS=$(C_O_FILES) $(S_O_FILES)
|
||||
|
||||
include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
|
||||
include $(RTEMS_ROOT)/make/leaf.cfg
|
||||
|
||||
#
|
||||
# (OPTIONAL) Add local stuff here using +=
|
||||
#
|
||||
|
||||
DEFINES +=
|
||||
CPPFLAGS +=
|
||||
CFLAGS +=
|
||||
|
||||
LD_PATHS +=
|
||||
LD_LIBS +=
|
||||
LDFLAGS +=
|
||||
|
||||
#
|
||||
# Add your list of files to delete here. The config files
|
||||
# already know how to delete some stuff, so you may want
|
||||
# to just run 'make clean' first to see what gets missed.
|
||||
# 'make clobber' already includes 'make clean'
|
||||
#
|
||||
|
||||
CLEAN_ADDITIONS +=
|
||||
CLOBBER_ADDITIONS +=
|
||||
|
||||
all: ${ARCH} $(SRCS) $(OBJS) $(PGM)
|
||||
$(INSTALL_VARIANT) -m 555 ${PGMS} ${PROJECT_RELEASE}/lib
|
||||
|
||||
# Install the program(s), appending _g or _p as appropriate.
|
||||
# for include files, just use $(INSTALL)
|
||||
@@ -0,0 +1,115 @@
|
||||
/* macros.inc
|
||||
*
|
||||
* This file assists the board independent startup code
|
||||
* by initializing the chip-select channels to
|
||||
* reflect the proper memory configuration.
|
||||
*
|
||||
* NOTE: No stack has been established when this routine
|
||||
* is invoked. It returns to start.s through ldsegs
|
||||
*
|
||||
* Submitted by:
|
||||
*
|
||||
* Erik Ivanenko
|
||||
* University of Toronto
|
||||
* erik.ivanenko@utoronto.ca
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
.set GDT_CODE_PTR , 0x10
|
||||
.set GDT_DATA_PTR , 0x18
|
||||
|
||||
.set BOARD_SELECT , 0x301
|
||||
.set BOARD_DATA , 0x302
|
||||
.set BOARD_LATCH , 0x303
|
||||
|
||||
|
||||
#define SetExRegByte(_register,_value) \
|
||||
movb $ ## _value, al; \
|
||||
movw $ ## _register, dx; \
|
||||
outb al, dx
|
||||
|
||||
#define SetExRegWord(_register,_value) \
|
||||
movw $ ## _value, ax; \
|
||||
movw $ ## _register, dx ; \
|
||||
outw ax, dx
|
||||
|
||||
|
||||
#define DESC2(lim_0_15, bas_0_15, bas_16_23, access, gran, bas_24_31) \
|
||||
.word lim_0_15 ; \
|
||||
.word bas_0_15 ; \
|
||||
.byte bas_16_23 ; \
|
||||
.byte access ; \
|
||||
.byte gran ; \
|
||||
.byte bas_24_31
|
||||
|
||||
#define DESC3( _base, _limit) \
|
||||
.word _limit ; \
|
||||
.long _base
|
||||
|
||||
/* THE GET_ACCESS IS CHANGED FROM 8E TO 9E */
|
||||
|
||||
#define INTERRUPT_GATE( _vector ) \
|
||||
.word _vector ; \
|
||||
.word GDT_CODE_PTR ; \
|
||||
.byte 0x0 ; \
|
||||
.byte 0x8E ; \
|
||||
.word 0x0
|
||||
|
||||
#define rLOAD_INDEX( _selector, _segment_register) \
|
||||
movl _selector , _segment_register ; \
|
||||
addb al, ( eax )
|
||||
|
||||
#define rLOAD_SEGMENT( _reg, _segment_register) \
|
||||
mov _reg , _segment_register ; \
|
||||
|
||||
/* #define rLOAD_SEGMENT( _reg, _segment_register) \
|
||||
.code16 ; \
|
||||
mov _reg , _segment_register ; \
|
||||
.code32
|
||||
*/
|
||||
#define pLOAD_SEGMENT( _selector, _segment_register) \
|
||||
movl $ ## _selector , eax ; .code16 ; \
|
||||
mov ax, _segment_register ; .code32
|
||||
|
||||
/* #define MOVE_WORD( _immed32, _reg ) \
|
||||
data16 ; \
|
||||
movl _immed32, _reg
|
||||
*/
|
||||
|
||||
#define MOVE_WORD( _immed32, _reg ) \
|
||||
movw _immed32, _reg
|
||||
|
||||
/* #define MOVE_IMMED_WORD( _immed32, _reg ) \
|
||||
data16 ; \
|
||||
mov $ ## _immed32, _reg
|
||||
|
||||
#define CS_OFF( _cs_symbol, _reg ) \
|
||||
data16 ; \
|
||||
mov _cs_symbol, _reg ; \
|
||||
data16 ;\
|
||||
andl $0x000ffff, _reg
|
||||
|
||||
#define _16_NOPS \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ; \
|
||||
nop ;
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -11,17 +11,15 @@ PROJECT_ROOT = @PROJECT_ROOT@
|
||||
PGM=${ARCH}/startup.rel
|
||||
|
||||
# C source names, if any, go here -- minus the .c
|
||||
C_PIECES=bspclean bspstart main sbrk setvec
|
||||
C_PIECES=bspclean bsppost bspstart main sbrk setvec
|
||||
C_FILES=$(C_PIECES:%=%.c)
|
||||
C_O_FILES=$(C_PIECES:%=${ARCH}/%.o)
|
||||
|
||||
H_FILES=
|
||||
|
||||
|
||||
# Assembly source names, if any, go here -- minus the .s
|
||||
# removed initcsu piece, ldsegs piece and flush
|
||||
S_PIECES= gdt idt interrupts interns reset_jmp
|
||||
|
||||
S_PIECES=
|
||||
S_FILES=$(S_PIECES:%=%.s)
|
||||
S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o)
|
||||
|
||||
|
||||
@@ -3,25 +3,15 @@
|
||||
#
|
||||
|
||||
|
||||
The doit shell file cd's to $H, which refers to the directory
|
||||
that contains the hello world test. The console is a raw com port.
|
||||
Certain test programs behave differently with different com port speeds.
|
||||
To test the programs, it is required that you hook up a terminal
|
||||
( or minicom or procomm it doesn't really matter ) to the comm port of
|
||||
the target hardware. You must ensure that the baud rate, parity etc
|
||||
is set properly. This is done on the target hardware within interns.s .
|
||||
( Set your terminal emulator to match. ) Currently, the settings
|
||||
are 9600,8,n,1 .
|
||||
The requirements for this BSP are only that the GAS used supports the
|
||||
.code16 directive. The GAS released with any GCC version 2.8.0 or better
|
||||
is required. The BSP was built with an egcs snapshot pre-1.0.2 and
|
||||
post-1.0.1. However, any egcs should work.
|
||||
|
||||
The format and layout of the file interns.s is taken from the
|
||||
intel ApBuilder software, freely distributed by Intel. Some
|
||||
easy macros ( SetExRegByte and SetExRegWord ) are basically lifted
|
||||
from the Intel macros. Similarly for the names of the IO ports.
|
||||
|
||||
This "port" begain with the forceCPU bsp. Hence I am sure that
|
||||
there is some real trash that is not appropriate. For example
|
||||
the act of copying the Interrupt Descriptor tables and Global
|
||||
descriptor tables "into our space". ( in start.s I think )
|
||||
The only "real" differences are in bspstart.c, where the initialization now
|
||||
configures all available RAM, (after setting up the Workspaces) as heap.
|
||||
The location of the stack was changed so that the heap was not trapped
|
||||
between low memory and the stack; the stack comes before the heap.
|
||||
|
||||
Erik
|
||||
|
||||
|
||||
@@ -1,14 +1,9 @@
|
||||
/* bsp_start()
|
||||
*
|
||||
/*
|
||||
* This routine starts the application. It includes application,
|
||||
* board, and monitor specific initialization and configuration.
|
||||
* The generic CPU dependent initialization has been performed
|
||||
* before this routine is invoked.
|
||||
*
|
||||
* INPUT: NONE
|
||||
*
|
||||
* OUTPUT: NONE
|
||||
*
|
||||
* COPYRIGHT (c) 1989-1998.
|
||||
* On-Line Applications Research Corporation (OAR).
|
||||
* Copyright assigned to U.S. Government, 1994.
|
||||
@@ -17,6 +12,12 @@
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* Ported to the i386ex and submitted by:
|
||||
*
|
||||
* Erik Ivanenko
|
||||
* University of Toronto
|
||||
* erik.ivanenko@utoronto.ca
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
@@ -24,12 +25,9 @@
|
||||
#include <rtems/libio.h>
|
||||
|
||||
#include <libcsupport.h>
|
||||
|
||||
#include <fcntl.h>
|
||||
|
||||
#ifdef PRINTON
|
||||
extern char inbyte(void);
|
||||
extern void outbyte(char);
|
||||
#ifdef STACK_CHECKER_ON
|
||||
#include <stackchk.h>
|
||||
#endif
|
||||
|
||||
/*
|
||||
@@ -42,23 +40,35 @@ rtems_configuration_table BSP_Configuration;
|
||||
|
||||
rtems_cpu_table Cpu_table;
|
||||
|
||||
char *rtems_progname;
|
||||
|
||||
/* Initialize whatever libc we are using
|
||||
* called from postdriver hook
|
||||
/*
|
||||
* Tells us where to put the workspace in case remote debugger is present.
|
||||
*/
|
||||
|
||||
extern rtems_unsigned32 rdb_start;
|
||||
|
||||
/*
|
||||
* bsp_libc_init
|
||||
*
|
||||
* Initialize whatever libc we are using called from bsp_postdriver_hook.
|
||||
*/
|
||||
|
||||
|
||||
void bsp_libc_init()
|
||||
{
|
||||
extern int end;
|
||||
rtems_unsigned32 heap_start;
|
||||
|
||||
heap_start = (rtems_unsigned32) &end;
|
||||
extern int heap_bottom;
|
||||
rtems_unsigned32 heap_start;
|
||||
rtems_unsigned32 heap_size;
|
||||
|
||||
heap_start = (rtems_unsigned32) &heap_bottom;
|
||||
if (heap_start & (CPU_ALIGNMENT-1))
|
||||
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
|
||||
|
||||
RTEMS_Malloc_Initialize((void *) heap_start, 64 * 1024, 0);
|
||||
|
||||
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
|
||||
|
||||
heap_size = BSP_Configuration.work_space_start -(void *) heap_start ;
|
||||
heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */
|
||||
|
||||
heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */
|
||||
RTEMS_Malloc_Initialize((void *) heap_start, heap_size, 0);
|
||||
|
||||
/*
|
||||
* Init the RTEMS libio facility to provide UNIX-like system
|
||||
* calls for use by newlib (ie: provide __rtems_open, __rtems_close, etc)
|
||||
@@ -104,7 +114,7 @@ bsp_pretasking_hook(void)
|
||||
|
||||
Stack_check_Initialize();
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef RTEMS_DEBUG
|
||||
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
|
||||
#endif
|
||||
@@ -112,45 +122,13 @@ bsp_pretasking_hook(void)
|
||||
|
||||
|
||||
/*
|
||||
* After drivers are setup, register some "filenames"
|
||||
* and open stdin, stdout, stderr files
|
||||
*
|
||||
* Newlib will automatically associate the files with these
|
||||
* (it hardcodes the numbers)
|
||||
* Use the shared bsp_postdriver_hook() implementation
|
||||
*/
|
||||
|
||||
void
|
||||
bsp_postdriver_hook(void)
|
||||
{
|
||||
int stdin_fd, stdout_fd, stderr_fd;
|
||||
int error_code;
|
||||
|
||||
error_code = 'S' << 24 | 'T' << 16;
|
||||
|
||||
if ((stdin_fd = __rtems_open("/dev/console", O_RDONLY, 0)) == -1)
|
||||
rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' );
|
||||
|
||||
if ((stdout_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1)
|
||||
rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' );
|
||||
|
||||
if ((stderr_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1)
|
||||
rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' );
|
||||
|
||||
if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2))
|
||||
rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' );
|
||||
}
|
||||
|
||||
void bsp_postdriver_hook(void);
|
||||
|
||||
void bsp_start( void )
|
||||
{
|
||||
|
||||
#ifdef PRINTON
|
||||
outbyte('a');
|
||||
outbyte('b');
|
||||
outbyte('c');
|
||||
outbyte ('S');
|
||||
#endif
|
||||
|
||||
/*
|
||||
* we do not use the pretasking_hook.
|
||||
*/
|
||||
@@ -169,7 +147,7 @@ void bsp_start( void )
|
||||
|
||||
Cpu_table.interrupt_table_offset = (void *)Interrupt_descriptor_table;
|
||||
|
||||
Cpu_table.interrupt_stack_size = 4096;
|
||||
Cpu_table.interrupt_stack_size = 4096; /* STACK_MINIMUM_SIZE */
|
||||
|
||||
Cpu_table.extra_mpci_receive_server_stack = 0;
|
||||
|
||||
@@ -179,24 +157,26 @@ void bsp_start( void )
|
||||
|
||||
BSP_Configuration = Configuration;
|
||||
|
||||
#if defined(RTEMS_POSIX_API)
|
||||
BSP_Configuration.work_space_size *= 3;
|
||||
#endif
|
||||
|
||||
BSP_Configuration.work_space_start = (void *)
|
||||
RAM_END - BSP_Configuration.work_space_size;
|
||||
|
||||
|
||||
#ifdef SPRINTON
|
||||
sprintf( x_buffer, "ram end : %u, work_space_size: %d\n",
|
||||
RAM_END , BSP_Configuration.work_space_size );
|
||||
do {
|
||||
outbyte ( x_buffer[i] );
|
||||
} while ( x_buffer[i++] != '\n');
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Add 1 region for Malloc in libc_low
|
||||
*/
|
||||
|
||||
BSP_Configuration.RTEMS_api_configuration->maximum_regions++;
|
||||
|
||||
/*
|
||||
* Account for the console's resources
|
||||
*/
|
||||
|
||||
/* console_reserve_resources( &BSP_Configuration ); */
|
||||
|
||||
|
||||
/*
|
||||
* Add 1 extension for newlib libc
|
||||
*/
|
||||
|
||||
@@ -17,60 +17,112 @@
|
||||
ENTRY(reset) ;
|
||||
SECTIONS
|
||||
{
|
||||
_rom_ints = 0x3fb0000;
|
||||
.ints 0x0100 :
|
||||
AT ( _rom_ints ) /* was 0x3fb3300 */
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupts section:
|
||||
*
|
||||
* This section defines the layout of the interrupts in ROM ( VMA ) as well as their
|
||||
* location in RAM (LMA). The _rom_ and _ram_ variables are used in start.s
|
||||
* in order for the code to move the interrupt vector tables from ROM to RAM
|
||||
* while still running in real-mode. The tables are moved from ROM, as the IDT
|
||||
* is initialized with only 16-bit offsets for the interrupt handlers.
|
||||
* This is purely an implementation issue. If you prefer the interrupt handlers
|
||||
* to be resident in flash, then you must provide the code to create the interrupt
|
||||
* gates with full 32bit offsets. The code in the current start.s does NOT support
|
||||
* interrupts in ROM by merely redefining their location.
|
||||
******************************************************************************/
|
||||
_rom_ints = 0x3ff0000; /* was 0x3fb0000 */
|
||||
_rom_ints_segment = 0xF000 ;
|
||||
_rom_ints_offset = 0x0000 ;
|
||||
|
||||
_ram_ints_segment = 0x0000 ;
|
||||
_ram_ints_offset = 0x0100 ;
|
||||
|
||||
|
||||
.ints _ram_ints_offset :
|
||||
AT ( _rom_ints )
|
||||
{
|
||||
_sints = .;
|
||||
*(.ints);
|
||||
_eints = ALIGN (0x010);
|
||||
}
|
||||
_cs4_ints_segment = 0x0010 ;
|
||||
_cs4_ints_offset = 0x0000 ;
|
||||
_cs6_t_ints_segment = 0xF000 ; /* was 0xF000 */
|
||||
_cs6_t_ints_offset = 0x0000 ; /* was 0x3300 */
|
||||
_cs6_t_ints_size = _eints - _sints ;
|
||||
|
||||
_rom_gdt = _rom_ints + _cs6_t_ints_size;
|
||||
.gdt 0x1000 :
|
||||
_ints_size = _eints - _sints ;
|
||||
/**************************************************************************************
|
||||
* GDT section:
|
||||
*
|
||||
* This section defines the locations of the GDT in ROM as well as in RAM. The _rom_ and
|
||||
* _ram_ variables are used by start.s to copy the GDT from ROM to RAM when still in
|
||||
* real-mode. The move from ROM to RAM is made as a writeable GDT is required for the
|
||||
* jump to protected mode to be successful.
|
||||
**************************************************************************************/
|
||||
|
||||
_rom_gdt = _rom_ints + _ints_size;
|
||||
_rom_gdt_segment = 0xF000;
|
||||
_rom_gdt_offset = _rom_ints_offset + _ints_size;
|
||||
|
||||
_ram_gdt_segment = 0x0000 ;
|
||||
_ram_gdt_offset = _ram_ints_offset + _ints_size;
|
||||
|
||||
.gdt _ram_gdt_offset :
|
||||
AT ( _rom_gdt )
|
||||
{
|
||||
_sgdt = .;
|
||||
*(.gdt);
|
||||
_egdt = ALIGN (0x10);
|
||||
}
|
||||
_cs4_gdt_segment = 0x0100 ; /* evaluates to 0x1000 */
|
||||
_cs4_gdt_offset = 0x0000 ;
|
||||
_cs6_t_gdt_segment = 0xF000;
|
||||
_cs6_t_gdt_offset = _cs6_t_ints_size; /* was 0x0 */
|
||||
_cs6_t_gdt_size = _egdt - _sgdt;
|
||||
_gdt_size = _egdt - _sgdt;
|
||||
|
||||
_rom_idt = _rom_gdt + _cs6_t_gdt_size + _cs6_t_ints_size ;
|
||||
.idt 0x1200 :
|
||||
/*****************************************************************************************
|
||||
* IDT section:
|
||||
*
|
||||
* This section defines the locations of the IDT in ROM as well as in RAM. The _rom_ and
|
||||
* _ram_ variables are used by start.s to copy the IDT from ROM to RAM when still in real-mode.
|
||||
* The move from ROM to RAM is required to enable RTEMS to hook the interrupts, however,
|
||||
* this move could be made when in protected mode.
|
||||
****************************************************************************************/
|
||||
|
||||
_rom_idt = _rom_gdt + _gdt_size ;
|
||||
_rom_idt_segment = 0xF000 ;
|
||||
_rom_idt_offset = _rom_gdt_offset + _gdt_size ;
|
||||
|
||||
_ram_idt_segment = 0x0000 ;
|
||||
_ram_idt_offset = _ram_gdt_offset + _gdt_size ;
|
||||
|
||||
.idt _ram_idt_offset :
|
||||
AT ( _rom_idt )
|
||||
{
|
||||
_sidt = .;
|
||||
*(.idt);
|
||||
_eidt = ALIGN (0x10);
|
||||
}
|
||||
_cs4_idt_segment = 0x0120;
|
||||
_cs4_idt_offset = 0x0000 ;
|
||||
_cs6_t_idt_segment = 0xF000 ;
|
||||
_cs6_t_idt_offset = _cs6_t_ints_size + _cs6_t_gdt_size ; /* was 0x1000 */
|
||||
_cs6_t_idt_size = _eidt - _sidt;
|
||||
_idt_size = _eidt - _sidt;
|
||||
|
||||
_rom_data_start = _rom_idt + _cs6_t_idt_size ;
|
||||
.data :
|
||||
AT ( _rom_data_start ) /* was 0x3fd0000 */
|
||||
/****************************************************************************************
|
||||
* data section:
|
||||
*
|
||||
* This section defines the locations of the data section in ROM as well as in RAM.
|
||||
* start.s copies the data section to RAM when in protected mode.
|
||||
***********************************************************************************/
|
||||
|
||||
_rom_data_start = _rom_idt + _idt_size ;
|
||||
|
||||
.data :
|
||||
AT ( _rom_data_start )
|
||||
{
|
||||
_sdata = .;
|
||||
*(.data);
|
||||
_edata = ALIGN( 0x10 ) ;
|
||||
}
|
||||
_data_start = ADDR(.data) ;
|
||||
data_start = _data_start ;
|
||||
_data_size = _edata - _sdata ;
|
||||
_edata = _data_start + _data_size ;
|
||||
|
||||
/**************************************************************************************
|
||||
* bss section:
|
||||
*
|
||||
* The bss section is the last section in RAM.
|
||||
*************************************************************************************/
|
||||
.bss :
|
||||
{
|
||||
_bss_start = .;
|
||||
@@ -81,11 +133,29 @@ SECTIONS
|
||||
_end = end;
|
||||
__end = end;
|
||||
}
|
||||
_bss_size = _ebss - _bss_start ;
|
||||
_bss_size = _ebss - _bss_start ;
|
||||
|
||||
|
||||
/**************************************************************************************
|
||||
* General variables:
|
||||
*
|
||||
* The stack_size variable is customizable here. The heap is located directly after
|
||||
* The stack in RAM. A routine within bspstart.c uses these variables to ensure that
|
||||
* the heap used by RTEMS is as large as the RAM remaining after all workspace configurations
|
||||
* are complete.
|
||||
*************************************************************************************/
|
||||
stack_size = 0x1000 ;
|
||||
stack_origin = end + stack_size ;
|
||||
heap_bottom = stack_origin + 4 ;
|
||||
|
||||
/***************************************************************************************
|
||||
* text section:
|
||||
*
|
||||
* This section is NOT copied into RAM. It is left in ROM, as the flash ROM is quick enough.
|
||||
***************************************************************************************/
|
||||
.text ( 0x3f80000 ):
|
||||
{
|
||||
CREATE_OBJECT_SYMBOLS
|
||||
text_start = . ;
|
||||
_text_start = . ;
|
||||
*(.text ) ;
|
||||
. = ALIGN (16);
|
||||
@@ -101,24 +171,38 @@ SECTIONS
|
||||
*(.ctors)
|
||||
LONG(0)
|
||||
__CTOR_END__ = .;
|
||||
. = ALIGN (4) ;
|
||||
__DTOR_LIST__ = .;
|
||||
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
|
||||
*(.dtors)
|
||||
LONG(0)
|
||||
__DTOR_END__ = .;
|
||||
_etext = ALIGN( 0x10 );
|
||||
_etext = ALIGN( 0x10 );
|
||||
_endtext = . ;
|
||||
}
|
||||
|
||||
.initial 0x3ff1000:
|
||||
/*******************************************************************************************
|
||||
* initial section:
|
||||
*
|
||||
* This section is defined after the data section. It must be in the top 64K of memory
|
||||
* to enable the initial short jmp from the reset section while still in real-mode. It
|
||||
* contains ALL initialization and data movement directives.
|
||||
******************************************************************************************/
|
||||
|
||||
.initial _rom_data_start + _data_size :
|
||||
{
|
||||
*(.initial);
|
||||
}
|
||||
|
||||
.reset 0x3fffff0:
|
||||
/*******************************************************************************************
|
||||
* reset section:
|
||||
*
|
||||
* This section contains the short jmp from the reset section to the initial section. It is
|
||||
* the first code executed on reset/power on.
|
||||
******************************************************************************************/
|
||||
|
||||
.reset 0x3fffff0:
|
||||
{
|
||||
*(.reset);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user