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powerpc/beatnik: Fix warnings

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This commit is contained in:
Joel Sherrill
2014-10-19 17:00:56 -05:00
parent 9b7631105c
commit 2cb449d2f3
6 changed files with 432 additions and 396 deletions
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c/src/lib/libbsp/powerpc/beatnik/include/bsp.h
+85 -55
View File
@@ -1,6 +1,8 @@
/*
* bsp.h -- contain BSP API definition.
*
*/
/*
* Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
*
* The license and distribution terms for this file may be
@@ -11,9 +13,12 @@
*
* Modified for the 'beatnik' BSP by T. Straumann, 2005-2007.
*/
#ifndef LIBBSP_BEATNIK_BSP_H
#define LIBBSP_BEATNIK_BSP_H
#ifndef ASM
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
@@ -24,26 +29,25 @@
#include <bsp/vectors.h>
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Board type */
typedef enum {
Unknown = 0,
MVME5500,
MVME6100
Unknown = 0,
MVME5500,
MVME6100
} BSP_BoardType;
BSP_BoardType
BSP_getBoardType();
BSP_BoardType BSP_getBoardType(void);
/* Discovery Version */
typedef enum {
unknown = 0,
GT_64260_A, /* Revision 0x10 */
GT_64260_B, /* Revision 0x20 */
MV_64360,
unknown = 0,
GT_64260_A, /* Revision 0x10 */
GT_64260_B, /* Revision 0x20 */
MV_64360,
} DiscoveryVersion;
/* Determine the type of discovery chip on this board; info
@@ -52,9 +56,7 @@ typedef enum {
* If a non-zero argument is passed, the routine panics
* (BSP_panic) if no recognized bridge is found;
*/
DiscoveryVersion
BSP_getDiscoveryVersion(int assertion);
DiscoveryVersion BSP_getDiscoveryVersion(int assertion);
/*
* confdefs.h overrides for this BSP:
@@ -65,18 +67,18 @@ BSP_getDiscoveryVersion(int assertion);
/*
* base address definitions for several devices
*/
#define BSP_MV64x60_BASE (0xf1000000)
#define BSP_MV64x60_DEV1_BASE (0xf1100000)
#define BSP_UART_IOBASE_COM1 ((BSP_MV64x60_DEV1_BASE)+0x20000)
#define BSP_UART_IOBASE_COM2 ((BSP_MV64x60_DEV1_BASE)+0x21000)
#define BSP_MV64x60_BASE (0xf1000000)
#define BSP_MV64x60_DEV1_BASE (0xf1100000)
#define BSP_UART_IOBASE_COM1 ((BSP_MV64x60_DEV1_BASE)+0x20000)
#define BSP_UART_IOBASE_COM2 ((BSP_MV64x60_DEV1_BASE)+0x21000)
#define BSP_UART_USE_SHARED_IRQS
#define BSP_NVRAM_BASE_ADDR (0xf1110000)
#define BSP_NVRAM_END_ADDR (0xf1117fff)
#define BSP_NVRAM_RTC_START (0xf1117ff8)
#define BSP_NVRAM_BASE_ADDR (0xf1110000)
#define BSP_NVRAM_END_ADDR (0xf1117fff)
#define BSP_NVRAM_RTC_START (0xf1117ff8)
#define BSP_NVRAM_BOOTPARMS_START (0xf1111000)
#define BSP_NVRAM_BOOTPARMS_END (0xf1111fff)
#define BSP_NVRAM_BOOTPARMS_START (0xf1111000)
#define BSP_NVRAM_BOOTPARMS_END (0xf1111fff)
/* This is only active/used during early init. It defines
@@ -85,18 +87,22 @@ BSP_getDiscoveryVersion(int assertion);
* override the PCI configuration (see gt_pci_init.c:BSP_pci_initialize)
*/
#define PCI_CONFIG_ADDR (BSP_MV64x60_BASE + 0xcf8)
#define PCI_CONFIG_DATA (BSP_MV64x60_BASE + 0xcfc)
#define PCI_CONFIG_ADDR (BSP_MV64x60_BASE + 0xcf8)
#define PCI_CONFIG_DATA (BSP_MV64x60_BASE + 0xcfc)
/* our wonderful PCI initialization remaps everything to CPU addresses
* - before calling BSP_pci_initialize() this is NOT VALID, however
* and the deprecated inl()/outl() etc won't work!
*/
#define _IO_BASE 0x00000000
/* wonderful MotLoad has the base address as seen from the CPU programmed into config space :-) */
#define PCI_MEM_BASE 0
#define PCI_MEM_BASE_ADJUSTMENT 0
#define PCI_DRAM_OFFSET 0
#define _IO_BASE 0x00000000
/* wonderful MotLoad has the base address as seen from the
* CPU programmed into config space :-)
*/
#define PCI_MEM_BASE 0
#define PCI_MEM_BASE_ADJUSTMENT 0
#define PCI_DRAM_OFFSET 0
extern void BSP_motload_pci_fixup(void);
/* PCI <-> local address mapping - no sophisticated windows
* (i.e., no support for cached regions etc. you read a BAR
@@ -106,20 +112,20 @@ BSP_getDiscoveryVersion(int assertion);
#define BSP_PCI2LOCAL_ADDR(a) ((uint32_t)(a))
#define BSP_LOCAL2PCI_ADDR(a) ((uint32_t)(a))
#define BSP_CONFIG_NUM_PCI_CACHE_SLOTS 32
#define BSP_CONFIG_NUM_PCI_CACHE_SLOTS 32
#define BSP_CONSOLE_PORT BSP_UART_COM1
#define BSP_UART_BAUD_BASE 115200
#define BSP_CONSOLE_PORT BSP_UART_COM1
#define BSP_UART_BAUD_BASE 115200
/* I2C Devices */
/* Note that the i2c addresses stated in the manual are
* left-shifted by one bit.
*/
#define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */
#define BSP_USR_I2C_ADDR (0xAA>>1) /* the user EEPROM */
#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */
#define BSP_VPD_I2C_ADDR (0xA8>>1) /* the VPD EEPROM */
#define BSP_USR_I2C_ADDR (0xAA>>1) /* the user EEPROM */
#define BSP_THM_I2C_ADDR (0x90>>1) /* the DS1621 temperature sensor & thermostat */
#define BSP_I2C_BUS_DESCRIPTOR gt64260_i2c_bus_descriptor
#define BSP_I2C_BUS_DESCRIPTOR gt64260_i2c_bus_descriptor
#define BSP_I2C_BUS0_NAME "/dev/i2c0"
@@ -129,11 +135,11 @@ BSP_getDiscoveryVersion(int assertion);
#define BSP_I2C_THM_NAME BSP_I2C_DS1621_NAME
#define BSP_I2C_DS1621_RAW_NAME "ds1621-raw"
#define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME)
#define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME)
#define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME)
#define BSP_I2C_VPD_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_VPD_EEPROM_NAME)
#define BSP_I2C_USR_EEPROM_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_USR_EEPROM_NAME)
#define BSP_I2C_DS1621_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_NAME)
#define BSP_I2C_THM_DEV_NAME BSP_I2C_DS1621_DEV_NAME
#define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME)
#define BSP_I2C_DS1621_RAW_DEV_NAME (BSP_I2C_BUS0_NAME"."BSP_I2C_DS1621_RAW_NAME)
/* Initialize the I2C driver and register all devices
@@ -148,8 +154,7 @@ BSP_getDiscoveryVersion(int assertion);
* /dev/i2c0.ds1621 (read-only; one byte: board-temp in degC)
* /dev/i2c0.ds1621-raw (read-write; transfer bytes to/from the ds1621)
*/
int
BSP_i2c_initialize();
int BSP_i2c_initialize(void);
/* Networking; */
#if defined(RTEMS_NETWORKING)
@@ -157,27 +162,29 @@ BSP_i2c_initialize();
#endif
/* NOT FOR PUBLIC USE BELOW HERE */
#define BSP_PCI_HOSE0_MEM_BASE 0x80000000 /* must be aligned to size */
#define BSP_PCI_HOSE0_MEM_SIZE 0x20000000
#define BSP_PCI_HOSE0_MEM_BASE 0x80000000 /* must be aligned to size */
#define BSP_PCI_HOSE0_MEM_SIZE 0x20000000
#define BSP_PCI_HOSE1_MEM_BASE 0xe0000000
#define BSP_PCI_HOSE1_MEM_BASE 0xe0000000
#define BSP_DEV_AND_PCI_IO_BASE 0xf0000000
#define BSP_DEV_AND_PCI_IO_SIZE 0x10000000
#define BSP_DEV_AND_PCI_IO_BASE 0xf0000000
#define BSP_DEV_AND_PCI_IO_SIZE 0x10000000
/* maintain coherency between CPU and GT64340 ethernet (& possibly other discovery components) */
#define BSP_RW_PAGE_ATTRIBUTES TRIV121_ATTR_M
/* maintain coherency between CPU and GT64340 Ethernet
* (andpossibly other Discovery components).
*/
#define BSP_RW_PAGE_ATTRIBUTES TRIV121_ATTR_M
extern unsigned BSP_pci_hose1_bus_base;
void BSP_pci_initialize();
void BSP_pci_initialize(void);
/* Exception Handling */
/* Use a task notepad to attach user exception handler info;
* may be changed by application startup code (EPICS uses 11)
*/
#define BSP_EXCEPTION_NOTEPAD 14
#define BSP_EXCEPTION_NOTEPAD 14
#ifndef ASM
@@ -257,14 +264,37 @@ extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
* 16-bit error status on error.
*
*/
extern unsigned short
(*_BSP_clear_vmebridge_errors)(int);
extern unsigned short (*_BSP_clear_vmebridge_errors)(int);
/*
* Prototypes for debug helpers
*/
void discovery_pic_set_debug_irq(int on);
void discovery_pic_install_debug_irq(void);
/*
* Prototypes for methods called only from .S for dependency tracking
*/
char *save_boot_params(
void *r3,
void *r4,
void *r5,
char *cmdline_start,
char *cmdline_end
);
void zero_bss(void);
/*
* Prototypes for methods in the BSP that cross file boundaries
*/
uint32_t probeMemoryEnd(void);
#endif
#ifdef __cplusplus
}
}
#endif
#endif /* !ASM */
#endif
c/src/lib/libbsp/powerpc/beatnik/irq/discovery_pic.c
+1 -1
View File
@@ -196,7 +196,7 @@ int i;
}
}
void discovery_dump_picregs(void)
static void discovery_dump_picregs(void)
{
printk(" ..GPP_IRQ. -- ..MAIN_HI. -- ..MAIN_LO.\n");
printk("Cause:"); pregs(thePic.causes);
c/src/lib/libbsp/powerpc/beatnik/marvell/gt_timer.c
+190 -190
View File
File diff suppressed because it is too large Load Diff
c/src/lib/libbsp/powerpc/beatnik/pci/pci_io_remap.c
+107 -109
View File
@@ -5,13 +5,13 @@
* ----------
* This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was
* created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
* Stanford Linear Accelerator Center, Stanford University.
* Stanford Linear Accelerator Center, Stanford University.
*
* Acknowledgement of sponsorship
* ------------------------------
* The 'beatnik' BSP was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
* Government disclaimer of liability
* ----------------------------------
@@ -49,6 +49,7 @@
#include <rtems/bspIo.h>
#include <bsp/pci.h>
#include <stdint.h>
#include "pci_io_remap.h"
#ifndef PCI_MULTI_FUN
#define PCI_MULTI_FUN 0x80
@@ -64,142 +65,139 @@
* of PCI-PCI bridges, too.
*
* RESTRICTIONS: 'offset' must be 4k aligned (PCI req.); no argument check
* on the bus numbers is done.
* on the bus numbers is done.
*
* RETURNS: 0 on success and a number > 0 indicating the number of
* non-32bit bridges found where the offset couldn't be added.
* Devices behind such a bridge are not accessible through I/O
* and should probably be switched off (not done by this code).
*/
int
rtems_pci_io_remap(int bus_from, int bus_to, uint32_t offset)
{
int rval = 0;
int rval = 0;
int bus, dev, fun, maxf;
int bar, numBars = 0;
uint8_t b;
uint16_t s;
uint32_t d;
unsigned int bas, lim;
int bus, dev, fun, maxf;
int bar, numBars = 0;
uint8_t b;
uint16_t s;
uint32_t d;
unsigned int bas, lim;
if ( offset & ((1<<12)-1) ) {
BSP_panic("rtems_pci_io_remap(): offset must be 4k aligned");
return -1;
}
if ( offset & ((1<<12)-1) ) {
BSP_panic("rtems_pci_io_remap(): offset must be 4k aligned");
return -1;
}
for ( bus=bus_from; bus < bus_to; bus++ ) {
for ( dev = 0; dev<PCI_MAX_DEVICES; dev++ ) {
for ( bus=bus_from; bus < bus_to; bus++ ) {
for ( dev = 0; dev<PCI_MAX_DEVICES; dev++ ) {
maxf = 1;
maxf = 1;
for ( fun = 0; fun < maxf; fun++ ) {
pci_read_config_word( bus, dev, fun, PCI_VENDOR_ID, &s );
if ( 0xffff == s )
continue;
for ( fun = 0; fun < maxf; fun++ ) {
pci_read_config_word( bus, dev, fun, PCI_VENDOR_ID, &s );
if ( 0xffff == s )
continue;
pci_read_config_byte( bus, dev, fun, PCI_HEADER_TYPE, &b );
pci_read_config_byte( bus, dev, fun, PCI_HEADER_TYPE, &b );
/* readjust the max. function number to scan if this is a multi-function
* device.
*/
if ( 0 == fun && (PCI_MULTI_FUN & b) )
maxf = PCI_MAX_FUNCTIONS;
/* readjust the max. function number to scan if this is a multi-function
* device.
*/
if ( 0 == fun && (PCI_MULTI_FUN & b) )
maxf = PCI_MAX_FUNCTIONS;
/* Check the header type; panic if unknown.
* header type 0 has 6 bars, header type 1 (PCI-PCI bridge) has 2
*/
b &= PCI_HEADER_TYPE_MSK;
switch ( b ) {
default:
printk("PCI header type %i (@%i/%i/%i)\n", b, bus, dev, fun);
BSP_panic("rtems_pci_io_remap(): unknown PCI header type");
return -1; /* keep compiler happy */
/* Check the header type; panic if unknown.
* header type 0 has 6 bars, header type 1 (PCI-PCI bridge) has 2
*/
b &= PCI_HEADER_TYPE_MSK;
switch ( b ) {
default:
printk("PCI header type %i (@%i/%i/%i)\n", b, bus, dev, fun);
BSP_panic("rtems_pci_io_remap(): unknown PCI header type");
return -1; /* keep compiler happy */
case PCI_HEADER_TYPE_CARDBUS:
printk("PCI header type %i (@%i/%i/%i)\n", b, bus, dev, fun);
BSP_panic("rtems_pci_io_remap(): don't know how to deal with Cardbus bridge");
return -1;
case PCI_HEADER_TYPE_CARDBUS:
printk("PCI header type %i (@%i/%i/%i)\n", b, bus, dev, fun);
BSP_panic("rtems_pci_io_remap(): don't know how to deal with Cardbus bridge");
return -1;
case PCI_HEADER_TYPE_NORMAL:
numBars = 6*4; /* loop below counts reg. offset in bytes */
break;
case PCI_HEADER_TYPE_NORMAL:
numBars = 6*4; /* loop below counts reg. offset in bytes */
break;
case PCI_HEADER_TYPE_BRIDGE:
numBars = 2*4; /* loop below counts reg. offset in bytes */
break;
case PCI_HEADER_TYPE_BRIDGE:
numBars = 2*4; /* loop below counts reg. offset in bytes */
break;
}
}
for ( bar = 0; bar < numBars; bar+=4 ) {
pci_read_config_dword( bus, dev, fun, PCI_BASE_ADDRESS_0 + bar, &d );
if ( PCI_BASE_ADDRESS_SPACE_IO & d ) {
/* It's an I/O BAR; remap */
d &= PCI_BASE_ADDRESS_IO_MASK;
if ( d ) {
/* IO bar was configured; add offset */
d += offset;
pci_write_config_dword( bus, dev, fun, PCI_BASE_ADDRESS_0 + bar, d );
}
} else {
/* skip upper half of 64-bit window */
d &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
if ( PCI_BASE_ADDRESS_MEM_TYPE_64 == d )
bar+=4;
}
}
for ( bar = 0; bar < numBars; bar+=4 ) {
pci_read_config_dword( bus, dev, fun, PCI_BASE_ADDRESS_0 + bar, &d );
if ( PCI_BASE_ADDRESS_SPACE_IO & d ) {
/* It's an I/O BAR; remap */
d &= PCI_BASE_ADDRESS_IO_MASK;
if ( d ) {
/* IO bar was configured; add offset */
d += offset;
pci_write_config_dword( bus, dev, fun, PCI_BASE_ADDRESS_0 + bar, d );
}
} else {
/* skip upper half of 64-bit window */
d &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
if ( PCI_BASE_ADDRESS_MEM_TYPE_64 == d )
bar+=4;
}
}
/* Now it's time to deal with bridges */
if ( PCI_HEADER_TYPE_BRIDGE == b ) {
/* must adjust the limit registers */
pci_read_config_byte( bus, dev, fun, PCI_IO_LIMIT, &b );
pci_read_config_word( bus, dev, fun, PCI_IO_LIMIT_UPPER16, &s );
lim = (s<<16) + (( b & PCI_IO_RANGE_MASK ) << 8);
lim += offset;
/* Now it's time to deal with bridges */
if ( PCI_HEADER_TYPE_BRIDGE == b ) {
/* must adjust the limit registers */
pci_read_config_byte( bus, dev, fun, PCI_IO_LIMIT, &b );
pci_read_config_word( bus, dev, fun, PCI_IO_LIMIT_UPPER16, &s );
lim = (s<<16) + (( b & PCI_IO_RANGE_MASK ) << 8);
lim += offset;
pci_read_config_byte( bus, dev, fun, PCI_IO_BASE, &b );
pci_read_config_word( bus, dev, fun, PCI_IO_BASE_UPPER16, &s );
bas = (s<<16) + (( b & PCI_IO_RANGE_MASK ) << 8);
bas += offset;
pci_read_config_byte( bus, dev, fun, PCI_IO_BASE, &b );
pci_read_config_word( bus, dev, fun, PCI_IO_BASE_UPPER16, &s );
bas = (s<<16) + (( b & PCI_IO_RANGE_MASK ) << 8);
bas += offset;
b &= PCI_IO_RANGE_TYPE_MASK;
switch ( b ) {
default:
printk("Unknown IO range type 0x%x (@%i/%i/%i)\n", b, bus, dev, fun);
BSP_panic("rtems_pci_io_remap(): unknown IO range type");
return -1;
b &= PCI_IO_RANGE_TYPE_MASK;
switch ( b ) {
default:
printk("Unknown IO range type 0x%x (@%i/%i/%i)\n", b, bus, dev, fun);
BSP_panic("rtems_pci_io_remap(): unknown IO range type");
return -1;
case PCI_IO_RANGE_TYPE_16:
if ( bas > 0xffff || lim > 0xffff ) {
printk("PCI I/O range type 1 (16bit) bridge (@%i/%i/%i) found:\n", bus, dev, fun);
printk("WARNING: base (0x%08x) or limit (0x%08x) exceed 16-bit;\n", bas, lim);
printk(" devices behind this bridge are NOT accessible!\n");
case PCI_IO_RANGE_TYPE_16:
if ( bas > 0xffff || lim > 0xffff ) {
printk("PCI I/O range type 1 (16bit) bridge (@%i/%i/%i) found:\n", bus, dev, fun);
printk("WARNING: base (0x%08x) or limit (0x%08x) exceed 16-bit;\n", bas, lim);
printk(" devices behind this bridge are NOT accessible!\n");
/* FIXME: should we disable devices behind this bridge ? */
bas = lim = 0;
}
break;
/* FIXME: should we disable devices behind this bridge ? */
bas = lim = 0;
}
break;
case PCI_IO_RANGE_TYPE_32:
break;
}
case PCI_IO_RANGE_TYPE_32:
break;
}
b = (uint8_t)((bas>>8) & PCI_IO_RANGE_MASK);
pci_write_config_byte( bus, dev, fun, PCI_IO_BASE, b );
b = (uint8_t)((bas>>8) & PCI_IO_RANGE_MASK);
pci_write_config_byte( bus, dev, fun, PCI_IO_BASE, b );
s = (uint16_t)((bas>>16)&0xffff);
pci_write_config_word( bus, dev, fun, PCI_IO_BASE_UPPER16, s);
s = (uint16_t)((bas>>16)&0xffff);
pci_write_config_word( bus, dev, fun, PCI_IO_BASE_UPPER16, s);
b = (uint8_t)((lim>>8) & PCI_IO_RANGE_MASK);
pci_write_config_byte( bus, dev, fun, PCI_IO_LIMIT, b );
s = (uint16_t)((lim>>16)&0xffff);
pci_write_config_word( bus, dev, fun, PCI_IO_LIMIT_UPPER16, s );
}
}
}
}
return rval;
b = (uint8_t)((lim>>8) & PCI_IO_RANGE_MASK);
pci_write_config_byte( bus, dev, fun, PCI_IO_LIMIT, b );
s = (uint16_t)((lim>>16)&0xffff);
pci_write_config_word( bus, dev, fun, PCI_IO_LIMIT_UPPER16, s );
}
}
}
}
return rval;
}
c/src/lib/libbsp/powerpc/beatnik/startup/bspstart.c
+7 -2
View File
@@ -143,8 +143,13 @@ char *BSP_commandline_string = cmdline_buf;
/* this routine is called early and must be safe with a not properly
* aligned stack
*/
char *
save_boot_params(void *r3, void *r4, void* r5, char *cmdline_start, char *cmdline_end)
char *save_boot_params(
void *r3,
void *r4,
void *r5,
char *cmdline_start,
char *cmdline_end
)
{
int i=cmdline_end-cmdline_start;
if ( i >= CMDLINE_BUF_SIZE )
c/src/lib/libbsp/powerpc/beatnik/vme/VMEConfig.h
+42 -39
View File
@@ -8,13 +8,13 @@
* ----------
* This software ('beatnik' RTEMS BSP for MVME6100 and MVME5500) was
* created by Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
* Stanford Linear Accelerator Center, Stanford University.
* Stanford Linear Accelerator Center, Stanford University.
*
* Acknowledgement of sponsorship
* ------------------------------
* The 'beatnik' BSP was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
* Government disclaimer of liability
* ----------------------------------
@@ -56,56 +56,59 @@
* hardcoded window lengths that match this
* layout when setting BATs:
*/
#define _VME_A32_WIN0_ON_PCI 0x90000000
#define _VME_A32_WIN0_ON_PCI 0x90000000
/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate
* CSR for space.
*/
#define _VME_CSR_ON_PCI 0x9e000000
#define _VME_A24_ON_PCI 0x9f000000
#define _VME_A16_ON_PCI 0x9fff0000
#define _VME_CSR_ON_PCI 0x9e000000
#define _VME_A24_ON_PCI 0x9f000000
#define _VME_A16_ON_PCI 0x9fff0000
/* start of the A32 window on the VME bus
* TODO: this should perhaps be a configuration option
*/
#define _VME_A32_WIN0_ON_VME 0x20000000
#define _VME_A32_WIN0_ON_VME 0x20000000
/* if _VME_DRAM_OFFSET is defined, the BSP
* will map our RAM onto the VME bus, starting
* at _VME_DRAM_OFFSET
*/
#define _VME_DRAM_OFFSET 0x90000000
#define _VME_DRAM_OFFSET 0x90000000
#define BSP_VME_INSTALL_IRQ_MGR(err) \
do { \
err = -1; \
switch (BSP_getBoardType()) { \
case MVME6100: \
err = theOps->install_irq_mgr( \
VMETSI148_IRQ_MGR_FLAG_SHARED, \
0, BSP_IRQ_GPP_0 + 20, \
1, BSP_IRQ_GPP_0 + 21, \
2, BSP_IRQ_GPP_0 + 22, \
3, BSP_IRQ_GPP_0 + 23, \
-1); \
break; \
\
case MVME5500: \
err = theOps->install_irq_mgr( \
VMEUNIVERSE_IRQ_MGR_FLAG_SHARED | \
VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND, \
0, BSP_IRQ_GPP_0 + 12, \
1, BSP_IRQ_GPP_0 + 13, \
2, BSP_IRQ_GPP_0 + 14, \
3, BSP_IRQ_GPP_0 + 15, \
-1); \
break; \
\
default: \
printk("WARNING: unknown board; "); \
break; \
} \
if ( err ) \
printk("VME interrupt manager NOT INSTALLED (error: %i)\n", err); \
extern int BSP_VMEInit(void);
extern int BSP_VMEIrqMgrInstall(void);
#define BSP_VME_INSTALL_IRQ_MGR(err) \
do { \
err = -1; \
switch (BSP_getBoardType()) { \
case MVME6100: \
err = theOps->install_irq_mgr( \
VMETSI148_IRQ_MGR_FLAG_SHARED, \
0, BSP_IRQ_GPP_0 + 20, \
1, BSP_IRQ_GPP_0 + 21, \
2, BSP_IRQ_GPP_0 + 22, \
3, BSP_IRQ_GPP_0 + 23, \
-1); \
break; \
\
case MVME5500: \
err = theOps->install_irq_mgr( \
VMEUNIVERSE_IRQ_MGR_FLAG_SHARED | \
VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND, \
0, BSP_IRQ_GPP_0 + 12, \
1, BSP_IRQ_GPP_0 + 13, \
2, BSP_IRQ_GPP_0 + 14, \
3, BSP_IRQ_GPP_0 + 15, \
-1); \
break; \
\
default: \
printk("WARNING: unknown board; "); \
break; \
} \
if ( err ) \
printk("VME interrupt manager NOT INSTALLED (error: %i)\n", err); \
} while (0)
#endif