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bsp/xilinx-zynq: Add cache support

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This commit is contained in:
Ric Claus
2013-08-26 09:53:06 +02:00
committed by Sebastian Huber
parent 2f0d5e453b
commit 2bd440ed58
3 changed files with 906 additions and 3 deletions
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c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
+2 -2
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@@ -123,8 +123,8 @@ libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
libbsp_a_SOURCES += include/cache_.h
libbsp_a_CPPFLAGS += -I$(srcdir)/include
# Start hooks
libbsp_a_SOURCES += startup/bspstarthooks.c
c/src/lib/libbsp/arm/xilinx-zynq/include/cache_.h
+886
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File diff suppressed because it is too large Load Diff
c/src/lib/libcpu/shared/src/cache_manager.c
+18 -1
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@@ -19,6 +19,11 @@
*
* rtems/c/src/lib/libcpu/CPU/cache_.h
*
* The cache implementation header file can define
* CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
* if it provides cache maintenance functions which operate on multiple lines.
* Otherwise a generic loop with single line operations will be used.
*
* The functions below are implemented with CPU dependent inline routines
* found in the cache.c files for each CPU. In the event that a CPU does
* not support a specific function for a cache it has, the CPU dependent
@@ -46,6 +51,9 @@ void
rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
{
#if defined(CPU_DATA_CACHE_ALIGNMENT)
#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
_CPU_cache_flush_data_range( d_addr, n_bytes );
#else
const void * final_address;
/*
@@ -65,6 +73,7 @@ rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
}
#endif
#endif
}
@@ -78,6 +87,9 @@ void
rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes )
{
#if defined(CPU_DATA_CACHE_ALIGNMENT)
#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
_CPU_cache_invalidate_data_range( d_addr, n_bytes );
#else
const void * final_address;
/*
@@ -97,6 +109,7 @@ rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes
d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
}
#endif
#endif
}
@@ -204,7 +217,10 @@ rtems_cache_disable_data( void )
void
rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes )
{
#if CPU_INSTRUCTION_CACHE_ALIGNMENT
#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
_CPU_cache_invalidate_instruction_range( i_addr, n_bytes );
#else
const void * final_address;
/*
@@ -224,6 +240,7 @@ rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n
i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
}
#endif
#endif
}