mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-22 07:17:00 +08:00
2002-02-28 Mike Panetta <ahuitzot@mindspring.com>
* console/sci.c, console/sci.h, console/console.c: Added new SCI driver. * start/start.c: Removed file. * start/start.S: New file, the asm portion of the updated start code. * start/configure.am: Added start.S, removed start.c * startup/start_c.c: New file, the C portion of the updated start code. Contains most of the code that was in the old start.c. * startup/configure.am: Added start_c.c to C_FILES. * include/bsp.h: Added include <rtems/bspIo.h>
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,14 @@
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2002-02-28 Mike Panetta <ahuitzot@mindspring.com>
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* console/sci.c, console/sci.h,
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console/console.c: Added new SCI driver.
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* start/start.c: Removed file.
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* start/start.S: New file, the asm portion of the updated start code.
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* start/configure.am: Added start.S, removed start.c
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* startup/start_c.c: New file, the C portion of the updated start code. Contains most of the code that was in the old start.c.
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* startup/configure.am: Added start_c.c to C_FILES.
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* include/bsp.h: Added include <rtems/bspIo.h>
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2001-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* configure.ac: Introduce RTEMS_BSP_CONFIGURE.
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@@ -6,9 +6,11 @@ AUTOMAKE_OPTIONS = foreign 1.4
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PGM = $(ARCH)/console.rel
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C_FILES = console.c
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C_FILES = console.c sci.c
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C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
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H_FILES = sci.h
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OBJS = $(C_O_FILES)
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include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,245 @@
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/****************************************************************************
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* File: sci.h
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*
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* Desc: This is the include file for the serial communications interface.
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*
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* Note: See bsp.h,confdefs.h,system.h for installing drivers into RTEMS.
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*
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* $Id$
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****************************************************************************/
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#ifndef _sci_h_
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#define _sci_h_
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/*******************************************************************************
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IOCTL commands for the sci driver.
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I'm still working on these...
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*******************************************************************************/
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#define SCI_IOCTL_PARITY_NONE 0x00 // no parity bit after the data bits
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#define SCI_IOCTL_PARITY_ODD 0x01 // parity bit added after data bits
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#define SCI_IOCTL_PARITY_EVEN 0x02 // parity bit added after data bits
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#define SCI_IOCTL_PARITY_MARK 0x03 // parity bit is lo, -12 volts, logical 1
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#define SCI_IOCTL_PARITY_SPACE 0x04 // parity bit is hi, +12 volts, logical 0
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#define SCI_IOCTL_PARITY_FORCED_ON 0x03 // parity bit is forced hi or lo
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#define SCI_IOCTL_PARITY_FORCED_OFF 0x04 // parity bit is forced hi or lo
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#define SCI_IOCTL_BAUD_RATE 0x20 // set the baud rate, arg is baud
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#define SCI_IOCTL_DATA_BITS 0x30 // set the data bits, arg is # bits
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#define SCI_IOCTL_STOP_BITS_1 0x40 // 1 stop bit after char frame
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#define SCI_IOCTL_STOP_BITS_2 0x41 // 2 stop bit after char frame
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#define SCI_IOCTL_MODE_NORMAL 0x50 // normal operating mode
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#define SCI_IOCTL_MODE_LOOP 0x51 // internal loopback mode
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#define SCI_IOCTL_FLOW_NONE 0x60 // no flow control
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#define SCI_IOCTL_FLOW_RTS_CTS 0x61 // hardware flow control
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#define SCI_IOCTL_SEND_BREAK 0x70 // send an rs-232 break
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#define SCI_IOCTL_MODE_1200 0x80 // 1200,n,8,1 download mode
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#define SCI_IOCTL_MODE_9600 0x81 // 9600,n,8,1 download mode
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#define SCI_IOCTL_MODE_9_BIT 0x82 // 9600,forced,8,1 command mode
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/*******************************************************************************
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SCI Registers
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*******************************************************************************/
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// SCI Control Register 0 (SCCR0) $FFFC08
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// 8 4 2 1 - 8 4 2 1 - 8 4 2 1 - 8 4 2 1
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// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
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// | | | | | | | | | | | | | | | |
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// | | | | | | | | | | | | | | | +----- 0 baud rate divisor
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// | | | | | | | | | | | | | | +------- 1 baud rate divisor
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// | | | | | | | | | | | | | +--------- 2 baud rate divisor
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// | | | | | | | | | | | | +----------- 3 baud rate divisor
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// | | | | | | | | | | | |
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// | | | | | | | | | | | +--------------- 4 baud rate divisor
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// | | | | | | | | | | +----------------- 5 baud rate divisor
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// | | | | | | | | | +------------------- 6 baud rate divisor
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// | | | | | | | | +--------------------- 7 baud rate divisor
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// | | | | | | | |
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// | | | | | | | +------------------------- 8 baud rate divisor
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// | | | | | | +--------------------------- 9 baud rate divisor
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// | | | | | +----------------------------- 10 baud rate divisor
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// | | | | +------------------------------- 11 baud rate divisor
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// | | | |
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// | | | +----------------------------------- 12 baud rate divisor
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// | | +------------------------------------- 13 unused
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// | +--------------------------------------- 14 unused
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// +----------------------------------------- 15 unused
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// 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 1 0 0 reset value - (64k baud?)
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#define SCI_BAUD_57_6K 9
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#define SCI_BAUD_38_4K 14
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#define SCI_BAUD_19_2K 27
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#define SCI_BAUD_9600 55
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#define SCI_BAUD_4800 109
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#define SCI_BAUD_2400 218
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#define SCI_BAUD_1200 437
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// SCI Control Register 1 (SCCR1) $FFFC0A
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// 8 4 2 1 - 8 4 2 1 - 8 4 2 1 - 8 4 2 1
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// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
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// | | | | | | | | | | | | | | | |
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// | | | | | | | | | | | | | | | +----- 0 send a break
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// | | | | | | | | | | | | | | +------- 1 rcvr wakeup mode
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// | | | | | | | | | | | | | +--------- 2 rcvr enable
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// | | | | | | | | | | | | +----------- 3 xmtr enable
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// | | | | | | | | | | | |
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// | | | | | | | | | | | +--------------- 4 idle line intr enable
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// | | | | | | | | | | +----------------- 5 rcvr intr enable
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// | | | | | | | | | +------------------- 6 xmit complete intr enable
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// | | | | | | | | +--------------------- 7 xmtr intr enable
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// | | | | | | | |
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// | | | | | | | +------------------------- 8 wakeup on address mark
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// | | | | | | +--------------------------- 9 mode 1=9 bits, 0=8 bits
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// | | | | | +----------------------------- 10 parity enable 1=on, 0=off
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// | | | | +------------------------------- 11 parity type 1=odd, 0=even
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// | | | |
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// | | | +----------------------------------- 12 idle line select
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// | | +------------------------------------- 13 wired-or mode
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// | +--------------------------------------- 14 loop mode
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// +----------------------------------------- 15 unused
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// 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 reset value
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#define SCI_SEND_BREAK 0x0001 // 0000-0000-0000-0001
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#define SCI_RCVR_WAKEUP 0x0002 // 0000-0000-0000-0010
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#define SCI_ENABLE_RCVR 0x0004 // 0000-0000-0000-0100
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#define SCI_ENABLE_XMTR 0x0008 // 0000-0000-0000-1000
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#define SCI_DISABLE_RCVR 0xFFFB // 1111-1111-1111-1011
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#define SCI_DISABLE_XMTR 0xFFF7 // 1111-1111-1111-0111
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#define SCI_ENABLE_INT_IDLE 0x0010 // 0000-0000-0001-0000
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#define SCI_ENABLE_INT_RX 0x0020 // 0000-0000-0010-0000
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#define SCI_ENABLE_INT_TX_DONE 0x0040 // 0000-0000-0100-0000
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#define SCI_ENABLE_INT_TX 0x0080 // 0000-0000-1000-0000
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#define SCI_DISABLE_INT_ALL 0xFF00 // 1111-1111-0000-0000 ???
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#define SCI_DISABLE_INT_RX 0xFFDF // 1111-1111-1101-1111
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#define SCI_CLEAR_RX_INT 0xFFBF // 1111-1111-1011-1111
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#define SCI_DISABLE_INT_TX 0xFF7F // 1111-1111-0111-1111
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#define SCI_CLEAR_TDRE 0xFEFF // 1111-1110-1111-1111
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#define SCI_RCVR_WAKE_ON_MARK 0x0100 // 0000-0001-0000-0000
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#define SCI_9_DATA_BITS 0x0200 // 0000-0010-0000-0000
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#define SCI_PARITY_ENABLE 0x0400 // 0000-0100-0000-0000
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#define SCI_PARITY_ODD 0x0800 // 0000-1000-0000-0000
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#define SCI_RCVR_WAKE_ON_IDLE 0xFEFF // 1111-1110-1111-1111
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#define SCI_8_DATA_BITS 0xFDFF // 1111-1101-1111-1111
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#define SCI_PARITY_DISABLE 0xFBFF // 1111-1011-1111-1111
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#define SCI_PARITY_EVEN 0xF7FF // 1111-0111-1111-1111
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#define SCI_PARITY_NONE 0xF3FF // 1111-0011-1111-1111
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#define SCI_IDLE_LINE_LONG 0x1000 // 0001-0000-0000-0000
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#define SCI_TXD_OPEN_DRAIN 0x2000 // 0010-0000-0000-0000
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#define SCI_LOOPBACK_MODE 0x4000 // 0100-0000-0000-0000
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#define SCI_SCCR1_UNUSED 0x8000 // 1000-0000-0000-0000
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// SCI Status Register (SCSR) $FFFC0C
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// 8 4 2 1 - 8 4 2 1 - 8 4 2 1 - 8 4 2 1
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// ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
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// | | | | | | | | | | | | | | | |
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// | | | | | | | | | | | | | | | +----- 0 PF - parity error
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// | | | | | | | | | | | | | | +------- 1 FE - framing error
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// | | | | | | | | | | | | | +--------- 2 NF - noise flag
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// | | | | | | | | | | | | +----------- 3 OR - overrun flag
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// | | | | | | | | | | | |
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// | | | | | | | | | | | +--------------- 4 IDLE - idle line detected
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// | | | | | | | | | | +----------------- 5 RAF - rcvr active flag
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// | | | | | | | | | +------------------- 6 RDRF - rcv data reg full
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// | | | | | | | | +--------------------- 7 TC - xmt complete flag
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// | | | | | | | |
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// | | | | | | | +------------------------- 8 TDRE - xmt data reg empty
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// | | | | | | +--------------------------- 9 always zero
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// | | | | | +----------------------------- 10 always zero
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// | | | | +------------------------------- 11 always zero
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// | | | |
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// | | | +----------------------------------- 12 always zero
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// | | +------------------------------------- 13 always zero
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// | +--------------------------------------- 14 always zero
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// +----------------------------------------- 15 always zero
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// 0 0 0 0 - 0 0 0 1 - 1 0 0 0 - 0 0 0 0 reset value
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#define SCI_ERROR_PARITY 0x0001 // 0000-0000-0000-0001
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#define SCI_ERROR_FRAMING 0x0002 // 0000-0000-0000-0010
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#define SCI_ERROR_NOISE 0x0004 // 0000-0000-0000-0100
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#define SCI_ERROR_OVERRUN 0x0008 // 0000-0000-0000-1000
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#define SCI_IDLE_LINE 0x0010 // 0000-0000-0001-0000
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#define SCI_RCVR_ACTIVE 0x0020 // 0000-0000-0010-0000
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#define SCI_RCVR_READY 0x0040 // 0000-0000-0100-0000
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#define SCI_XMTR_IDLE 0x0080 // 0000-0000-1000-0000
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#define SCI_CLEAR_RX_INT 0xFFBF // 1111-1111-1011-1111
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#define SCI_XMTR_READY 0x0100 // 0000-0001-0000-0000
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#define SCI_CLEAR_TDRE 0xFEFF // 1111-1110-1111-1111
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#define SCI_XMTR_AVAILABLE 0x0180 // 0000-0001-1000-0000
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/*******************************************************************************
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Function prototypes
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*******************************************************************************/
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#ifdef __cplusplus
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extern "C" {
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#endif
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// look at console_open to see how this is called
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const rtems_termios_callbacks * SciGetTermiosHandlers( signed32 polled );
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/* SCI interrupt */
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//rtems_isr SciIsr( rtems_vector_number vector );
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//signed32 SciOpenPolled ( signed32 major, signed32 minor, void *arg );
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//signed32 SciOpenInterrupt ( signed32 major, signed32 minor, void *arg );
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//signed32 SciClose ( signed32 major, signed32 minor, void *arg );
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//signed32 SciWritePolled ( signed32 minor, const char *buf, signed32 len );
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//signed32 SciWriteInterrupt( signed32 minor, const char *buf, signed32 len );
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//signed32 SciReadPolled ( signed32 minor );
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//signed32 SciSetAttributes ( signed32 minor, const struct termios *t );
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#ifdef __cplusplus
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}
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#endif
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#endif // _sci_h_
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@@ -22,6 +22,7 @@ extern "C" {
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#include <bspopts.h>
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#include <rtems.h>
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#include <rtems/bspIo.h>
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#include <clockdrv.h>
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#include <console.h>
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#include <iosupp.h>
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@@ -35,6 +36,7 @@ extern "C" {
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* - Interrupt stack space is not minimum if defined.
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*/
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#define CONSOLE_SCI
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/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
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/* #define CONFIGURE_INTERRUPT_STACK_MEMORY (TBD * 1024) */
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@@ -102,7 +104,7 @@ extern char _copy_data_from_rom[];
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#define RAW_PUTS(str) \
|
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{ register char *ptr = str; \
|
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while (*ptr) outbyte(*ptr++); \
|
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while (*ptr) SCI_output_char(*ptr++); \
|
||||
}
|
||||
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#define RAW_PUTI(n) { \
|
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@@ -111,7 +113,7 @@ extern char _copy_data_from_rom[];
|
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RAW_PUTS("0x"); \
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for (i=28;i>=0;i -= 4) { \
|
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j = (n>>i) & 0xf; \
|
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outbyte( (j>9 ? j-10+'a' : j+'0') ); \
|
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SCI_output_char( (j>9 ? j-10+'a' : j+'0') ); \
|
||||
} \
|
||||
}
|
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|
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|
||||
@@ -33,7 +33,7 @@
|
||||
/* System Clock definitions */
|
||||
#define XTAL 32768.0 /* crystal frequency in Hz */
|
||||
|
||||
#if 0
|
||||
#if 1
|
||||
/* Default MRM clock rate (8.388688 MHz) set by CPU32: */
|
||||
#define MRM_W 0 /* system clock parameters */
|
||||
#define MRM_X 0
|
||||
@@ -47,7 +47,7 @@
|
||||
#define MRM_Y 0x0f
|
||||
#endif
|
||||
|
||||
#if 1
|
||||
#if 0
|
||||
/* 25.16582 MHz: */
|
||||
#define MRM_W 1 /* system clock parameters */
|
||||
#define MRM_X 1
|
||||
@@ -60,6 +60,8 @@
|
||||
|
||||
/* macros/functions */
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
/*
|
||||
* This prototype really should have the noreturn attribute but
|
||||
* that causes a warning. Not sure how to fix that.
|
||||
@@ -68,4 +70,6 @@
|
||||
static void reboot(void);
|
||||
__inline__ static void reboot() {asm("trap #15; .word 0x0063");}
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* _MRM_H_ */
|
||||
|
||||
@@ -33,7 +33,7 @@ rtems_isr Spurious_Isr(
|
||||
rtems_vector_number vector
|
||||
)
|
||||
{
|
||||
int sp = 0;
|
||||
//int sp = 0;
|
||||
const char * const VectDescrip[] = {
|
||||
_Spurious_Error_[0], _Spurious_Error_[0], _Spurious_Error_[1],
|
||||
_Spurious_Error_[2], _Spurious_Error_[3], _Spurious_Error_[4],
|
||||
@@ -58,11 +58,11 @@ rtems_isr Spurious_Isr(
|
||||
_Spurious_Error_[27], _Spurious_Error_[27], _Spurious_Error_[27],
|
||||
_Spurious_Error_[27], _Spurious_Error_[28]};
|
||||
|
||||
asm volatile ( "movea.l %%sp,%0 " : "=a" (sp) : "0" (sp) );
|
||||
//asm volatile ( "movea.l %%sp,%0 " : "=a" (sp) : "0" (sp) );
|
||||
|
||||
_CPU_ISR_Set_level( 7 );
|
||||
_UART_flush();
|
||||
|
||||
//_UART_flush();
|
||||
#if 0
|
||||
RAW_PUTS("\n\rRTEMS: Spurious interrupt: ");
|
||||
RAW_PUTS((char *)VectDescrip[( (vector>64) ? 64 : vector )]);
|
||||
RAW_PUTS("\n\rRTEMS: Vector: ");
|
||||
@@ -70,7 +70,7 @@ rtems_isr Spurious_Isr(
|
||||
RAW_PUTS(" sp: ");
|
||||
RAW_PUTI(sp);
|
||||
RAW_PUTS("\n\r");
|
||||
|
||||
#endif
|
||||
bsp_cleanup();
|
||||
|
||||
/* BDM SIGEMT */
|
||||
|
||||
@@ -6,10 +6,10 @@ AUTOMAKE_OPTIONS = foreign 1.4
|
||||
|
||||
PGM = $(ARCH)/start.o
|
||||
|
||||
C_FILES = start.c
|
||||
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
|
||||
S_FILES = start.S
|
||||
S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
|
||||
|
||||
OBJS = $(C_O_FILES)
|
||||
OBJS = $(S_O_FILES)
|
||||
|
||||
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
|
||||
include $(top_srcdir)/../../../../../../automake/compile.am
|
||||
@@ -28,6 +28,6 @@ all-local: $(ARCH) $(OBJS) $(PGM) $(TMPINSTALL_FILES)
|
||||
|
||||
.PRECIOUS: $(PGM)
|
||||
|
||||
EXTRA_DIST = start.c
|
||||
EXTRA_DIST = start.S
|
||||
|
||||
include $(top_srcdir)/../../../../../../automake/local.am
|
||||
|
||||
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* $Id
|
||||
*/
|
||||
|
||||
#include "mrm332.h"
|
||||
#include "asm.h"
|
||||
#include <sim.h>
|
||||
|
||||
BEGIN_CODE
|
||||
|
||||
/* Put the header necessary for the modified CPU32bug to automatically
|
||||
start up rtems: */
|
||||
#if 0
|
||||
.long 0xbeefbeef ;
|
||||
#endif
|
||||
.long 0 ;
|
||||
.long start ;
|
||||
|
||||
.global start
|
||||
start:
|
||||
|
||||
oriw #0x0700,sr
|
||||
movel #end, d0
|
||||
addl #_StackSize,d0
|
||||
movel d0,sp
|
||||
movel d0,a6
|
||||
|
||||
|
||||
/* include in ram_init.S */
|
||||
/*
|
||||
* Initalize the SIM module.
|
||||
* The stack pointer is not usable until the RAM chip select lines
|
||||
* are configured. The following code must remain inline.
|
||||
*/
|
||||
|
||||
/* Module Configuration Register */
|
||||
/* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
|
||||
lea SIMCR, a0
|
||||
movew #FRZSW,d0
|
||||
oriw #SAM(0,8,SHEN),d0
|
||||
oriw #(MM*SIM_MM),d0
|
||||
oriw #SAM(SIM_IARB,0,IARB),d0
|
||||
movew d0, a0@
|
||||
|
||||
jsr start_c /* Jump to the C startup code */
|
||||
|
||||
END_CODE
|
||||
|
||||
#if 0
|
||||
|
||||
/* Synthesizer Control Register */
|
||||
/* see section(s) 4.8 */
|
||||
/* end include in ram_init.S */
|
||||
*SYNCR = (unsigned short int)
|
||||
( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
|
||||
while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
|
||||
/* include in ram_init.S */
|
||||
*SYNCR = (unsigned short int)
|
||||
( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
|
||||
|
||||
/* System Protection Control Register */
|
||||
/* !!! can only write to once after reset !!! */
|
||||
/* see section 3.8.4 of the SIM Reference Manual */
|
||||
*SYPCR = (unsigned char)( HME | BME );
|
||||
|
||||
/* Periodic Interrupr Control Register */
|
||||
/* see section 3.8.2 of the SIM Reference Manual */
|
||||
*PICR = (unsigned short int)
|
||||
( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) );
|
||||
/* ^^^ zero disables interrupt, don't enable here or ram_init will
|
||||
be wrong. It's enabled below. */
|
||||
|
||||
/* Periodic Interrupt Timer Register */
|
||||
/* see section 3.8.3 of the SIM Reference Manual */
|
||||
*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
|
||||
/* 1.098mS interrupt, assuming 32.768 KHz input clock */
|
||||
|
||||
/* Port C Data */
|
||||
/* load values before enabled */
|
||||
*PORTC = (unsigned char) 0x0;
|
||||
|
||||
/* Port E and F Data Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*PORTE0 = (unsigned char) 0;
|
||||
*PORTF0 = (unsigned char) 0;
|
||||
|
||||
/* Port E and F Data Direction Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*DDRE = (unsigned char) 0xff;
|
||||
*DDRF = (unsigned char) 0xfd;
|
||||
|
||||
/* Port E and F Pin Assignment Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*PEPAR = (unsigned char) 0;
|
||||
*PFPAR = (unsigned char) 0;
|
||||
|
||||
/* end of SIM initalization code */
|
||||
/* end include in ram_init.S */
|
||||
|
||||
/*
|
||||
* Initialize RAM by copying the .data section out of ROM (if
|
||||
* needed) and "zero-ing" the .bss section.
|
||||
*/
|
||||
{
|
||||
register char *src = _etext;
|
||||
register char *dst = _copy_start;
|
||||
|
||||
if (_copy_data_from_rom)
|
||||
/* ROM has data at end of text; copy it. */
|
||||
while (dst < _edata)
|
||||
*dst++ = *src++;
|
||||
|
||||
/* Zero bss */
|
||||
for (dst = _clear_start; dst< end; dst++)
|
||||
{
|
||||
*dst = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize vector table.
|
||||
*/
|
||||
{
|
||||
m68k_isr_entry *monitors_vector_table;
|
||||
|
||||
m68k_get_vbr(monitors_vector_table);
|
||||
|
||||
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
|
||||
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
|
||||
M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */
|
||||
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
|
||||
M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */
|
||||
|
||||
m68k_set_vbr(&M68Kvec);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initalize the board.
|
||||
*/
|
||||
Spurious_Initialize();
|
||||
console_init();
|
||||
|
||||
/*
|
||||
* Execute main with arguments argc and agrv.
|
||||
*/
|
||||
boot_card(1,__argv);
|
||||
reboot();
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,259 +0,0 @@
|
||||
/*
|
||||
* $Id
|
||||
*/
|
||||
|
||||
#include <mrm332.h>
|
||||
#include <sim.h>
|
||||
#define __START_C__
|
||||
#include "bsp.h"
|
||||
|
||||
m68k_isr_entry M68Kvec[256];
|
||||
m68k_isr_entry vectors[256];
|
||||
char * const __argv[]= {"main", ""};
|
||||
|
||||
void boot_card(int argc, char * const argv[]);
|
||||
|
||||
/*
|
||||
* This prototype really should have the noreturn attribute but
|
||||
* that causes a warning. Not sure how to fix that.
|
||||
*/
|
||||
/* void dumby_start () __attribute__ ((noreturn)); */
|
||||
void dumby_start ();
|
||||
|
||||
void dumby_start() {
|
||||
|
||||
/* Put the header necessary for the modified CPU32bug to automatically
|
||||
start up rtems: */
|
||||
asm volatile ( ".long 0xbeefbeef ;
|
||||
.long 0 ;
|
||||
.long start");
|
||||
|
||||
/* We need to by-pass the link instruction since the RAM chip-
|
||||
select pins are not yet configured. */
|
||||
asm volatile ( ".global start ;
|
||||
start:");
|
||||
|
||||
/* disable interrupts, copy CPU32bug vectors, load stack pointer */
|
||||
asm volatile ( "oriw #0x0700, %sr;
|
||||
movel #end, %d0;
|
||||
addl #_StackSize,%d0;
|
||||
movel %d0,%sp;
|
||||
movel %d0,%a6"
|
||||
);
|
||||
|
||||
/* include in ram_init.S */
|
||||
/*
|
||||
* Initalize the SIM module.
|
||||
* The stack pointer is not usable until the RAM chip select lines
|
||||
* are configured. The following code must remain inline.
|
||||
*/
|
||||
|
||||
/* Module Configuration Register */
|
||||
/* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
|
||||
*SIMCR = (unsigned short int)
|
||||
(FRZSW | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
|
||||
|
||||
/* Synthesizer Control Register */
|
||||
/* see section(s) 4.8 */
|
||||
/* end include in ram_init.S */
|
||||
*SYNCR = (unsigned short int)
|
||||
( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
|
||||
while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
|
||||
/* include in ram_init.S */
|
||||
*SYNCR = (unsigned short int)
|
||||
( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
|
||||
|
||||
/* System Protection Control Register */
|
||||
/* !!! can only write to once after reset !!! */
|
||||
/* see section 3.8.4 of the SIM Reference Manual */
|
||||
*SYPCR = (unsigned char)( HME | BME );
|
||||
|
||||
/* Periodic Interrupr Control Register */
|
||||
/* see section 3.8.2 of the SIM Reference Manual */
|
||||
*PICR = (unsigned short int)
|
||||
( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) );
|
||||
/* ^^^ zero disables interrupt, don't enable here or ram_init will
|
||||
be wrong. It's enabled below. */
|
||||
|
||||
/* Periodic Interrupt Timer Register */
|
||||
/* see section 3.8.3 of the SIM Reference Manual */
|
||||
*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
|
||||
/* 1.098mS interrupt, assuming 32.768 KHz input clock */
|
||||
|
||||
/* Port C Data */
|
||||
/* load values before enabled */
|
||||
*PORTC = (unsigned char) 0x0;
|
||||
|
||||
#if 0
|
||||
/* Don't touch these on MRM, they are set up by CPU32bug at boot time. */
|
||||
|
||||
/* Chip-Select Base Address Register */
|
||||
/* see section 7 of the SIM Reference Manual */
|
||||
*CSBARBT = (unsigned short int)
|
||||
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
|
||||
*CSBAR0 = (unsigned short int)
|
||||
(((0x000000 >> 8)&0xfff8) | BS_1M ); /* 1M bytes located at 0x0000 */
|
||||
*CSBAR1 = (unsigned short int)
|
||||
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
|
||||
*CSBAR2 = (unsigned short int)
|
||||
(((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
|
||||
*CSBAR3 = (unsigned short int)
|
||||
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
|
||||
*CSBAR4 = (unsigned short int)
|
||||
(((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
|
||||
*CSBAR5 = (unsigned short int)
|
||||
(0xfff8 | BS_64K); /* AVEC interrupts */
|
||||
|
||||
#if 0
|
||||
#ifdef EFI332_v040b
|
||||
*CSBAR6 = (unsigned short int)
|
||||
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
|
||||
*CSBAR8 = (unsigned short int) /* PCMCIA IOCS */
|
||||
(((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */
|
||||
*CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */
|
||||
(((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */
|
||||
#else /* EFI332_v040b */
|
||||
*CSBAR10 = (unsigned short int)
|
||||
(((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
|
||||
#endif /* EFI332_v040b */
|
||||
#endif
|
||||
|
||||
/* Chip-Select Options Registers */
|
||||
/* see section 7 of the SIM Reference Manual */
|
||||
#ifdef FLASHWRITE
|
||||
*CSORBT = (unsigned short int)
|
||||
( BothBytes | ReadWrite | SyncAS | WaitStates_0 | UserSupSpace );
|
||||
#else /* FLASHWRITE */
|
||||
*CSORBT = (unsigned short int)
|
||||
( BothBytes | ReadOnly | SyncAS | WaitStates_0 | UserSupSpace );
|
||||
#endif /* FLASHWRITE */
|
||||
*CSOR0 = (unsigned short int)
|
||||
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
|
||||
*CSOR1 = (unsigned short int)
|
||||
( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
|
||||
*CSOR2 = (unsigned short int)
|
||||
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
|
||||
*CSOR3 = (unsigned short int)
|
||||
( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
|
||||
*CSOR4 = (unsigned short int)
|
||||
( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
|
||||
*CSOR5 = (unsigned short int)
|
||||
( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
|
||||
|
||||
#if 0
|
||||
#ifdef EFI332_v040b
|
||||
*CSOR6 = (unsigned short int)
|
||||
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
|
||||
*CSOR8 = (unsigned short int)
|
||||
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
|
||||
*CSOR9 = (unsigned short int)
|
||||
( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
|
||||
#else /* EFI332_v040b */
|
||||
*CSOR10 = (unsigned short int)
|
||||
( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
|
||||
#endif /* EFI332_v040b */
|
||||
#endif
|
||||
|
||||
/* Chip Select Pin Assignment Register 0 */
|
||||
/* see section 7 of the SIM Reference Manual */
|
||||
*CSPAR0 = (unsigned short int)(
|
||||
SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */
|
||||
SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */
|
||||
SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */
|
||||
SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */
|
||||
SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */
|
||||
SAM(CS16bit,CS_0,0x000c)| /* W/!R */
|
||||
SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */
|
||||
);
|
||||
|
||||
/* Chip Select Pin Assignment Register 1 */
|
||||
/* see section 7 of the SIM Reference Manual */
|
||||
#ifdef EFI332_v040b
|
||||
*CSPAR1 = (unsigned short int)(
|
||||
SAM(DisOut,CS_10,0x300)| /* ECLK */
|
||||
SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */
|
||||
SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */
|
||||
SAM(DisOut,CS_7,0x00c) | /* PC4 */
|
||||
SAM(CS16bit,CS_6,0x003) /* ROM !OE */
|
||||
);
|
||||
#else /* EFI332_v040b */
|
||||
*CSPAR1 = (unsigned short int)(
|
||||
SAM(CS16bit,CS_10,0x300)| /* ROM !OE */
|
||||
SAM(DisOut,CS_9,0x0c0) | /* PC6 */
|
||||
SAM(DisOut,CS_8,0x030) | /* PC5 */
|
||||
SAM(DisOut,CS_7,0x00c) | /* PC4 */
|
||||
SAM(DisOut,CS_6,0x003) /* PC3 */
|
||||
);
|
||||
#endif /* EFI332_v040b */
|
||||
|
||||
#endif /* Don't touch on MRM */
|
||||
|
||||
/* Port E and F Data Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*PORTE0 = (unsigned char) 0;
|
||||
*PORTF0 = (unsigned char) 0;
|
||||
|
||||
/* Port E and F Data Direction Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*DDRE = (unsigned char) 0xff;
|
||||
*DDRF = (unsigned char) 0xfd;
|
||||
|
||||
/* Port E and F Pin Assignment Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*PEPAR = (unsigned char) 0;
|
||||
*PFPAR = (unsigned char) 0;
|
||||
|
||||
/* end of SIM initalization code */
|
||||
/* end include in ram_init.S */
|
||||
|
||||
/*
|
||||
* Initialize RAM by copying the .data section out of ROM (if
|
||||
* needed) and "zero-ing" the .bss section.
|
||||
*/
|
||||
{
|
||||
register char *src = _etext;
|
||||
register char *dst = _copy_start;
|
||||
|
||||
if (_copy_data_from_rom)
|
||||
/* ROM has data at end of text; copy it. */
|
||||
while (dst < _edata)
|
||||
*dst++ = *src++;
|
||||
|
||||
/* Zero bss */
|
||||
for (dst = _clear_start; dst< end; dst++)
|
||||
{
|
||||
*dst = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize vector table.
|
||||
*/
|
||||
{
|
||||
m68k_isr_entry *monitors_vector_table;
|
||||
|
||||
m68k_get_vbr(monitors_vector_table);
|
||||
|
||||
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
|
||||
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
|
||||
M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */
|
||||
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
|
||||
M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */
|
||||
|
||||
m68k_set_vbr(&M68Kvec);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initalize the board.
|
||||
*/
|
||||
Spurious_Initialize();
|
||||
console_init();
|
||||
|
||||
/*
|
||||
* Execute main with arguments argc and agrv.
|
||||
*/
|
||||
boot_card(1,__argv);
|
||||
reboot();
|
||||
|
||||
}
|
||||
|
||||
@@ -8,7 +8,7 @@ VPATH = @srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared
|
||||
|
||||
PGM = $(ARCH)/startup.rel
|
||||
|
||||
C_FILES = bsplibc.c bsppost.c bspstart.c bspclean.c bootcard.c \
|
||||
C_FILES = start_c.c bsplibc.c bsppost.c bspstart.c bspclean.c bootcard.c \
|
||||
m68kpretaskinghook.c main.c sbrk.c setvec.c gnatinstallhandler.c
|
||||
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
|
||||
|
||||
|
||||
@@ -23,5 +23,5 @@ void bsp_cleanup(void)
|
||||
{
|
||||
/* interrupt driven stdio must be flushed */
|
||||
_CPU_ISR_Set_level( 7 );
|
||||
_UART_flush();
|
||||
//_UART_flush();
|
||||
}
|
||||
|
||||
@@ -34,10 +34,10 @@ __DYNAMIC = 0;
|
||||
* Declare some sizes.
|
||||
*/
|
||||
_RamBase = DEFINED(_RamBase) ? _RamBase : 0x03000;
|
||||
_RamSize = DEFINED(_RamSize) ? _RamSize : 0x80000;
|
||||
_RamSize = DEFINED(_RamSize) ? _RamSize : 0x7d000;
|
||||
_RamEnd = _RamBase + _RamSize;
|
||||
_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x10000;
|
||||
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
|
||||
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x2000;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
|
||||
@@ -0,0 +1,124 @@
|
||||
/*
|
||||
* $Id
|
||||
*/
|
||||
|
||||
#include <mrm332.h>
|
||||
#include <sim.h>
|
||||
#define __START_C__
|
||||
#include "bsp.h"
|
||||
|
||||
m68k_isr_entry M68Kvec[256];
|
||||
m68k_isr_entry vectors[256];
|
||||
char * const __argv[]= {"main", ""};
|
||||
|
||||
void boot_card(int argc, char * const argv[]);
|
||||
|
||||
/*
|
||||
* This prototype really should have the noreturn attribute but
|
||||
* that causes a warning. Not sure how to fix that.
|
||||
*/
|
||||
/* void dumby_start () __attribute__ ((noreturn)); */
|
||||
void start_c ();
|
||||
|
||||
void start_c() {
|
||||
|
||||
/* Synthesizer Control Register */
|
||||
/* see section(s) 4.8 */
|
||||
/* end include in ram_init.S */
|
||||
*SYNCR = (unsigned short int)
|
||||
( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
|
||||
while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */
|
||||
/* include in ram_init.S */
|
||||
*SYNCR = (unsigned short int)
|
||||
( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
|
||||
|
||||
/* System Protection Control Register */
|
||||
/* !!! can only write to once after reset !!! */
|
||||
/* see section 3.8.4 of the SIM Reference Manual */
|
||||
*SYPCR = (unsigned char)( HME | BME );
|
||||
|
||||
/* Periodic Interrupr Control Register */
|
||||
/* see section 3.8.2 of the SIM Reference Manual */
|
||||
*PICR = (unsigned short int)
|
||||
( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) );
|
||||
/* ^^^ zero disables interrupt, don't enable here or ram_init will
|
||||
be wrong. It's enabled below. */
|
||||
|
||||
/* Periodic Interrupt Timer Register */
|
||||
/* see section 3.8.3 of the SIM Reference Manual */
|
||||
*PITR = (unsigned short int)( SAM(0x09,0,PITM) );
|
||||
/* 1.098mS interrupt, assuming 32.768 KHz input clock */
|
||||
|
||||
/* Port C Data */
|
||||
/* load values before enabled */
|
||||
*PORTC = (unsigned char) 0x0;
|
||||
|
||||
/* Port E and F Data Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*PORTE0 = (unsigned char) 0;
|
||||
*PORTF0 = (unsigned char) 0;
|
||||
|
||||
/* Port E and F Data Direction Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*DDRE = (unsigned char) 0xff;
|
||||
*DDRF = (unsigned char) 0xfd;
|
||||
|
||||
/* Port E and F Pin Assignment Register */
|
||||
/* see section 9 of the SIM Reference Manual */
|
||||
*PEPAR = (unsigned char) 0;
|
||||
*PFPAR = (unsigned char) 0;
|
||||
|
||||
/* end of SIM initalization code */
|
||||
/* end include in ram_init.S */
|
||||
|
||||
/*
|
||||
* Initialize RAM by copying the .data section out of ROM (if
|
||||
* needed) and "zero-ing" the .bss section.
|
||||
*/
|
||||
{
|
||||
register char *src = _etext;
|
||||
register char *dst = _copy_start;
|
||||
|
||||
if (_copy_data_from_rom)
|
||||
/* ROM has data at end of text; copy it. */
|
||||
while (dst < _edata)
|
||||
*dst++ = *src++;
|
||||
|
||||
/* Zero bss */
|
||||
for (dst = _clear_start; dst< end; dst++)
|
||||
{
|
||||
*dst = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize vector table.
|
||||
*/
|
||||
{
|
||||
m68k_isr_entry *monitors_vector_table;
|
||||
|
||||
m68k_get_vbr(monitors_vector_table);
|
||||
|
||||
M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
|
||||
M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
|
||||
M68Kvec[ 31 ] = monitors_vector_table[ 31 ]; /* level 7 interrupt */
|
||||
M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
|
||||
M68Kvec[ 66 ] = monitors_vector_table[ 66 ]; /* user defined */
|
||||
|
||||
m68k_set_vbr(&M68Kvec);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initalize the board.
|
||||
*/
|
||||
Spurious_Initialize();
|
||||
//console_init();
|
||||
|
||||
/*
|
||||
* Execute main with arguments argc and agrv.
|
||||
*/
|
||||
boot_card(1,__argv);
|
||||
reboot();
|
||||
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user