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bsp/stm32h7: Import from STM32CubeMX-5.6.0

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Update #3910.
This commit is contained in:
Sebastian Huber
2020-10-27 06:11:44 +01:00
parent db94626bc3
commit 2131228f79
259 changed files with 706411 additions and 0 deletions
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bsps/arm/stm32h7/hal/stm32h7xx_hal.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_adc.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_adc_ex.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_cec.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_comp.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_cortex.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_crc.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_crc_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_crc_ex.c
* @author MCD Application Team
* @brief Extended CRC HAL module driver.
* This file provides firmware functions to manage the extended
* functionalities of the CRC peripheral.
*
@verbatim
================================================================================
##### How to use this driver #####
================================================================================
[..]
(+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup CRCEx CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
* @brief Extended Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Extended configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the generating polynomial
(+) Configure the input data inversion
(+) Configure the output data inversion
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC polynomial if different from default one.
* @param hcrc CRC handle
* @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
* This parameter is written in normal representation, e.g.
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
* @param PolyLength CRC polynomial length.
* This parameter can be one of the following values:
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
{
}
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
status = HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
status = HAL_ERROR;
break;
}
if (status == HAL_OK)
{
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
}
/* Return function status */
return status;
}
/**
* @brief Set the Reverse Input data mode.
* @param hcrc CRC handle
* @param InputReverseMode Input Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
* @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set input data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the Reverse Output data mode.
* @param hcrc CRC handle
* @param OutputReverseMode Output Data inversion mode.
* This parameter can be one of the following values:
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set output data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsps/arm/stm32h7/hal/stm32h7xx_hal_cryp.c
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/**
******************************************************************************
* @file stm32h7xx_hal_cryp_ex.c
* @author MCD Application Team
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
* + Extended AES processing functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The CRYP extension HAL driver can be used after AES-GCM or AES-CCM
Encryption/Decryption to get the authentication messages.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (CRYP)
/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{
*/
#ifdef HAL_CRYP_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup CRYPEx_Private_Defines
* @{
*/
#define CRYP_PHASE_INIT 0x00000000U
#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
/* CTR0 information to use in CCM algorithm */
#define CRYP_CCM_CTR0_0 0x07FFFFFFU
#define CRYP_CCM_CTR0_3 0xFFFFFF00U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions---------------------------------------------------------*/
/** @addtogroup CRYPEx_Exported_Functions
* @{
*/
/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
* @brief CRYPEx Extended processing functions.
*
@verbatim
==============================================================================
##### Extended AES processing functions #####
==============================================================================
[..] This section provides functions allowing to generate the authentication
TAG in Polling mode
(+)HAL_CRYPEx_AESGCM_GenerateAuthTAG
(+)HAL_CRYPEx_AESCCM_GenerateAuthTAG
they should be used after Encrypt/Decrypt operation.
@endverbatim
* @{
*/
/**
* @brief generate the GCM authentication TAG.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param AuthTag: Pointer to the authentication buffer
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tickstart;
uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
}
else /* Initialization phase has not been performed*/
{
/* Disable the Peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Sequence error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
/* Select final phase */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
/*ALGODIR bit must be set to ‘0’.*/
hcryp->Instance->CR &= ~CRYP_CR_ALGODIR;
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
#if !defined (CRYP_VER_2_2)
/* STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(inputlength);
}
#if !defined (CRYP_VER_2_2)
else/* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(inputlength);
}
else
{
/* Nothing to do */
}
}
#endif /*End of not defined CRYP_VER_2_2*/
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP Peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Read the authentication TAG in the output FIFO */
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
/* Disable the peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
}
else
{
/* Busy error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @brief AES CCM Authentication TAG generation.
* @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
* the configuration information for CRYP module
* @param AuthTag: Pointer to the authentication buffer
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tagaddr = (uint32_t)AuthTag;
uint32_t ctr0 [4] = {0};
uint32_t ctr0addr = (uint32_t)ctr0;
uint32_t tickstart;
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
__HAL_LOCK(hcryp);
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_BUSY;
/* Check if initialization phase has already been performed */
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
{
/* Change the CRYP phase */
hcryp->Phase = CRYPEx_PHASE_FINAL;
}
else /* Initialization phase has not been performed*/
{
/* Disable the peripheral */
__HAL_CRYP_DISABLE(hcryp);
/* Sequence error code field */
hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
/* Disable CRYP to start the final phase */
__HAL_CRYP_DISABLE(hcryp);
/* Select final phase & ALGODIR bit must be set to ‘0’. */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Write the counter block in the IN FIFO, CTR0 information from B0
data has to be swapped according to the DATATYPE*/
ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0;
ctr0[1] = hcryp->Init.B0[1];
ctr0[2] = hcryp->Init.B0[2];
ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
#if !defined (CRYP_VER_2_2)
/*STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
if (hcryp->Version >= REV_ID_B)
#endif /*End of not defined CRYP_VER_2_2*/
{
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
#if !defined (CRYP_VER_2_2)
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
{
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
ctr0addr += 4U;
hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
}
else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
ctr0addr += 4U;
hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
}
else
{
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
}
#endif /*End of not defined CRYP_VER_2_2*/
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
/* Disable the CRYP peripheral Clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
return HAL_ERROR;
}
}
}
/* Read the Auth TAG in the IN FIFO */
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
tagaddr += 4U;
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUT;
/* Change the CRYP peripheral state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcryp);
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
}
else
{
/* Busy error code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
#endif /* HAL_CRYP_MODULE_ENABLED */
/**
* @}
*/
#endif /* CRYP */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsps/arm/stm32h7/hal/stm32h7xx_hal_dac.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_dfsdm.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_dfsdm_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_dfsdm_ex.c
* @author MCD Application Team
* @brief DFSDM Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionality of the DFSDM Peripheral Controller:
* + Set and get pulses skipping on channel.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_DFSDM_MODULE_ENABLED
#if defined(DFSDM_CHDLYR_PLSSKP)
/** @defgroup DFSDMEx DFSDMEx
* @brief DFSDM Extended HAL module driver
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions
* @{
*/
/** @defgroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions
* @brief DFSDM extended channel operation functions
*
@verbatim
===============================================================================
##### Extended channel operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Set and get value of pulses skipping on channel
@endverbatim
* @{
*/
/**
* @brief Set value of pulses skipping.
* @param hdfsdm_channel DFSDM channel handle.
* @param PulsesValue Value of pulses to be skipped.
* This parameter must be a number between Min_Data = 0 and Max_Data = 63.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check pulses value */
assert_param(IS_DFSDM_CHANNEL_SKIPPING_VALUE(PulsesValue));
/* Check DFSDM channel state */
if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
{
/* Set new value of pulses skipping */
hdfsdm_channel->Instance->CHDLYR = (PulsesValue & DFSDM_CHDLYR_PLSSKP);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @brief Get value of pulses skipping.
* @param hdfsdm_channel DFSDM channel handle.
* @param PulsesValue Value of pulses to be skipped.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check DFSDM channel state */
if (hdfsdm_channel->State == HAL_DFSDM_CHANNEL_STATE_READY)
{
/* Get value of remaining pulses to be skipped */
*PulsesValue = (hdfsdm_channel->Instance->CHDLYR & DFSDM_CHDLYR_PLSSKP);
}
else
{
status = HAL_ERROR;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DFSDM_CHDLYR_PLSSKP */
#endif /* HAL_DFSDM_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_hsem.c
* @author MCD Application Team
* @brief HSEM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the semaphore peripheral:
* + Semaphore Take function (2-Step Procedure) , non blocking
* + Semaphore FastTake function (1-Step Procedure) , non blocking
* + Semaphore Status check
* + Semaphore Clear Key Set and Get
* + Release and release all functions
* + Semaphore notification enabling and disabling and callnack functions
* + IRQ handler management
*
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
(++) the semaphore ID from 0 to 31
(++) the process ID from 0 to 255
(#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
(++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
(#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
(++) the semaphore ID from 0_ID to 31
(++) It returns 1 if the given semaphore is taken otherwise (Free) zero
(#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
(++) the semaphore ID from 0 to 31
(++) the process ID from 0 to 255:
(++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
semaphore remains taken (locked)
(#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
This function takes as parameters :
(++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
(++) the Master ID:
(++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the
Key or the MasterID doesn't match, semaphores remains taken (locked)
(#)Semaphores Release all key functions:
(++) HAL_HSEM_SetClearKey() to set semaphore release all Key
(++) HAL_HSEM_GetClearKey() to get release all Key
(#)Semaphores notification functions :
(++) HAL_HSEM_ActivateNotification to activate a notification callback on
a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
semaphores (bitfield).
(++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
(++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
Used by the notification functions
*** HSEM HAL driver macros list ***
=============================================
[..] Below the list of most used macros in HSEM HAL driver.
(+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
[..] Example of use :
[..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
[..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example.
(+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
(+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
(+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
(+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
(+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup HSEM HSEM
* @brief HSEM HAL module driver
* @{
*/
#ifdef HAL_HSEM_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#if defined(DUAL_CORE)
#ifndef HSEM_R_MASTERID
#define HSEM_R_MASTERID HSEM_R_COREID
#endif
#ifndef HSEM_RLR_MASTERID
#define HSEM_RLR_MASTERID HSEM_RLR_COREID
#endif
#ifndef HSEM_CR_MASTERID
#define HSEM_CR_MASTERID HSEM_CR_COREID
#endif
#endif /* DUAL_CORE */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
* @{
*/
/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
* @brief HSEM Take and Release functions
*
@verbatim
==============================================================================
##### HSEM Take and Release functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Take a semaphore with 2 Step method
(+) Fast Take a semaphore with 1 Step method
(+) Check semaphore state Taken or not
(+) Release a semaphore
(+) Release all semaphore at once
@endverbatim
* @{
*/
/**
* @brief Take a semaphore in 2 Step mode.
* @param SemID: semaphore ID from 0 to 31
* @param ProcessID: Process ID from 0 to 255
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
assert_param(IS_HSEM_PROCESSID(ProcessID));
#if USE_MULTI_CORE_SHARED_CODE != 0U
/* First step write R register with MasterID, processID and take bit=1*/
HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
{
/*take success when MasterID and ProcessID match and take bit set*/
return HAL_OK;
}
#else
/* First step write R register with MasterID, processID and take bit=1*/
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
{
/*take success when MasterID and ProcessID match and take bit set*/
return HAL_OK;
}
#endif
/* Semaphore take fails*/
return HAL_ERROR;
}
/**
* @brief Fast Take a semaphore with 1 Step mode.
* @param SemID: semaphore ID from 0 to 31
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
#if USE_MULTI_CORE_SHARED_CODE != 0U
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
{
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
#else
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
{
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
#endif
/* Semaphore take fails */
return HAL_ERROR;
}
/**
* @brief Check semaphore state Taken or not.
* @param SemID: semaphore ID
* @retval HAL HSEM state
*/
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
{
return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
}
/**
* @brief Release a semaphore.
* @param SemID: semaphore ID from 0 to 31
* @param ProcessID: Process ID from 0 to 255
* @retval None
*/
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
{
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
assert_param(IS_HSEM_PROCESSID(ProcessID));
/* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */
#if USE_MULTI_CORE_SHARED_CODE != 0U
HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID));
#else
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
#endif
}
/**
* @brief Release All semaphore used by a given Master .
* @param Key: Semaphore Key , value from 0 to 0xFFFF
* @param CoreID: CoreID of the CPU that is using semaphores to be released
* @retval None
*/
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
{
assert_param(IS_HSEM_KEY(Key));
assert_param(IS_HSEM_COREID(CoreID));
HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
}
/**
* @}
*/
/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
* @brief HSEM Set and Get Key functions.
*
@verbatim
==============================================================================
##### HSEM Set and Get Key functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Set semaphore Key
(+) Get semaphore Key
@endverbatim
* @{
*/
/**
* @brief Set semaphore Key .
* @param Key: Semaphore Key , value from 0 to 0xFFFF
* @retval None
*/
void HAL_HSEM_SetClearKey(uint32_t Key)
{
assert_param(IS_HSEM_KEY(Key));
MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
}
/**
* @brief Get semaphore Key .
* @retval Semaphore Key , value from 0 to 0xFFFF
*/
uint32_t HAL_HSEM_GetClearKey(void)
{
return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
}
/**
* @}
*/
/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
* @brief HSEM Notification functions.
*
@verbatim
==============================================================================
##### HSEM IRQ handler management and Notification functions #####
==============================================================================
[..] This section provides HSEM IRQ handler and Notification function.
@endverbatim
* @{
*/
/**
* @brief Activate Semaphore release Notification for a given Semaphores Mask .
* @param SemMask: Mask of Released semaphores
* @retval Semaphore Key
*/
void HAL_HSEM_ActivateNotification(uint32_t SemMask)
{
#if USE_MULTI_CORE_SHARED_CODE != 0U
/*enable the semaphore mask interrupts */
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/*Use interrupt line 0 for CPU1 Master */
HSEM->C1IER |= SemMask;
}
else /* HSEM_CPU2_COREID */
{
/*Use interrupt line 1 for CPU2 Master*/
HSEM->C2IER |= SemMask;
}
#else
HSEM_COMMON->IER |= SemMask;
#endif
}
/**
* @brief Deactivate Semaphore release Notification for a given Semaphores Mask .
* @param SemMask: Mask of Released semaphores
* @retval Semaphore Key
*/
void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
{
#if USE_MULTI_CORE_SHARED_CODE != 0U
/*enable the semaphore mask interrupts */
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/*Use interrupt line 0 for CPU1 Master */
HSEM->C1IER &= ~SemMask;
}
else /* HSEM_CPU2_COREID */
{
/*Use interrupt line 1 for CPU2 Master*/
HSEM->C2IER &= ~SemMask;
}
#else
HSEM_COMMON->IER &= ~SemMask;
#endif
}
/**
* @brief This function handles HSEM interrupt request
* @retval None
*/
void HAL_HSEM_IRQHandler(void)
{
uint32_t statusreg;
#if USE_MULTI_CORE_SHARED_CODE != 0U
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/* Get the list of masked freed semaphores*/
statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
/*Disable Interrupts*/
HSEM->C1IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM->C1ICR = ((uint32_t)statusreg);
}
else /* HSEM_CPU2_COREID */
{
/* Get the list of masked freed semaphores*/
statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
/*Disable Interrupts*/
HSEM->C2IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM->C2ICR = ((uint32_t)statusreg);
}
#else
/* Get the list of masked freed semaphores*/
statusreg = HSEM_COMMON->MISR;
/*Disable Interrupts*/
HSEM_COMMON->IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM_COMMON->ICR = ((uint32_t)statusreg);
#endif
/* Call FreeCallback */
HAL_HSEM_FreeCallback(statusreg);
}
/**
* @brief Semaphore Released Callback.
* @param SemMask: Mask of Released semaphores
* @retval None
*/
__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(SemMask);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_HSEM_FreeCallback can be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_HSEM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_i2c_ex.c
* @author MCD Application Team
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32H7xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode(s)
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
(++) HAL_I2CEx_EnableWakeUp()
(++) HAL_I2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Wake Up Feature
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Enable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Disable I2C wakeup from Stop mode(s).
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
{
/* Check the parameters */
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable wakeup from stop mode */
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
}
/**
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsps/arm/stm32h7/hal/stm32h7xx_hal_i2s.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_i2s_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_i2s_ex.c
* @author MCD Application Team
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
* + Extension features Functions
*
@verbatim
==============================================================================
##### I2S Extension features #####
==============================================================================
The I2S Full duplex feature is not supported by this HAL Driver
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsps/arm/stm32h7/hal/stm32h7xx_hal_irda.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_iwdg.c
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/**
******************************************************************************
* @file stm32h7xx_hal_iwdg.c
* @author MCD Application Team
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and Start functions
* + IO operation functions
*
@verbatim
==============================================================================
##### IWDG Generic features #####
==============================================================================
[..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
(+) Once the IWDG is started, the LSI is forced ON and both can not be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG1() or __HAL_DBGMCU_FREEZE2_IWDG2() and
__HAL_DBGMCU_UnFreeze_IWDG1 or __HAL_DBGMCU_UnFreeze2_IWDG2() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM16 CH1 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
##### How to use this driver #####
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts counting down.
(++) Enable write access to configuration registers:
IWDG_PR, IWDG_RLR and IWDG_WINR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(++) Wait for status flags to be reset.
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function with exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
*** IWDG HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
the reload register
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions
* @{
*/
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions.
*
@verbatim
===============================================================================
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Manage Window option.
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
* @{
*/
/**
* @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart;
/* Check the IWDG handle allocation */
if (hiwdg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload;
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while (hiwdg->Instance->SR != 0x00u)
{
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* If window parameter is different than current value, modify window
register */
if (hiwdg->Instance->WINR != hiwdg->Init.Window)
{
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
even if window feature is disabled, Watchdog will be reloaded by writing
windows register */
hiwdg->Instance->WINR = hiwdg->Init.Window;
}
else
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
* @{
*/
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_IWDG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsps/arm/stm32h7/hal/stm32h7xx_hal_jpeg.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_lptim.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_ltdc.c
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/**
******************************************************************************
* @file stm32h7xx_hal_ltdc_ex.c
* @author MCD Application Team
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
#if defined (LTDC) && defined (DSI)
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
@endverbatim
* @{
*/
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsps/arm/stm32h7/hal/stm32h7xx_hal_mdios.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_mdma.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_mmc.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_mmc_ex.c
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/**
******************************************************************************
* @file stm32h7xx_hal_mmc_ex.c
* @author MCD Application Team
* @brief MMC card Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The MMC Extension HAL driver can be used as follows:
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
(+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup MMCEx MMCEx
* @brief MMC Extended HAL module driver
* @{
*/
#ifdef HAL_MMC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup MMCEx_Exported_Functions
* @{
*/
/** @addtogroup MMCEx_Exported_Functions_Group1
* @brief Multibuffer functions
*
@verbatim
==============================================================================
##### Multibuffer functions #####
==============================================================================
[..]
This section provides functions allowing to configure the multibuffer mode and start read and write
multibuffer mode for MMC HAL driver.
@endverbatim
* @{
*/
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hmmc: MMC handle
* @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
* @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize)
{
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
hmmc->Instance->IDMABSIZE= (uint32_t) (MMC_BLOCKSIZE * BufferSize);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc: MMC handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t errorstate;
uint32_t add = BlockAdd;
if(hmmc->State == HAL_MMC_STATE_READY)
{
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Read Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc: MMC handle
* @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t add = BlockAdd;
if(hmmc->State == HAL_MMC_STATE_READY)
{
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Write Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->State = HAL_MMC_STATE_READY;
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Change the DMA Buffer0 or Buffer1 address on the fly.
* @param hmmc: pointer to a MMC_HandleTypeDef structure.
* @param Buffer: the buffer to be changed, This parameter can be one of
* the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
* @param pDataBuffer: The new address
* @note The BUFFER0 address can be changed only when the current transfer use
* BUFFER1 and the BUFFER1 address can be changed only when the current
* transfer use BUFFER0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer)
{
if(Buffer == MMC_DMA_BUFFER0)
{
/* change the buffer0 address */
hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer;
}
else
{
/* change the memory1 address */
hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_MMC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsps/arm/stm32h7/hal/stm32h7xx_hal_nand.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_nor.c
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bsps/arm/stm32h7/hal/stm32h7xx_hal_opamp.c
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