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arm: Fix arm_cp15_set_translation_table_entries()

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In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.

Close #4068.
This commit is contained in:
Sebastian Huber
2020-09-17 08:20:35 +02:00
parent 9979042a3a
commit 20d82377a6
2 changed files with 17 additions and 1 deletions
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bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
+1 -1
View File
@@ -107,7 +107,7 @@ static uint32_t set_translation_table_entries(
#define MPIDR_UP (1 << 30)
const uint32_t mpidr = arm_cp15_get_multiprocessor_affinity();
if ((mpidr & (MPIDR_MX_FMT | MPIDR_UP)) == MPIDR_MX_FMT) {
arm_cp15_tlb_invalidate_entry_all_asids(mva);
arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(mva);
}
else
#endif
cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
+16
View File
@@ -646,6 +646,22 @@ arm_cp15_tlb_invalidate_entry_all_asids(const void *mva)
);
}
ARM_CP15_TEXT_SECTION static inline void
arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(const void *mva)
{
ARM_SWITCH_REGISTERS;
mva = ARM_CP15_TLB_PREPARE_MVA(mva);
__asm__ volatile (
ARM_SWITCH_TO_ARM
"mcr p15, 0, %[mva], c8, c3, 3\n"
ARM_SWITCH_BACK
: ARM_SWITCH_OUTPUT
: [mva] "r" (mva)
);
}
ARM_CP15_TEXT_SECTION static inline void
arm_cp15_tlb_instruction_invalidate(void)
{