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bsps/microblaze: Allow copying FDT from U-Boot
This commit is contained in:
Maldonado, Sergio E. (GSFC-580.0)
committed by
Joel Sherrill
Joel Sherrill
parent
7e119562ae
commit
1fbfc4eeac
@@ -49,14 +49,17 @@ extern "C" {
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#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
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#define BSP_FDT_IS_SUPPORTED
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#ifndef BSP_START_COPY_FDT_FROM_U_BOOT
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extern const unsigned char system_dtb[];
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extern const size_t system_dtb_size;
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#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
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#endif /* BSP_MICROBLAZE_FPGA_USE_FDT */
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void microblaze_enable_icache(void);
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void microblaze_enable_dcache(void);
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void microblaze_invalidate_icache(void);
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void microblaze_invalidate_dcache(void);
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void microblaze_invalidate_dcache_range(unsigned int cacheaddr, unsigned int len);
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#ifdef __cplusplus
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}
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@@ -30,6 +30,8 @@
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bspopts.h>
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.globl _crtinit
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.align 2
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.ent _crtinit
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@@ -75,7 +77,9 @@ _crtinit:
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brlid r15, __init /* Invoke language initialization functions */
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nop
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#endif /* __rtems__ */
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#ifdef BSP_START_COPY_FDT_FROM_U_BOOT /* Boot loaders may pass the device tree in r5 */
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brlid r15, bsp_fdt_copy /* Do not touch r5 until bsp_fdt_copy() is called */
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#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
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addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */
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addi r7, r0, 0
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#ifndef __rtems__
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@@ -0,0 +1,104 @@
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/******************************************************************************
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* Copyright (c) 2008 - 2020 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/******************************************************************************
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*
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*
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* microblaze_invalidate_dcache_range (unsigned int cacheaddr, unsigned int len)
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*
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* Invalidate a Dcache range
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*
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* Parameters:
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* 'cacheaddr' - address in the Dcache where invalidation begins
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* 'len ' - length (in bytes) worth of Dcache to be invalidated
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*
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*
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*******************************************************************************/
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#include <bspopts.h>
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#define MICROBLAZE_MSR_DCACHE_ENABLE 0x00000080
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#define MICROBLAZE_MSR_INTR_ENABLE 0x00000002
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#ifndef XPAR_MICROBLAZE_USE_DCACHE
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#define XPAR_MICROBLAZE_USE_DCACHE 1
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#endif
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#ifndef XPAR_MICROBLAZE_ALLOW_DCACHE_WR
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#define XPAR_MICROBLAZE_ALLOW_DCACHE_WR 1
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#endif
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#ifndef XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
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#define MB_VERSION_LT_v720
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#define MB_HAS_WRITEBACK_SET 0
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#else
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#define MB_HAS_WRITEBACK_SET XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK
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#endif
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.text
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.globl microblaze_invalidate_dcache_range
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.ent microblaze_invalidate_dcache_range
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.align 2
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microblaze_invalidate_dcache_range:
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#if (XPAR_MICROBLAZE_USE_DCACHE==1) && (XPAR_MICROBLAZE_ALLOW_DCACHE_WR==1)
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#ifdef MB_VERSION_LT_v720 /* Disable Dcache and interrupts before invalidating */
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mfs r9, rmsr
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andi r10, r9, ~(MICROBLAZE_MSR_DCACHE_ENABLE | MICROBLAZE_MSR_INTR_ENABLE)
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mts rmsr, r10
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#endif
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BEQI r6, L_done /* Skip loop if size is zero */
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ADD r6, r5, r6 /* Compute end address */
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ADDIK r6, r6, -1
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ANDI r6, r6, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN) /* Align end down to cache line */
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ANDI r5, r5, -(4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN) /* Align start down to cache line */
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#if MB_HAS_WRITEBACK_SET == 0 /* Use a different scheme for MB version < v7.20 or when caches are write-through */
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L_start:
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CMPU r18, r5, r6 /* Are we at the end? */
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BLTI r18, L_done
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wdc r5, r0
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#if defined (__arch64__ )
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addlik r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) /* Increment the address by 4 */
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breai L_start /* Branch to the beginning of the loop */
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#else
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brid L_start /* Branch to the beginning of the loop */
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addik r5, r5, (BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4) /* Increment the address by 4 (delay slot) */
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#endif
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#else
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RSUBK r6, r5, r6
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/* r6 will now contain (count of bytes - (4 * BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN)) */
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L_start:
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wdc.clear r5, r6 /* Invalidate the cache line only if the address matches */
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#if defined (__arch64__ )
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addlik r6, r6, -(BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4)
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beagei r6, L_start
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#else
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bneid r6, L_start
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addik r6, r6, -(BSP_MICROBLAZE_FPGA_DCACHE_LINE_LEN * 4)
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#endif
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#endif
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L_done:
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rtsd r15, 8
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#ifdef MB_VERSION_LT_v720 /* restore MSR only for MB version < v7.20 */
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mts rmsr, r9
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#else
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nop
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#endif
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#else
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rtsd r15, 8
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nop
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#endif
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.end microblaze_invalidate_dcache_range
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@@ -27,12 +27,46 @@
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#include <bspopts.h>
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#include <bsp/microblaze-fdt-support.h>
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#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
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#include <bsp/fdt.h>
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#include <libfdt.h>
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#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
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/* use external dtb provided by u-boot */
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#include <sys/param.h>
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#ifndef BSP_FDT_BLOB_SIZE_MAX
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#define BSP_FDT_BLOB_SIZE_MAX 0
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#endif
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static RTEMS_ALIGNED(8) uint32_t
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system_dtb[BSP_FDT_BLOB_SIZE_MAX / sizeof(uint32_t)];
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void bsp_fdt_copy(const void *src)
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{
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const volatile uint32_t *s = (const uint32_t *) src;
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uint32_t *d = RTEMS_DECONST(uint32_t *, &system_dtb[0]);
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if (s != d) {
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size_t m = MIN(sizeof(system_dtb), fdt_totalsize(src));
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size_t aligned_size = roundup2(m, CPU_CACHE_LINE_BYTES);
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size_t n = (m + sizeof(*d) - 1) / sizeof(*d);
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size_t i;
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for (i = 0; i < n; ++i) {
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d[i] = s[i];
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}
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rtems_cache_flush_multiple_data_lines(d, aligned_size);
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}
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}
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#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
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#ifdef BSP_MICROBLAZE_FPGA_USE_FDT
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#ifndef BSP_START_COPY_FDT_FROM_U_BOOT
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/* use internal bsp dtb */
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#include BSP_MICROBLAZE_FPGA_DTB_HEADER_PATH
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#endif /* BSP_START_COPY_FDT_FROM_U_BOOT */
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const void *bsp_fdt_get(void)
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{
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@@ -80,6 +80,10 @@ links:
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uid: linkcmds
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- role: build-dependency
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uid: ../../bspopts
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- role: build-dependency
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uid: ../../optfdtuboot
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- role: build-dependency
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uid: ../../optfdtmxsz
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type: build
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use-after: []
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use-before: []
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@@ -38,6 +38,7 @@ source:
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- bsps/microblaze/microblaze_fpga/start/microblaze_enable_icache.S
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- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache.S
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- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_icache.S
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- bsps/microblaze/microblaze_fpga/start/microblaze_invalidate_dcache_range.S
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- bsps/microblaze/shared/dev/serial/uartlite.c
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- bsps/microblaze/shared/dev/serial/uartlite_l.c
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- bsps/microblaze/shared/fdt/microblaze-fdt-support.c
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