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2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>

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PR 1573/cpukit
	* cpu_asm.S, rtems/asm.h, rtems/score/cpu.h: Add a per cpu data
	structure which contains the information required by RTEMS for each
	CPU core. This encapsulates information such as thread executing,
	heir, idle and dispatch needed.
This commit is contained in:
Joel Sherrill
2010-06-29 00:31:09 +00:00
parent b616350ec9
commit 1ef0afe60a
4 changed files with 42 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cpukit/score/cpu/h8300/ChangeLog
+8
View File
@@ -1,3 +1,11 @@
2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>
PR 1573/cpukit
* cpu_asm.S, rtems/asm.h, rtems/score/cpu.h: Add a per cpu data
structure which contains the information required by RTEMS for each
CPU core. This encapsulates information such as thread executing,
heir, idle and dispatch needed.
2010-04-25 Joel Sherrill <joel.sherrilL@OARcorp.com>
* rtems/score/cpu.h: Remove warning in _CPU_Context_Initialize.
cpukit/score/cpu/h8300/cpu_asm.S
+34 -40
View File
@@ -18,6 +18,8 @@
#include "config.h"
#endif
#include <rtems/asm.h>
#include <rtems/score/percpu.h>
;.equ RUNCONTEXT_ARG, er0
;.equ HEIRCONTEXT_ARG, er1
@@ -51,9 +53,9 @@
.align 2
.global __CPU_Context_switch
.global SYM(_CPU_Context_switch)
__CPU_Context_switch:
SYM(_CPU_Context_switch):
/* Save Context */
#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
stc.w ccr,@(0:16,er0)
@@ -80,9 +82,9 @@ restore:
.align 2
.global __CPU_Context_restore
.global SYM(_CPU_Context_restore)
__CPU_Context_restore:
SYM(_CPU_Context_restore):
#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
mov.l er0,er1
@@ -100,13 +102,11 @@ __CPU_Context_restore:
*/
.align 2
.global __ISR_Handler
.extern __ISR_Nest_level
.extern __Vector_table
.extern __Context_switch_necessary
.global SYM(_ISR_Handler)
.extern SYM(_Vector_table)
__ISR_Handler:
SYM(_ISR_Handler):
#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
mov.l er1,@-er7
mov.l er2,@-er7
@@ -118,24 +118,24 @@ __ISR_Handler:
/* Set IRQ Stack */
orc #0xc0,ccr
mov.l er7,er6 ; save stack pointer
mov.l @__ISR_Nest_level,er1
mov.l @ISR_NEST_LEVEL,er1
bne nested
mov.l @__CPU_Interrupt_stack_high,er7
mov.l @INTERRUPT_STACK_HIGH,er7
nested:
mov.l er6,@-er7 ; save sp so pop regardless of nest level
;; Inc system counters
mov.l @__ISR_Nest_level,er1
mov.l @ISR_NEST_LEVEL,er1
inc.l #1,er1
mov.l er1,@__ISR_Nest_level
mov.l @__Thread_Dispatch_disable_level,er1
mov.l er1,@ISR_NEST_LEVEL
mov.l @SYM(_Thread_Dispatch_disable_level),er1
inc.l #1,er1
mov.l er1,@__Thread_Dispatch_disable_level
mov.l er1,@SYM(_Thread_Dispatch_disable_level)
/* Vector to ISR */
mov.l @__ISR_Vector_table,er1
mov.l @SYM(_ISR_Vector_table),er1
mov er0,er2 ; copy vector
shll.l er2
shll.l er2 ; vector = vector * 4 (sizeof(int))
@@ -144,34 +144,28 @@ nested:
jsr @er1 ; er0 = arg1 =vector
orc #0xc0,ccr
mov.l @__ISR_Nest_level,er1
mov.l @ISR_NEST_LEVEL,er1
dec.l #1,er1
mov.l er1,@__ISR_Nest_level
mov.l @__Thread_Dispatch_disable_level,er1
mov.l er1,@ISR_NEST_LEVEL
mov.l @SYM(_Thread_Dispatch_disable_level),er1
dec.l #1,er1
mov.l er1,@__Thread_Dispatch_disable_level
bne exit
mov.l er1,@SYM(_Thread_Dispatch_disable_level)
bne exit
mov.b @__Context_Switch_necessary,er1
bne bframe ; If yes then dispatch next task
mov.b @__ISR_Signals_to_thread_executing,er1
beq exit ; If no signals waiting
mov.b @DISPATCH_NEEDED,er1
beq exit ; If no then exit
/* Context switch here through ISR_Dispatch */
bframe:
orc #0xc0,ccr
orc #0xc0,ccr
/* Pop Stack */
mov @er7+,er6
mov er6,er7
mov.l #0,er2
mov.l er2,@__ISR_Signals_to_thread_executing
mov @er7+,er6
mov er6,er7
/* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
mov.l #0xc0000000,er2 /* Disable IRQ */
or.l #_ISR_Dispatch,er2
or.l #SYM(_ISR_Dispatch),er2
mov.l er2,@-er7
rte
@@ -200,12 +194,12 @@ exit:
*/
.align 2
.global _ISR_Dispatch
.global SYM(_ISR_Dispatch)
_ISR_Dispatch:
SYM(_ISR_Dispatch):
#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
jsr @__Thread_Dispatch
jsr @SYM(_Thread_Dispatch)
mov @er7+,er6
mov @er7+,er5
mov @er7+,er4
@@ -218,14 +212,14 @@ _ISR_Dispatch:
.align 2
.global __CPU_Context_save_fp
.global SYM(_CPU_Context_save_fp)
__CPU_Context_save_fp:
SYM(_CPU_Context_save_fp):
rts
.align 2
.global __CPU_Context_restore_fp
.global SYM(_CPU_Context_restore_fp)
__CPU_Context_restore_fp:
SYM(_CPU_Context_restore_fp):
rts
cpukit/score/cpu/h8300/rtems/asm.h
-3
View File
@@ -37,7 +37,6 @@
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#define ASM
#include <rtems/score/h8300.h>
/*
@@ -116,5 +115,3 @@
#define EXTERN(sym) .globl SYM (sym)
#endif
asm( \".h8300h\" );
cpukit/score/cpu/h8300/rtems/score/cpu.h
-20
View File
@@ -431,26 +431,6 @@ typedef struct {
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/*
* On some CPUs, RTEMS supports a software managed interrupt stack.
* This stack is allocated by the Interrupt Manager and the switch
* is performed in _ISR_Handler. These variables contain pointers
* to the lowest and highest addresses in the chunk of memory allocated
* for the interrupt stack. Since it is unknown whether the stack
* grows up or down (in general), this give the CPU dependent
* code the option of picking the version it wants to use.
*
* NOTE: These two variables are required if the macro
* CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
*
* H8300 Specific Information:
*
* XXX
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
/*
* Nothing prevents the porter from declaring more CPU specific variables.
*