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https://gitlab.rtems.org/rtems/rtos/rtems.git
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LIBPCI: added DRVMGR model for PCI bus
This commit is contained in:
Daniel Hellstrom
@@ -40,6 +40,11 @@ libpci_a_SOURCES += pci_get_dev.c
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libpci_a_SOURCES += pci_irq.c
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libpci_a_SOURCES += pci_print.c
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# Driver manager PCI bus
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libpci_a_SOURCES += pci_bus.c
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include_drvmgrdir = $(includedir)/drvmgr
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include_drvmgr_HEADERS = pci_bus.h
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endif
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include $(srcdir)/preinstall.am
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,159 @@
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/* PCI bus driver Interface.
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*
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* COPYRIGHT (c) 2008.
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* Cobham Gaisler AB.
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*
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* General part of PCI Bus driver. The driver is typically
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* initialized from the PCI host driver separating the host
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* driver from the common parts in PCI drivers.
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* The PCI library must be initialized before starting the
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* PCI bus driver. The PCI library have set up BARs and
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* assigned system IRQs for targets.
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* This PCI bus driver rely on the PCI library (pci.c) for
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* interrupt registeration (pci_interrupt_register) and PCI
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* target set up.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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*/
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#ifndef __PCI_BUS_H__
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#define __PCI_BUS_H__
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#include <drvmgr/drvmgr.h>
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#include <pci.h>
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#include <pci/access.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* PCI Driver ID generation (VENDOR: 16-bit, DEVICE: 16-bit) */
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#define DRIVER_PCI_ID(vendor, device) \
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DRIVER_ID(DRVMGR_BUS_TYPE_PCI, \
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((((vendor) & 0xffff) << 16) | ((device) & 0xffff)))
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/* PCI Driver ID generation (CLASS: 24-bit) */
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#define DRIVER_PCI_CLASS(class) \
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DRIVER_ID(DRVMGR_BUS_TYPE_PCI, ((1 << 32) | ((class) & 0xffffff)))
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/* PCI driver IDs (DRIVER_PCI_VENDOR_DEVICE or DRIVER_PCI_CLASS_NAME) */
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#define DRIVER_PCI_GAISLER_RASTAIO_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO)
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#define DRIVER_PCI_GAISLER_RASTATMTC_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_TMTC)
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#define DRIVER_PCI_GAISLER_GR701_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_701)
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#define DRIVER_PCI_GAISLER_RASTAADCDAC_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC)
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#define DRIVER_PCI_GAISLER_TMTC_1553_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_TMTC_1553)
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#define DRIVER_PCI_GAISLER_RASTA_SPW_ROUTER_ID DRIVER_PCI_ID(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_SPW_RTR)
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struct pci_dev_id {
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uint16_t vendor;
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uint16_t device;
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uint16_t subvendor;
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uint16_t subdevice;
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uint32_t class; /* 24 lower bits */
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};
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struct pci_dev_id_match {
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uint16_t vendor;
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uint16_t device;
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uint16_t subvendor;
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uint16_t subdevice;
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uint32_t class; /* 24 lower bits */
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uint32_t class_mask; /* 24 lower bits */
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};
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#define PCIID_DEVVEND(vendor, device) \
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{vendor, device, PCI_ID_ANY, PCI_ID_ANY, 0, 0}
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#define PCIID_END_TABLE {0, 0, 0, 0, 0, 0}
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enum {
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/* A Device has up to 6 BARs and an optional ROM BAR */
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PCIDEV_RES_BAR1 = 0,
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PCIDEV_RES_BAR2 = 1,
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PCIDEV_RES_BAR3 = 2,
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PCIDEV_RES_BAR4 = 3,
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PCIDEV_RES_BAR5 = 4,
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PCIDEV_RES_BAR6 = 5,
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PCIDEV_RES_ROM = 6,
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};
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/* Maximum Number of Resources of a device */
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#define PCIDEV_RES_CNT (PCIDEV_RES_ROM + 1)
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/* IO, MEMIO or MEM resource. Can be BAR, ROM or Bridge Window */
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struct pcibus_res {
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uint32_t address; /* Base Address, CPU accessible */
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uint32_t size; /* 0=Unimplemented, 0!=Resource Size */
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struct pci_res *res; /* PCI-layer resource */
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};
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struct pci_dev_info {
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struct pci_dev_id id;
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uint8_t rev;
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uint8_t irq; /* 0 = NO IRQ */
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pci_dev_t pcidev;
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struct pcibus_res resources[PCIDEV_RES_CNT];
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struct pci_dev *pci_device;
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};
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struct pci_drv_info {
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struct drvmgr_drv general; /* General bus info */
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/* PCI specific bus information */
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struct pci_dev_id_match *ids; /* Supported hardware */
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};
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/* Access routines */
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struct pcibus_regmem_ops {
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drvmgr_r8 r8;
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drvmgr_r16 r16;
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drvmgr_r32 r32;
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drvmgr_r64 r64;
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drvmgr_w8 w8;
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drvmgr_w16 w16;
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drvmgr_w32 w32;
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drvmgr_w64 w64;
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};
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/* Let driver configure PCI bus driver */
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struct pcibus_config {
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struct drvmgr_map_entry *maps_up;
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struct drvmgr_map_entry *maps_down;
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};
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/* PCI Configuration Space Access - Not implemented (use PCI Lib directly) */
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#define PCI_FUNC_CFG_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_CFG)
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#define PCI_FUNC_CFG_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_CFG)
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#define PCI_FUNC_CFG_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_CFG)
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#define PCI_FUNC_CFG_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_CFG)
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#define PCI_FUNC_CFG_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_CFG)
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#define PCI_FUNC_CFG_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_CFG)
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/* PCI I/O Register Access - Not implemented (use PCI Lib directly) */
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#define PCI_FUNC_IO_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_IO)
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#define PCI_FUNC_IO_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_IO)
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#define PCI_FUNC_IO_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_IO)
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#define PCI_FUNC_IO_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_IO)
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#define PCI_FUNC_IO_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_IO)
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#define PCI_FUNC_IO_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_IO)
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/* PCI Register Access over Memory Space (Little Endian) */
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#define PCI_FUNC_MREG_R8 DRVMGR_RWFUNC(RW_SIZE_1|RW_READ|RW_MEMREG)
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#define PCI_FUNC_MREG_R16 DRVMGR_RWFUNC(RW_SIZE_2|RW_READ|RW_MEMREG|RW_LITTLE)
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#define PCI_FUNC_MREG_R32 DRVMGR_RWFUNC(RW_SIZE_4|RW_READ|RW_MEMREG|RW_LITTLE)
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#define PCI_FUNC_MREG_W8 DRVMGR_RWFUNC(RW_SIZE_1|RW_WRITE|RW_MEMREG)
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#define PCI_FUNC_MREG_W16 DRVMGR_RWFUNC(RW_SIZE_2|RW_WRITE|RW_MEMREG|RW_LITTLE)
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#define PCI_FUNC_MREG_W32 DRVMGR_RWFUNC(RW_SIZE_4|RW_WRITE|RW_MEMREG|RW_LITTLE)
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/* Weak default PCI driver resources, override this from project configuration
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* to set PCI Bus resources used to configure PCI device drivers.
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*/
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extern struct drvmgr_bus_res pcibus_drv_resources;
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/* Attach a PCI bus on top of a PCI Host device */
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extern int pcibus_register(struct drvmgr_dev *dev, struct pcibus_config *cfg);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -63,4 +63,13 @@ PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci/ids_extra.h
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$(PROJECT_INCLUDE)/pci/irq.h: pci/irq.h $(PROJECT_INCLUDE)/pci/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pci/irq.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/pci/irq.h
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$(PROJECT_INCLUDE)/drvmgr/$(dirstamp):
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@$(MKDIR_P) $(PROJECT_INCLUDE)/drvmgr
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@: > $(PROJECT_INCLUDE)/drvmgr/$(dirstamp)
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PREINSTALL_DIRS += $(PROJECT_INCLUDE)/drvmgr/$(dirstamp)
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$(PROJECT_INCLUDE)/drvmgr/pci_bus.h: pci_bus.h $(PROJECT_INCLUDE)/drvmgr/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/drvmgr/pci_bus.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/drvmgr/pci_bus.h
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endif
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