mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-08-24 06:48:26 +08:00
Beagle: GPIO support (for BBB)
GPIO Driver Development for BeagleBone Black based on the generic GPIO API
This commit is contained in:
Ketul Shah
Ben Gras
@@ -39,6 +39,8 @@ include_bsp_HEADERS += ../shared/include/arm-release-id.h
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include_bsp_HEADERS += ../shared/include/start.h
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include_bsp_HEADERS += include/irq.h
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include_bsp_HEADERS += include/i2c.h
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include_bsp_HEADERS += include/beagleboneblack.h
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include_bsp_HEADERS += include/bbb-gpio.h
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include_libcpu_HEADERS =
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include_libcpu_HEADERS += ../../../libcpu/arm/shared/include/arm-cp15.h
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@@ -82,6 +84,7 @@ libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
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libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
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libbsp_a_SOURCES += ../../shared/sbrk.c
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libbsp_a_SOURCES += ../../shared/src/stackalloc.c
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libbsp_a_SOURCES += ../../shared/gpio.c
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libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
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libbsp_a_SOURCES += ../../shared/timerstub.c
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libbsp_a_SOURCES += ../../shared/cpucounterread.c
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@@ -114,6 +117,9 @@ libbsp_a_SOURCES += ../../shared/console.c \
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# I2C
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libbsp_a_SOURCES += misc/i2c.c
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# GPIO
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libbsp_a_SOURCES += gpio/bbb-gpio.c
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#RTC
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libbsp_a_SOURCES += rtc.c
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libbsp_a_SOURCES += ../../shared/tod.c
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,43 @@
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/**
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* @file
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*
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* @ingroup arm_beagle
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*
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* @brief BeagleBone Black BSP definitions.
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*/
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/**
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* Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_BEAGLE_BBB_GPIO_H
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#define LIBBSP_ARM_BEAGLE_BBB_GPIO_H
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/**
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* @brief BeagleBone Black GPIO functions.
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*/
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#define BBB_DIGITAL_IN 2
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#define BBB_DIGITAL_OUT 1
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/**
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* @brief BeagleBone Black GPIO pad configuration.
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*/
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#define BBB_PUDEN (1 << 3)
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#define BBB_PUDDIS ~BBB_PUDEN
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#define BBB_PU_EN (1 << 4)
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#define BBB_PD_EN ~BBB_PU_EN
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#define BBB_MUXMODE(X) (X & 0x7)
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_BEAGLE_BBB_GPIO_H */
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@@ -0,0 +1,72 @@
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/**
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* @file
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*
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* @ingroup arm_beagle
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*
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* @brief BeagleBone Black BSP definitions.
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*/
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/**
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* Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H
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#define LIBBSP_ARM_BEAGLE_BEAGLEBONEBLACK_H
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/* In general GPIOs of BeagleBone Black/White can be addressed
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* using two 46-pin dual-row expansion connectors P9 and P8,
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* which are also known as Expansion A and Expansion B Connectors,
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* respectively.
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*
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* Each Expansion Connector consists of 23 pins. So 2x23 pins would
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* be available. It has 4 GPIO Banks each consists of 32 pins each.
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* Toatal number of pins are 128 (32x4).
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*
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* So for mapping between generalized pin name and the unique pin
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* numbers in this header file Macros are declared.
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*/
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/* USER LEDs of BeagleBone Black */
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#define BBB_LED_USR0 53 /* USR LED0 */
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#define BBB_LED_USR1 54 /* USR LED1 */
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#define BBB_LED_USR2 55 /* USR LED2 */
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#define BBB_LED_USR3 56 /* USR LED3 */
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/* Header P8 of BeagleBone Black */
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#define BBB_P8_7 66 /* GPIO2_2 */
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#define BBB_P8_8 67 /* GPIO2_3 */
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#define BBB_P8_9 69 /* GPIO2_5 */
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#define BBB_P8_10 68 /* GPIO2_4 */
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#define BBB_P8_11 45 /* GPIO1_13 */
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#define BBB_P8_12 44 /* GPIO1_12 */
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#define BBB_P8_13 23 /* GPIO0_23 */
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#define BBB_P8_14 26 /* GPIO0_26 */
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#define BBB_P8_15 47 /* GPIO1_15 */
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#define BBB_P8_16 46 /* GPIO1_14 */
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#define BBB_P8_17 27 /* GPIO0_27 */
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#define BBB_P8_18 65 /* GPIO2_1 */
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#define BBB_P8_19 22 /* GPIO0_22 */
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#define BBB_P8_26 61 /* GPIO1_29 */
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/* Header P9 of BeagleBone Black */
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#define BBB_P9_11 30 /* GPIO0_30 */
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#define BBB_P9_12 60 /* GPIO1_28 */
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#define BBB_P9_13 31 /* GPIO0_31 */
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#define BBB_P9_14 50 /* GPIO1_18 */
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#define BBB_P9_15 48 /* GPIO1_16 */
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#define BBB_P9_16 51 /* GPIO1_19 */
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#define BBB_P9_17 5 /* GPIO0_5 */
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#define BBB_P9_18 4 /* GPIO0_4 */
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#define BBB_P9_23 49 /* GPIO1_17 */
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#define BBB_P9_24 15 /* GPIO0_15 */
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#define BBB_P9_26 14 /* GPIO1_14 */
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#define BBB_P9_27 115/* GPIO3_19 */
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#define BBB_P9_30 112/* GPIO3_16 */
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#define BBB_P9_41 20 /* GPIO0_20 */
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#define BBB_P9_42 7 /* GPIO0_7 */
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#endif /* LIBBSP_ARM_BEAGLE_GPIO_H */
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@@ -31,6 +31,7 @@
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#include <stdint.h>
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#include <bsp/start.h>
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#include <bsp/default-initial-extension.h>
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#include <bsp/beagleboneblack.h>
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#include <rtems.h>
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#include <rtems/irq-extension.h>
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@@ -169,6 +170,17 @@ static inline void flush_data_cache(void)
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#define BEAGLE_BASE_UART_3 0x49020000
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#endif
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/* GPIO pin config */
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#if IS_AM335X
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#define BSP_GPIO_PIN_COUNT 128
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#define BSP_GPIO_PINS_PER_BANK 32
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#endif
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#if IS_DM3730
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#define BSP_GPIO_PIN_COUNT 192
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#define BSP_GPIO_PINS_PER_BANK 32
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#endif
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/* i2c stuff */
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typedef struct {
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uint32_t rx_or_tx;
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@@ -339,4 +351,4 @@ static inline void write_ttbr0(uint32_t bar)
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*/
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BSP_START_TEXT_SECTION void beagle_setup_mmu_and_cache(void);
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#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
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#endif /* LIBBSP_ARM_BEAGLE_BSP_H */
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@@ -110,6 +110,14 @@ $(PROJECT_INCLUDE)/bsp/i2c.h: include/i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2c.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2c.h
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$(PROJECT_INCLUDE)/bsp/beagleboneblack.h: include/beagleboneblack.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/beagleboneblack.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/beagleboneblack.h
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$(PROJECT_INCLUDE)/bsp/bbb-gpio.h: include/bbb-gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bbb-gpio.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bbb-gpio.h
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$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
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@@ -300,3 +300,171 @@
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#define AM335X_RTC_KICK0_KEY 0x83E70B13
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#define AM335X_RTC_KICK1_KEY 0x95A4F1E0
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/* GPIO memory-mapped registers */
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#define AM335X_GPIO0_BASE 0x44E07000
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/* GPIO Bank 0 base Register */
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#define AM335X_GPIO1_BASE 0x4804C000
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/* GPIO Bank 1 base Register */
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#define AM335X_GPIO2_BASE 0x481AC000
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/* GPIO Bank 2 base Register */
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#define AM335X_GPIO3_BASE 0x481AE000
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/* GPIO Bank 3 base Register */
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#define AM335X_GPIO_REVISION 0x00
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#define AM335X_GPIO_SYSCONFIG 0x10
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#define AM335X_GPIO_EOI 0x20
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#define AM335X_GPIO_IRQSTATUS_RAW_0 0x24
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#define AM335X_GPIO_IRQSTATUS_RAW_1 0x28
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#define AM335X_GPIO_IRQSTATUS_0 0x2C
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#define AM335X_GPIO_IRQSTATUS_1 0x30
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#define AM335X_GPIO_IRQSTATUS_SET_0 0x34
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#define AM335X_GPIO_IRQSTATUS_SET_1 0x38
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#define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C
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#define AM335X_GPIO_IRQSTATUS_CLR_1 0x40
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#define AM335X_GPIO_IRQWAKEN_0 0x44
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#define AM335X_GPIO_IRQWAKEN_1 0x48
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#define AM335X_GPIO_SYSSTATUS 0x114
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#define AM335X_GPIO_CTRL 0x130
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#define AM335X_GPIO_OE 0x134
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#define AM335X_GPIO_DATAIN 0x138
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#define AM335X_GPIO_DATAOUT 0x13C
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#define AM335X_GPIO_LEVELDETECT0 0x140
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#define AM335X_GPIO_LEVELDETECT1 0x144
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#define AM335X_GPIO_RISINGDETECT 0x148
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#define AM335X_GPIO_FALLINGDETECT 0x14C
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#define AM335X_GPIO_DEBOUNCENABLE 0x150
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#define AM335X_GPIO_DEBOUNCINGTIME 0x154
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#define AM335X_GPIO_CLEARDATAOUT 0x190
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#define AM335X_GPIO_SETDATAOUT 0x194
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/* AM335X Pad Configuration Register Base */
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#define AM335X_PADCONF_BASE 0x44E10000
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/* Memory mapped register offset for Control Module */
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#define AM335X_CONF_GPMC_AD0 0x800
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#define AM335X_CONF_GPMC_AD1 0x804
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#define AM335X_CONF_GPMC_AD2 0x808
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#define AM335X_CONF_GPMC_AD3 0x80C
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#define AM335X_CONF_GPMC_AD4 0x810
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#define AM335X_CONF_GPMC_AD5 0x814
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#define AM335X_CONF_GPMC_AD6 0x818
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#define AM335X_CONF_GPMC_AD7 0x81C
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#define AM335X_CONF_GPMC_AD8 0x820
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#define AM335X_CONF_GPMC_AD9 0x824
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#define AM335X_CONF_GPMC_AD10 0x828
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#define AM335X_CONF_GPMC_AD11 0x82C
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#define AM335X_CONF_GPMC_AD12 0x830
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#define AM335X_CONF_GPMC_AD13 0x834
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#define AM335X_CONF_GPMC_AD14 0x838
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#define AM335X_CONF_GPMC_AD15 0x83C
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#define AM335X_CONF_GPMC_A0 0x840
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#define AM335X_CONF_GPMC_A1 0x844
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#define AM335X_CONF_GPMC_A2 0x848
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#define AM335X_CONF_GPMC_A3 0x84C
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#define AM335X_CONF_GPMC_A4 0x850
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#define AM335X_CONF_GPMC_A5 0x854
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#define AM335X_CONF_GPMC_A6 0x858
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#define AM335X_CONF_GPMC_A7 0x85C
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#define AM335X_CONF_GPMC_A8 0x860
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#define AM335X_CONF_GPMC_A9 0x864
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#define AM335X_CONF_GPMC_A10 0x868
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#define AM335X_CONF_GPMC_A11 0x86C
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#define AM335X_CONF_GPMC_WAIT0 0x870
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#define AM335X_CONF_GPMC_WPN 0x874
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#define AM335X_CONF_GPMC_BEN1 0x878
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#define AM335X_CONF_GPMC_CSN0 0x87C
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#define AM335X_CONF_GPMC_CSN1 0x880
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#define AM335X_CONF_GPMC_CSN2 0x884
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#define AM335X_CONF_GPMC_CSN3 0x888
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#define AM335X_CONF_GPMC_CLK 0x88C
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#define AM335X_CONF_GPMC_ADVN_ALE 0x890
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#define AM335X_CONF_GPMC_OEN_REN 0x894
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#define AM335X_CONF_GPMC_WEN 0x898
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#define AM335X_CONF_GPMC_BEN0_CLE 0x89C
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#define AM335X_CONF_LCD_DATA0 0x8A0
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#define AM335X_CONF_LCD_DATA1 0x8A4
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#define AM335X_CONF_LCD_DATA2 0x8A8
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#define AM335X_CONF_LCD_DATA3 0x8AC
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#define AM335X_CONF_LCD_DATA4 0x8B0
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#define AM335X_CONF_LCD_DATA5 0x8B4
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#define AM335X_CONF_LCD_DATA6 0x8B8
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#define AM335X_CONF_LCD_DATA7 0x8BC
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#define AM335X_CONF_LCD_DATA8 0x8C0
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#define AM335X_CONF_LCD_DATA9 0x8C4
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#define AM335X_CONF_LCD_DATA10 0x8C8
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#define AM335X_CONF_LCD_DATA11 0x8CC
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#define AM335X_CONF_LCD_DATA12 0x8D0
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#define AM335X_CONF_LCD_DATA13 0x8D4
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#define AM335X_CONF_LCD_DATA14 0x8D8
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#define AM335X_CONF_LCD_DATA15 0x8DC
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#define AM335X_CONF_LCD_VSYNC 0x8E0
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#define AM335X_CONF_LCD_HSYNC 0x8E4
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#define AM335X_CONF_LCD_PCLK 0x8E8
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#define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC
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#define AM335X_CONF_MMC0_DAT3 0x8F0
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#define AM335X_CONF_MMC0_DAT2 0x8F4
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#define AM335X_CONF_MMC0_DAT1 0x8F8
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#define AM335X_CONF_MMC0_DAT0 0x8FC
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#define AM335X_CONF_MMC0_CLK 0x900
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#define AM335X_CONF_MMC0_CMD 0x904
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#define AM335X_CONF_MII1_COL 0x908
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#define AM335X_CONF_MII1_CRS 0x90C
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#define AM335X_CONF_MII1_RX_ER 0x910
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#define AM335X_CONF_MII1_TX_EN 0x914
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#define AM335X_CONF_MII1_RX_DV 0x918
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#define AM335X_CONF_MII1_TXD3 0x91C
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#define AM335X_CONF_MII1_TXD2 0x920
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#define AM335X_CONF_MII1_TXD1 0x924
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#define AM335X_CONF_MII1_TXD0 0x928
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#define AM335X_CONF_MII1_TX_CLK 0x92C
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#define AM335X_CONF_MII1_RX_CLK 0x930
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#define AM335X_CONF_MII1_RXD3 0x934
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#define AM335X_CONF_MII1_RXD2 0x938
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#define AM335X_CONF_MII1_RXD1 0x93C
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#define AM335X_CONF_MII1_RXD0 0x940
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#define AM335X_CONF_RMII1_REF_CLK 0x944
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#define AM335X_CONF_MDIO 0x948
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#define AM335X_CONF_MDC 0x94C
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#define AM335X_CONF_SPI0_SCLK 0x950
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#define AM335X_CONF_SPI0_D0 0x954
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#define AM335X_CONF_SPI0_D1 0x958
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#define AM335X_CONF_SPI0_CS0 0x95C
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#define AM335X_CONF_SPI0_CS1 0x960
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#define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964
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#define AM335X_CONF_UART0_CTSN 0x968
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#define AM335X_CONF_UART0_RTSN 0x96C
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#define AM335X_CONF_UART0_RXD 0x970
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#define AM335X_CONF_UART0_TXD 0x974
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#define AM335X_CONF_UART1_CTSN 0x978
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#define AM335X_CONF_UART1_RTSN 0x97C
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#define AM335X_CONF_UART1_RXD 0x980
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#define AM335X_CONF_UART1_TXD 0x984
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#define AM335X_CONF_I2C0_SDA 0x988
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#define AM335X_CONF_I2C0_SCL 0x98C
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#define AM335X_CONF_MCASP0_ACLKX 0x990
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#define AM335X_CONF_MCASP0_FSX 0x994
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#define AM335X_CONF_MCASP0_AXR0 0x998
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#define AM335X_CONF_MCASP0_AHCLKR 0x99C
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#define AM335X_CONF_MCASP0_ACLKR 0x9A0
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#define AM335X_CONF_MCASP0_FSR 0x9A4
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#define AM335X_CONF_MCASP0_AXR1 0x9A8
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#define AM335X_CONF_MCASP0_AHCLKX 0x9AC
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#define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0
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#define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4
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#define AM335X_CONF_WARMRSTN 0x9B8
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#define AM335X_CONF_NNMI 0x9C0
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#define AM335X_CONF_TMS 0x9D0
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#define AM335X_CONF_TDI 0x9D4
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#define AM335X_CONF_TDO 0x9D8
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#define AM335X_CONF_TCK 0x9DC
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#define AM335X_CONF_TRSTN 0x9E0
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#define AM335X_CONF_EMU0 0x9E4
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#define AM335X_CONF_EMU1 0x9E8
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#define AM335X_CONF_RTC_PWRONRSTN 0x9F8
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#define AM335X_CONF_PMIC_POWER_EN 0x9FC
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#define AM335X_CONF_EXT_WAKEUP 0xA00
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#define AM335X_CONF_RTC_KALDO_ENN 0xA04
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#define AM335X_CONF_USB0_DRVVBUS 0xA1C
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||||
#define AM335X_CONF_USB1_DRVVBUS 0xA34
|
||||
Reference in New Issue
Block a user