bsp/altera-cyclone-v: Enable unified L2 cache

c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c

@@ -55,7 +55,11 @@ bool _CPU_SMP_Start_processor(uint32_t cpu_index)
       ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK
     );
 
-    started = true;
+    /*
+     * Wait for secondary processor to complete its basic initialization so
+     * that we can enable the unified L2 cache.
+     */
+    started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
   } else {
     started = false;
   }
@@ -76,6 +80,9 @@ void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
       NULL
     );
     assert(sc == RTEMS_SUCCESSFUL);
+
+    /* Enable unified L2 cache */
+    rtems_cache_enable_data();
   }
 }
 

c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c

@@ -104,5 +104,9 @@ BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
   arm_a9mpcore_start_hook_1();
   bsp_start_copy_sections();
   setup_mmu_and_cache();
+#ifndef RTEMS_SMP
+  /* Enable unified L2 cache */
+  rtems_cache_enable_data();
+#endif
   bsp_start_clear_bss();
 }