rtems: Conditionally define rtems_interrupt_frame

Update #2808.
This commit is contained in:
Sebastian Huber
2016-11-18 07:30:32 +01:00
parent 8ef8a32d00
commit 141e16d225
16 changed files with 21 additions and 16 deletions
+6 -1
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@@ -98,13 +98,18 @@ typedef Context_Control rtems_context;
typedef Context_Control_fp rtems_context_fp;
#endif
#if (CPU_ISR_PASSES_FRAME_POINTER == TRUE)
/**
* @brief Defines the format of the interrupt stack frame as it appears to a
* user ISR.
*
* This data structure may not be defined on all ports
* This data structure is only provided if the interrupt stack frame is passed
* to the ISR handler.
*
* @see rtems_interrupt_catch().
*/
typedef CPU_Interrupt_frame rtems_interrupt_frame;
#endif
/**
* @brief Information structure returned by the Heap Handler via the Region
+1 -1
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@@ -118,7 +118,7 @@
#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
#define CPU_HARDWARE_FP FALSE
+1 -1
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@@ -115,7 +115,7 @@ extern "C" {
*
* XXX document implementation including references if appropriate
*/
#define CPU_ISR_PASSES_FRAME_POINTER 1
#define CPU_ISR_PASSES_FRAME_POINTER TRUE
/**
* @def CPU_HARDWARE_FP
+1 -1
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@@ -117,7 +117,7 @@ extern "C" {
*
*/
#define CPU_ISR_PASSES_FRAME_POINTER 1
#define CPU_ISR_PASSES_FRAME_POINTER TRUE
/*
* Does the CPU have hardware floating point?
+1 -1
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@@ -60,7 +60,7 @@ extern "C" {
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/*
* Some family members have no FP, some have an FPU such as the i387
+1 -1
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@@ -113,7 +113,7 @@ extern "C" {
*
* XXX document implementation including references if appropriate
*/
#define CPU_ISR_PASSES_FRAME_POINTER 1
#define CPU_ISR_PASSES_FRAME_POINTER TRUE
/**
* @def CPU_HARDWARE_FP
+1 -1
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@@ -129,7 +129,7 @@ extern "C" {
*
* XXX document implementation including references if appropriate
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/**
* @def CPU_HARDWARE_FP
+1 -1
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@@ -61,7 +61,7 @@ extern "C" {
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/*
* Some family members have no FP, some have an FPU such as the
+1 -1
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@@ -136,7 +136,7 @@ extern "C" {
*
*/
#define CPU_ISR_PASSES_FRAME_POINTER 1
#define CPU_ISR_PASSES_FRAME_POINTER TRUE
+1 -1
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@@ -130,7 +130,7 @@ extern "C" {
*
* XXX document implementation including references if appropriate
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/**
* @def CPU_HARDWARE_FP
+1 -1
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@@ -107,7 +107,7 @@ extern "C" {
*
*/
#define CPU_ISR_PASSES_FRAME_POINTER 1
#define CPU_ISR_PASSES_FRAME_POINTER TRUE
/*
* Does the CPU have hardware floating point?
+1 -1
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@@ -544,7 +544,7 @@ typedef struct CPU_Interrupt_frame {
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/*
* Should the saving of the floating point registers be deferred
+1 -1
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@@ -87,7 +87,7 @@ extern "C" {
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/*
* Does the CPU have hardware floating point?
+1 -1
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@@ -107,7 +107,7 @@ extern "C" {
* The SPARC port does not pass an Interrupt Stack Frame pointer to
* interrupt handlers.
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/**
* Does the CPU have hardware floating point?
+1 -1
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@@ -84,7 +84,7 @@ extern "C" {
* number (0)?
*/
#define CPU_ISR_PASSES_FRAME_POINTER 0
#define CPU_ISR_PASSES_FRAME_POINTER FALSE
/*
* Does the CPU have hardware floating point?
+1 -1
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@@ -58,7 +58,7 @@ typedef void * ISR_Handler_entry;
/**
* Pointer to an ISR Handler
*/
#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
#if (CPU_ISR_PASSES_FRAME_POINTER == TRUE)
typedef ISR_Handler ( *ISR_Handler_entry )(
ISR_Vector_number,
CPU_Interrupt_frame *