mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-20 16:08:37 +08:00
@@ -98,13 +98,18 @@ typedef Context_Control rtems_context;
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typedef Context_Control_fp rtems_context_fp;
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#endif
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#if (CPU_ISR_PASSES_FRAME_POINTER == TRUE)
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/**
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* @brief Defines the format of the interrupt stack frame as it appears to a
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* user ISR.
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*
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* This data structure may not be defined on all ports
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* This data structure is only provided if the interrupt stack frame is passed
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* to the ISR handler.
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*
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* @see rtems_interrupt_catch().
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*/
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typedef CPU_Interrupt_frame rtems_interrupt_frame;
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#endif
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/**
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* @brief Information structure returned by the Heap Handler via the Region
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@@ -118,7 +118,7 @@
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#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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#define CPU_HARDWARE_FP FALSE
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@@ -115,7 +115,7 @@ extern "C" {
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*
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* XXX document implementation including references if appropriate
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 1
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#define CPU_ISR_PASSES_FRAME_POINTER TRUE
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/**
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* @def CPU_HARDWARE_FP
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@@ -117,7 +117,7 @@ extern "C" {
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*
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 1
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#define CPU_ISR_PASSES_FRAME_POINTER TRUE
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/*
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* Does the CPU have hardware floating point?
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@@ -60,7 +60,7 @@ extern "C" {
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* number (0)?
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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/*
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* Some family members have no FP, some have an FPU such as the i387
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@@ -113,7 +113,7 @@ extern "C" {
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*
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* XXX document implementation including references if appropriate
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 1
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#define CPU_ISR_PASSES_FRAME_POINTER TRUE
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/**
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* @def CPU_HARDWARE_FP
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@@ -129,7 +129,7 @@ extern "C" {
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*
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* XXX document implementation including references if appropriate
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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/**
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* @def CPU_HARDWARE_FP
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@@ -61,7 +61,7 @@ extern "C" {
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* number (0)?
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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/*
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* Some family members have no FP, some have an FPU such as the
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@@ -136,7 +136,7 @@ extern "C" {
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*
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 1
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#define CPU_ISR_PASSES_FRAME_POINTER TRUE
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@@ -130,7 +130,7 @@ extern "C" {
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*
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* XXX document implementation including references if appropriate
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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/**
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* @def CPU_HARDWARE_FP
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@@ -107,7 +107,7 @@ extern "C" {
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*
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 1
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#define CPU_ISR_PASSES_FRAME_POINTER TRUE
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/*
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* Does the CPU have hardware floating point?
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@@ -544,7 +544,7 @@ typedef struct CPU_Interrupt_frame {
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* number (0)?
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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/*
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* Should the saving of the floating point registers be deferred
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@@ -87,7 +87,7 @@ extern "C" {
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* number (0)?
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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/*
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* Does the CPU have hardware floating point?
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@@ -107,7 +107,7 @@ extern "C" {
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* The SPARC port does not pass an Interrupt Stack Frame pointer to
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* interrupt handlers.
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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/**
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* Does the CPU have hardware floating point?
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@@ -84,7 +84,7 @@ extern "C" {
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* number (0)?
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*/
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#define CPU_ISR_PASSES_FRAME_POINTER 0
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#define CPU_ISR_PASSES_FRAME_POINTER FALSE
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/*
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* Does the CPU have hardware floating point?
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@@ -58,7 +58,7 @@ typedef void * ISR_Handler_entry;
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/**
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* Pointer to an ISR Handler
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*/
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#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
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#if (CPU_ISR_PASSES_FRAME_POINTER == TRUE)
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typedef ISR_Handler ( *ISR_Handler_entry )(
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ISR_Vector_number,
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CPU_Interrupt_frame *
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