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https://gitlab.rtems.org/rtems/rtos/rtems.git
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cpukit/microblaze: Add exception framework
This patch updates the CPU_Exception_frame to include all necessary registers, combines hardware snd software exception handlers into a shared vector, provides an architecture-specific hook for taking control of exception handling, and moves exception handling over to actually using the CPU_Exception_frame instead of a minimal interrupt stack frame. As the significant contents of _exception_handler.S have been entirely rewritten, the copyright information on this file has been updated to reflect that.
This commit is contained in:
Kinsey Moore
committed by
Joel Sherrill
Joel Sherrill
parent
37543e1968
commit
127980c799
@@ -1,52 +1,103 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/* SPDX-License-Identifier: BSD-2-Clause */
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/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
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/**
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* @file
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*
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* @ingroup RTEMSBSPsMicroBlaze
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*
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* @brief MicroBlaze exception handler implementation
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*/
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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/*
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* Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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1. Redistributions source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of Xilinx nor the names of its contributors may be
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used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
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IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems/score/cpu.h>
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.text
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.globl _exception_handler # Exception Handler Label
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.align 2
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_exception_handler:
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#ifndef __rtems__
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rtsd r17, 0
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/* Subtract exception frame */
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addik r1, r1, -(CPU_EXCEPTION_FRAME_SIZE)
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/* Store program state */
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swi r2, r1, MICROBLAZE_EXCEPTION_FRAME_R2
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R3
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swi r4, r1, MICROBLAZE_EXCEPTION_FRAME_R4
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swi r5, r1, MICROBLAZE_EXCEPTION_FRAME_R5
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swi r6, r1, MICROBLAZE_EXCEPTION_FRAME_R6
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swi r7, r1, MICROBLAZE_EXCEPTION_FRAME_R7
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swi r8, r1, MICROBLAZE_EXCEPTION_FRAME_R8
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swi r9, r1, MICROBLAZE_EXCEPTION_FRAME_R9
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swi r10, r1, MICROBLAZE_EXCEPTION_FRAME_R10
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swi r11, r1, MICROBLAZE_EXCEPTION_FRAME_R11
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swi r12, r1, MICROBLAZE_EXCEPTION_FRAME_R12
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swi r13, r1, MICROBLAZE_EXCEPTION_FRAME_R13
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swi r14, r1, MICROBLAZE_EXCEPTION_FRAME_R14
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swi r15, r1, MICROBLAZE_EXCEPTION_FRAME_R15
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swi r16, r1, MICROBLAZE_EXCEPTION_FRAME_R16
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swi r17, r1, MICROBLAZE_EXCEPTION_FRAME_R17
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swi r18, r1, MICROBLAZE_EXCEPTION_FRAME_R18
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swi r19, r1, MICROBLAZE_EXCEPTION_FRAME_R19
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swi r20, r1, MICROBLAZE_EXCEPTION_FRAME_R20
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swi r21, r1, MICROBLAZE_EXCEPTION_FRAME_R21
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swi r22, r1, MICROBLAZE_EXCEPTION_FRAME_R22
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swi r23, r1, MICROBLAZE_EXCEPTION_FRAME_R23
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swi r24, r1, MICROBLAZE_EXCEPTION_FRAME_R24
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swi r25, r1, MICROBLAZE_EXCEPTION_FRAME_R25
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swi r26, r1, MICROBLAZE_EXCEPTION_FRAME_R26
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swi r27, r1, MICROBLAZE_EXCEPTION_FRAME_R27
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swi r28, r1, MICROBLAZE_EXCEPTION_FRAME_R28
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swi r29, r1, MICROBLAZE_EXCEPTION_FRAME_R29
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swi r30, r1, MICROBLAZE_EXCEPTION_FRAME_R30
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swi r31, r1, MICROBLAZE_EXCEPTION_FRAME_R31
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/* Retrieve and store MSR */
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mfs r3, rmsr
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_MSR
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/* Retrieve and store EAR */
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mfs r3, rear
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_EAR
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/* Retrieve and store ESR */
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mfs r3, resr
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_ESR
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/* Retrieve and store BTR */
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mfs r3, rbtr
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_BTR
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/* Calculate and store original stack pointer */
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addik r3, r1, CPU_EXCEPTION_FRAME_SIZE
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swi r3, r1, MICROBLAZE_EXCEPTION_FRAME_R1
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/* set parameter 1 to CPU Exception frame */
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addi r5, r1, 0
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/* call into the debug framework */
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braid _MicroBlaze_Exception_handle
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nop
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#else /* __rtems__ */
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/* Subtract stack frame */
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addik r1, r1, -52
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swi r5, r1, 8
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addi r5, r0, 0xFFFF
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braid _ISR_Handler
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nop
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#endif /* __rtems__ */
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@@ -1,52 +0,0 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
|
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met:
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|
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1. Redistributions source code must retain the above copyright notice,
|
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this list of conditions and the following disclaimer.
|
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|
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2. Redistributions in binary form must reproduce the above copyright
|
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notice, this list of conditions and the following disclaimer in the
|
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documentation and/or other materials provided with the distribution.
|
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|
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3. Neither the name of Xilinx nor the names of its contributors may be
|
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used to endorse or promote products derived from this software without
|
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specific prior written permission.
|
||||
|
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
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IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
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TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
|
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
|
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.text
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.globl _hw_exception_handler # HW Exception Handler Label
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.align 2
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_hw_exception_handler:
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#ifndef __rtems__
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rtsd r17, 0
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nop
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#else /* __rtems__ */
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/* Subtract stack frame */
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addik r1, r1, -52
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swi r5, r1, 8
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addi r5, r0, 0xFFFF
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braid _ISR_Handler
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nop
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#endif /* __rtems__ */
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@@ -76,7 +76,12 @@ _vector_interrupt:
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.section .vectors.hw_exception, "ax"
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.align 2
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_vector_hw_exception:
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brai _hw_exception_handler
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/*
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* Hardware and software exceptions are handled identically with the MSR[EiP]
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* bit differentiating them and determining which register should be used for
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* return.
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*/
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brai _exception_handler
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.section .text
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.globl _start1
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@@ -38,6 +38,10 @@
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#include "config.h"
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#endif
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#include <inttypes.h>
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#include <rtems/bspIo.h>
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#include <rtems/fatal.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/tls.h>
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#include <rtems/score/wkspace.h>
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@@ -75,6 +79,60 @@ void _CPU_Context_Initialize(
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void _CPU_Exception_frame_print( const CPU_Exception_frame *ctx )
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{
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printk(
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"\n"
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"R0 = 0x%08" PRIx32 " R17 = %p\n"
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"R1 = 0x%08" PRIx32 " R18 = 0x%08" PRIx32 "\n"
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"R2 = 0x%08" PRIx32 " R19 = 0x%08" PRIx32 "\n"
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"R3 = 0x%08" PRIx32 " R20 = 0x%08" PRIx32 "\n"
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"R4 = 0x%08" PRIx32 " R21 = 0x%08" PRIx32 "\n"
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"R5 = 0x%08" PRIx32 " R22 = 0x%08" PRIx32 "\n"
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"R6 = 0x%08" PRIx32 " R23 = 0x%08" PRIx32 "\n"
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"R7 = 0x%08" PRIx32 " R24 = 0x%08" PRIx32 "\n"
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"R8 = 0x%08" PRIx32 " R25 = 0x%08" PRIx32 "\n"
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"R9 = 0x%08" PRIx32 " R26 = 0x%08" PRIx32 "\n"
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"R10 = 0x%08" PRIx32 " R27 = 0x%08" PRIx32 "\n"
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"R11 = 0x%08" PRIx32 " R28 = 0x%08" PRIx32 "\n"
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"R12 = 0x%08" PRIx32 " R29 = 0x%08" PRIx32 "\n"
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"R13 = 0x%08" PRIx32 " R30 = 0x%08" PRIx32 "\n"
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"R14 = %p" " R31 = 0x%08" PRIx32 "\n"
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"R15 = %p" " ESR = 0x%08" PRIx32 "\n"
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"R16 = %p" " EAR = %p\n",
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0, ctx->r17,
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ctx->r1, ctx->r18,
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ctx->r2, ctx->r19,
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ctx->r3, ctx->r20,
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ctx->r4, ctx->r21,
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ctx->r5, ctx->r22,
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ctx->r6, ctx->r23,
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ctx->r7, ctx->r24,
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ctx->r8, ctx->r25,
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ctx->r9, ctx->r26,
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ctx->r10, ctx->r27,
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ctx->r11, ctx->r28,
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ctx->r12, ctx->r29,
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ctx->r13, ctx->r30,
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ctx->r14, ctx->r31,
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ctx->r15, ctx->esr,
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ctx->r16, ctx->ear
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);
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printk(
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"MSR = 0x%08" PRIx32 " %s%s%s%s%s%s%s%s%s%s%s%s\n",
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ctx->msr,
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( ctx->msr & MICROBLAZE_MSR_VM ) ? "VM " : "",
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( ctx->msr & MICROBLAZE_MSR_UM ) ? "UM " : "",
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( ctx->msr & MICROBLAZE_MSR_PVR ) ? "PVR " : "",
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( ctx->msr & MICROBLAZE_MSR_EIP ) ? "EiP " : "",
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( ctx->msr & MICROBLAZE_MSR_EE ) ? "EE " : "",
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( ctx->msr & MICROBLAZE_MSR_DCE ) ? "DCE " : "",
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( ctx->msr & MICROBLAZE_MSR_DZO ) ? "DZO " : "",
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( ctx->msr & MICROBLAZE_MSR_ICE ) ? "ICE " : "",
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( ctx->msr & MICROBLAZE_MSR_FSL ) ? "FSL " : "",
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( ctx->msr & MICROBLAZE_MSR_BIP ) ? "BiP " : "",
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( ctx->msr & MICROBLAZE_MSR_C ) ? "C " : "",
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( ctx->msr & MICROBLAZE_MSR_IE ) ? "IE " : ""
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);
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}
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void _CPU_ISR_Set_level( uint32_t level )
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@@ -118,3 +176,30 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
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while ( true ) {
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}
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}
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MicroBlaze_Exception_handler installed_exception_handler = NULL;
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void _MicroBlaze_Exception_install_handler(
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MicroBlaze_Exception_handler new_handler,
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MicroBlaze_Exception_handler *old_handler
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)
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{
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if ( old_handler != NULL ) {
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*old_handler = installed_exception_handler;
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}
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installed_exception_handler = new_handler;
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}
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void _MicroBlaze_Exception_handle( CPU_Exception_frame *ef )
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{
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/* EiP is not set for user exceptions which are unused and not hooked */
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if (
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( ef->msr & MICROBLAZE_MSR_EIP ) != 0
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&& installed_exception_handler != NULL
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) {
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installed_exception_handler( ef );
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}
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rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) ef );
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}
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@@ -54,9 +54,6 @@ _ISR_Handler:
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swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
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swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
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xori r3, r5, 0xFFFF
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beqi r3, do_exception
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/* Disable dispatching */
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lwi r3, r0, _Per_CPU_Information + 16
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addik r3, r3, 1
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@@ -180,13 +177,3 @@ thread_dispatch:
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addik r1, r1, 52
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bri quick_exit
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do_exception:
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/* exception no longer in progress */
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mfs r3, rmsr
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andni r3, r3, 0x200
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mts rmsr, r3
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addi r5, r0, 9
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add r6, r0, r1
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brai _Terminate
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@@ -65,6 +65,44 @@
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#define CPU_MODES_INTERRUPT_MASK 0x00000001
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#define MICROBLAZE_EXCEPTION_FRAME_R1 0
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#define MICROBLAZE_EXCEPTION_FRAME_R2 4
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#define MICROBLAZE_EXCEPTION_FRAME_R3 8
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#define MICROBLAZE_EXCEPTION_FRAME_R4 12
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#define MICROBLAZE_EXCEPTION_FRAME_R5 16
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#define MICROBLAZE_EXCEPTION_FRAME_R6 20
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#define MICROBLAZE_EXCEPTION_FRAME_R7 24
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#define MICROBLAZE_EXCEPTION_FRAME_R8 28
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#define MICROBLAZE_EXCEPTION_FRAME_R9 32
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#define MICROBLAZE_EXCEPTION_FRAME_R10 36
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#define MICROBLAZE_EXCEPTION_FRAME_R11 40
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#define MICROBLAZE_EXCEPTION_FRAME_R12 44
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#define MICROBLAZE_EXCEPTION_FRAME_R13 48
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#define MICROBLAZE_EXCEPTION_FRAME_R14 52
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#define MICROBLAZE_EXCEPTION_FRAME_R15 56
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#define MICROBLAZE_EXCEPTION_FRAME_R16 60
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#define MICROBLAZE_EXCEPTION_FRAME_R17 64
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#define MICROBLAZE_EXCEPTION_FRAME_R18 68
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#define MICROBLAZE_EXCEPTION_FRAME_R19 72
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#define MICROBLAZE_EXCEPTION_FRAME_R20 76
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#define MICROBLAZE_EXCEPTION_FRAME_R21 80
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#define MICROBLAZE_EXCEPTION_FRAME_R22 84
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#define MICROBLAZE_EXCEPTION_FRAME_R23 88
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#define MICROBLAZE_EXCEPTION_FRAME_R24 92
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#define MICROBLAZE_EXCEPTION_FRAME_R25 96
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#define MICROBLAZE_EXCEPTION_FRAME_R26 100
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#define MICROBLAZE_EXCEPTION_FRAME_R27 104
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#define MICROBLAZE_EXCEPTION_FRAME_R28 108
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#define MICROBLAZE_EXCEPTION_FRAME_R29 112
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#define MICROBLAZE_EXCEPTION_FRAME_R30 116
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#define MICROBLAZE_EXCEPTION_FRAME_R31 120
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#define MICROBLAZE_EXCEPTION_FRAME_MSR 124
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#define MICROBLAZE_EXCEPTION_FRAME_EAR 128
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#define MICROBLAZE_EXCEPTION_FRAME_ESR 132
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#define MICROBLAZE_EXCEPTION_FRAME_BTR 136
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#define CPU_EXCEPTION_FRAME_SIZE 140
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#ifndef ASM
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#ifdef __cplusplus
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@@ -139,8 +177,23 @@ typedef struct {
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#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
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#define MICROBLAZE_MSR_IE (1 << 1)
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#define MICROBLAZE_MSR_EE (1 << 8)
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/*
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* bit definitions in the documentation are reversed for all special registers
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* such that bit 0 is the most significant bit
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*/
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#define MICROBLAZE_MSR_VM ( 1 << 13 )
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#define MICROBLAZE_MSR_UM ( 1 << 11 )
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#define MICROBLAZE_MSR_PVR ( 1 << 10 )
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#define MICROBLAZE_MSR_EIP ( 1 << 9 )
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#define MICROBLAZE_MSR_EE ( 1 << 8 )
|
||||
#define MICROBLAZE_MSR_DCE ( 1 << 7 )
|
||||
#define MICROBLAZE_MSR_DZO ( 1 << 6 )
|
||||
#define MICROBLAZE_MSR_ICE ( 1 << 5 )
|
||||
#define MICROBLAZE_MSR_FSL ( 1 << 4 )
|
||||
#define MICROBLAZE_MSR_BIP ( 1 << 3 )
|
||||
#define MICROBLAZE_MSR_C ( 1 << 2 )
|
||||
#define MICROBLAZE_MSR_IE ( 1 << 1 )
|
||||
|
||||
|
||||
#define _CPU_MSR_GET( _msr_value ) \
|
||||
do { \
|
||||
@@ -228,8 +281,42 @@ void _CPU_Context_Initialize(
|
||||
#define CPU_PER_CPU_CONTROL_SIZE 0
|
||||
|
||||
typedef struct {
|
||||
/* TODO: enumerate registers */
|
||||
uint32_t r[32];
|
||||
/* r0 is unnecessary since it is always 0 */
|
||||
uint32_t r1;
|
||||
uint32_t r2;
|
||||
uint32_t r3; /* return 1/scratch */
|
||||
uint32_t r4; /* return 2/scratch */
|
||||
uint32_t r5; /* param 1/scratch */
|
||||
uint32_t r6; /* param 2/scratch */
|
||||
uint32_t r7; /* param 3/scratch */
|
||||
uint32_t r8; /* param 4/scratch */
|
||||
uint32_t r9; /* param 5/scratch */
|
||||
uint32_t r10; /* param 6/scratch */
|
||||
uint32_t r11; /* scratch */
|
||||
uint32_t r12; /* scratch */
|
||||
uint32_t r13;
|
||||
uint32_t *r14; /* Interrupt Link Register */
|
||||
uint32_t *r15; /* Link Register */
|
||||
uint32_t *r16; /* Trap/Debug Link Register */
|
||||
uint32_t *r17; /* Exception Link Register */
|
||||
uint32_t r18;
|
||||
uint32_t r19;
|
||||
uint32_t r20;
|
||||
uint32_t r21;
|
||||
uint32_t r22;
|
||||
uint32_t r23;
|
||||
uint32_t r24;
|
||||
uint32_t r25;
|
||||
uint32_t r26;
|
||||
uint32_t r27;
|
||||
uint32_t r28;
|
||||
uint32_t r29;
|
||||
uint32_t r30;
|
||||
uint32_t r31;
|
||||
uint32_t msr; /* Machine Status Register */
|
||||
uint32_t *ear; /* Exception Address Register */
|
||||
uint32_t esr; /* Exception Status Register */
|
||||
uint32_t *btr; /* Branch Target Register */
|
||||
} CPU_Exception_frame;
|
||||
|
||||
/* end of Priority handler macros */
|
||||
@@ -246,6 +333,17 @@ void _CPU_ISR_install_vector(
|
||||
CPU_ISR_handler *old_handler
|
||||
);
|
||||
|
||||
typedef void ( *MicroBlaze_Exception_handler )( CPU_Exception_frame *ef );
|
||||
|
||||
void _MicroBlaze_Exception_install_handler(
|
||||
MicroBlaze_Exception_handler new_handler,
|
||||
MicroBlaze_Exception_handler *old_handler
|
||||
);
|
||||
|
||||
void _MicroBlaze_Exception_handle(
|
||||
CPU_Exception_frame *ef
|
||||
);
|
||||
|
||||
void _CPU_Context_switch(
|
||||
Context_Control *run,
|
||||
Context_Control *heir
|
||||
|
||||
@@ -26,7 +26,6 @@ source:
|
||||
- bsps/microblaze/microblaze_fpga/fdt/bsp_fdt.c
|
||||
- bsps/microblaze/microblaze_fpga/irq/irq.c
|
||||
- bsps/microblaze/microblaze_fpga/start/_exception_handler.S
|
||||
- bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S
|
||||
- bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
|
||||
- bsps/microblaze/microblaze_fpga/start/bspreset.c
|
||||
- bsps/microblaze/microblaze_fpga/start/bspstart.c
|
||||
|
||||
Reference in New Issue
Block a user