bsps: Option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0

Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM
GIC support.  Enable this option for arm/altera-cyclone-v and
arm/xilinx-zynq BSPs by default.

bsps/arm/altera-cyclone-v/include/bsp.h

@@ -60,8 +60,6 @@ extern "C" {
 
 #define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
 
-#define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
-
 #define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
 
 #define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )

bsps/shared/dev/irq/arm-gicv2.c

@@ -56,18 +56,18 @@
 /*
  * The following variants
  *
- *  - GICv1 with Security Extensions,
- *  - GICv2 without Security Extensions, or
- *  - within Secure processor mode
+ * - GICv1 with Security Extensions,
+ * - GICv2 without Security Extensions, and
+ * - GICv2 with Security Extensions and in Secure processor mode
  *
  * have the ability to assign group 0 or 1 to individual interrupts.  Group
  * 0 interrupts can be configured to raise an FIQ exception.  This enables
  * the use of NMIs with respect to RTEMS.
  *
- * BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
- * define.  Use arm_gic_irq_set_group() to change the group of an
- * interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
- * defined).
+ * Use arm_gic_irq_set_group() to change the group of an interrupt (default
+ * group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined).  To use FIQ
+ * interrupts, you have to install an FIQ exception handler and enable FIQs in
+ * the Current Program Status Register (CPSR).
  */
 #ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
 #define DIST_ICDDCR (GIC_DIST_ICDDCR_ENABLE_GRP_1 | GIC_DIST_ICDDCR_ENABLE)

spec/build/bsps/dev/irq/objarmgicv2.yml

@@ -15,6 +15,8 @@ install:
   - bsps/include/dev/irq/arm-gic-regs.h
   - bsps/include/dev/irq/arm-gic-tm27.h
 links:
+- role: build-dependency
+  uid: optarmgic-enable-fiq-for-group-0
 - role: build-dependency
   uid: grpaarch64gic
 - role: build-dependency

spec/build/bsps/dev/irq/objarmgicv3.yml

@@ -16,6 +16,8 @@ install:
   - bsps/include/dev/irq/arm-gic-tm27.h
   - bsps/include/dev/irq/arm-gicv3.h
 links:
+- role: build-dependency
+  uid: optarmgic-enable-fiq-for-group-0
 - role: build-dependency
   uid: optarmgic-icc-bpr0
 - role: build-dependency

spec/build/bsps/dev/irq/optarmgic-enable-fiq-for-group-0.yml

@@ -0,0 +1,31 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-boolean: null
+- define-condition: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by:
+  - bsps/arm/altera-cyclone-v
+  - bsps/arm/xilinx-zynq
+  value: true
+- enabled-by: true
+  value: false
+description: |
+  This option enables the use FIQ interrupts for GIC group 0 interrupts.  The
+  ARM Generic Interrupt Controller (GIC) variants GICv1 with Security
+  Extensions, GICv2 without Security Extensions, GICv2 with Security Extensions
+  and in Secure processor mode, GICv3 and GICv4 in Secure processor mode, GICv3
+  and GICv4 with GICD_CTLR.DS == 1 have the ability to assign group 0 or 1 to
+  individual interrupts.  Group 0 interrupts can be configured to raise an FIQ
+  exception.  This enables the use of NMIs with respect to RTEMS.  Use
+  arm_gic_irq_set_group() to change the group of an interrupt (default group is
+  1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is defined).  To use FIQ interrupts,
+  you have to install an FIQ exception handler and enable FIQs in the Current
+  Program Status Register (CPSR).
+enabled-by: true
+format: '{}'
+links: []
+name: BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
+type: build