score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.

Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.

cpukit/score/cpu/arm/rtems/score/arm.h

@@ -54,6 +54,10 @@ extern "C" {
   #define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
 #endif
 
+#if defined(__ARM_ARCH_7A__)
+  #define ARM_MULTILIB_CACHE_LINE_MAX_64
+#endif
+
 #if !defined(__SOFTFP__)
   #if defined(__ARM_NEON__)
     #define ARM_MULTILIB_VFP_D32

cpukit/score/cpu/arm/rtems/score/cpu.h

@@ -145,8 +145,11 @@
 
 #define CPU_STACK_GROWS_UP FALSE
 
-/* FIXME: Is this the right value? */
-#define CPU_CACHE_LINE_BYTES 32
+#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64)
+  #define CPU_CACHE_LINE_BYTES 32
+#else
+  #define CPU_CACHE_LINE_BYTES 64
+#endif
 
 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )