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bsp/altera-cyclone-v: Add Alteras hwlib
Add files from Alteras hwlib
This commit is contained in:
Ralf Kirchner
committed by
Sebastian Huber
Sebastian Huber
parent
f73cfe99d0
commit
0b03ca39a4
@@ -0,0 +1,13 @@
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HWLIB
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=====
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Hwlib is a collection of sources provided by Altera for the Cyclone-V.
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As hwlib is third party software, please keep modifications and additions
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to the sources to a minimum for easy maintenance. Otherwise updating to a
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new version of hwlib released by Altera can become difficult.
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The hwlib directory contains only those files from Alteras hwlib which are
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required by the BSP (the whole hwlib was considered too big).
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The directory structure within the hwlib directory is equivalent to Alteras
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hwlib directory structure. For easy maintenance only whole files have been
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left out.
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@@ -0,0 +1,390 @@
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/*! \file
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* Altera - SoC FPGA Address Space Manager
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*/
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/******************************************************************************
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*
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* Copyright 2013 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
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* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __ALT_ADDR_SPACE_H__
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#define __ALT_ADDR_SPACE_H__
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#include <stdbool.h>
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#include "hwlib.h"
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#include "socal/hps.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif /* __cplusplus */
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/******************************************************************************/
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// ARM Level 2 Cache Controller L2C-310 Register Interface
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// Address Filtering Start Register
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// The Address Filtering Start Register is a read and write register.
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// Bits Field Description
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// :-------|:--------------------------|:-----------------------------------------
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// [31:20] | address_filtering_start | Address filtering start address for
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// | | bits [31:20] of the filtering address.
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// [19:1] | Reserved | SBZ/RAZ
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// [0] | address_filtering_enable | 0 - address filtering disabled
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// | | 1 - address filtering enabled.
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// Address Filtering Start Register Address
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#define L2_CACHE_ADDR_FILTERING_START_OFST 0xC00
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#define L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST)
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// Address Filtering Start Register - Start Value Mask
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#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
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// Address Filtering Start Register - Reset Start Address Value (1 MB)
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#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
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// Address Filtering Start Register - Enable Flag Mask
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#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001
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// Address Filtering Start Register - Reset Enable Flag Value (Enabled)
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#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1
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// Address Filtering End Register
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// The Address Filtering End Register is a read and write register.
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// Bits Field Description
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// :-------|:--------------------------|:-----------------------------------------
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// [31:20] | address_filtering_end | Address filtering end address for bits
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// | | [31:20] of the filtering address.
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// [19:0] | Reserved | SBZ/RAZ
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// Address Filtering End Register Address
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#define L2_CACHE_ADDR_FILTERING_END_OFST 0xC04
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#define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST)
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// Address Filtering End Register - End Value Mask
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#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000
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// Address Filtering End Register - Reset End Address Value (3 GB)
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#define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000
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#ifndef __ASSEMBLY__
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/******************************************************************************/
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/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager
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*
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* This module contains group APIs for managing the HPS address space. This
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* module contains group APIs to manage:
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* * Memory Map Control
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* * Memory Coherence
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* * Cache Managment
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* * MMU Managment
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*
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* @{
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*/
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/******************************************************************************/
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/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control
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*
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* This group API provides functions to map and remap selected address ranges
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* into the accessible (visible) views of the MPU and non MPU address spaces.
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*
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* \b Caveats
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*
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* \b NOTE: Caution should be observed when remapping address 0 to different
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* memory. The code performing the remapping operation should not be executing
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* in the address range being remapped to different memory.
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*
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* For example, if address 0 is presently mapped to OCRAM and the code is
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* preparing to remap address 0 to SDRAM, then the code must not be executing in
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* the range 0 to 64 KB as this address space is about to be remapped to
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* different memory. If the code performing the remap operation is executing
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* from OCRAM then it needs to be executing from its permanently mapped OCRAM
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* address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR).
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*
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* \b NOTE: The MPU address space view is controlled by two disparate hardware
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* control interfaces: the L3 remap register and the L2 cache address filtering
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* registers. To complicate matters, the L3 remap register is write-only which
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* means not only that current remap register state cannot be read but also that
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* a read-modify-write operation cannot be performed on the register.
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*
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* This should not present a problem in most use case scenarios except for the
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* case where a current MPU address space mapping of 0 to SDRAM is being changed
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* to to a mapping of 0 to Boot ROM or OCRAM.
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*
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* In this case, a two step process whereby the L3 remap register is first set
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* to the new desired MPU address 0 mapping and then the L2 cache address
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* filtering registers have their address ranges adjusted accordingly must be
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* followed. An example follows:
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\verbatim
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// 1 MB reset default value for address filtering start
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#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
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uint32_t addr_filt_start;
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uint32_t addr_filt_end;
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// Perform L3 remap register programming first by setting the desired new MPU
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// address space 0 mapping. Assume OCRAM for the example.
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alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...);
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// Next, adjust the L2 cache address filtering range. Set the start address to
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// the default reset value and retain the existing end address configuration.
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alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end);
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if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET)
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{
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alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end);
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}
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\endverbatim
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* @{
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*/
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/******************************************************************************/
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/*!
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* This type definition enumerates the MPU address space attributes.
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*
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* The MPU address space consists of the ARM Cortex A9 processors and associated
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* processor peripherals (cache, MMU).
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*/
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typedef enum ALT_ADDR_SPACE_MPU_ATTR_e
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{
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ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, /*!< Maps the Boot ROM to address
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* 0x0 for the MPU L3 master. Note
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* that the Boot ROM is also
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* always mapped to address
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* 0xfffd_0000 for the MPU L3
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* master independent of
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* attribute.
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*/
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ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address
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* 0x0 for the MPU L3 master. Note
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* that the On-chip RAM is also
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* always mapped to address
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* 0xffff_0000 for the MPU L3
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* master independent of this
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* attribute.
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*/
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} ALT_ADDR_SPACE_MPU_ATTR_t;
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/******************************************************************************/
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/*!
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* This type definition enumerates the non-MPU address space attributes.
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*
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* The non-MPU address space consists of the non-MPU L3 masters including the
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* DMA controllers (standalone and those built into peripherals), the F2H AXI
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* Bridge, and the DAP.
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*/
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typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e
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{
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ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM, /*!< Maps the SDRAM to address 0x0
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* for the non-MPU L3 masters.
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*/
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ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM /*!< Maps the On-chip RAM to address
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* 0x0 for the non-MPU L3
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* masters. Note that the On-chip
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* RAM is also always mapped to
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* address 0xffff_0000 for the
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* non-MPU L3 masters independent
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* of this attribute.
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*/
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} ALT_ADDR_SPACE_NONMPU_ATTR_t;
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/******************************************************************************/
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/*!
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* This type definition enumerates the HPS to FPGA bridge accessiblity
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* attributes.
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*/
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typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e
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{
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ALT_ADDR_SPACE_H2F_INACCESSIBLE, /*!< The H2F AXI Bridge is not
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* visible to L3 masters. Accesses
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* to the associated address range
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* return an AXI decode error to
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* the master.
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*/
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ALT_ADDR_SPACE_H2F_ACCESSIBLE /*!< The H2F AXI Bridge is visible
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* to L3 masters.
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*/
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} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t;
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/******************************************************************************/
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/*!
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* This type definition enumerates the Lightweight HPS to FPGA bridge
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* accessiblity attributes.
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*/
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typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e
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{
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ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, /*!< The LWH2F AXI Bridge is not
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* visible to L3 masters. Accesses
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* to the associated address range
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* return an AXI decode error to
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* the master.
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*/
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ALT_ADDR_SPACE_LWH2F_ACCESSIBLE /*!< The LWH2F AXI Bridge is visible
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* to L3 masters.
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*/
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} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t;
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/******************************************************************************/
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/*!
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* Configures the mapped and accessible (visible) address ranges for the HPS
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* MPU, non-MPU, and Bridge address spaces.
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*
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* \param mpu_attr
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* The MPU address space configuration attributes.
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*
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* \param nonmpu_attr
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* The non-MPU address space configuration attributes.
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*
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* \param h2f_attr
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* The H2F Bridge attribute mapping and accessibility attributes.
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*
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* \param lwh2f_attr
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* The Lightweight H2F Bridge attribute mapping and accessibility
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* attributes.
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*
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*
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* \retval ALT_E_SUCCESS The operation was succesful.
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* \retval ALT_E_ERROR The operation failed.
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* \retval ALT_E_INV_OPTION One or more invalid attribute options were
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* specified.
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*/
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ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
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ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
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ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr,
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ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr);
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/******************************************************************************/
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/*!
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* Maps SDRAM to address 0x0 for the MPU address space view.
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*
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* When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest
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* 64KB of the boot region are accessible because the size of the Boot ROM and
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* on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MB) to
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* 0xC0000000 (3GB) access SDRAM and addresses in the range 0xC0000000 (3GB) to
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* 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MB of SDRAM is not
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* accessible to the MPU unless address 0 is remapped to SDRAM after reset.
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*
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* This function remaps the addresses between 0x0 to 0x100000 (1MB) to access
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* SDRAM.
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*
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* \internal
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* The remap to address 0x0 is achieved by configuring the L2 cache Address
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* Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM
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* AXI (M1) master port by calling:
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*
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* alt_l2_addr_filter_cfg_set(0x0, <current_addr_filt_end_value>);
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*
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* See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
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* Reference Manual, Section 3.3.12 Address Filtering </em>.
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* \endinternal
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*
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* \retval ALT_E_SUCCESS The operation was succesful.
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* \retval ALT_E_ERROR The operation failed.
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*/
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ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void);
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/*! @} */
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/******************************************************************************/
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/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter
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*
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* The L2 cache address filter controls where physical addresses within certain
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* ranges of the MPU address space are directed.
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*
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* The L2 cache has master port connections to the L3 interconnect and the SDRAM
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* controller. A programmable address filter controls which portions of the
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* 32-bit physical address space use each master.
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*
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* When l2 address filtering is configured and enabled, a physical address will
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* be redirected to one master or the other based upon the address filter
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* configuration.
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*
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* If \b address_filter_start <= \e physical_address < \b address_filter_end:
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* * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller)
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* * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect)
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*
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* See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
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* Reference Manual, Section 3.3.12 Address Filtering </em> for more information.
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* @{
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*/
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/******************************************************************************/
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/*!
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* Get the L2 cache address filtering configuration settings.
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*
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* \param addr_filt_start
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* [out] An output parameter variable for the address filtering
|
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* start address for the range of physical addresses redirected to
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* the SDRAM AXI master port. The value returned is always a 1 MB
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* aligned address.
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*
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* \param addr_filt_end
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* [out] An output parameter variable for the address filtering
|
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* end address for the range of physical addresses redirected to
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* the SDRAM AXI master port. The value returned is always a 1 MB
|
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* aligned address.
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*
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* \retval ALT_E_SUCCESS The operation was successful.
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* \retval ALT_E_ERROR The operation failed.
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* \retval ALT_E_BAD_ARG An bad argument was passed. Either \e addr_filt_start
|
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* or \e addr_filt_end or both are invalid addresses.
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*/
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ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
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uint32_t* addr_filt_end);
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/******************************************************************************/
|
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/*!
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* Set the L2 cache address filtering configuration settings.
|
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*
|
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* Address filtering start and end values must be 1 MB aligned.
|
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*
|
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* \param addr_filt_start
|
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* The address filtering start address for the range of physical
|
||||
* addresses redirected to the SDRAM AXI master port. Only bits
|
||||
* [31:20] of the address are valid. Any bits outside the range
|
||||
* [31:20] are invalid and will cause an error status to be
|
||||
* returned.
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*
|
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* \param addr_filt_end
|
||||
* The address filtering end address for the range of physical
|
||||
* addresses redirected to the SDRAM AXI master port. Only bits
|
||||
* [31:20] of the address are valid. Any bits outside the range
|
||||
* [31:20] are invalid and will cause an error status to be
|
||||
* returned.
|
||||
*
|
||||
* \retval ALT_E_SUCCESS The operation was succesful.
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||||
* \retval ALT_E_ERROR The operation failed.
|
||||
* \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
|
||||
* more address arguments do not satisfy the argument
|
||||
* constraints.
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*/
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ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
|
||||
uint32_t addr_filt_end);
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __ALT_ADDR_SPACE_H__ */
|
||||
@@ -0,0 +1,95 @@
|
||||
/*! \file
|
||||
* Contains the definition of an opaque data structure that contains raw
|
||||
* configuration information for a clock group.
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright 2013 Altera Corporation. All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ALT_CLK_GRP_H__
|
||||
#define __ALT_CLK_GRP_H__
|
||||
|
||||
#include "hwlib.h"
|
||||
#include "socal/alt_clkmgr.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
/*! This type definition enumerates the clock groups
|
||||
*/
|
||||
typedef enum ALT_CLK_GRP_e
|
||||
{
|
||||
ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */
|
||||
|
||||
ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */
|
||||
|
||||
ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */
|
||||
|
||||
} ALT_CLK_GRP_t;
|
||||
|
||||
|
||||
|
||||
/*! This type definition defines an opaque data structure for holding the
|
||||
* configuration settings for a complete clock group.
|
||||
*/
|
||||
typedef struct ALT_CLK_GROUP_RAW_CFG_s
|
||||
{
|
||||
uint32_t verid; /*!< SoC FPGA version identifier. This field
|
||||
* encapsulates the silicon identifier and
|
||||
* version information associated with this
|
||||
* clock group configuration. It is used to
|
||||
* assert that this clock group configuration
|
||||
* is valid for this device.
|
||||
*/
|
||||
uint32_t siliid2; /*!< Reserved register - reserved for future
|
||||
* device IDs or capability flags/
|
||||
*/
|
||||
ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator */
|
||||
|
||||
|
||||
/*! This union holds the raw register values for configuration of the set of
|
||||
* possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
|
||||
* identifies the valid clock group union data member.
|
||||
*/
|
||||
union ALT_CLK_GROUP_RAW_CFG_u
|
||||
{
|
||||
ALT_CLKMGR_MAINPLL_t mainpllgrp; /*!< Raw clock group configuration for Main PLL group */
|
||||
ALT_CLKMGR_PERPLL_t perpllgrp; /*!< Raw clock group configuration for Peripheral PLL group */
|
||||
ALT_CLKMGR_SDRPLL_t sdrpllgrp; /*!< Raw clock group configuration for SDRAM PLL group */
|
||||
} clkgrp;
|
||||
} ALT_CLK_GROUP_RAW_CFG_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __ALT_CLK_GRP_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,52 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright 2013 Altera Corporation. All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ALT_HWLIBS_VER_H__
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* Set of macros to provide version information
|
||||
*
|
||||
***********************************************************************/
|
||||
|
||||
/* This is the major revision of the Altera ACDS Release */
|
||||
#define ALTERA_ACDS_MAJOR_REV 13
|
||||
|
||||
/* This is the minor revision of the Altera ACDS Release */
|
||||
#define ALTERA_ACDS_MINOR_REV 0
|
||||
|
||||
/* This is an internal HwLibs revision control code. */
|
||||
/* End-users should NOT depend upon the value of this field */
|
||||
#define ALTERA_HWLIBS_REV 0
|
||||
|
||||
/* This is a text string containing the current release and service pack IDs */
|
||||
#define ALTERA_ACDS_REV_STR "13.0SP1"
|
||||
|
||||
#endif /* __ALT_HWLIBS_VER_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,156 @@
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright 2013 Altera Corporation. All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ALT_MPUSCU_H__
|
||||
#define __ALT_MPUSCU_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
/************************************************************************************************************/
|
||||
/* alt_mpuscu.h */
|
||||
/* */
|
||||
/* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */
|
||||
/* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */
|
||||
/* */
|
||||
/************************************************************************************************************/
|
||||
|
||||
#ifndef ALT_HPS_ADDR
|
||||
#define ALT_HPS_ADDR 0x00
|
||||
#endif
|
||||
|
||||
|
||||
/* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */
|
||||
/* and is the address of the base of the Snoop Control Unit (SCU) */
|
||||
#define GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET)
|
||||
#define CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET)
|
||||
#define CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
|
||||
#define CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET)
|
||||
#define CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
|
||||
|
||||
|
||||
/* offsets */
|
||||
/* Global Timer offsets */
|
||||
#define GLOBALTMR_MODULE_BASE_OFFSET 0x00000200
|
||||
#define GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000
|
||||
#define GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004
|
||||
#define GLOBALTMR_CTRL_REG_OFFSET 0x00000008
|
||||
#define GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C
|
||||
#define GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010
|
||||
#define GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014
|
||||
#define GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018
|
||||
|
||||
/* Global Timer bitmasks */
|
||||
#define GLOBALTMR_ENABLE_BIT 0x00000001
|
||||
#define GLOBALTMR_COMP_ENABLE_BIT 0x00000002
|
||||
#define GLOBALTMR_INT_ENABLE_BIT 0x00000004
|
||||
#define GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008
|
||||
#define GLOBALTMR_PS_MASK 0x0000FF00
|
||||
#define GLOBALTMR_PS_SHIFT 8
|
||||
#define GLOBALTMR_INT_STATUS_BIT 0x00000001
|
||||
|
||||
/* Global timer constants */
|
||||
#define GLOBALTMR_MAX 0xFFFFFFFF
|
||||
#define GLOBALTMR_PS_MAX 0x000000FF
|
||||
|
||||
|
||||
/* Private timer offsets */
|
||||
#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600
|
||||
#define CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000
|
||||
#define CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004
|
||||
#define CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008
|
||||
#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C
|
||||
|
||||
/* Private timer bitmasks */
|
||||
#define CPU_PRIV_TMR_ENABLE 0x00000001
|
||||
#define CPU_PRIV_TMR_AUTO_RELOAD 0x00000002
|
||||
#define CPU_PRIV_TMR_INT_EN 0x00000004
|
||||
#define CPU_PRIV_TMR_PS_MASK 0x0000FF00
|
||||
#define CPU_PRIV_TMR_PS_SHIFT 8
|
||||
#define CPU_PRIV_TMR_INT_STATUS 0x00000001
|
||||
|
||||
/* Private timer constants */
|
||||
#define CPU_PRIV_TMR_MAX 0xFFFFFFFF
|
||||
#define CPU_PRIV_TMR_PS_MAX 0x000000FF
|
||||
|
||||
|
||||
|
||||
/* Watchdog timer offsets */
|
||||
#define WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620
|
||||
#define WDOG_LOAD_REG_OFFSET 0x00000000
|
||||
#define WDOG_CNTR_REG_OFFSET 0x00000004
|
||||
#define WDOG_CTRL_REG_OFFSET 0x00000008
|
||||
#define WDOG_INTSTAT_REG_OFFSET 0x0000000C
|
||||
#define WDOG_RSTSTAT_REG_OFFSET 0x00000010
|
||||
#define WDOG_DISABLE_REG_OFFSET 0x00000014
|
||||
|
||||
/* Watchdog timer bitmasks : */
|
||||
/* Control Register bitmasks */
|
||||
#define WDOG_TMR_ENABLE 0x00000001
|
||||
#define WDOG_AUTO_RELOAD 0x00000002
|
||||
#define WDOG_INT_EN 0x00000004
|
||||
#define WDOG_WDT_MODE 0x00000008
|
||||
#define WDOG_PS_MASK 0x0000FF00
|
||||
#define WDOG_PS_SHIFT 8
|
||||
/* Interrupt Status Register bitmasks */
|
||||
#define WDOG_INT_STAT_BIT 0x00000001
|
||||
/* Reset Status Register bitmasks */
|
||||
#define WDOG_RST_STAT_BIT 0x00000001
|
||||
|
||||
/* Watchdog timer constants */
|
||||
#define WDOG_TMR_MAX UINT32_MAX
|
||||
#define WDOG_PS_MAX UINT8_MAX
|
||||
#define WDOG_DISABLE_VAL0 0x12345678
|
||||
#define WDOG_DISABLE_VAL1 0x87654321
|
||||
|
||||
|
||||
|
||||
/* Interrupt Manager offsets */
|
||||
/* <Add definitions here> */
|
||||
#define INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100
|
||||
#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000
|
||||
#define INT_DIST_TYPE_REG 0x00000004
|
||||
|
||||
|
||||
/* Upper bound of the MPUSCU address space */
|
||||
#define MPUSCU_MAX 0x00001FFF
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __ALT_MPUSCU_H__ */
|
||||
@@ -0,0 +1,249 @@
|
||||
/*! \file
|
||||
* Altera - SoC Reset Manager
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright 2013 Altera Corporation. All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __ALT_RESET_MGR_H__
|
||||
#define __ALT_RESET_MGR_H__
|
||||
|
||||
#include "hwlib.h"
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! \addtogroup RST_MGR The Reset Manager
|
||||
*
|
||||
* The Reset Manager API defines functions for accessing, configuring, and
|
||||
* controlling the HPS reset behavior.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/*! \addtogroup RST_MGR_STATUS Reset Status
|
||||
*
|
||||
* This functional group provides information on various aspects of SoC reset
|
||||
* status and timeout events.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/*!
|
||||
* This type definition enumerates the set of reset causes and timeout events as
|
||||
* register mask values.
|
||||
*/
|
||||
typedef enum ALT_RESET_EVENT_e
|
||||
{
|
||||
/*! Power-On Voltage Detector Cold Reset */
|
||||
ALT_RESET_EVENT_PORVOLTRST = 0x00000001,
|
||||
|
||||
/*! nPOR Pin Cold Reset */
|
||||
ALT_RESET_EVENT_NPORPINRST = 0x00000002,
|
||||
|
||||
/*! FPGA Core Cold Reset */
|
||||
ALT_RESET_EVENT_FPGACOLDRST = 0x00000004,
|
||||
|
||||
/*! CONFIG_IO Cold Reset */
|
||||
ALT_RESET_EVENT_CONFIGIOCOLDRST = 0x00000008,
|
||||
|
||||
/*! Software Cold Reset */
|
||||
ALT_RESET_EVENT_SWCOLDRST = 0x00000010,
|
||||
|
||||
/*! nRST Pin Warm Reset */
|
||||
ALT_RESET_EVENT_NRSTPINRST = 0x00000100,
|
||||
|
||||
/*! FPGA Core Warm Reset */
|
||||
ALT_RESET_EVENT_FPGAWARMRST = 0x00000200,
|
||||
|
||||
/*! Software Warm Reset */
|
||||
ALT_RESET_EVENT_SWWARMRST = 0x00000400,
|
||||
|
||||
/*! MPU Watchdog 0 Warm Reset */
|
||||
ALT_RESET_EVENT_MPUWD0RST = 0x00001000,
|
||||
|
||||
/*! MPU Watchdog 1 Warm Reset */
|
||||
ALT_RESET_EVENT_MPUWD1RST = 0x00002000,
|
||||
|
||||
/*! L4 Watchdog 0 Warm Reset */
|
||||
ALT_RESET_EVENT_L4WD0RST = 0x00004000,
|
||||
|
||||
/*! L4 Watchdog 1 Warm Reset */
|
||||
ALT_RESET_EVENT_L4WD1RST = 0x00008000,
|
||||
|
||||
/*! FPGA Core Debug Reset */
|
||||
ALT_RESET_EVENT_FPGADBGRST = 0x00040000,
|
||||
|
||||
/*! DAP Debug Reset */
|
||||
ALT_RESET_EVENT_CDBGREQRST = 0x00080000,
|
||||
|
||||
/*! SDRAM Self-Refresh Timeout */
|
||||
ALT_RESET_EVENT_SDRSELFREFTIMEOUT = 0x01000000,
|
||||
|
||||
/*! FPGA manager handshake Timeout */
|
||||
ALT_RESET_EVENT_FPGAMGRHSTIMEOUT = 0x02000000,
|
||||
|
||||
/*! SCAN manager handshake Timeout */
|
||||
ALT_RESET_EVENT_SCANHSTIMEOUT = 0x04000000,
|
||||
|
||||
/*! FPGA handshake Timeout */
|
||||
ALT_RESET_EVENT_FPGAHSTIMEOUT = 0x08000000,
|
||||
|
||||
/*! ETR Stall Timeout */
|
||||
ALT_RESET_EVENT_ETRSTALLTIMEOUT = 0x10000000
|
||||
} ALT_RESET_EVENT_t;
|
||||
|
||||
/******************************************************************************/
|
||||
/*!
|
||||
* Gets the reset and timeout events that caused the last reset.
|
||||
*
|
||||
* The ALT_RESET_EVENT_t enumeration values should be used to selectively
|
||||
* examine the returned reset cause(s).
|
||||
*
|
||||
* \returns A mask of the reset and/or timeout events that caused the last
|
||||
* reset.
|
||||
*/
|
||||
uint32_t alt_reset_event_get(void);
|
||||
|
||||
/******************************************************************************/
|
||||
/*!
|
||||
* Clears the reset and timeout events that caused the last reset.
|
||||
*
|
||||
* \param event_mask
|
||||
* A mask of the selected reset and timeout events to clear in the
|
||||
* Reset Manager \e stat register. The mask selection can be formed
|
||||
* using the ALT_RESET_EVENT_t enumeration values.
|
||||
*
|
||||
* \retval ALT_E_SUCCESS The operation was succesful.
|
||||
* \retval ALT_E_ERROR The operation failed.
|
||||
*/
|
||||
ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask);
|
||||
|
||||
/*! @} */
|
||||
|
||||
/******************************************************************************/
|
||||
/*! \addtogroup RST_MGR_CTRL Reset Control
|
||||
*
|
||||
* This functional group provides global and selective reset control for the SoC
|
||||
* and its constituent modules.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************************************************************************/
|
||||
/*!
|
||||
* Initiate a cold reset of the SoC.
|
||||
*
|
||||
* If this function is successful, then it should never return.
|
||||
*
|
||||
* \retval ALT_E_SUCCESS The operation was succesful.
|
||||
* \retval ALT_E_ERROR The operation failed.
|
||||
*/
|
||||
ALT_STATUS_CODE alt_reset_cold_reset(void);
|
||||
|
||||
/******************************************************************************/
|
||||
/*!
|
||||
* Initiate a warm reset of the SoC.
|
||||
*
|
||||
* Perform a hardware sequenced warm reset of the SoC. A hardware sequenced
|
||||
* reset handshake with certain modules can optionally be requested in an
|
||||
* attempt to ensure an orderly reset transition.
|
||||
*
|
||||
* \param warm_reset_delay
|
||||
* Specifies the number of cycles after the Reset Manager releases
|
||||
* the Clock Manager reset before releasing any other hardware
|
||||
* controlled resets. Value must be greater than 16 and less than
|
||||
* 256.
|
||||
*
|
||||
* \param nRST_pin_clk_assertion
|
||||
* Specifies that number of clock cycles (osc1_clk?) to externally
|
||||
* assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <=
|
||||
* (2**20 - 1). A value of 0 prevents any assertion of nRST.
|
||||
*
|
||||
* \param sdram_refresh
|
||||
* Controls whether the contents of SDRAM survive a hardware
|
||||
* sequenced warm reset. The reset manager requests the SDRAM
|
||||
* controller to put SDRAM devices into self-refresh mode before
|
||||
* asserting warm reset signals. An argument value of \b true
|
||||
* enables the option, \b false disables the option.
|
||||
*
|
||||
* \param fpga_mgr_handshake
|
||||
* Controls whether a handshake between the reset manager and FPGA
|
||||
* manager occurs before a warm reset. The handshake is used to
|
||||
* warn the FPGA manager that a warm reset is imminent so it can
|
||||
* prepare for it by driving its output clock to a quiescent state
|
||||
* to avoid glitches. An argument value of \b true enables the
|
||||
* option, \b false disables the option.
|
||||
*
|
||||
* \param scan_mgr_handshake
|
||||
* Controls whether a handshake between the reset manager and scan
|
||||
* manager occurs before a warm reset. The handshake is used to
|
||||
* warn the scan manager that a warm reset is imminent so it can
|
||||
* prepare for it by driving its output clock to a quiescent state
|
||||
* to avoid glitches. An argument value of \b true enables the
|
||||
* option, \b false disables the option.
|
||||
*
|
||||
* \param fpga_handshake
|
||||
* Controls whether a handshake between the reset manager and the
|
||||
* FPGA occurs before a warm reset. The handshake is used to warn
|
||||
* the FPGA that a warm reset is imminent so that the FPGA prepare
|
||||
* for the reset event in soft IP. An argument value of \b true
|
||||
* enables the option, \b false disables the option.
|
||||
*
|
||||
* \param etr_stall
|
||||
* Controls whether the ETR is requested to idle its AXI master
|
||||
* interface (i.e. finish outstanding transactions and not initiate
|
||||
* any more) to the L3 Interconnect before a warm reset. An
|
||||
* argument value of \b true enables the option, \b false disables
|
||||
* the option.
|
||||
*
|
||||
* \retval ALT_E_SUCCESS The operation was succesful.
|
||||
* \retval ALT_E_ERROR The operation failed.
|
||||
*/
|
||||
ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
|
||||
uint32_t nRST_pin_clk_assertion,
|
||||
bool sdram_refresh,
|
||||
bool fpga_mgr_handshake,
|
||||
bool scan_mgr_handshake,
|
||||
bool fpga_handshake,
|
||||
bool etr_stall);
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*! @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __ALT_RESET_MGR_H__ */
|
||||
@@ -0,0 +1,190 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright 2013 Altera Corporation. All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HWLIB_H__
|
||||
#define __HWLIB_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
#include <cstddef>
|
||||
#include <cstdbool>
|
||||
#include <cstdint>
|
||||
#else /* __cplusplus */
|
||||
#include <stddef.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include "alt_hwlibs_ver.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*!
|
||||
* The type definition for status codes returned by the HWLIB.
|
||||
*/
|
||||
typedef int32_t ALT_STATUS_CODE;
|
||||
|
||||
/*! Definitions of status codes returned by the HWLIB. */
|
||||
|
||||
/*! The operation was successful. */
|
||||
#define ALT_E_SUCCESS 0
|
||||
|
||||
/*! The operation failed. */
|
||||
#define ALT_E_ERROR (-1)
|
||||
/*! FPGA configuration error detected.*/
|
||||
#define ALT_E_FPGA_CFG (-2)
|
||||
/*! FPGA CRC error detected. */
|
||||
#define ALT_E_FPGA_CRC (-3)
|
||||
/*! An error occurred on the FPGA configuration bitstream input source. */
|
||||
#define ALT_E_FPGA_CFG_STM (-4)
|
||||
/*! The FPGA is powered off. */
|
||||
#define ALT_E_FPGA_PWR_OFF (-5)
|
||||
/*! The SoC does not currently control the FPGA. */
|
||||
#define ALT_E_FPGA_NO_SOC_CTRL (-6)
|
||||
/*! The FPGA is not in USER mode. */
|
||||
#define ALT_E_FPGA_NOT_USER_MODE (-7)
|
||||
/*! An argument violates a range constraint. */
|
||||
#define ALT_E_ARG_RANGE (-8)
|
||||
/*! A bad argument value was passed. */
|
||||
#define ALT_E_BAD_ARG (-9)
|
||||
/*! The operation is invalid or illegal. */
|
||||
#define ALT_E_BAD_OPERATION (-10)
|
||||
/*! An invalid option was selected. */
|
||||
#define ALT_E_INV_OPTION (-11)
|
||||
/*! An operation or response timeout period expired. */
|
||||
#define ALT_E_TMO (-12)
|
||||
/*! The argument value is reserved or unavailable. */
|
||||
#define ALT_E_RESERVED (-13)
|
||||
/*! A clock is not enabled or violates an operational constraint. */
|
||||
#define ALT_E_BAD_CLK (-14)
|
||||
/*! The version ID is invalid. */
|
||||
#define ALT_E_BAD_VERSION (-15)
|
||||
/*! The buffer does not contain enough free space for the operation. */
|
||||
#define ALT_E_BUF_OVF (-20)
|
||||
|
||||
|
||||
/*!
|
||||
* Indicates a FALSE condition.
|
||||
*/
|
||||
#define ALT_E_FALSE (0)
|
||||
/*!
|
||||
* Indicates a TRUE condition.
|
||||
*/
|
||||
#define ALT_E_TRUE (1)
|
||||
|
||||
/* Note, additional positive status codes may be defined to return
|
||||
* a TRUE condition with additional information */
|
||||
|
||||
|
||||
/* Some other useful definitions */
|
||||
|
||||
/*!
|
||||
* Specifies the current major and minor revision of the HWLibs. The
|
||||
* MS four decimal digits specify the Altera ACDS release number, the
|
||||
* LS two decimal digits specify minor revisions of the HWLibs, if any.
|
||||
*
|
||||
* A typical use is:
|
||||
* \code
|
||||
* #if ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0)
|
||||
* \endcode
|
||||
* for a dependency on the major or minor ACDS revision
|
||||
* or
|
||||
* \code
|
||||
* #if ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12)
|
||||
* \endcode
|
||||
* for a dependency on the hwlibs revision
|
||||
*
|
||||
*/
|
||||
#define ALT_HWLIBS_VERSION(a,b,c) (((a)*10000)+((b)*100)+(c))
|
||||
|
||||
#define ALTERA_HWLIBS_VERSION_CODE ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \
|
||||
ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV)
|
||||
|
||||
/*!
|
||||
* Allow some parts of the documentation to be hidden by setting to zero
|
||||
*/
|
||||
#define ALTERA_INTERNAL_ONLY_DOCS 1
|
||||
|
||||
|
||||
/*!
|
||||
* Provide base address of MPU address space
|
||||
*/
|
||||
|
||||
#ifndef ALT_HPS_ADDR
|
||||
#define ALT_HPS_ADDR 0
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* These constants are sometimes useful:
|
||||
*/
|
||||
#define ALT_MILLISECS_IN_A_SEC 1000
|
||||
#define ALT_MICROSECS_IN_A_SEC 1000000
|
||||
#define ALT_NANOSECS_IN_A_SEC 1000000000
|
||||
|
||||
#define ALT_TWO_TO_POW0 (1)
|
||||
#define ALT_TWO_TO_POW1 (1<<1)
|
||||
#define ALT_TWO_TO_POW2 (1<<2)
|
||||
#define ALT_TWO_TO_POW3 (1<<3)
|
||||
#define ALT_TWO_TO_POW4 (1<<4)
|
||||
#define ALT_TWO_TO_POW5 (1<<5)
|
||||
#define ALT_TWO_TO_POW6 (1<<6)
|
||||
#define ALT_TWO_TO_POW7 (1<<7)
|
||||
#define ALT_TWO_TO_POW8 (1<<8)
|
||||
#define ALT_TWO_TO_POW9 (1<<9)
|
||||
#define ALT_TWO_TO_POW10 (1<<10)
|
||||
#define ALT_TWO_TO_POW11 (1<<11)
|
||||
#define ALT_TWO_TO_POW12 (1<<12)
|
||||
#define ALT_TWO_TO_POW13 (1<<13)
|
||||
#define ALT_TWO_TO_POW14 (1<<14)
|
||||
#define ALT_TWO_TO_POW15 (1<<15)
|
||||
#define ALT_TWO_TO_POW16 (1<<16)
|
||||
#define ALT_TWO_TO_POW17 (1<<17)
|
||||
#define ALT_TWO_TO_POW18 (1<<18)
|
||||
#define ALT_TWO_TO_POW19 (1<<19)
|
||||
#define ALT_TWO_TO_POW20 (1<<20)
|
||||
#define ALT_TWO_TO_POW21 (1<<21)
|
||||
#define ALT_TWO_TO_POW22 (1<<22)
|
||||
#define ALT_TWO_TO_POW23 (1<<23)
|
||||
#define ALT_TWO_TO_POW24 (1<<24)
|
||||
#define ALT_TWO_TO_POW25 (1<<25)
|
||||
#define ALT_TWO_TO_POW26 (1<<26)
|
||||
#define ALT_TWO_TO_POW27 (1<<27)
|
||||
#define ALT_TWO_TO_POW28 (1<<28)
|
||||
#define ALT_TWO_TO_POW29 (1<<29)
|
||||
#define ALT_TWO_TO_POW30 (1<<30)
|
||||
#define ALT_TWO_TO_POW31 (1<<31)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __HWLIB_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,356 @@
|
||||
/*******************************************************************************
|
||||
* *
|
||||
* Copyright 2013 Altera Corporation. All Rights Reserved. *
|
||||
* *
|
||||
* Redistribution and use in source and binary forms, with or without *
|
||||
* modification, are permitted provided that the following conditions are met: *
|
||||
* *
|
||||
* 1. Redistributions of source code must retain the above copyright notice, *
|
||||
* this list of conditions and the following disclaimer. *
|
||||
* *
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice, *
|
||||
* this list of conditions and the following disclaimer in the documentation *
|
||||
* and/or other materials provided with the distribution. *
|
||||
* *
|
||||
* 3. The name of the author may not be used to endorse or promote products *
|
||||
* derived from this software without specific prior written permission. *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
|
||||
* *
|
||||
*******************************************************************************/
|
||||
|
||||
/*! \file Altera - ALT_SOCAL */
|
||||
|
||||
#ifndef __ALTERA_SOCAL_H__
|
||||
#define __ALTERA_SOCAL_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*!
|
||||
* \addtogroup ALT_SOCAL_UTIL SoCAL Utilities
|
||||
*
|
||||
* This file contains utility and support functions for the Altera SoCAL.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define ALT_CAST(type, ptr) ptr
|
||||
#else /* __ASSEMBLY__ */
|
||||
/*! Cast the pointer to specified pointer type.
|
||||
*
|
||||
* Note: This macro expands to \e ptr value only for assembler language
|
||||
* targets.
|
||||
*
|
||||
* \param type The pointer type to cast to
|
||||
* \param ptr The pointer to apply the type cast to
|
||||
*/
|
||||
#define ALT_CAST(type, ptr) ((type) (ptr))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
||||
/*!
|
||||
* \addtogroup ALT_SOCAL_UTIL_RW_FUNC SoCAL Memory Read/Write Utilities
|
||||
*
|
||||
* This section implements read and write functionality for various
|
||||
* memory untis. The memory unit terms used for these functions are
|
||||
* consistent with those used in the ARM Architecture Reference Manual
|
||||
* ARMv7-A and ARMv7-R edition manual. The terms used for units of memory are:
|
||||
*
|
||||
* Unit of Memory | Abbreviation | Size in Bits
|
||||
* :---------------|:-------------|:------------:
|
||||
* Byte | byte | 8
|
||||
* Half Word | hword | 16
|
||||
* Word | word | 32
|
||||
* Double Word | dword | 64
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! Write the 8 bit byte to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param src - 8 bit data byte to write to memory
|
||||
*/
|
||||
#define alt_write_byte(dest, src) (*ALT_CAST(volatile uint8_t *, (dest)) = (src))
|
||||
|
||||
/*! Read and return the 8 bit byte from the source address in device memory.
|
||||
* \param src Read source pointer address
|
||||
* \returns 8 bit data byte value
|
||||
*/
|
||||
#define alt_read_byte(src) (*ALT_CAST(volatile uint8_t *, (src)))
|
||||
|
||||
/*! Write the 16 bit half word to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param src - 16 bit data half word to write to memory
|
||||
*/
|
||||
#define alt_write_hword(dest, src) (*ALT_CAST(volatile uint16_t *, (dest)) = (src))
|
||||
|
||||
/*! Read and return the 16 bit half word from the source address in device memory.
|
||||
* \param src Read source pointer address
|
||||
* \returns 16 bit data half word value
|
||||
*/
|
||||
#define alt_read_hword(src) (*ALT_CAST(volatile uint16_t *, (src)))
|
||||
|
||||
/*! Write the 32 bit word to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param src - 32 bit data word to write to memory
|
||||
*/
|
||||
#define alt_write_word(dest, src) (*ALT_CAST(volatile uint32_t *, (dest)) = (src))
|
||||
|
||||
/*! Read and return the 32 bit word from the source address in device memory.
|
||||
* \param src Read source pointer address
|
||||
* \returns 32 bit data word value
|
||||
*/
|
||||
#define alt_read_word(src) (*ALT_CAST(volatile uint32_t *, (src)))
|
||||
|
||||
/*! Write the 64 bit double word to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param src - 64 bit data double word to write to memory
|
||||
*/
|
||||
#define alt_write_dword(dest, src) (*ALT_CAST(volatile uint64_t *, (dest)) = (src))
|
||||
|
||||
/*! Read and return the 64 bit double word from the source address in device memory.
|
||||
* \param src Read source pointer address
|
||||
* \returns 64 bit data double word value
|
||||
*/
|
||||
#define alt_read_dword(src) (*ALT_CAST(volatile uint64_t *, (src)))
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* \addtogroup ALT_SOCAL_UTIL_SC_FUNC SoCAL Memory Bit Set/Clr/XOR/Replace Utilities
|
||||
*
|
||||
* This section implements useful macros to set, clear, change, and replace
|
||||
* selected bits within a word in memory or a memory-mapped register.
|
||||
* @{
|
||||
*
|
||||
*/
|
||||
|
||||
/*! Set selected bits in the 8 bit byte at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to set in destination byte
|
||||
*/
|
||||
#define alt_setbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) | (bits)))
|
||||
|
||||
/*! Clear selected bits in the 8 bit byte at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to clear in destination byte
|
||||
*/
|
||||
#define alt_clrbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) & ~(bits)))
|
||||
|
||||
/*! Change or toggle selected bits in the 8 bit byte at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to change in destination byte
|
||||
*/
|
||||
#define alt_xorbits_byte(dest, bits) (alt_write_byte(dest, alt_read_byte(dest) ^ (bits)))
|
||||
|
||||
/*! Replace selected bits in the 8 bit byte at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param msk - Bits to replace in destination byte
|
||||
* \param src - Source bits to write to cleared bits in destination byte
|
||||
*/
|
||||
#define alt_replbits_byte(dest, msk, src) (alt_write_byte(dest,(alt_read_byte(dest) & ~(msk)) | ((src) & (msk))))
|
||||
|
||||
/*! Set selected bits in the 16 bit halfword at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to set in destination halfword
|
||||
*/
|
||||
#define alt_setbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) | (bits)))
|
||||
|
||||
/*! Clear selected bits in the 16 bit halfword at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to clear in destination halfword
|
||||
*/
|
||||
#define alt_clrbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) & ~(bits)))
|
||||
|
||||
/*! Change or toggle selected bits in the 16 bit halfword at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to change in destination halfword
|
||||
*/
|
||||
#define alt_xorbits_hword(dest, bits) (alt_write_hword(dest, alt_read_hword(dest) ^ (bits)))
|
||||
|
||||
/*! Replace selected bits in the 16 bit halfword at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param msk - Bits to replace in destination halfword
|
||||
* \param src - Source bits to write to cleared bits in destination halfword
|
||||
*/
|
||||
#define alt_replbits_hword(dest, msk, src) (alt_write_hword(dest,(alt_read_hword(dest) & ~(msk)) | ((src) & (msk))))
|
||||
|
||||
/*! Set selected bits in the 32 bit word at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to set in destination word
|
||||
*/
|
||||
#define alt_setbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) | (bits)))
|
||||
|
||||
/*! Clear selected bits in the 32 bit word at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to clear in destination word
|
||||
*/
|
||||
#define alt_clrbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) & ~(bits)))
|
||||
|
||||
/*! Change or toggle selected bits in the 32 bit word at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to change in destination word
|
||||
*/
|
||||
#define alt_xorbits_word(dest, bits) (alt_write_word(dest, alt_read_word(dest) ^ (bits)))
|
||||
|
||||
/*! Replace selected bits in the 32 bit word at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param msk - Bits to replace in destination word
|
||||
* \param src - Source bits to write to cleared bits in destination word
|
||||
*/
|
||||
#define alt_replbits_word(dest, msk, src) (alt_write_word(dest,(alt_read_word(dest) & ~(msk)) | ((src) & (msk))))
|
||||
|
||||
/*! Set selected bits in the 64 bit doubleword at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to set in destination doubleword
|
||||
*/
|
||||
#define alt_setbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) | (bits)))
|
||||
|
||||
/*! Clear selected bits in the 64 bit doubleword at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to clear in destination doubleword
|
||||
*/
|
||||
#define alt_clrbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) & ~(bits)))
|
||||
|
||||
/*! Change or toggle selected bits in the 64 bit doubleword at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param bits - Bits to change in destination doubleword
|
||||
*/
|
||||
#define alt_xorbits_dword(dest, bits) (alt_write_dword(dest, alt_read_dword(dest) ^ (bits)))
|
||||
|
||||
/*! Replace selected bits in the 64 bit doubleword at the destination address in device memory.
|
||||
* \param dest - Destination pointer address
|
||||
* \param msk - Bits to replace in destination doubleword
|
||||
* \param src - Source bits to write to cleared bits in destination word
|
||||
*/
|
||||
#define alt_replbits_dword(dest, msk, src) (alt_write_dword(dest,(alt_read_dword(dest) & ~(msk)) | ((src) & (msk))))
|
||||
|
||||
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* \addtogroup ALT_SOCAL_TYPE_IND_FUNC SoCAL Indirect (pointer-based) Utilities
|
||||
*
|
||||
* This section implements two other useful forms of the alt_write_*() macros above that
|
||||
* are preferable to use in some situations. These use an intermediate pointer (defined
|
||||
* in the containing compile unit) to move data in an indirect manner. These compile to very
|
||||
* tight ARM code, equivalent to the above versions.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! Write the 8 bit byte to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param tmptr - Temporary pointer to byte data
|
||||
* \param src - 8 bit data value to write to memory
|
||||
*/
|
||||
#define alt_indwrite_byte(dest, tmptr, src) {(tmptr)=ALT_CAST(uint8_t*,(dest));(*ALT_CAST(volatile uint8_t*,(tmptr))=(src));}
|
||||
|
||||
/*! Write the 8 bit byte to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param tmptr - Temporary pointer to byte data
|
||||
* \param src - Read destination pointer address
|
||||
*/
|
||||
#define alt_indread_byte(dest, tmptr, src) {(tmptr)=ALT_CAST(uint8_t*,(src));(*ALT_CAST(volatile uint8_t*,(dest))=*(tmptr));}
|
||||
|
||||
/*! Write the 16 bit halfword to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param tmptr - Temporary pointer to halfword data
|
||||
* \param src - 16 bit data value to write to memory
|
||||
*/
|
||||
#define alt_indwrite_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(dest));(*ALT_CAST(volatile uint16_t*,(tmptr))=(src));}
|
||||
|
||||
/*! Write the 16 bit halfword to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param tmptr - Temporary pointer to halfword data
|
||||
* \param src - Read destination pointer address
|
||||
*/
|
||||
#define alt_indread_hword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint16_t*,(src));(*ALT_CAST(volatile uint16_t*,(dest))=*(tmptr));}
|
||||
|
||||
/*! Write the 32 bit word to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param tmptr - Temporary pointer to word data
|
||||
* \param src - 32 bit data value to write to memory
|
||||
*/
|
||||
#define alt_indwrite_word(dest, tmptr, src) {(tmptr)=ALT_CAST(uint32_t*,(dest));(*ALT_CAST(volatile uint32_t*,(tmptr))=(src));}
|
||||
|
||||
/*! Write the 32 bit word to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param tmptr - Temporary pointer to word data
|
||||
* \param src - Read destination pointer address
|
||||
*/
|
||||
#define alt_indread_word(dest, tmptr, src) {(tmptr)=ALT_CAST(uint32_t*,(src));(*ALT_CAST(volatile uint32_t*,(dest))=*(tmptr));}
|
||||
|
||||
/*! Write the 64 bit dword to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param tmptr - Temporary pointer to double-word data
|
||||
* \param src - 64 bit data value to write to memory
|
||||
*/
|
||||
#define alt_indwrite_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(dest));(*ALT_CAST(volatile uint64_t*,(tmptr))=(src));}
|
||||
|
||||
/*! Write the 64 bit dword to the destination address in device memory.
|
||||
* \param dest - Write destination pointer address
|
||||
* \param tmptr - Temporary pointer to double-word data
|
||||
* \param src - Read destination pointer address
|
||||
*/
|
||||
#define alt_indread_dword(dest, tmptr, src) {(tmptr)=ALT_CAST(uint64_t*,(src));(*ALT_CAST(volatile uint64_t*,(dest))=*(tmptr));}
|
||||
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* \addtogroup ALT_SOCAL_CMPL_ASRT_FUNC SoCAL Compile Assert Utilities
|
||||
*
|
||||
* This section implements an assert-type functionality in the compiler rather than in the
|
||||
* debug run-time code. Additional macros can be built on the basic structure and defined
|
||||
* to test various conditions and throw a compile-time error if necessary.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! alt_cat_compile_assert_text() concatenates text.
|
||||
* \param txta - The first text fragment to be joined
|
||||
* \param txtb - The second text fragment to be joined
|
||||
*/
|
||||
#define alt_cat_compile_assert_text(txta, txtb) txta##txtb
|
||||
|
||||
/*! alt_form_compile_assert_line() is the basis of other functions that check various
|
||||
* conditions and possibly throw a compile-time error in response, giving an
|
||||
* assert equivalent that operates at compile time rather than at run-time.
|
||||
* \param test - Any valid boolean expression
|
||||
* \param file - The filename where this expression is located (ASCII string)
|
||||
* \param line - The line number where this expression is located
|
||||
*/
|
||||
#define alt_form_compile_assert_line(test, file, line) \
|
||||
typedef char alt_cat_compile_assert_text(assertion_at_##file##_line_, line)[2*!!(test)-1]
|
||||
|
||||
/*! alt_check_struct_size() throws a compile-time error if the structure size (a) is
|
||||
* larger than the size of the reference (b). \n
|
||||
* alt_check_struct_size() works with groups of bitfields up to much larger
|
||||
* structure sizes.
|
||||
* \param a - Structure to be evaluated
|
||||
* \param b - Reference size
|
||||
*/
|
||||
#define alt_check_struct_size(a, b) alt_form_compile_assert_line((sizeof(a) <= sizeof(b)),__FILE__,__LINE__)
|
||||
|
||||
|
||||
/*! @} */
|
||||
/*! @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* __ALTERA_SOCAL_H__ */
|
||||
@@ -0,0 +1,184 @@
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* alt_address_space.c - API for the Altera SoC FPGA address space.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright 2013 Altera Corporation. All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include <stddef.h>
|
||||
#include "alt_address_space.h"
|
||||
#include "socal/alt_l3.h"
|
||||
#include "socal/socal.h"
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
|
||||
ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
|
||||
ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_bridge_attr,
|
||||
ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_bridge_attr)
|
||||
{
|
||||
uint32_t remap_reg_val = 0;
|
||||
|
||||
// Parameter checking and validation...
|
||||
if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM)
|
||||
{
|
||||
remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_BOOTROM);
|
||||
}
|
||||
else if (mpu_attr == ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM)
|
||||
{
|
||||
remap_reg_val |= ALT_L3_REMAP_MPUZERO_SET(ALT_L3_REMAP_MPUZERO_E_OCRAM);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ALT_E_INV_OPTION;
|
||||
}
|
||||
|
||||
if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM)
|
||||
{
|
||||
remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_SDRAM);
|
||||
}
|
||||
else if (nonmpu_attr == ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM)
|
||||
{
|
||||
remap_reg_val |= ALT_L3_REMAP_NONMPUZERO_SET(ALT_L3_REMAP_NONMPUZERO_E_OCRAM);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ALT_E_INV_OPTION;
|
||||
}
|
||||
|
||||
if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_INACCESSIBLE)
|
||||
{
|
||||
remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_INVISIBLE);
|
||||
}
|
||||
else if (h2f_bridge_attr == ALT_ADDR_SPACE_H2F_ACCESSIBLE)
|
||||
{
|
||||
remap_reg_val |= ALT_L3_REMAP_H2F_SET(ALT_L3_REMAP_H2F_E_VISIBLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ALT_E_INV_OPTION;
|
||||
}
|
||||
|
||||
if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_INACCESSIBLE)
|
||||
{
|
||||
remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_INVISIBLE);
|
||||
}
|
||||
else if (lwh2f_bridge_attr == ALT_ADDR_SPACE_LWH2F_ACCESSIBLE)
|
||||
{
|
||||
remap_reg_val |= ALT_L3_REMAP_LWH2F_SET(ALT_L3_REMAP_LWH2F_E_VISIBLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ALT_E_INV_OPTION;
|
||||
}
|
||||
|
||||
// Perform the remap.
|
||||
alt_write_word(ALT_L3_REMAP_ADDR, remap_reg_val);
|
||||
|
||||
return ALT_E_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
// Remap the MPU address space view of address 0 to access the SDRAM controller.
|
||||
// This is done by setting the L2 cache address filtering register start address
|
||||
// to 0 and leaving the address filtering address end address value
|
||||
// unmodified. This causes all physical addresses in the range
|
||||
// address_filter_start <= physical_address < address_filter_end to be directed
|
||||
// to the to the AXI Master Port M1 which is connected to the SDRAM
|
||||
// controller. All other addresses are directed to AXI Master Port M0 which
|
||||
// connect the MPU subsystem to the L3 interconnect.
|
||||
//
|
||||
// It is unnecessary to modify the MPU remap options in the L3 remap register
|
||||
// because those options only affect addresses in the MPU subsystem address
|
||||
// ranges that are now redirected to the SDRAM controller and never reach the L3
|
||||
// interconnect anyway.
|
||||
ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void)
|
||||
{
|
||||
uint32_t addr_filt_end = (alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR) &
|
||||
L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
|
||||
return alt_l2_addr_filter_cfg_set(0x0, addr_filt_end);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
// Return the L2 cache address filtering registers configuration settings in the
|
||||
// user provided start and end address range out parameters.
|
||||
ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
|
||||
uint32_t* addr_filt_end)
|
||||
{
|
||||
if (addr_filt_start == NULL || addr_filt_end == NULL)
|
||||
{
|
||||
return ALT_E_BAD_ARG;
|
||||
}
|
||||
|
||||
uint32_t addr_filt_start_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_START_ADDR);
|
||||
uint32_t addr_filt_end_reg = alt_read_word(L2_CACHE_ADDR_FILTERING_END_ADDR);
|
||||
|
||||
*addr_filt_start = (addr_filt_start_reg & L2_CACHE_ADDR_FILTERING_START_ADDR_MASK);
|
||||
*addr_filt_end = (addr_filt_end_reg & L2_CACHE_ADDR_FILTERING_END_ADDR_MASK);
|
||||
return ALT_E_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
|
||||
uint32_t addr_filt_end)
|
||||
{
|
||||
// Address filtering start and end values must be 1 MB aligned.
|
||||
if ( (addr_filt_start & ~L2_CACHE_ADDR_FILTERING_START_ADDR_MASK)
|
||||
|| (addr_filt_end & ~L2_CACHE_ADDR_FILTERING_END_ADDR_MASK) )
|
||||
{
|
||||
return ALT_E_ARG_RANGE;
|
||||
}
|
||||
|
||||
// While it is possible to set the address filtering end value above its
|
||||
// reset value and thereby access a larger SDRAM address range, it is not
|
||||
// recommended. Doing so would potentially obscure any mapped HPS to FPGA
|
||||
// bridge address spaces and peripherals on the L3 interconnect.
|
||||
if (addr_filt_end > L2_CACHE_ADDR_FILTERING_END_RESET)
|
||||
{
|
||||
return ALT_E_ARG_RANGE;
|
||||
}
|
||||
|
||||
// NOTE: ARM (ARM DDI 0246F CoreLink Level 2 Cache Controller L2C-310 TRM)
|
||||
// recommends programming the Address Filtering End Register before the
|
||||
// Address Filtering Start Register to avoid unpredictable behavior between
|
||||
// the two writes.
|
||||
alt_write_word(L2_CACHE_ADDR_FILTERING_END_ADDR, addr_filt_end);
|
||||
// It is recommended that address filtering always remain enabled.
|
||||
addr_filt_start |= L2_CACHE_ADDR_FILTERING_ENABLE_MASK;
|
||||
alt_write_word(L2_CACHE_ADDR_FILTERING_START_ADDR, addr_filt_start);
|
||||
|
||||
return ALT_E_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/******************************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,135 @@
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* alt_reset_manager.c - API for the Altera SoC FPGA reset manager.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright 2013 Altera Corporation. All Rights Reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
|
||||
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "alt_reset_manager.h"
|
||||
#include "socal/socal.h"
|
||||
#include "socal/hps.h"
|
||||
#include "socal/alt_rstmgr.h"
|
||||
|
||||
/////
|
||||
|
||||
|
||||
uint32_t alt_reset_event_get(void)
|
||||
{
|
||||
return alt_read_word(ALT_RSTMGR_STAT_ADDR);
|
||||
}
|
||||
|
||||
ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask)
|
||||
{
|
||||
alt_write_word(ALT_RSTMGR_STAT_ADDR, event_mask);
|
||||
return ALT_E_SUCCESS;
|
||||
}
|
||||
|
||||
ALT_STATUS_CODE alt_reset_cold_reset(void)
|
||||
{
|
||||
alt_write_word(ALT_RSTMGR_CTL_ADDR, ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK);
|
||||
return ALT_E_SUCCESS;
|
||||
}
|
||||
|
||||
ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
|
||||
uint32_t nRST_pin_clk_assertion,
|
||||
bool sdram_refresh_enable,
|
||||
bool fpga_mgr_handshake,
|
||||
bool scan_mgr_handshake,
|
||||
bool fpga_handshake,
|
||||
bool etr_stall)
|
||||
{
|
||||
// Cached register values
|
||||
uint32_t ctrl_reg = ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK;
|
||||
uint32_t counts_reg = 0;
|
||||
|
||||
/////
|
||||
|
||||
// Validate warm_reset_delay is above 16 and below the field width
|
||||
if ((warm_reset_delay < 16) || (warm_reset_delay >= (1 << ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH)))
|
||||
{
|
||||
return ALT_E_BAD_ARG;
|
||||
}
|
||||
|
||||
// Validate nRST_pin_clk_assertion delay is non-zero and below the field width
|
||||
if (!nRST_pin_clk_assertion)
|
||||
{
|
||||
return ALT_E_ERROR;
|
||||
}
|
||||
if (nRST_pin_clk_assertion >= (1 << ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH))
|
||||
{
|
||||
return ALT_E_BAD_ARG;
|
||||
}
|
||||
|
||||
// Update counts register with warm_reset_delay information
|
||||
counts_reg |= ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(warm_reset_delay);
|
||||
|
||||
// Update counts register with nRST_pin_clk_assertion information
|
||||
counts_reg |= ALT_RSTMGR_COUNTS_NRSTCNT_SET(nRST_pin_clk_assertion);
|
||||
|
||||
/////
|
||||
|
||||
// Update ctrl register with the specified option flags
|
||||
|
||||
if (sdram_refresh_enable)
|
||||
{
|
||||
ctrl_reg |= ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK;
|
||||
}
|
||||
|
||||
if (fpga_mgr_handshake)
|
||||
{
|
||||
ctrl_reg |= ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK;
|
||||
}
|
||||
|
||||
if (scan_mgr_handshake)
|
||||
{
|
||||
ctrl_reg |= ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK;
|
||||
}
|
||||
|
||||
if (fpga_handshake)
|
||||
{
|
||||
ctrl_reg |= ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK;
|
||||
}
|
||||
|
||||
if (etr_stall)
|
||||
{
|
||||
ctrl_reg |= ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK;
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
// Commit registers to hardware
|
||||
alt_write_word(ALT_RSTMGR_COUNTS_ADDR, counts_reg);
|
||||
alt_write_word(ALT_RSTMGR_CTL_ADDR, ctrl_reg);
|
||||
|
||||
return ALT_E_SUCCESS;
|
||||
}
|
||||
Reference in New Issue
Block a user