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or1ksim: Fix bug at UART driver.

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Fix some UART register addresses and implementation bugs that
were causing malfunction of console driver on real hardware.

hello and ticker samples are tested and working fine now on mor1kx
based SoC on Atlys FPGA board.
BSP_OR1K_OR1KSIM_PERIPHCLK has been changed to 50MHz as with mor1kx/atlys
SoC; this change has no effect on the current simulators that RTEMS run
on.
This commit is contained in:
Hesham ALMatary
2015-04-14 11:10:14 -05:00
committed by Joel Sherrill
parent 1dc6662276
commit 0a73de2fc8
3 changed files with 16 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files
c/src/lib/libbsp/or1k/or1ksim/configure.ac
+1 -1
View File
@@ -16,7 +16,7 @@ RTEMS_BSP_CONFIGURE
RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
RTEMS_BSPOPTS_SET([BSP_OR1K_OR1KSIM_PERIPHCLK],[*],[100000000U])
RTEMS_BSPOPTS_SET([BSP_OR1K_OR1KSIM_PERIPHCLK],[*],[50000000U])
RTEMS_BSPOPTS_HELP([BSP_OR1K_OR1KSIM_PERIPHCLK],[or1ksim PERIPHCLK clock frequency in Hz])
RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
c/src/lib/libbsp/or1k/or1ksim/console/uart.c
+11 -24
View File
@@ -46,39 +46,34 @@ static uint32_t uart_get_baud(const console_tbl *ct)
static void uart_set_baud(int baud)
{
int divisor = (OR1KSIM_BSP_CLOCK_FREQ) / (16 * baud);
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) |=
uint16_t divisor = (OR1KSIM_BSP_CLOCK_FREQ) / (16 * baud);
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) =
OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB;
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW) = divisor & 0xff;
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH) =
(divisor >> 8) & 0xff;
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) &=
~(OR1KSIM_BSP_UART_REG_LINE_CTRL_DLAB);
(divisor >> 8);
}
static void uart_initialize(int minor)
{
/* Disable all interrupts */
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_INT_ENABLE) = 0x00;
/* Set baud rate */
uart_set_baud(OR1KSIM_UART_DEFAULT_BAUD);
/* Set data pattern configuration */
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) =
OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8;
/* Reset receiver and transmitter */
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_FIFO_CTRL) =
OR1KSIM_BSP_UART_REG_FIFO_CTRL_ENABLE_FIFO |
OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_RCVR |
OR1KSIM_BSP_UART_REG_FIFO_CTRL_CLEAR_XMIT |
OR1KSIM_BSP_UART_REG_FIFO_CTRL_TRIGGER_14;
/* Set data pattern configuration */
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_CTRL) =
OR1KSIM_BSP_UART_REG_LINE_CTRL_WLEN8 &
(OR1KSIM_BSP_UART_REG_LINE_CTRL_STOP |
OR1KSIM_BSP_UART_REG_LINE_CTRL_PARITY);
/* Disable all interrupts */
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_INT_ENABLE) = 0x00;
/* Set baud rate */
uart_set_baud(OR1KSIM_UART_DEFAULT_BAUD);
}
static int uart_first_open(int major, int minor, void *arg)
@@ -115,9 +110,6 @@ static int uart_read_polled(int minor)
static void uart_write_polled(int minor, char c)
{
unsigned char lsr;
const uint32_t transmit_finished =
(OR1KSIM_BSP_UART_REG_LINE_STATUS_TEMT |
OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE);
/* Wait until there is no pending data in the transmitter FIFO (empty) */
do {
@@ -125,11 +117,6 @@ static void uart_write_polled(int minor, char c)
} while (!(lsr & OR1KSIM_BSP_UART_REG_LINE_STATUS_THRE));
OR1KSIM_REG(OR1KSIM_BSP_UART_REG_TX) = c;
/* Wait until trasmit data is finished */
do {
lsr = OR1KSIM_REG(OR1KSIM_BSP_UART_REG_LINE_STATUS);
} while ( (lsr & transmit_finished) != transmit_finished );
}
static ssize_t uart_write(
c/src/lib/libbsp/or1k/or1ksim/include/or1ksim.h
+4 -4
View File
@@ -35,7 +35,7 @@
* @{
*/
#define OR1KSIM_REG(x) (*((volatile char *) (x)))
#define OR1KSIM_REG(x) (*((volatile unsigned char *) (x)))
#define OR1KSIM_BIT(n) (1 << (n))
/** @} */
@@ -45,14 +45,14 @@
*
* @{
*/
#define OR1KSIM_BSP_CLOCK_FREQ 100000000UL
#define OR1KSIM_BSP_CLOCK_FREQ 50000000UL
#define OR1KSIM_BSP_UART_BASE 0x90000000
#define OR1KSIM_BSP_UART_REG_TX (OR1KSIM_BSP_UART_BASE+0)
#define OR1KSIM_BSP_UART_REG_RX (OR1KSIM_BSP_UART_BASE+0)
#define OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW (OR1KSIM_BSP_UART_BASE+1)
#define OR1KSIM_BSP_UART_REG_DEV_LATCH_LOW (OR1KSIM_BSP_UART_BASE+0)
#define OR1KSIM_BSP_UART_REG_DEV_LATCH_HIGH (OR1KSIM_BSP_UART_BASE+1)
#define OR1KSIM_BSP_UART_REG_INT_ENABLE (OR1KSIM_BSP_UART_BASE+2)
#define OR1KSIM_BSP_UART_REG_INT_ENABLE (OR1KSIM_BSP_UART_BASE+1)
#define OR1KSIM_BSP_UART_REG_INT_ID (OR1KSIM_BSP_UART_BASE+2)
#define OR1KSIM_BSP_UART_REG_FIFO_CTRL (OR1KSIM_BSP_UART_BASE+2)
#define OR1KSIM_BSP_UART_REG_LINE_CTRL (OR1KSIM_BSP_UART_BASE+3)