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cpukit/aarch64: Use correct stack for nested interrupts

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When AArch64 exception support was first written, nested exceptions were
configured using the wrong stack. This happened to work since any
changes were unwound from the stack before dispatch occurred. This
implements correct behavior for all SP0 interrupt vectors.

Closes #5140
This commit is contained in:
Kinsey Moore
2025-08-06 10:41:10 -05:00
committed by Joel Sherrill
parent f664b84280
commit 046ea144a9
1 changed files with 4 additions and 0 deletions
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cpukit/score/cpu/aarch64/aarch64-exception-default.S
+4
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@@ -118,6 +118,7 @@ Vector_table_el3:
* using SP0.
*/
curr_el_sp0_sync:
msr spsel, #0
sub sp, sp, #AARCH64_EXCEPTION_FRAME_SIZE /* reserve space for CEF */
str lr, [sp, #AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET] /* shove lr into CEF */
bl .push_exception_context_start /* bl to CEF store routine */
@@ -142,12 +143,14 @@ curr_el_sp0_sync_get_pc: /* The current PC is now in LR */
.balign 0x80
/* The exception handler for IRQ exceptions from the current EL using SP0. */
curr_el_sp0_irq:
msr spsel, #0
stp x0, lr, [sp, #-0x10]! /* Push x0,lr on to the stack */
ldr JUMP_REG(0), =aarch64_exception_sp0_irq
JUMP_HANDLER
.balign 0x80
/* The exception handler for FIQ exceptions from the current EL using SP0. */
curr_el_sp0_fiq:
msr spsel, #0
stp x0, lr, [sp, #-0x10]! /* Push x0,lr on to the stack */
ldr JUMP_REG(0), =aarch64_exception_sp0_fiq
JUMP_HANDLER
@@ -157,6 +160,7 @@ curr_el_sp0_fiq:
* SP0.
*/
curr_el_sp0_serror:
msr spsel, #0
stp x0, lr, [sp, #-0x10]! /* Push x0,lr on to the stack */
ldr JUMP_REG(0), =aarch64_exception_sp0_serror
JUMP_HANDLER