1013 Commits

Author	SHA1	Message	Date
ZhangJing	c3d33f39d4	[bsp]增加超睿DP1000 bsp支持	2025-05-30 13:32:58 +08:00
Yaochenger	f4e619a17c	移除无用文件，该文件未被任何BSP使用	2025-05-30 09:32:08 +08:00
Yaochenger	5889db6819	[libcpu/common] 修正对RV32E的支持，RV32E不支持s2寄存器，修改为s1寄存器	2025-05-30 09:32:08 +08:00
zhangjing	e3d7bbb47c	[libcpu][risc-v]:add comment for the round down of symb_pc	2025-05-28 19:37:51 +08:00
zhangjing	3922ec7e99	[libcpu][risc-v] fix:only map the 1GB space where the original code segment is located	2025-05-28 19:37:51 +08:00
rcitach	aee8920d07	import re	2025-04-28 10:52:58 +08:00
rcitach	5833e02e2f	Fix Aarch64 architecture runtime issues ... 该问题由5b3320624da5149fc21c2d3e1f321d855e3d0dfe引入，导致工具链编译时加上了 -std=gnu99,其他架构是否出问题暂时未知	2025-04-28 10:52:58 +08:00
mouch6131	86df886c7f	libcpu: aarch64: Fix NORMAL_NOCACHE_MEM attr (#10180) ... Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com> Signed-off-by: mouch6131 <187177037@qq.com> Co-authored-by: Cliff Chen <cliff.chen@rock-chips.com>	2025-04-13 22:12:00 +08:00
Chen Wang	312f9dbc08	libcpu: riscv: declare external symbols inside ... libcpu/risc-v/common64/mmu.c uses the external symbol "__bss_end" (this symbol generally is defined in the link script file) and depends on the extern declaration of this symbol in the bsp's "board.h". This is not a problem in implementation, but it is not a good habit. If this extern symbol is used locally, just declare it locally should be better. In this way, there will be no dependency of the kernel core on the bsp header file. And there will be no special requirements for the bsp board code, such as the need to make extern declarations for these "__bss_end" symbols in "board.h". This patch currently only explicitly externly declares "__bss_end" inside libcpu itself. The code of "#include <board.h>" is kept, because the modification involved is too large, it is necessary to clean up the bsp involved before cleaning this include code line uniformly. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-04-11 14:15:12 +08:00
Chen Wang	5c9f61879c	libcpu: cleanup undefined rt_hw_mmu_kernel_map_init (#10177) ... * libcpu: cleanup undefined rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init() is declared in header files but no definition found, cleanup the code. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init is an undefined function, calling it is meaningless. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-04-11 07:54:21 +08:00
zms123456	883bdfa9ef	[libcpu][aarch64]fix gicv3 mpidr table (#9284) ... * fix gicv3 mpidr error * phytium should support rt_cpu_mpidr_table by using common_setup	2025-03-28 11:08:28 +08:00
CYFS	b0e7cba9fd	[bsp][stm32][artpi]:fix artpi nano (#10122)	2025-03-18 22:55:13 +08:00
Rbb666	cb098c4eea	[fix]Fix cm33 compilation problem when block is turned on	2025-03-17 19:13:34 +08:00
ligr	9da813b151	[libcpu][risc-v]add code for handling exception scenarios in _unmap_area.	2025-03-17 17:40:55 +08:00
ligr	b04aacbd94	[libcpu][risc-v]remove unused parameter 'size' for func _unmap_area. ... Signed-off-by: ligr <liguorui1213@163.com>	2025-03-17 17:40:55 +08:00
latercomer	40360efe1d	解决rt_interrupt_from_thread和rt_interrupt_to_thread指针赋值错误 ... Signed-off-by: latercomer <latercomer@qq.com>	2025-03-17 16:45:59 +08:00
latercomer	b8e9f7e0f5	修复rt_hw_context_switch_to和rt_hw_context_switch的形参 ... Signed-off-by: latercomer <latercomer@qq.com>	2025-03-17 16:45:59 +08:00
latercomer	130b5ba653	解决rt_hw_context_switch_interrupt形参定义不一致 ... Signed-off-by: latercomer <latercomer@qq.com>	2025-03-17 16:45:59 +08:00
latercomer	9e13f67018	删除libcpu/sim/simulator中msvc编译器多余代码，为后续支持mingw64做准备 ... Signed-off-by: latercomer <latercomer@qq.com>	2025-03-17 16:45:59 +08:00
Guorui Li	5a09694f05	[libcpu][risc-v]add comments for rt_hw_mem_setup_early. (#10102)	2025-03-12 09:40:46 +08:00
Kai	f7d542155f	[libcpu][riscv] add a doc for wch saving the irq stack as stack-512 (#10063)	2025-03-03 23:13:11 +08:00
Guorui Li	7f05592592	[libcpu][risc-v]add comments for rv64 sv39 mmu APIs. (#10053)	2025-03-02 00:03:13 +08:00
Guorui Li	8adae0725d	[bugfix][risc-v]fix the PPN length error in GET_PPN(pte). (#10020)	2025-02-28 08:23:46 +08:00
Shell	9386411d13	feat: mm: added affinity pages allocator ... This patch introduces a tagged pages allocator to address the existing problems of page aliasing on specific platforms and the requirement of page coloring. It implements an affinity-id aware page manager by separating the runtime page list into two types: a normal single linked-list and a multi-dimensional affinity-list. Changes: - Introduced tagged pages allocator and managing algorithm for affinity pages list - Modified components to support affinity-id list management - Updated page allocation and freeing functions to handle tagged pages - Added configuration options for page affinity block size and debugging - Modified mmap and elf loading to respect affinity settings - Enhanced page list management to support multi-dimensional affinity-list Signed-off-by: Shell <smokewood@qq.com>	2025-02-25 11:26:30 +08:00
kenneth.liu	2be83d5cad	libcpu: riscv: fixed ARCH_RISCV_VECTOR issue ... description: Using the vector instruction set to trigger an illegal instruction exception when ARCH_SISCV_VECTOR=y. analysis: When initializing the thread stack, the rt_cw_stack_init function did not enable VS for SSTATUS. Solution: When ARCH_SISCV_VECTOR=y, increment the initial value of sstatus by 0x600(SSTATUS_VS). Signed-off-by: Liu Gui <kenneth.liu@sophgo.com>	2025-02-22 14:17:54 -05:00
GuEe-GUI	d41a0351db	[AARCH64] Update kernel's boot link for ARM64 ... Signed-off-by: GuEe-GUI <2991707448@qq.com>	2025-02-11 14:58:18 +08:00
Chen Wang	c66374705a	libcpu: riscv: rv64: fixed warnings ... When building bsp/cvitek/c906_little, compiler reports: ``` .../rt-thread/libcpu/risc-v/rv64/trap.c: In function 'handle_trap': .../rt-thread/libcpu/risc-v/rv64/trap.c:106:13: warning: implicit declaration of function 'rt_hw_tick_isr'; did you mean 'rt_hw_stack_init'? [-Wimplicit-function-declaration] 106 | rt_hw_tick_isr(); | ^~~~~~~~~~~~~~ | rt_hw_stack_init .../rt-thread/libcpu/risc-v/rv64/trap.c:110:13: warning: implicit declaration of function 'rt_hw_irq_isr'; did you mean 'rt_hw_soft_irq_isr'? [-Wimplicit-function-declaration] 110 | rt_hw_irq_isr(); | ^~~~~~~~~~~~~ | rt_hw_soft_irq_isr ``` rt_hw_tick_isr()/rt_hw_irq_isr() are implemented by bsp, but libcpu/risc-v/rv64 doesn't declare them, so compiler warns. There are three BSPs using 'rv64' (libcpu/risc-v/rv64): - `bsp/cvitek/c906_little/rtconfig.py` - `bsp/juicevm/rtconfig.py` - `bsp/k210/rtconfig.py` `handle_trap` in `libcpu/risc-v/rv64` is defined as weak. BSP can use this function directly or define and overload it by itself. If bsp use this function directly, bsp need to pay attention to the fact that three functions will be called in this function: - `rt_hw_soft_irq_isr` - `rt_hw_tick_isr` - `rt_hw_irq_isr` In `libcpu/risc-v/rv64`, `rt_hw_soft_irq_isr` has a weak definition, while the other two do not. This means that if the bsp does not overload `handle_trap`, bsp must define `rt_hw_tick_isr` and `rt_hw_irq_isr` itself. This is also the practice of `bsp/cvitek/c906_little`. There is also a similar bsp `bsp/k210`, and the form of `bsp/juicevm` implements `handle_trap` by itself. It seems that `rt_hw_tick_isr` and `rt_hw_irq_isr` are not required to be implemented by all BSPs using `libcpu/risc-v/rv64`. The premise for BSP to implement them is that it does not overload `handle_trap`. So declaring `rt_hw_tick_isr` and `rt_hw_irq_isr` with extern in `libcpu/risc-v/rv64` is not proper. In addition, the `rt_hw_tick_isr/rt_hw_irq_isr` are only used by `libcpu/risc-v/rv64`, so it is not worth putting the declaration in `./include/rthw.h`. Sum up, the best solution is to add weak definition to `rt_hw_tick_isr/rt_hw_irq_isr` as existing `rt_hw_soft_irq_isr`. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-01-29 20:28:38 -05:00
Chen Wang	2dfbae2853	libcpu: riscv: common: fixed build warnings ... When building bsp/cvitek/c906_little, compiler warns: ``` .../rt-thread/libcpu/risc-v/common/trap_common.c: In function 'rt_hw_interrupt_install': .../rt-thread/libcpu/risc-v/common/trap_common.c:50:11: warning: unused variable 'user_param' [-Wunused-variable] 50 | void *user_param = param; | ^~~~~~~~~~ .../rt-thread/libcpu/risc-v/common/trap_common.c: In function 'rt_rv32_system_irq_handler': .../rt-thread/libcpu/risc-v/common/trap_common.c:77:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 77 | s_stack_frame = (rt_hw_stack_frame_t *)mscratch; | ^ ``` Fixed these warnings as per indication from gcc. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-01-29 20:28:38 -05:00
Chen Wang	123ed1be1b	bsp: qemu-virt64-riscv: remove config RISCV_S_MODE ... RISCV_S_MODE configuration only affects the code in libcpu/risc-v/virt64, and the only bsp using this libcpu is qemu-virt64-riscv. Considering s-mode is the default mode RT-Thread running on virt64 machine, it seems unnecessary to make RISCV_S_MODE a Kconfig option. Solution: Remove RISCV_S_MODE from Kconfig and define it as a macro in the code in libcpu/risc-v/virt64. Plus, due to this macro is only related to virt64, rename RISCV_S_MODE to RISCV_VIRT64_S_MODE. Update the .config/rtconfig.h in this patch. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-01-10 17:14:13 +08:00
Meco Man	97b9cc5000	fix: add \n for addr2line hint	2025-01-08 17:54:46 -05:00
Shell	7ff75e21fa	feat: arm64: mmu: auto-sensing of best paging stride ... Improves the memory mapping process by dynamically selecting the optimal paging stride (4K or 2M) based on virtual address alignment and mapping size. This eliminates the need for upfront stride determination, enhancing flexibility and maintainability in memory management. Changes: - Replaced fixed stride selection logic with a dynamic decision loop. - Removed `npages` calculation and replaced with `remaining_sz` to track unprocessed memory size. - Added assertions to ensure `size` is properly aligned to the smallest page size. - Adjusted loop to dynamically determine and apply the appropriate stride (4K or 2M) for each mapping iteration. - Updated virtual and physical address increments to use the dynamically selected stride. Signed-off-by: Shell <smokewood@qq.com>	2024-12-13 23:38:32 -05:00
GuEe-GUI	78f318aa8f	[FIXUP] __rt_clz loss in aarch64 ... Signed-off-by: GuEe-GUI <2991707448@qq.com>	2024-12-13 10:39:20 +08:00
kurisaw	2c3ee65d7f	rzn2l-rsk support studio	2024-12-04 10:11:04 +08:00
kurisaw	3f1a62cfe3	[libcpu][drivers] cortex-r52 abnormal takeover and software rtc naming change	2024-12-04 10:11:04 +08:00
heyuanjie87	03a9729eb8	[libcpu/riscv]解决smp下cpuport.h中的编译问题 (#9714)	2024-11-29 09:39:41 +08:00
heyuanjie87	d3820ed77e	给vector模块添加构建脚本	2024-11-27 18:04:59 +08:00
heyuanjie87	3268716c4f	[libcpu][riscv]virt64使用通用vector支持代码	2024-11-27 18:04:59 +08:00
Shell	b7520e262b	feat: Kconfig: moving the arm64 specified configs to sub-menu ... Just for better readability. Signed-off-by: Shell <smokewood@qq.com>	2024-11-24 13:44:34 -05:00
Shell	fe2b124345	feat: arm64 ASID support ... Support for ARM64 ASID to enhance virtual memory management efficiency by reducing the need for TLB flushes during address space switches. These changes improve performance especially for multi-process systems. Changes: - Added `ARCH_USING_ASID` configuration in `libcpu/aarch64/Kconfig`. - Defined ASID-related constants in `mmu.h`. - Updated `TLBI_ARG` macro to include ASID manipulation. - Implemented ASID allocation mechanism with spinlock synchronization. - Enhanced TLB invalidation to support ASID-specific operations. - Modified `rt_hw_aspace_switch` to use ASIDs when switching address spaces. - Adjusted debug logging and function documentation to reflect ASID usage. - Refactored AArch64 MMU and TLB handling for ASID integration. Signed-off-by: Shell <smokewood@qq.com>	2024-11-24 13:44:34 -05:00
heyuanjie87	2a684126c0	[libcpu][riscv]纠正pv_offset的对齐检查	2024-11-21 19:23:11 -05:00
GuEe-GUI	5dda65c21b	[DM/FIXUP] add cortex-m23's cpuport.h ... Signed-off-by: GuEe-GUI <2991707448@qq.com>	2024-11-20 16:11:10 +08:00
GuEe-GUI	1bef42c64c	[DM/FIXUP] remove some redundant INIT_EXPORT ... Signed-off-by: GuEe-GUI <2991707448@qq.com>	2024-11-18 15:03:23 +08:00
zhujiale	44515624e2	[libcpu] fix No memory higher than 1 GB is mapped	2024-11-17 21:13:07 -05:00
zhujiale	96da7abd3e	[libcpu] fix No memory higher than 1 GB is mapped	2024-11-17 21:13:07 -05:00
heyuanjie87	2b21b095f9	[libcpu]riscv使用call指令解决长跳转问题	2024-11-15 14:34:32 +08:00
kurisaw	2241f4676b	[libcpu][component] fixed the r52 kernel gcc context switch assembly	2024-11-06 16:09:52 +08:00
Shell	a573ea06b7	🚚 renaming: move smp to smp_call	2024-11-03 10:08:45 +08:00
Shell	2f6d98bfcb	feat: smp_call: added signaling call_req ... This patch introduces `rt_smp_call_request` API to handle queued requests across cores with user provided data buffer, which provides a way to request IPI through a non-blocking pattern. It also resolved several issues in the old implementation: - Multiple requests from different cores can not be queued in the work object of the target core. - Data racing on `rt_smp_work` of same core. If multiple requests came in turns, or if the call is used by the target cpu, while a new request is coming, the value will be overwrite. - Memory vulnerability. The rt_smp_event is allocated on stack, though the caller may not wait until the call is done. - API naming problem. Actually we don't provide a way to issue an IPI to ANY core in mask. What the API do is aligned to MANY pattern. - FUNC_IPI registering to PIC. Changes: - Declared and configured the new `RT_SMP_CALL_IPI` to support functional IPIs for task requests across cores. - Replaced the single `rt_smp_work` array with `call_req_cores` to manage per-core call requests safely. - Added `_call_req_take` and `_call_req_release` functions for atomic handling of request lifetimes, preventing data race conditions. - Replaced single event handling with a queue-based approach (`call_queue`) for efficient multi-request processing per core. - Introduced `rt_smp_call_ipi_handler` to process queued requests, reducing IPI contention by only sending new requests when needed. - Implemented `_smp_call_remote_request` to handle remote requests with specific flags, enabling more flexible core-to-core task signaling. - Refined `rt_smp_call_req_init` to initialize and track requests with atomic usage flags, mitigating potential memory vulnerabilities. Signed-off-by: Shell <smokewood@qq.com>	2024-11-03 10:08:45 +08:00
Shell	40cd8cce99	feat: Added rt_interrupt_context* family for nested interrupt handling ... These changes introduce the rt_interrupt_context family, providing a mechanism for managing nested interrupts. The context management ensures proper storage and retrieval of interrupt states, improving reliability in nested interrupt scenarios by enabling context tracking across different interrupt levels. This enhancement is essential for platforms where nested interrupt handling is crucial, such as in real- time or multi-threaded applications. Changes: - Defined rt_interrupt_context structure with context and node fields in `rtdef.h` to support nested interrupts. - Added rt_slist_pop function in `rtservice.h` for simplified node removal in singly linked lists. - Declared rt_interrupt_context_push, rt_interrupt_context_pop, and rt_interrupt_context_get functions in `rtthread.h` to manage the interrupt/exception stack. - Modified AArch64 CPU support in `cpuport.h` to include rt_hw_show_register for debugging registers. - Refactored `_rt_hw_trap_irq` in `trap.c` for context-aware IRQ handling, with stack push/pop logic to handle nested contexts. - Implemented interrupt context push, pop, and retrieval logic in `irq.c` to manage context at the CPU level. Signed-off-by: Shell <smokewood@qq.com>	2024-11-03 10:08:45 +08:00
Kai	7bf8589fad	[libcpu][cortex-m7] use hw atomic	2024-11-01 18:45:00 -04:00