1032 Commits

Author	SHA1	Message	Date
Yonggang Luo	27e3460b88	Remove unused rt_hw_set_gtimer_frq	2025-10-13 21:44:36 +08:00
Yonggang Luo	5ae232b6d0	bsp/w60x: fixes cppcheck: (#10781) ... [cpp_check.py 80 INFO] bsp/w60x/drivers/drv_rtc.c:58:11: error: Syntax Error: AST broken, binary operator '&=' doesn't have two operands. [internalAstError] [cpp_check.py 80 INFO] libcpu/arm/s3c24x0/rtc.c:34:12: error: Expression 'RTCCON|=RTCCON|=0x01' depends on order of evaluation of side effects [unknownEvaluationOrder]	2025-10-11 09:28:52 +08:00
Yonggang Luo	62bc4ba774	Remove rarely used rt_time_t ... next_delay should be rt_tick_t Use time_t for RT_DEVICE_CTRL_RTC_GET_TIME	2025-10-10 20:21:40 +08:00
zhangyan	cc72712173	[CPU/AARCH64] 增加 libcpu/aarch64 KERNEL_ASPACE_START 配置 #10757 ... 针对不同的 Aarch64 BSP 针对 KERNEL_VADDR_START 宏定义进行区分	2025-10-10 11:02:28 +08:00
R b b666	2b65a6f2a7	fix:Fixed compilation error for libcpu/cortex-m4. (#10756)	2025-09-28 16:08:02 +08:00
Haojin Tang	893ae7d7ba	fix(risc-v, virt64, plic): use volatile rw for claim and complete	2025-09-03 09:48:22 +08:00
Haojin Tang	db4fb4c243	fix(risc-v, mmu): fix type mismatch of _query	2025-09-01 18:44:24 +08:00
Haojin Tang	157d809634	fix(risc-v/virt64, cpp): add spaces to fix Wliteral-suffix	2025-09-01 18:43:04 +08:00
Haojin Tang	b27e405faa	fix(riscv, cpp): remove rt_hw_cpu_id in cpuport.h to fix error	2025-09-01 18:42:08 +08:00
maosql	9567564e86	fix: warnings generated by Kconfig.	2025-09-01 11:50:41 +08:00
Rbb666	882d1958dd	[libcpu][cortex-m33]Added HardFault_Handler to save floating point registers	2025-08-20 18:17:19 +08:00
Rbb666	990fc23628	[libcpu][cortex-m4]Added HardFault_Handler to save floating point registers.	2025-08-19 21:40:57 +08:00
R b b666	2f19ba6ce7	[libcpu ][cm3]The parameter passed to the unified rt_exception_hook is exception_stack. (#10619)	2025-08-19 21:15:47 +08:00
Yulong Wang	e7a40ae6ec	[lwp][rv64] restore tp register in arch_thread_signal_enter to fix user-mode memory access	2025-07-23 09:38:35 +08:00
GuEe-GUI	8a4890a9e5	[ARCH/AARCH64] Update Hypercall API ... Signed-off-by: GuEe-GUI <2991707448@qq.com>	2025-07-16 12:52:51 +08:00
GUI	3d72290b38	[aarch64]Fixup linker warning #10466	2025-07-08 14:10:04 +08:00
GuEe-GUI	d698bb487e	Fixup the boot EL check ... The boot EL will save in x0, when current EL is EL3, kernel will jump to the EL2 after EL3. But the x0 value is **3**, The init for EL2 will not work. To fix it: the EL3 should jump to the EL2 init branch with not check, and when SoC boot in EL2, kernel will jump to the EL2 test branch. Link: https://club.rt-thread.org/ask/question/ec320a6765389f67.html Signed-off-by: wusongjie <wusongjie@rt-thread.com>	2025-07-07 10:58:52 +08:00
GuEe-GUI	a894796566	[CPU/AARCH64] Fixup MMU ... 1. Configure the kernel default vaddr by RAM and TEXT offset. 2. Check the p_addr 2M align when set the stride in `rt_hw_mmu_map`. Signed-off-by: GuEe-GUI <2991707448@qq.com>	2025-07-04 16:37:29 +08:00
kurisaw	4f903298a2	libcpu/bsp: fix the M33 assembly syntax errors and fix the compilation error of bsp	2025-06-24 11:04:01 +08:00
ZhangJing	c3d33f39d4	[bsp]增加超睿DP1000 bsp支持	2025-05-30 13:32:58 +08:00
Yaochenger	f4e619a17c	移除无用文件，该文件未被任何BSP使用	2025-05-30 09:32:08 +08:00
Yaochenger	5889db6819	[libcpu/common] 修正对RV32E的支持，RV32E不支持s2寄存器，修改为s1寄存器	2025-05-30 09:32:08 +08:00
zhangjing	e3d7bbb47c	[libcpu][risc-v]:add comment for the round down of symb_pc	2025-05-28 19:37:51 +08:00
zhangjing	3922ec7e99	[libcpu][risc-v] fix:only map the 1GB space where the original code segment is located	2025-05-28 19:37:51 +08:00
rcitach	aee8920d07	import re	2025-04-28 10:52:58 +08:00
rcitach	5833e02e2f	Fix Aarch64 architecture runtime issues ... 该问题由5b3320624da5149fc21c2d3e1f321d855e3d0dfe引入，导致工具链编译时加上了 -std=gnu99,其他架构是否出问题暂时未知	2025-04-28 10:52:58 +08:00
mouch6131	86df886c7f	libcpu: aarch64: Fix NORMAL_NOCACHE_MEM attr (#10180) ... Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com> Signed-off-by: mouch6131 <187177037@qq.com> Co-authored-by: Cliff Chen <cliff.chen@rock-chips.com>	2025-04-13 22:12:00 +08:00
Chen Wang	312f9dbc08	libcpu: riscv: declare external symbols inside ... libcpu/risc-v/common64/mmu.c uses the external symbol "__bss_end" (this symbol generally is defined in the link script file) and depends on the extern declaration of this symbol in the bsp's "board.h". This is not a problem in implementation, but it is not a good habit. If this extern symbol is used locally, just declare it locally should be better. In this way, there will be no dependency of the kernel core on the bsp header file. And there will be no special requirements for the bsp board code, such as the need to make extern declarations for these "__bss_end" symbols in "board.h". This patch currently only explicitly externly declares "__bss_end" inside libcpu itself. The code of "#include <board.h>" is kept, because the modification involved is too large, it is necessary to clean up the bsp involved before cleaning this include code line uniformly. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-04-11 14:15:12 +08:00
Chen Wang	5c9f61879c	libcpu: cleanup undefined rt_hw_mmu_kernel_map_init (#10177) ... * libcpu: cleanup undefined rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init() is declared in header files but no definition found, cleanup the code. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * bsp: allwinner: d1: remove calling of rt_hw_mmu_kernel_map_init rt_hw_mmu_kernel_map_init is an undefined function, calling it is meaningless. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --------- Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-04-11 07:54:21 +08:00
zms123456	883bdfa9ef	[libcpu][aarch64]fix gicv3 mpidr table (#9284) ... * fix gicv3 mpidr error * phytium should support rt_cpu_mpidr_table by using common_setup	2025-03-28 11:08:28 +08:00
CYFS	b0e7cba9fd	[bsp][stm32][artpi]:fix artpi nano (#10122)	2025-03-18 22:55:13 +08:00
Rbb666	cb098c4eea	[fix]Fix cm33 compilation problem when block is turned on	2025-03-17 19:13:34 +08:00
ligr	9da813b151	[libcpu][risc-v]add code for handling exception scenarios in _unmap_area.	2025-03-17 17:40:55 +08:00
ligr	b04aacbd94	[libcpu][risc-v]remove unused parameter 'size' for func _unmap_area. ... Signed-off-by: ligr <liguorui1213@163.com>	2025-03-17 17:40:55 +08:00
latercomer	40360efe1d	解决rt_interrupt_from_thread和rt_interrupt_to_thread指针赋值错误 ... Signed-off-by: latercomer <latercomer@qq.com>	2025-03-17 16:45:59 +08:00
latercomer	b8e9f7e0f5	修复rt_hw_context_switch_to和rt_hw_context_switch的形参 ... Signed-off-by: latercomer <latercomer@qq.com>	2025-03-17 16:45:59 +08:00
latercomer	130b5ba653	解决rt_hw_context_switch_interrupt形参定义不一致 ... Signed-off-by: latercomer <latercomer@qq.com>	2025-03-17 16:45:59 +08:00
latercomer	9e13f67018	删除libcpu/sim/simulator中msvc编译器多余代码，为后续支持mingw64做准备 ... Signed-off-by: latercomer <latercomer@qq.com>	2025-03-17 16:45:59 +08:00
Guorui Li	5a09694f05	[libcpu][risc-v]add comments for rt_hw_mem_setup_early. (#10102)	2025-03-12 09:40:46 +08:00
Kai	f7d542155f	[libcpu][riscv] add a doc for wch saving the irq stack as stack-512 (#10063)	2025-03-03 23:13:11 +08:00
Guorui Li	7f05592592	[libcpu][risc-v]add comments for rv64 sv39 mmu APIs. (#10053)	2025-03-02 00:03:13 +08:00
Guorui Li	8adae0725d	[bugfix][risc-v]fix the PPN length error in GET_PPN(pte). (#10020)	2025-02-28 08:23:46 +08:00
Shell	9386411d13	feat: mm: added affinity pages allocator ... This patch introduces a tagged pages allocator to address the existing problems of page aliasing on specific platforms and the requirement of page coloring. It implements an affinity-id aware page manager by separating the runtime page list into two types: a normal single linked-list and a multi-dimensional affinity-list. Changes: - Introduced tagged pages allocator and managing algorithm for affinity pages list - Modified components to support affinity-id list management - Updated page allocation and freeing functions to handle tagged pages - Added configuration options for page affinity block size and debugging - Modified mmap and elf loading to respect affinity settings - Enhanced page list management to support multi-dimensional affinity-list Signed-off-by: Shell <smokewood@qq.com>	2025-02-25 11:26:30 +08:00
kenneth.liu	2be83d5cad	libcpu: riscv: fixed ARCH_RISCV_VECTOR issue ... description: Using the vector instruction set to trigger an illegal instruction exception when ARCH_SISCV_VECTOR=y. analysis: When initializing the thread stack, the rt_cw_stack_init function did not enable VS for SSTATUS. Solution: When ARCH_SISCV_VECTOR=y, increment the initial value of sstatus by 0x600(SSTATUS_VS). Signed-off-by: Liu Gui <kenneth.liu@sophgo.com>	2025-02-22 14:17:54 -05:00
GuEe-GUI	d41a0351db	[AARCH64] Update kernel's boot link for ARM64 ... Signed-off-by: GuEe-GUI <2991707448@qq.com>	2025-02-11 14:58:18 +08:00
Chen Wang	c66374705a	libcpu: riscv: rv64: fixed warnings ... When building bsp/cvitek/c906_little, compiler reports: ``` .../rt-thread/libcpu/risc-v/rv64/trap.c: In function 'handle_trap': .../rt-thread/libcpu/risc-v/rv64/trap.c:106:13: warning: implicit declaration of function 'rt_hw_tick_isr'; did you mean 'rt_hw_stack_init'? [-Wimplicit-function-declaration] 106 | rt_hw_tick_isr(); | ^~~~~~~~~~~~~~ | rt_hw_stack_init .../rt-thread/libcpu/risc-v/rv64/trap.c:110:13: warning: implicit declaration of function 'rt_hw_irq_isr'; did you mean 'rt_hw_soft_irq_isr'? [-Wimplicit-function-declaration] 110 | rt_hw_irq_isr(); | ^~~~~~~~~~~~~ | rt_hw_soft_irq_isr ``` rt_hw_tick_isr()/rt_hw_irq_isr() are implemented by bsp, but libcpu/risc-v/rv64 doesn't declare them, so compiler warns. There are three BSPs using 'rv64' (libcpu/risc-v/rv64): - `bsp/cvitek/c906_little/rtconfig.py` - `bsp/juicevm/rtconfig.py` - `bsp/k210/rtconfig.py` `handle_trap` in `libcpu/risc-v/rv64` is defined as weak. BSP can use this function directly or define and overload it by itself. If bsp use this function directly, bsp need to pay attention to the fact that three functions will be called in this function: - `rt_hw_soft_irq_isr` - `rt_hw_tick_isr` - `rt_hw_irq_isr` In `libcpu/risc-v/rv64`, `rt_hw_soft_irq_isr` has a weak definition, while the other two do not. This means that if the bsp does not overload `handle_trap`, bsp must define `rt_hw_tick_isr` and `rt_hw_irq_isr` itself. This is also the practice of `bsp/cvitek/c906_little`. There is also a similar bsp `bsp/k210`, and the form of `bsp/juicevm` implements `handle_trap` by itself. It seems that `rt_hw_tick_isr` and `rt_hw_irq_isr` are not required to be implemented by all BSPs using `libcpu/risc-v/rv64`. The premise for BSP to implement them is that it does not overload `handle_trap`. So declaring `rt_hw_tick_isr` and `rt_hw_irq_isr` with extern in `libcpu/risc-v/rv64` is not proper. In addition, the `rt_hw_tick_isr/rt_hw_irq_isr` are only used by `libcpu/risc-v/rv64`, so it is not worth putting the declaration in `./include/rthw.h`. Sum up, the best solution is to add weak definition to `rt_hw_tick_isr/rt_hw_irq_isr` as existing `rt_hw_soft_irq_isr`. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-01-29 20:28:38 -05:00
Chen Wang	2dfbae2853	libcpu: riscv: common: fixed build warnings ... When building bsp/cvitek/c906_little, compiler warns: ``` .../rt-thread/libcpu/risc-v/common/trap_common.c: In function 'rt_hw_interrupt_install': .../rt-thread/libcpu/risc-v/common/trap_common.c:50:11: warning: unused variable 'user_param' [-Wunused-variable] 50 | void *user_param = param; | ^~~~~~~~~~ .../rt-thread/libcpu/risc-v/common/trap_common.c: In function 'rt_rv32_system_irq_handler': .../rt-thread/libcpu/risc-v/common/trap_common.c:77:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 77 | s_stack_frame = (rt_hw_stack_frame_t *)mscratch; | ^ ``` Fixed these warnings as per indication from gcc. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-01-29 20:28:38 -05:00
Chen Wang	123ed1be1b	bsp: qemu-virt64-riscv: remove config RISCV_S_MODE ... RISCV_S_MODE configuration only affects the code in libcpu/risc-v/virt64, and the only bsp using this libcpu is qemu-virt64-riscv. Considering s-mode is the default mode RT-Thread running on virt64 machine, it seems unnecessary to make RISCV_S_MODE a Kconfig option. Solution: Remove RISCV_S_MODE from Kconfig and define it as a macro in the code in libcpu/risc-v/virt64. Plus, due to this macro is only related to virt64, rename RISCV_S_MODE to RISCV_VIRT64_S_MODE. Update the .config/rtconfig.h in this patch. Signed-off-by: Chen Wang <unicorn_wang@outlook.com>	2025-01-10 17:14:13 +08:00
Meco Man	97b9cc5000	fix: add \n for addr2line hint	2025-01-08 17:54:46 -05:00
Shell	7ff75e21fa	feat: arm64: mmu: auto-sensing of best paging stride ... Improves the memory mapping process by dynamically selecting the optimal paging stride (4K or 2M) based on virtual address alignment and mapping size. This eliminates the need for upfront stride determination, enhancing flexibility and maintainability in memory management. Changes: - Replaced fixed stride selection logic with a dynamic decision loop. - Removed `npages` calculation and replaced with `remaining_sz` to track unprocessed memory size. - Added assertions to ensure `size` is properly aligned to the smallest page size. - Adjusted loop to dynamically determine and apply the appropriate stride (4K or 2M) for each mapping iteration. - Updated virtual and physical address increments to use the dynamically selected stride. Signed-off-by: Shell <smokewood@qq.com>	2024-12-13 23:38:32 -05:00