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[CPU/AARCH64] Fixup MMU
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Browse Source 
1. Configure the kernel default vaddr by RAM and TEXT offset.
2. Check the p_addr 2M align when set the stride in `rt_hw_mmu_map`.

Signed-off-by: GuEe-GUI <2991707448@qq.com>
This commit is contained in:
GuEe-GUI
2025-06-30 12:48:48 +08:00
committed by Rbb666
parent fcd0b1e679
commit a894796566
1 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
libcpu/aarch64/common/mmu.c
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@@ -54,7 +54,7 @@
/* restrict virtual address on usage of RT_NULL */
#ifndef KERNEL_VADDR_START
#define KERNEL_VADDR_START 0x1000
#define KERNEL_VADDR_START (ARCH_RAM_OFFSET + ARCH_TEXT_OFFSET)
#endif
volatile unsigned long MMUTable[512] __attribute__((aligned(4 * 1024)));
@@ -283,7 +283,9 @@ void *rt_hw_mmu_map(rt_aspace_t aspace, void *v_addr, void *p_addr, size_t size,
while (remaining_sz)
{
if (((rt_ubase_t)v_addr & ARCH_SECTION_MASK) || (remaining_sz < ARCH_SECTION_SIZE))
if (((rt_ubase_t)v_addr & ARCH_SECTION_MASK) ||
((rt_ubase_t)p_addr & ARCH_SECTION_MASK) ||
(remaining_sz < ARCH_SECTION_SIZE))
{
/* legacy 4k mapping */
stride = ARCH_PAGE_SIZE;