mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-02-07 09:52:08 +08:00
[bsp/raspi3-64]fix gpio drvier
This commit is contained in:
bigmagic
@@ -146,7 +146,7 @@ CONFIG_RT_USING_SERIAL=y
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# CONFIG_RT_SERIAL_USING_DMA is not set
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CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_CAN is not set
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# CONFIG_RT_USING_HWTIMER is not set
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CONFIG_RT_USING_HWTIMER=y
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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CONFIG_RT_USING_PIN=y
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@@ -465,7 +465,9 @@ CONFIG_BSP_USING_UART=y
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CONFIG_RT_USING_UART1=y
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CONFIG_BSP_USING_PIN=y
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CONFIG_BSP_USING_CORETIMER=y
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# CONFIG_BSP_USING_SYSTIMER is not set
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CONFIG_BSP_USING_SYSTIMER=y
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CONFIG_RT_USING_SYSTIMER1=y
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# CONFIG_RT_USING_SYSTIMER3 is not set
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# CONFIG_BSP_USING_I2C is not set
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# CONFIG_BSP_USING_SPI is not set
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# CONFIG_BSP_USING_WDT is not set
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@@ -5,7 +5,6 @@ from building import *
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cwd = GetCurrentDir()
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src = Split('''
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board.c
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bcm283x.c
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drv_uart.c
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''')
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CPPPATH = [cwd]
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -17,6 +17,7 @@
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#include "cp15.h"
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#include "mmu.h"
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#include "raspi.h"
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#ifdef BSP_USING_CORETIMER
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static rt_uint64_t timerStep;
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@@ -13,10 +13,6 @@
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#include <stdint.h>
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#include <rthw.h>
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#include <bcm283x.h>
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#define __REG32 HWREG32
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extern unsigned char __bss_start;
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extern unsigned char __bss_end;
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File diff suppressed because it is too large
Load Diff
@@ -11,19 +11,20 @@
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#ifndef __DRV_GPIO_H__
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#define __DRV_GPIO_H__
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <rtdebug.h>
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#include <rtdbg.h>
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#include "interrupt.h"
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#include "bcm283x.h"
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#include "raspi.h"
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#include "board.h"
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#include "interrupt.h"
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#define GPIO_IRQ_NUM 3
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#define IRQ_GPIO0 49
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#define IRQ_GPIO1 50
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#define IRQ_GPIO2 51
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#define IRQ_GPIO3 52
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struct gpio_irq_def
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{
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void *irq_arg[32];
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@@ -8,58 +8,60 @@
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* 2019-07-29 zdzn first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "bcm283x.h"
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#include "drv_timer.h"
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#include <drivers/hwtimer.h>
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#include "cp15.h"
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#include "interrupt.h"
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#include "raspi.h"
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static void rt_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state)
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#ifdef BSP_USING_SYSTIMER
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static void raspi_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state)
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{
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if (state == 0)
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hwtimer->ops->stop(hwtimer);
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}
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static rt_err_t rt_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
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static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
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{
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rt_err_t result = RT_EOK;
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rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
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int timer_id = timer->timer_id;
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if (mode == HWTIMER_MODE_PERIOD)
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timer->cnt = cnt;
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else
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timer->cnt = 0;
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__DSB();
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__sync_synchronize();
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if (timer_id == 1)
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{
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rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_1);
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rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
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STIMER_C1 = STIMER_CLO + cnt;
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}
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else if (timer_id == 3)
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{
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rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_3);
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rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
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STIMER_C3 = STIMER_CLO + cnt;
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}
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else
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result = -RT_ERROR;
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__DSB();
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__sync_synchronize();
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return result;
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}
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static void rt_systimer_stop(rt_hwtimer_t *hwtimer)
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static void raspi_systimer_stop(rt_hwtimer_t *hwtimer)
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{
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rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
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int timer_id = timer->timer_id;
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if (timer_id == 1)
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rt_hw_interrupt_mask(IRQ_SYSTIMER_MATCH_1);
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rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1);
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else if (timer_id == 3)
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rt_hw_interrupt_mask(IRQ_SYSTIMER_MATCH_3);
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rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3);
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}
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static rt_err_t rt_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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{
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/* The frequency value is an immutable value. */
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if (cmd == HWTIMER_CTRL_FREQ_SET)
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@@ -72,23 +74,17 @@ static rt_err_t rt_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg
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}
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}
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const static struct rt_hwtimer_ops systimer_ops =
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{
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rt_systimer_init,
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rt_systimer_start,
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rt_systimer_stop,
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RT_NULL,
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rt_systimer_ctrl
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};
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void rt_device_systimer_isr(int vector, void *param)
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{
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rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param;
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rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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int timer_id = timer->timer_id;
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__DSB();
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__sync_synchronize();
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if (timer_id == 1)
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{
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STIMER_CS = 0x2;
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@@ -99,15 +95,29 @@ void rt_device_systimer_isr(int vector, void *param)
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STIMER_CS = 0x8;
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STIMER_C3 = STIMER_CLO + timer->cnt;
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}
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__DSB();
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__sync_synchronize();
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rt_device_hwtimer_isr(hwtimer);
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}
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#ifdef RT_USING_SYSTIMER1
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static struct rt_hwtimer_device _hwtimer1;
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static rt_systimer_t _systimer1;
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#endif
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#ifdef RT_USING_SYSTIMER3
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static struct rt_hwtimer_device _hwtimer3;
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static struct rt_systimer_device _systimer1;
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static struct rt_systimer_device _systimer3;
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static rt_systimer_t _systimer3;
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#endif
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const static struct rt_hwtimer_ops systimer_ops =
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{
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raspi_systimer_init,
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raspi_systimer_start,
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raspi_systimer_stop,
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RT_NULL,
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raspi_systimer_ctrl
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};
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static const struct rt_hwtimer_info _info =
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{
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@@ -117,15 +127,20 @@ static const struct rt_hwtimer_info _info =
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HWTIMER_CNTMODE_UP /* count mode (inc/dec) */
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};
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#endif
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int rt_hw_systimer_init(void)
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{
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#ifdef BSP_USING_SYSTIMER
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#ifdef RT_USING_SYSTIMER1
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_systimer1.timer_id =1;
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_hwtimer1.ops = &systimer_ops;
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_hwtimer1.info = &_info;
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rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1);
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rt_hw_interrupt_install(IRQ_SYSTIMER_MATCH_1, rt_device_systimer_isr, &_hwtimer1, "systimer1");
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rt_hw_interrupt_umask(IRQ_SYSTIMER_MATCH_1);
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rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_hwtimer1, "systimer1");
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rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
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#endif
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#ifdef RT_USING_SYSTIMER3
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@@ -133,9 +148,12 @@ int rt_hw_systimer_init(void)
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_hwtimer3.ops = &systimer_ops;
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_hwtimer3.info = &_info;
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rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3);
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rt_hw_interrupt_install(IRQ_SYSTIMER_MATCH_3, rt_device_systimer_isr, &_hwtimer3, "systimer3");
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rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_hwtimer3, "systimer3");
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rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
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#endif
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#endif
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return 0;
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}
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INIT_DEVICE_EXPORT(rt_hw_systimer_init);
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@@ -12,11 +12,10 @@
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "raspi.h"
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#include "board.h"
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#include "drv_uart.h"
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#include <rtdevice.h>
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#define AUX_BASE (0x3F000000 + 0x215000)
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struct hw_uart_device
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@@ -34,20 +33,19 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
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if (uart->hw_base == AUX_BASE)
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{
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rt_uint32_t value;
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rt_uint32_t value;
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/* GPIO function set */
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value = GPIO_GPFSEL1;
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value &= ~(7<<12); /* GPIO14 */
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value |= 2<<12 ; /* ALT5 */
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value &= ~(7<<15); /* GPIO15 */
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value |= 2<<15 ; /* ALT5 */
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GPIO_GPFSEL1 = value;
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value = BCM283X_GPIO_GPFSEL(1);
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value &= ~(7 << 12); /* GPIO14 */
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value |= 2 << 12 ; /* ALT5 */
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value &= ~(7 << 15); /* GPIO15 */
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value |= 2 << 15 ; /* ALT5 */
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BCM283X_GPIO_GPFSEL(1) = value;
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/* PullUD disable */
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GPIO_GPPUD = 0;
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GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15);
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GPIO_GPPUDCLK0 = 0;
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BCM283X_GPIO_GPPUD = 0;
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BCM283X_GPIO_GPPUDCLK(0) = (1 << 14) | (1 << 15);
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BCM283X_GPIO_GPPUDCLK(0) = 0;
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AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */
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AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */
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@@ -12,60 +12,160 @@
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#ifndef __RASPI_H__
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#define __RASPI_H__
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#include "bcm283x.h"
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#include <rthw.h>
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#define PIN_MAGIC (0x5A)
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#define PIN_NUM(_N) (sizeof(_N) / sizeof(_N[0]))
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#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
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enum gpio_code
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typedef enum
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{
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GPIO_CODE_PHY = 0,
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GPIO_CODE_BCM,
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GPIO_CODE_WIRING,
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GPIO_CODE_NUM,
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};
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BCM_GPIO_PIN_0 = 0,
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BCM_GPIO_PIN_1,
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BCM_GPIO_PIN_2,
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BCM_GPIO_PIN_3,
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BCM_GPIO_PIN_4,
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BCM_GPIO_PIN_5,
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BCM_GPIO_PIN_6,
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BCM_GPIO_PIN_7,
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BCM_GPIO_PIN_8,
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BCM_GPIO_PIN_9,
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BCM_GPIO_PIN_10,
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BCM_GPIO_PIN_11,
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BCM_GPIO_PIN_12,
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BCM_GPIO_PIN_13,
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BCM_GPIO_PIN_14,
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BCM_GPIO_PIN_15,
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BCM_GPIO_PIN_16,
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BCM_GPIO_PIN_17,
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BCM_GPIO_PIN_18,
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BCM_GPIO_PIN_19,
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BCM_GPIO_PIN_20,
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BCM_GPIO_PIN_21,
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BCM_GPIO_PIN_22,
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BCM_GPIO_PIN_23,
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BCM_GPIO_PIN_24,
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BCM_GPIO_PIN_25,
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BCM_GPIO_PIN_26,
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BCM_GPIO_PIN_27,
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BCM_GPIO_PIN_28,
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BCM_GPIO_PIN_29,
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BCM_GPIO_PIN_30,
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BCM_GPIO_PIN_31,
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BCM_GPIO_PIN_32,
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BCM_GPIO_PIN_33,
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BCM_GPIO_PIN_34,
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BCM_GPIO_PIN_35,
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BCM_GPIO_PIN_36,
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BCM_GPIO_PIN_37,
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BCM_GPIO_PIN_38,
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BCM_GPIO_PIN_39,
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BCM_GPIO_PIN_40,
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BCM_GPIO_PIN_41,
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BCM_GPIO_PIN_42,
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BCM_GPIO_PIN_43,
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BCM_GPIO_PIN_44,
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BCM_GPIO_PIN_45,
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BCM_GPIO_PIN_46,
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BCM_GPIO_PIN_47,
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BCM_GPIO_PIN_48,
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BCM_GPIO_PIN_49,
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BCM_GPIO_PIN_50,
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BCM_GPIO_PIN_51,
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BCM_GPIO_PIN_52,
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BCM_GPIO_PIN_53,
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BCM_GPIO_PIN_NULL,
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} bcm_gpio_pin;
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enum rpi_pin_name
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typedef enum
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{
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RPI_SDA0 = 0,
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RPI_SCL0,
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RPI_SDA1,
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RPI_SCL1,
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RPI_GPIO_GCLK,
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RPI_CAM_CLK,
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RPI_LAN_RUN,
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RPI_SPI_CE1_N,
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RPI_SPI_CE0_N,
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RPI_SPI_MISO,
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RPI_SPI_MOSI,
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RPI_SPI_SCLK,
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RPI_TXD0,
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RPI_RXD0,
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RPI_STATUS_LED_N,
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RPI_GPIO_GEN0,
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RPI_GPIO_GEN1,
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RPI_CAM_GPIO,
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RPI_GPIO_GEN3,
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RPI_GPIO_GEN4,
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RPI_GPIO_GEN5,
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RPI_GPIO_GEN6,
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RPI_GPIO_GEN2,
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RPI_GPIO_GEN7,
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RPI_GPIO_GEN8,
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RPI_GPIO_GEN9,
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RPI_GPIO_GEN10,
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RPI_PWM0_OUT,
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RPI_PWM1_OUT,
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RPI_HDMI_HPD_P,
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RPI_SD_CARD_DET,
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RPI_SD_CLK_R,
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RPI_SD_CMD_R,
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RPI_SD_DATA0_R,
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RPI_SD_DATA1_R,
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RPI_SD_DATA2_R,
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RPI_SD_DATA3_R,
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RPI_GPIO_PIN_NUM,
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};
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BCM283X_GPIO_FSEL_INPT = 0x00, /*!< Input 0b000 */
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BCM283X_GPIO_FSEL_OUTP = 0x01, /*!< Output 0b001 */
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BCM283X_GPIO_FSEL_ALT0 = 0x04, /*!< Alternate function 0 0b100 */
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BCM283X_GPIO_FSEL_ALT1 = 0x05, /*!< Alternate function 1 0b101 */
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BCM283X_GPIO_FSEL_ALT2 = 0x06, /*!< Alternate function 2 0b110, */
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BCM283X_GPIO_FSEL_ALT3 = 0x07, /*!< Alternate function 3 0b111 */
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BCM283X_GPIO_FSEL_ALT4 = 0x03, /*!< Alternate function 4 0b011 */
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BCM283X_GPIO_FSEL_ALT5 = 0x02, /*!< Alternate function 5 0b010 */
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BCM283X_GPIO_FSEL_MASK = 0x07 /*!< Function select bits mask 0b111 */
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} gpio_function_select;
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typedef enum
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{
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BCM283X_GPIO_PUD_OFF = 0x00, /*!< Off ? disable pull-up/down 0b00 */
|
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BCM283X_GPIO_PUD_DOWN = 0x01, /*!< Enable Pull Down control 0b01 */
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BCM283X_GPIO_PUD_UP = 0x02 /*!< Enable Pull Up control 0b10 */
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} gpio_pud_mode;
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|
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#define BCM283X_CORE_CLK_HZ 250000000 /* 50 MHz */
|
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/* Base Address */
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#define PER_BASE (0x3F000000)
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#define PER_BASE_40000000 (0x40000000)
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||||
//#define BCM283X_PERI_BASE (0x3F000000)
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||||
//#define BCM283X_PER_BASE_40000000 (0x40000000)
|
||||
|
||||
/* Base Address Registers Offset */
|
||||
#define ST_BASE_OFFSET (0x003000)
|
||||
#define GPIO_PAD_OFFSET (0x100000)
|
||||
#define CLOCK_BASE_OFFSET (0x101000)
|
||||
#define GPIO_BASE_OFFSET (0x200000)
|
||||
#define SPI0_BASE_OFFSET (0x204000)
|
||||
#define BSC0_BASE_OFFSET (0x205000)
|
||||
#define GPIO_PWM_OFFSET (0x20C000)
|
||||
#define AUX_BASE_OFFSET (0x215000)
|
||||
#define SPI1_BASE_OFFSET (0x215080)
|
||||
#define SPI2_BASE_OFFSET (0x2150C0)
|
||||
#define BSC1_BASE_OFFSET (0x804000)
|
||||
#define BSC2_BASE_OFFSET (0x805000)
|
||||
|
||||
/* IRQ */
|
||||
#define IRQ_SYSTEM_TIMER_0 0
|
||||
#define IRQ_SYSTEM_TIMER_1 1
|
||||
#define IRQ_SYSTEM_TIMER_2 2
|
||||
#define IRQ_SYSTEM_TIMER_3 3
|
||||
#define IRQ_USB 9
|
||||
#define IRQ_AUX 29
|
||||
#define IRQ_PCM 55
|
||||
#define IRQ_ARM_TIMER 64
|
||||
#define IRQ_ARM_MAILBOX 65
|
||||
|
||||
/* Interrupt Controler */
|
||||
#define IRQ_BASE (PER_BASE + 0xB200)
|
||||
#define IRQ_PEND_BASIC __REG32(IRQ_BASE + 0x0000)
|
||||
#define IRQ_PEND1 __REG32(IRQ_BASE + 0x0004)
|
||||
#define IRQ_PEND2 __REG32(IRQ_BASE + 0x0008)
|
||||
#define IRQ_FIQ_CONTROL __REG32(IRQ_BASE + 0x000C)
|
||||
#define IRQ_ENABLE1 __REG32(IRQ_BASE + 0x0010)
|
||||
#define IRQ_ENABLE2 __REG32(IRQ_BASE + 0x0014)
|
||||
#define IRQ_ENABLE_BASIC __REG32(IRQ_BASE + 0x0018)
|
||||
#define IRQ_DISABLE1 __REG32(IRQ_BASE + 0x001C)
|
||||
#define IRQ_DISABLE2 __REG32(IRQ_BASE + 0x0020)
|
||||
#define IRQ_DISABLE_BASIC __REG32(IRQ_BASE + 0x0024)
|
||||
|
||||
|
||||
/* Defines for WDT*/
|
||||
#define PM_BASE (PER_BASE + GPIO_PAD_OFFSET)
|
||||
#define PM_RSTC __REG32(PM_BASE + 0x001C)
|
||||
#define PM_RSTS __REG32(PM_BASE + 0x0020)
|
||||
#define PM_WDOG __REG32(PM_BASE + 0x0024)
|
||||
|
||||
#define PM_PASSWORD 0x5a000000
|
||||
#define PM_WDOG_TIME_SET 0x000fffff
|
||||
#define PM_RSTC_WRCFG_CLR 0xffffffcf
|
||||
#define PM_RSTS_HADWRH_SET 0x00000040
|
||||
#define PM_RSTC_WRCFG_SET 0x00000030
|
||||
#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
|
||||
#define PM_RSTC_RESET 0x00000102
|
||||
#define PM_RSTS_PARTITION_CLR 0xfffffaaa
|
||||
|
||||
/* Defines for System Timer */
|
||||
#define STIMER_BASE (PER_BASE + ST_BASE_OFFSET)
|
||||
#define STIMER_CS __REG32(STIMER_BASE + 0x0000)
|
||||
#define STIMER_CLO __REG32(STIMER_BASE + 0x0004)
|
||||
#define STIMER_CHI __REG32(STIMER_BASE + 0x0008)
|
||||
#define STIMER_C0 __REG32(STIMER_BASE + 0x000C)
|
||||
#define STIMER_C1 __REG32(STIMER_BASE + 0x0010)
|
||||
#define STIMER_C2 __REG32(STIMER_BASE + 0x0014)
|
||||
#define STIMER_C3 __REG32(STIMER_BASE + 0x0018)
|
||||
|
||||
#define DELAY_MICROS(micros) \
|
||||
do{ \
|
||||
@@ -73,4 +173,273 @@ enum rpi_pin_name
|
||||
while (STIMER_CLO < compare); \
|
||||
} while (0) \
|
||||
|
||||
/* Defines for GPIO */
|
||||
#define BCM283X_GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET)
|
||||
#define BCM283X_GPIO_GPFSEL(n) __REG32(BCM283X_GPIO_BASE + 0x0000 + 0x4 * n) /* GPIO Function Select 32bit R/W */
|
||||
#define BCM283X_GPIO_GPSET(n) __REG32(BCM283X_GPIO_BASE + 0x001C + 0x4 * n) /* GPIO Pin Output Set */
|
||||
#define BCM283X_GPIO_GPCLR(n) __REG32(BCM283X_GPIO_BASE + 0x0028 + 0x4 * n) /* GPIO Pin Output Clear */
|
||||
#define BCM2835_GPIO_GPLEV(n) __REG32(BCM283X_GPIO_BASE + 0x0034 + 0x4 * n) /* GPIO Pin Level */
|
||||
#define BCM283X_GPIO_GPEDS(n) __REG32(BCM283X_GPIO_BASE + 0x0040 + 0x4 * n) /* GPIO Pin Event Detect Status */
|
||||
#define BCM283X_GPIO_GPREN(n) __REG32(BCM283X_GPIO_BASE + 0x004c + 0x4 * n) /* GPIO Pin Rising Edge Detect Enable */
|
||||
#define BCM283X_GPIO_GPFEN(n) __REG32(BCM283X_GPIO_BASE + 0x0058 + 0x4 * n) /* GPIO Pin Falling Edge Detect Enable */
|
||||
#define BCM283X_GPIO_GPHEN(n) __REG32(BCM283X_GPIO_BASE + 0x0064 + 0x4 * n) /* GPIO Pin High Detect Enable */
|
||||
#define BCM283X_GPIO_GPLEN(n) __REG32(BCM283X_GPIO_BASE + 0x0070 + 0x4 * n) /* GPIO Pin Low Detect Enable */
|
||||
#define BCM283X_GPIO_GPAREN(n) __REG32(BCM283X_GPIO_BASE + 0x007C + 0x4 * n) /* GPIO Pin Async. Rising Edge Detect */
|
||||
#define BCM283X_GPIO_GPAFEN(n) __REG32(BCM283X_GPIO_BASE + 0x0088 + 0x4 * n) /* GPIO Pin Async. Falling Edge Detect */
|
||||
#define BCM283X_GPIO_GPPUD __REG32(BCM283X_GPIO_BASE + 0x0094) /* GPIO Pin Pull-up/down Enable */
|
||||
#define BCM283X_GPIO_GPPUDCLK(n) __REG32(BCM283X_GPIO_BASE + 0x0098 + 0x4 * n) /* GPIO Pin Pull-up/down Enable Clock */
|
||||
|
||||
#define GPIO_FSEL_NUM(pin) (pin/10)
|
||||
#define GPIO_FSEL_SHIFT(pin) ((pin%10)*3)
|
||||
#define GPIO_FSEL(pin, mode) \
|
||||
do{ \
|
||||
__sync_synchronize(); \
|
||||
BCM283X_GPIO_GPFSEL(GPIO_FSEL_NUM(pin)) |= ((mode & BCM283X_GPIO_FSEL_MASK) << GPIO_FSEL_SHIFT(pin)); \
|
||||
} while (0) \
|
||||
|
||||
/* Defines for I2C */
|
||||
#define BCM283X_BSC0_BASE (PER_BASE + BSC0_BASE_OFFSET) //for i2c0
|
||||
#define BCM283X_BSC1_BASE (PER_BASE + BSC1_BASE_OFFSET) //for i2c1
|
||||
#define BCM283X_BSC2_BASE (PER_BASE + BSC2_BASE_OFFSET) //for hdmi i2c not use
|
||||
|
||||
#define BCM283X_BSC_C(BASE) __REG32(BASE + 0x0000) /* BSC Master Control */
|
||||
#define BCM283X_BSC_S(BASE) __REG32(BASE + 0x0004) /* BSC Master Status */
|
||||
#define BCM283X_BSC_DLEN(BASE) __REG32(BASE + 0x0008) /* BSC Master Data Length */
|
||||
#define BCM283X_BSC_A(BASE) __REG32(BASE + 0x000c) /* BSC Master Slave Address */
|
||||
#define BCM283X_BSC_FIFO(BASE) __REG32(BASE + 0x0010) /* BSC Master Data FIFO */
|
||||
#define BCM283X_BSC_DIV(BASE) __REG32(BASE + 0x0014) /* BSC Master Clock Divider */
|
||||
#define BCM283X_BSC_DEL(BASE) __REG32(BASE + 0x0018) /* BSC Master Data Delay */
|
||||
#define BCM283X_BSC_CLKT(BASE) __REG32(BASE + 0x001c) /* BSC Master Clock Stretch Timeout */
|
||||
|
||||
/* Register masks for C Register */
|
||||
#define BSC_C_I2CEN 0x00008000 /* I2C Enable, 0 = disabled, 1 = enabled */
|
||||
#define BSC_C_INTR 0x00000400 /* Interrupt on RX */
|
||||
#define BSC_C_INTT 0x00000200 /* Interrupt on TX */
|
||||
#define BSC_C_INTD 0x00000100 /* Interrupt on DONE */
|
||||
#define BSC_C_ST 0x00000080 /* Start transfer, 1 = Start a new transfer */
|
||||
#define BSC_C_CLEAR_1 0x00000020 /* Clear FIFO Clear */
|
||||
#define BSC_C_CLEAR_2 0x00000010 /* Clear FIFO Clear */
|
||||
#define BSC_C_READ 0x00000001 /* Read transfer */
|
||||
|
||||
/* Register masks for S Register */
|
||||
#define BSC_S_CLKT 0x00000200 /* Clock stretch timeout */
|
||||
#define BSC_S_ERR 0x00000100 /* ACK error */
|
||||
#define BSC_S_RXF 0x00000080 /* RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
|
||||
#define BSC_S_TXE 0x00000040 /* TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
|
||||
#define BSC_S_RXD 0x00000020 /* RXD FIFO contains data */
|
||||
#define BSC_S_TXD 0x00000010 /* TXD FIFO can accept data */
|
||||
#define BSC_S_RXR 0x00000008 /* RXR FIFO needs reading (full) */
|
||||
#define BSC_S_TXW 0x00000004 /* TXW FIFO needs writing (full) */
|
||||
#define BSC_S_DONE 0x00000002 /* Transfer DONE */
|
||||
#define BSC_S_TA 0x00000001 /* Transfer Active */
|
||||
|
||||
#define BSC_FIFO_SIZE (16) /* BSC FIFO size */
|
||||
|
||||
/* Defines for SPI */
|
||||
#define BCM283X_SPI0_BASE (PER_BASE + SPI0_BASE_OFFSET)
|
||||
#define BCM283X_SPI1_BASE (PER_BASE + SPI1_BASE_OFFSET)
|
||||
#define BCM283X_SPI2_BASE (PER_BASE + SPI2_BASE_OFFSET)
|
||||
|
||||
#define BCM283X_SPI0_CS(BASE) __REG32(BASE + 0x0000) /* SPI Master Control and Status */
|
||||
#define BCM283X_SPI0_FIFO(BASE) __REG32(BASE + 0x0004) /* SPI Master TX and RX FIFOs */
|
||||
#define BCM283X_SPI0_CLK(BASE) __REG32(BASE + 0x0008) /* SPI Master Clock Divider */
|
||||
#define BCM283X_SPI0_DLEN(BASE) __REG32(BASE + 0x000c) /* SPI Master Data Length */
|
||||
#define BCM283X_SPI0_LTOH(BASE) __REG32(BASE + 0x0010) /* SPI LOSSI mode TOH */
|
||||
#define BCM283X_SPI0_DC(BASE) __REG32(BASE + 0x0014) /* SPI DMA DREQ Controls */
|
||||
|
||||
/* Register masks for SPI0_CS */
|
||||
#define BCM283X_SPI0_CS_LEN_LONG 0x02000000 /* Enable Long data word in Lossi mode if DMA_LEN is set */
|
||||
#define BCM283X_SPI0_CS_DMA_LEN 0x01000000 /* Enable DMA mode in Lossi mode */
|
||||
#define BCM283X_SPI0_CS_CSPOL2 0x00800000 /* Chip Select 2 Polarity */
|
||||
#define BCM283X_SPI0_CS_CSPOL1 0x00400000 /* Chip Select 1 Polarity */
|
||||
#define BCM283X_SPI0_CS_CSPOL0 0x00200000 /* Chip Select 0 Polarity */
|
||||
#define BCM283X_SPI0_CS_RXF 0x00100000 /* RXF - RX FIFO Full */
|
||||
#define BCM283X_SPI0_CS_RXR 0x00080000 /* RXR RX FIFO needs Reading (full) */
|
||||
#define BCM283X_SPI0_CS_TXD 0x00040000 /* TXD TX FIFO can accept Data */
|
||||
#define BCM283X_SPI0_CS_RXD 0x00020000 /* RXD RX FIFO contains Data */
|
||||
#define BCM283X_SPI0_CS_DONE 0x00010000 /* Done transfer Done */
|
||||
#define BCM283X_SPI0_CS_TE_EN 0x00008000 /* Unused */
|
||||
#define BCM283X_SPI0_CS_LMONO 0x00004000 /* Unused */
|
||||
#define BCM283X_SPI0_CS_LEN 0x00002000 /* LEN LoSSI enable */
|
||||
#define BCM283X_SPI0_CS_REN 0x00001000 /* REN Read Enable */
|
||||
#define BCM283X_SPI0_CS_ADCS 0x00000800 /* ADCS Automatically Deassert Chip Select */
|
||||
#define BCM283X_SPI0_CS_INTR 0x00000400 /* INTR Interrupt on RXR */
|
||||
#define BCM283X_SPI0_CS_INTD 0x00000200 /* INTD Interrupt on Done */
|
||||
#define BCM283X_SPI0_CS_DMAEN 0x00000100 /* DMAEN DMA Enable */
|
||||
#define BCM283X_SPI0_CS_TA 0x00000080 /* Transfer Active */
|
||||
#define BCM283X_SPI0_CS_CSPOL 0x00000040 /* Chip Select Polarity */
|
||||
#define BCM283X_SPI0_CS_CLEAR 0x00000030 /* Clear FIFO Clear RX and TX */
|
||||
#define BCM283X_SPI0_CS_CLEAR_RX 0x00000020 /* Clear FIFO Clear RX */
|
||||
#define BCM283X_SPI0_CS_CLEAR_TX 0x00000010 /* Clear FIFO Clear TX */
|
||||
#define BCM283X_SPI0_CS_CPOL 0x00000008 /* Clock Polarity */
|
||||
#define BCM283X_SPI0_CS_CPHA 0x00000004 /* Clock Phase */
|
||||
#define BCM283X_SPI0_CS_CS 0x00000003 /* Chip Select */
|
||||
|
||||
/* ARM Timer */
|
||||
#define ARM_TIMER_BASE (PER_BASE + 0xB000)
|
||||
#define ARM_TIMER_LOAD __REG32(ARM_TIMER_BASE + 0x400)
|
||||
#define ARM_TIMER_VALUE __REG32(ARM_TIMER_BASE + 0x404)
|
||||
#define ARM_TIMER_CTRL __REG32(ARM_TIMER_BASE + 0x408)
|
||||
#define ARM_TIMER_IRQCLR __REG32(ARM_TIMER_BASE + 0x40C)
|
||||
#define ARM_TIMER_RAWIRQ __REG32(ARM_TIMER_BASE + 0x410)
|
||||
#define ARM_TIMER_MASKIRQ __REG32(ARM_TIMER_BASE + 0x414)
|
||||
#define ARM_TIMER_RELOAD __REG32(ARM_TIMER_BASE + 0x418)
|
||||
#define ARM_TIMER_PREDIV __REG32(ARM_TIMER_BASE + 0x41C)
|
||||
#define ARM_TIMER_CNTR __REG32(ARM_TIMER_BASE + 0x420)
|
||||
|
||||
/* ARM Core Timer */
|
||||
#define C0TIMER_INTCTL __REG32(PER_BASE_40000000 + 0x40) /* Core0 timers Interrupt control */
|
||||
#define C1TIMER_INTCTL __REG32(PER_BASE_40000000 + 0x44) /* Core1 timers Interrupt control */
|
||||
#define C2TIMER_INTCTL __REG32(PER_BASE_40000000 + 0x48) /* Core2 timers Interrupt control */
|
||||
#define C3TIMER_INTCTL __REG32(PER_BASE_40000000 + 0x4C) /* Core3 timers Interrupt control */
|
||||
#define CORETIMER_INTCTL(n) __REG32(PER_BASE_40000000 + 0x40 + n*4) /* Coren timers Interrupt control */
|
||||
|
||||
/*
|
||||
* Gtimer IRQ flag
|
||||
*/
|
||||
#define SYSTEM_TIMER_IRQ_0 (1 << 0)
|
||||
#define SYSTEM_TIMER_IRQ_1 (1 << 1)
|
||||
#define SYSTEM_TIMER_IRQ_2 (1 << 2)
|
||||
#define SYSTEM_TIMER_IRQ_3 (1 << 3)
|
||||
|
||||
#define NON_SECURE_TIMER_IRQ (1 << 1)
|
||||
|
||||
/* ARM Core Mailbox interrupt */
|
||||
#define C0MB_INTCTL __REG32(PER_BASE_40000000 + 0x50) /* Core0 Mailboxes Interrupt control */
|
||||
#define C1MB_INTCTL __REG32(PER_BASE_40000000 + 0x54) /* Core1 Mailboxes Interrupt control */
|
||||
#define C2MB_INTCTL __REG32(PER_BASE_40000000 + 0x58) /* Core2 Mailboxes Interrupt control */
|
||||
#define C3MB_INTCTL __REG32(PER_BASE_40000000 + 0x5C) /* Core3 Mailboxes Interrupt control */
|
||||
#define COREMB_INTCTL(n) __REG32(PER_BASE_40000000 + 0x50 + 4*n) /* Coren Mailboxes Interrupt control */
|
||||
|
||||
/* ARM Core IRQ/FIQ status */
|
||||
#define C0_IRQSOURCE __REG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */
|
||||
#define C1_IRQSOURCE __REG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */
|
||||
#define C2_IRQSOURCE __REG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */
|
||||
#define C3_IRQSOURCE __REG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */
|
||||
#define C0_FIQSOURCE __REG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */
|
||||
#define C1_FIQSOURCE __REG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */
|
||||
#define C2_FIQSOURCE __REG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */
|
||||
#define C3_FIQSOURCE __REG32(PER_BASE_40000000 + 0x7C) /* Core3 FIQ Source */
|
||||
#define CORE_IRQSOURCE(n) __REG32(PER_BASE_40000000 + 0x60+ n*0x4)
|
||||
#define CORE_FIQSOURCE(n) __REG32(PER_BASE_40000000 + 0x70+ n*0x4)
|
||||
|
||||
#define CORE_MAILBOX3_SET(n) __REG32(PER_BASE_40000000 + 0x8C + n*0x10)
|
||||
#define CORE_MAILBOX3_CLEAR(n) __REG32(PER_BASE_40000000 + 0xCC + n*0x10)
|
||||
#define CORE_MAILBOX2_SET(n) __REG32(PER_BASE_40000000 + 0x88 + n*0x10)
|
||||
#define CORE_MAILBOX2_CLEAR(n) __REG32(PER_BASE_40000000 + 0xC8 + n*0x10)
|
||||
#define CORE_MAILBOX1_SET(n) __REG32(PER_BASE_40000000 + 0x84 + n*0x10)
|
||||
#define CORE_MAILBOX1_CLEAR(n) __REG32(PER_BASE_40000000 + 0xC4 + n*0x10)
|
||||
#define CORE_MAILBOX0_SET(n) __REG32(PER_BASE_40000000 + 0x80 + n*0x10)
|
||||
#define CORE_MAILBOX0_CLEAR(n) __REG32(PER_BASE_40000000 + 0xC0 + n*0x10)
|
||||
|
||||
/* For SMP IPI use MailBox0 */
|
||||
#define IPI_MAILBOX_SET CORE_MAILBOX0_SET
|
||||
#define IPI_MAILBOX_CLEAR CORE_MAILBOX0_CLEAR
|
||||
#define IPI_MAILBOX_INT_MASK (0x01)
|
||||
|
||||
enum spi_bit_order
|
||||
{
|
||||
BCM283X_SPI_BIT_ORDER_LSBFIRST = 0, /*!< LSB First */
|
||||
BCM283X_SPI_BIT_ORDER_MSBFIRST = 1 /*!< MSB First */
|
||||
};
|
||||
|
||||
enum spi_mode
|
||||
{
|
||||
BCM283X_SPI_MODE0 = 0, /*!< CPOL = 0, CPHA = 0 */
|
||||
BCM283X_SPI_MODE1 = 1, /*!< CPOL = 0, CPHA = 1 */
|
||||
BCM283X_SPI_MODE2 = 2, /*!< CPOL = 1, CPHA = 0 */
|
||||
BCM283X_SPI_MODE3 = 3 /*!< CPOL = 1, CPHA = 1 */
|
||||
};
|
||||
|
||||
enum spi_chip_select
|
||||
{
|
||||
BCM283X_SPI_CS0 = 0, /*!< Chip Select 0 */
|
||||
BCM283X_SPI_CS1 = 1, /*!< Chip Select 1 */
|
||||
BCM283X_SPI_CS2 = 2, /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
|
||||
BCM283X_SPI_CS_NONE = 3 /*!< No CS, control it yourself */
|
||||
};
|
||||
|
||||
enum spi_clock_divider
|
||||
{
|
||||
BCM283X_SPI_CLOCK_DIVIDER_65536 = 0, /*!< 65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_32768 = 32768, /*!< 32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_16384 = 16384, /*!< 16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_8192 = 8192, /*!< 8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_4096 = 4096, /*!< 4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_512 = 512, /*!< 512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_256 = 256, /*!< 256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_128 = 128, /*!< 128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_64 = 64, /*!< 64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_32 = 32, /*!< 32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_16 = 16, /*!< 16 = 15.625MHz on Rpi2, 25MHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_8 = 8, /*!< 8 = 31.25MHz on Rpi2, 50MHz on RPI3 */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_4 = 4, /*!< 4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably. */
|
||||
BCM283X_SPI_CLOCK_DIVIDER_2 = 2, /*!< 2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to work reliably.*/
|
||||
BCM283X_SPI_CLOCK_DIVIDER_1 = 1 /*!< 1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536 */
|
||||
};
|
||||
|
||||
/*redefine for raspi*/
|
||||
typedef gpio_function_select raspi_pin_select;
|
||||
typedef enum
|
||||
{
|
||||
RPI_GPIO_P1_01 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_02 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_03 = BCM_GPIO_PIN_2,
|
||||
RPI_GPIO_P1_04 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_05 = BCM_GPIO_PIN_3,
|
||||
RPI_GPIO_P1_06 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_07 = BCM_GPIO_PIN_4,
|
||||
RPI_GPIO_P1_08 = BCM_GPIO_PIN_14,
|
||||
RPI_GPIO_P1_09 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_10 = BCM_GPIO_PIN_15,
|
||||
RPI_GPIO_P1_11 = BCM_GPIO_PIN_17,
|
||||
RPI_GPIO_P1_12 = BCM_GPIO_PIN_18,
|
||||
RPI_GPIO_P1_13 = BCM_GPIO_PIN_27,
|
||||
RPI_GPIO_P1_14 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_15 = BCM_GPIO_PIN_22,
|
||||
RPI_GPIO_P1_16 = BCM_GPIO_PIN_23,
|
||||
RPI_GPIO_P1_17 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_18 = BCM_GPIO_PIN_24,
|
||||
RPI_GPIO_P1_19 = BCM_GPIO_PIN_10,
|
||||
RPI_GPIO_P1_20 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_21 = BCM_GPIO_PIN_9,
|
||||
RPI_GPIO_P1_22 = BCM_GPIO_PIN_25,
|
||||
RPI_GPIO_P1_23 = BCM_GPIO_PIN_11,
|
||||
RPI_GPIO_P1_24 = BCM_GPIO_PIN_8,
|
||||
RPI_GPIO_P1_25 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_26 = BCM_GPIO_PIN_7,
|
||||
RPI_GPIO_P1_27 = BCM_GPIO_PIN_0,
|
||||
RPI_GPIO_P1_28 = BCM_GPIO_PIN_1,
|
||||
RPI_GPIO_P1_29 = BCM_GPIO_PIN_5,
|
||||
RPI_GPIO_P1_30 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_31 = BCM_GPIO_PIN_6,
|
||||
RPI_GPIO_P1_32 = BCM_GPIO_PIN_12,
|
||||
RPI_GPIO_P1_33 = BCM_GPIO_PIN_13,
|
||||
RPI_GPIO_P1_34 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_35 = BCM_GPIO_PIN_19,
|
||||
RPI_GPIO_P1_36 = BCM_GPIO_PIN_16,
|
||||
RPI_GPIO_P1_37 = BCM_GPIO_PIN_26,
|
||||
RPI_GPIO_P1_38 = BCM_GPIO_PIN_20,
|
||||
RPI_GPIO_P1_39 = BCM_GPIO_PIN_NULL,
|
||||
RPI_GPIO_P1_40 = BCM_GPIO_PIN_21,
|
||||
} raspi_gpio_pin;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BCM283X_I2C_CLOCK_DIVIDER_2500 = 2500, /* 2500 = 10us = 100 kHz */
|
||||
BCM283X_I2C_CLOCK_DIVIDER_626 = 626, /* 622 = 2.504us = 399.3610 kHz */
|
||||
BCM283X_I2C_CLOCK_DIVIDER_150 = 150, /* 150 = 60ns = 1.666 MHz (default at reset) */
|
||||
BCM283X_I2C_CLOCK_DIVIDER_148 = 148 /* 148 = 59ns = 1.689 MHz */
|
||||
} i2c_clock_divider;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BCM283X_I2C_REASON_OK = 0x00, /* Success */
|
||||
BCM283X_I2C_REASON_ERROR_NACK = 0x01, /* Received a NACK */
|
||||
BCM283X_I2C_REASON_ERROR_CLKT = 0x02, /* Received Clock Stretch Timeout */
|
||||
BCM283X_I2C_REASON_ERROR_DATA = 0x04 /* Not all data is sent / received */
|
||||
} i2c_reason_codes;
|
||||
|
||||
#endif
|
||||
|
||||
@@ -101,6 +101,7 @@
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_HWTIMER
|
||||
#define RT_USING_PIN
|
||||
#define RT_USING_SDIO
|
||||
#define RT_SDIO_STACK_SIZE 2048
|
||||
@@ -193,6 +194,8 @@
|
||||
#define RT_USING_UART1
|
||||
#define BSP_USING_PIN
|
||||
#define BSP_USING_CORETIMER
|
||||
#define BSP_USING_SYSTIMER
|
||||
#define RT_USING_SYSTIMER1
|
||||
#define BSP_USING_SDIO
|
||||
#define BSP_USING_SDIO0
|
||||
|
||||
|
||||
@@ -11,7 +11,6 @@
|
||||
#ifndef __CP15_H__
|
||||
#define __CP15_H__
|
||||
|
||||
#include "bcm283x.h"
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
|
||||
#endif
|
||||
|
||||
@@ -12,12 +12,12 @@
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "cp15.h"
|
||||
#include "armv8.h"
|
||||
|
||||
#include <board.h>
|
||||
#include "interrupt.h"
|
||||
|
||||
#define MAX_HANDLERS 72
|
||||
|
||||
|
||||
@@ -14,6 +14,8 @@
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#include "raspi.h"
|
||||
|
||||
#define INT_IRQ 0x00
|
||||
#define INT_FIQ 0x01
|
||||
|
||||
|
||||
Reference in New Issue
Block a user