add raspi2 and raspi3 BSP

This commit is contained in:
bigmagic
2020-01-10 10:38:21 +08:00
parent d0098acd88
commit fdde8ab198
164 changed files with 18306 additions and 3 deletions
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mainmenu "RT-Thread Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config BCM2836_SOC
bool
select ARCH_ARM_CORTEX_A7
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
source "driver/Kconfig"
@@ -22,7 +22,7 @@ Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
# make a building
DoBuilding(TARGET, objs)

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@@ -8,13 +8,13 @@ CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../..'
RTT_ROOT = r'../../..'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
EXEC_PATH = r'/opt/gcc-arm-none-eabi-5_4-2016q3/bin'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
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# Raspberry PI 3B(32位)板级支持包说明
## 1. 简介
树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发,莓派3采用4核Broadcom BCM2837 (ARMv8)芯片、双核VideoCore IV GPU和1GB内存。
这份RT-Thread BSP是针对 Raspberry Pi 3B (32位)的一份移植,树莓派价格便宜, 使用者甚众,是研究和运行RT-Thread的可选平台之一。
随着RT-Thread的发展,它越来越多的向一些Cortex-A等AP类处理器提供支持,例如全志的ARM9、Cortex-A处理器,Xilinx的Zynq处理器等。
而RT-Thread也是一套高度社区化发展的操作系统,所以在一些方向推进上希望以社区化方式,大家一起来推动的方式向前发展,在这个过程中RT-Thread得到了不同开发者、不同领域的应用,一步步把RT-Thread推向成熟。而在Cortex-A平台上,目前最流行的硬件平台是树莓派,分树莓派[2B](https://www.raspberrypi.org/products/raspberry-pi-2-model-b/)、[3B](https://www.raspberrypi.org/products/raspberry-pi-3-model-b/)以及最新的[4B](https://www.raspberrypi.org/products/raspberry-pi-4-model-b/)等。
RT-Thread对树莓派的支持主要从树莓派2B开始,它是一个四核Cortex-A7的平台,以32位单核的模式运行。后续将推动着RT-Thread向树莓派3,四核Cortex-A53 64位模式发展(中间当然也可能出现四核Cortex-A7模式执行的过渡性版本)。
![raspi3_f](figures/raspi3_f.jpg)
![raspi3_b](figures/raspi3_b.jpg)
当前Raspberry Pi 3B对应的硬件特性:
| 硬件 | 描述 |
|------- | ------------------------------- |
| CPU | quad-core ARM Cortex A53(ARMv8) |
| 主频 | 1.2 GHz |
| GPU | VideoCore IV |
| GPU频率 | 400MHz |
| Memory | 1GB (0x0000000 - 0x40000000) |
| | 其中0x3f000000 - 0x40000000为peripheral |
硬件引脚分布情况
![GPIO-Pinout-Diagram-2](figures/GPIO-Pinout-Diagram-2.png)
## 2. 编译说明
Windows环境下推荐使用[env工具][1]进行编译。
Linux下推荐使用gcc工具 [gcc-arm-none-eabi-4_8-2014q1_linux][2],如果还没有编译工具,下载后,解开文件。
```
tar vxf gcc-arm-none-eabi-4_8-2014q1_linux.tar.bz2
```
Linux环境下需要修改编译器目录设置,修改`bsp/raspi3-32/rtconfig.py`中的
```
EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
```
为编译工具的实际所在目录,这里注意要加上后缀 `/bin`
进入到`rt-thread/bsp/raspi3-32`目录中,运行以下命令:
```
scons
```
来编译这个板级支持包。如果编译正确无误,会产生rtthread.elf、kernel7.img文件。
kernel7.img即是要cp到raspberry SD卡中根目录的文件
### 2.1 eclipse 编码环境 ###
第一步: 安装 eclipse cdt
第二步: 打开 eclipse cdt 设置workspace ,推荐设置于xxx\xxx\rt-thread\bsp
第三步: Import 工程 General-> Existing Peojects into Workspace 然后 Browse.. 你的raspi3目录,点击Finish
btw:编译依旧使用scons,目前不支持qemu debug,后期如果有大佬实现ARM JTAG调试
## 3. 执行
### 3.1 下载[raspbian镜像][3],生成可以运行的raspbian SD卡
Windows下,去[etcher.io][4]下载etcher,这是个可以烧写img的工具
解开下载的镜像文件, linux下使用如下的命令
```
unzip 2018-06-27-raspbian-stretch-lite.zip
```
准备一张空SD卡,linux环境下,插入电脑并执行
```
sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
```
**注意: /dev/xxx 要换成真实环境中的SD卡所在设置,千万不要弄错。**
Windows环境下,执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
最后把kernel7.img放入SD boot分区,覆盖原来的文件。
### 3.2 准备好串口线
目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出,连线情况如下图所示:
![raspberrypi-console](figures/raspberrypi-console.png)
串口参数: 115200 8N1 ,硬件和软件流控为关。
按上面的方法做好SD卡后,插入树莓派3B,通电可以在串口上看到如下所示的输出信息:
```text
heap: 0x0005d784 - 0x0045d784
\ | /
- RT - Thread Operating System
/ | \ 4.0.2 build Jan 9 2020
2006 - 2019 Copyright by rt-thread team
[I/I2C] I2C bus [i2c0] registered
[I/I2C] I2C bus [i2c1] registered
[I/SDIO] SD card capacity 15558144 KB.
found part[0], begin: 1048576, size: 63.0MB
found part[1], begin: 67108864, size: 14.793GB
file system initialization done!
boot cpu:3
msh />cpu = 0x00000003
cpu 3 startup.
start OK: CPU 3
boot cpu:2
cpu = 0x00000002
cpu 2 startup.
start OK: CPU 2
boot cpu:1
cpu = 0x00000001
cpu 1 startup.
start OK: CPU 1
Hello RT-Thread!
msh />
```
## 4. 支持情况
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: |
| UART | 支持 | UART0|
| GPIO | 支持 | |
| IIC | 支持 | |
| SPI | 支持 | |
| CPU Timer | 支持 | |
| SD卡驱动 | 支持 | |
## 5. 联系人信息
维护人:[bernard][5]
[1]: https://www.rt-thread.org/page/download.html
[2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2
[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
[4]: https://etcher.io
[5]: https://github.com/BernardXiong
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# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
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import os
import sys
import rtconfig
from rtconfig import RTT_ROOT
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
# make a building
DoBuilding(TARGET, objs)
@@ -0,0 +1,9 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
@@ -0,0 +1,18 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 bernard the first version
*/
#include <rtthread.h>
int main(int argc, char** argv)
{
rt_kprintf("Hello RT-Thread!\n");
return 0;
}
@@ -0,0 +1,29 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 bernard the first version
*/
#include <rtthread.h>
#ifdef BSP_USING_SDIO0
#include <dfs_fs.h>
int mnt_init(void)
{
rt_thread_delay(RT_TICK_PER_SECOND);
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("file system initialization done!\n");
}
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
*/
#ifndef __ARMV7_H__
#define __ARMV7_H__
/* the exception stack without VFP registers */
struct rt_hw_exp_stack
{
unsigned long r0;
unsigned long r1;
unsigned long r2;
unsigned long r3;
unsigned long r4;
unsigned long r5;
unsigned long r6;
unsigned long r7;
unsigned long r8;
unsigned long r9;
unsigned long r10;
unsigned long fp;
unsigned long ip;
unsigned long sp;
unsigned long lr;
unsigned long pc;
unsigned long cpsr;
};
struct rt_hw_stack
{
unsigned long cpsr;
unsigned long r0;
unsigned long r1;
unsigned long r2;
unsigned long r3;
unsigned long r4;
unsigned long r5;
unsigned long r6;
unsigned long r7;
unsigned long r8;
unsigned long r9;
unsigned long r10;
unsigned long fp;
unsigned long ip;
unsigned long lr;
unsigned long pc;
};
#define USERMODE 0x10
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define MONITORMODE 0x16
#define ABORTMODE 0x17
#define HYPMODE 0x1b
#define UNDEFMODE 0x1b
#define MODEMASK 0x1f
#define NOINT 0xc0
#define T_Bit (1<<5)
#define F_Bit (1<<6)
#define I_Bit (1<<7)
#define A_Bit (1<<8)
#define E_Bit (1<<9)
#define J_Bit (1<<24)
#endif
@@ -0,0 +1,183 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
* 2019-07-28 zdzn add smp support
*/
#include "../rtconfig.h"
.section .text, "ax"
#ifdef RT_USING_SMP
#define rt_hw_interrupt_disable rt_hw_local_irq_disable
#define rt_hw_interrupt_enable rt_hw_local_irq_enable
#endif
/*
* rt_base_t rt_hw_interrupt_disable();
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mrs r0, cpsr
cpsid i
bx lr
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
msr cpsr, r0
bx lr
/*
* void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread);
* r0 --> to (thread stack)
* r1 --> to_thread
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
ldr sp, [r0] @ get new task stack pointer
#ifdef RT_USING_SMP
mov r0, r1
bl rt_cpus_lock_status_restore
#endif /*RT_USING_SMP*/
b rt_hw_context_switch_exit
.section .bss.share.isr
_guest_switch_lvl:
.word 0
.globl vmm_virq_update
.section .text.isr, "ax"
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread);
* r0 --> from (from_thread stack)
* r1 --> to (to_thread stack)
* r2 --> to_thread
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
stmfd sp!, {r0-r12, lr} @ push lr & register file
mrs r4, cpsr
tst lr, #0x01
orrne r4, r4, #0x20 @ it's thumb code
stmfd sp!, {r4} @ push cpsr
#ifdef RT_USING_LWP
stmfd sp, {r13, r14}^ @ push usr_sp usr_lr
sub sp, #8
#endif
#ifdef RT_USING_FPU
/* fpu context */
vmrs r6, fpexc
tst r6, #(1<<30)
beq 1f
vstmdb sp!, {d0-d15}
vstmdb sp!, {d16-d31}
vmrs r5, fpscr
stmfd sp!, {r5}
1:
stmfd sp!, {r6}
#endif
str sp, [r0] @ store sp in preempted tasks TCB
ldr sp, [r1] @ get new task stack pointer
#ifdef RT_USING_SMP
mov r0, r2
bl rt_cpus_lock_status_restore
#endif /*RT_USING_SMP*/
b rt_hw_context_switch_exit
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
*/
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_UND, 0x1B
.equ Mode_SYS, 0x1F
.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
#ifdef RT_USING_SMP
/* r0 :svc_mod context
* r1 :addr of from_thread's sp
* r2 :addr of to_thread's sp
* r3 :to_thread's tcb
*/
str r0, [r1]
ldr sp, [r2]
mov r0, r3
bl rt_cpus_lock_status_restore
b rt_hw_context_switch_exit
#else /*RT_USING_SMP*/
ldr r2, =rt_thread_switch_interrupt_flag
ldr r3, [r2]
cmp r3, #1
beq _reswitch
ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1
str r0, [ip]
str r3, [r2]
_reswitch:
ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
str r1, [r2]
bx lr
#endif /*RT_USING_SMP*/
.global rt_hw_context_switch_exit
rt_hw_context_switch_exit:
#ifdef RT_USING_SMP
#ifdef RT_USING_SIGNALS
mov r0, sp
cps #Mode_IRQ
bl rt_signal_check
cps #Mode_SVC
mov sp, r0
#endif
#endif
#ifdef RT_USING_FPU
/* fpu context */
ldmfd sp!, {r6}
vmsr fpexc, r6
tst r6, #(1<<30)
beq 1f
ldmfd sp!, {r5}
vmsr fpscr, r5
vldmia sp!, {d16-d31}
vldmia sp!, {d0-d15}
#endif
#ifdef RT_USING_LWP
ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */
add sp, #8
#endif
ldmfd sp!, {r4}
msr spsr_cxsf, r4 /* original mode */
ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
*/
#include "raspi.h"
#ifndef __CP15_H__
#define __CP15_H__
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#define __WFI() __asm__ volatile ("wfi":::"memory")
#define __WFE() __asm__ volatile ("wfe":::"memory")
#define __SEV() __asm__ volatile ("sev")
__STATIC_FORCEINLINE void __ISB(void)
{
__asm__ volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__asm__ volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__asm__ volatile ("dmb 0xF":::"memory");
}
#ifdef RT_USING_SMP
static inline void send_ipi_msg(int cpu, int ipi_vector)
{
IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
}
static inline void setup_bootstrap_addr(int cpu, int addr)
{
CORE_MAILBOX3_SET(cpu) = addr;
}
static inline void enable_cpu_ipi_intr(int cpu)
{
COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
}
static inline void enable_cpu_timer_intr(int cpu)
{
CORETIMER_INTCTL(cpu) = 0x8;
}
static inline void enable_cntv(void)
{
rt_uint32_t cntv_ctl;
cntv_ctl = 1;
asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
}
static inline void disable_cntv(void)
{
rt_uint32_t cntv_ctl;
cntv_ctl = 0;
asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
}
static inline void mask_cntv(void)
{
rt_uint32_t cntv_ctl;
cntv_ctl = 2;
asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
}
static inline void unmask_cntv(void)
{
rt_uint32_t cntv_ctl;
cntv_ctl = 1;
asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl)); // write CNTV_CTL
}
static inline rt_uint64_t read_cntvct(void)
{
rt_uint32_t val,val1;
asm volatile ("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
return (val);
}
static inline rt_uint64_t read_cntvoff(void)
{
rt_uint64_t val;
asm volatile ("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
return (val);
}
static inline rt_uint32_t read_cntv_tval(void)
{
rt_uint32_t val;
asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val));
return val;
}
static inline void write_cntv_tval(rt_uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val));
return;
}
static inline rt_uint32_t read_cntfrq(void)
{
rt_uint32_t val;
asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val));
return val;
}
static inline rt_uint32_t read_cntctrl(void)
{
rt_uint32_t val;
asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val));
return val;
}
static inline uint32_t write_cntctrl(uint32_t val)
{
asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val));
return val;
}
#endif
unsigned long rt_cpu_get_smp_id(void);
void rt_cpu_mmu_disable(void);
void rt_cpu_mmu_enable(void);
void rt_cpu_tlb_set(volatile unsigned long*);
void rt_cpu_dcache_clean_flush(void);
void rt_cpu_icache_flush(void);
void rt_cpu_vector_set_base(unsigned int addr);
void rt_hw_mmu_init(void);
void rt_hw_vector_init(void);
void set_timer_counter(unsigned int counter);
void set_timer_control(unsigned int control);
#endif
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.globl rt_cpu_get_smp_id
rt_cpu_get_smp_id:
mrc p15, #0, r0, c0, c0, #5
bx lr
.globl rt_cpu_vector_set_base
rt_cpu_vector_set_base:
/* clear SCTRL.V to customize the vector address */
mrc p15, #0, r1, c1, c0, #0
bic r1, #(1 << 13)
mcr p15, #0, r1, c1, c0, #0
/* set up the vector address */
mcr p15, #0, r0, c12, c0, #0
dsb
bx lr
.globl rt_hw_cpu_dcache_enable
rt_hw_cpu_dcache_enable:
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x00000004
mcr p15, #0, r0, c1, c0, #0
bx lr
.globl rt_hw_cpu_icache_enable
rt_hw_cpu_icache_enable:
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x00001000
mcr p15, #0, r0, c1, c0, #0
bx lr
_FLD_MAX_WAY:
.word 0x3ff
_FLD_MAX_IDX:
.word 0x7ff
.globl set_timer_counter
set_timer_counter:
mcr p15, #0, r0, c14, c3, #0 @ write virtual timer timerval register
bx lr
.globl set_timer_control
set_timer_control:
mcr p15, #0, r0, c14, c3, #1 @ write virtual timer control register
bx lr
.globl rt_cpu_dcache_clean_flush
rt_cpu_dcache_clean_flush:
push {r4-r11}
dmb
mrc p15, #1, r0, c0, c0, #1 @ read clid register
ands r3, r0, #0x7000000 @ get level of coherency
mov r3, r3, lsr #23
beq finished
mov r10, #0
loop1:
add r2, r10, r10, lsr #1
mov r1, r0, lsr r2
and r1, r1, #7
cmp r1, #2
blt skip
mcr p15, #2, r10, c0, c0, #0
isb
mrc p15, #1, r1, c0, c0, #0
and r2, r1, #7
add r2, r2, #4
ldr r4, _FLD_MAX_WAY
ands r4, r4, r1, lsr #3
clz r5, r4
ldr r7, _FLD_MAX_IDX
ands r7, r7, r1, lsr #13
loop2:
mov r9, r4
loop3:
orr r11, r10, r9, lsl r5
orr r11, r11, r7, lsl r2
mcr p15, #0, r11, c7, c14, #2
subs r9, r9, #1
bge loop3
subs r7, r7, #1
bge loop2
skip:
add r10, r10, #2
cmp r3, r10
bgt loop1
finished:
dsb
isb
pop {r4-r11}
bx lr
.globl rt_cpu_icache_flush
rt_cpu_icache_flush:
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
dsb
isb
bx lr
.globl rt_hw_cpu_dcache_disable
rt_hw_cpu_dcache_disable:
push {r4-r11, lr}
bl rt_cpu_dcache_clean_flush
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #0x00000004
mcr p15, #0, r0, c1, c0, #0
pop {r4-r11, lr}
bx lr
.globl rt_hw_cpu_icache_disable
rt_hw_cpu_icache_disable:
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #0x00001000
mcr p15, #0, r0, c1, c0, #0
bx lr
.globl rt_cpu_mmu_disable
rt_cpu_mmu_disable:
mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #1
mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit
dsb
bx lr
.globl rt_cpu_mmu_enable
rt_cpu_mmu_enable:
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x001
mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit
dsb
bx lr
.globl rt_cpu_tlb_set
rt_cpu_tlb_set:
mcr p15, #0, r0, c2, c0, #0
dmb
bx lr
+91
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
* 2019-07-28 zdzn add smp support
*/
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#include "cp15.h"
int rt_hw_cpu_id(void)
{
int cpu_id;
__asm__ volatile (
"mrc p15, 0, %0, c0, c0, 5"
:"=r"(cpu_id)
);
cpu_id &= 0xf;
return cpu_id;
};
#ifdef RT_USING_SMP
void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
{
lock->slock = 0;
}
void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
{
unsigned long tmp;
unsigned long newval;
rt_hw_spinlock_t lockval;
__asm__ __volatile__(
"pld [%0]"
::"r"(&lock->slock)
);
__asm__ __volatile__(
"1: ldrex %0, [%3]\n"
" add %1, %0, %4\n"
" strex %2, %1, [%3]\n"
" teq %2, #0\n"
" bne 1b"
: "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
: "r" (&lock->slock), "I" (1 << 16)
: "cc");
while (lockval.tickets.next != lockval.tickets.owner)
{
__WFE();
lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
}
__DMB();
}
void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
{
__DMB();
lock->tickets.owner++;
__DSB();
__SEV();
}
#endif /*RT_USING_SMP*/
/**
* @addtogroup ARM CPU
*/
/*@{*/
/** shutdown CPU */
void rt_hw_cpu_shutdown()
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
while (level)
{
RT_ASSERT(0);
}
}
/*@}*/
+186
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/5/3 Bernard first version
* 2019-07-28 zdzn add smp support
* 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues,
* write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
*/
#include <rthw.h>
#include <rtthread.h>
#include "cp15.h"
#include <board.h>
#define MAX_HANDLERS 72
#ifdef RT_USING_SMP
#define rt_interrupt_nest rt_cpu_self()->irq_nest
#else
extern volatile rt_uint8_t rt_interrupt_nest;
#endif
const unsigned int VECTOR_BASE = 0x00;
extern void rt_cpu_vector_set_base(unsigned int addr);
extern int system_vectors;
void rt_hw_vector_init(void)
{
rt_cpu_vector_set_base((unsigned int)&system_vectors);
}
/* exception and interrupt handler table */
struct rt_irq_desc isr_table[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
extern int system_vectors;
static void default_isr_handler(int vector, void *param)
{
#ifdef RT_USING_SMP
rt_kprintf("cpu %d unhandled irq: %d\n", rt_hw_cpu_id(),vector);
#else
rt_kprintf("unhandled irq: %d\n",vector);
#endif
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_uint32_t index;
/* mask all of interrupts */
IRQ_DISABLE_BASIC = 0x000000ff;
IRQ_DISABLE1 = 0xffffffff;
IRQ_DISABLE2 = 0xffffffff;
for (index = 0; index < MAX_HANDLERS; index ++)
{
isr_table[index].handler = default_isr_handler;
isr_table[index].param = NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
isr_table[index].counter = 0;
#endif
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
if (vector < 32)
{
IRQ_DISABLE1 = (1 << vector);
}
else if (vector < 64)
{
vector = vector % 32;
IRQ_DISABLE2 = (1 << vector);
}
else
{
vector = vector - 64;
IRQ_DISABLE_BASIC = (1 << vector);
}
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
if (vector < 32)
{
IRQ_ENABLE1 = (1 << vector);
}
else if (vector < 64)
{
vector = vector % 32;
IRQ_ENABLE2 = (1 << vector);
}
else
{
vector = vector - 64;
IRQ_ENABLE_BASIC = (1 << vector);
}
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}
#ifdef RT_USING_SMP
void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
{
__DSB();
if (cpu_mask & 0x1)
{
send_ipi_msg(0, ipi_vector);
}
if (cpu_mask & 0x2)
{
send_ipi_msg(1, ipi_vector);
}
if (cpu_mask & 0x4)
{
send_ipi_msg(2, ipi_vector);
}
if (cpu_mask & 0x8)
{
send_ipi_msg(3, ipi_vector);
}
__DSB();
}
#endif
#ifdef RT_USING_SMP
void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
{
/* note: ipi_vector maybe different with irq_vector */
rt_hw_interrupt_install(ipi_vector, ipi_isr_handler, 0, "IPI_HANDLER");
}
#endif
@@ -0,0 +1,18 @@
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#include <rthw.h>
#include <board.h>
#define INT_IRQ 0x00
#define INT_FIQ 0x01
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
void rt_hw_interrupt_umask(int vector);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
#endif
+188
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-01-10 bernard porting to AM1808
* 2019-07-28 zdzn add smp support
*/
#include "mmu.h"
/* dump 2nd level page table */
void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
{
int i;
int fcnt = 0;
for (i = 0; i < 256; i++)
{
rt_uint32_t pte2 = ptb[i];
if ((pte2 & 0x3) == 0)
{
if (fcnt == 0)
rt_kprintf(" ");
rt_kprintf("%04x: ", i);
fcnt++;
if (fcnt == 16)
{
rt_kprintf("fault\n");
fcnt = 0;
}
continue;
}
if (fcnt != 0)
{
rt_kprintf("fault\n");
fcnt = 0;
}
rt_kprintf(" %04x: %x: ", i, pte2);
if ((pte2 & 0x3) == 0x1)
{
rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
((pte2 >> 7) | (pte2 >> 4))& 0xf,
(pte2 >> 15) & 0x1,
((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
}
else
{
rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
}
}
}
void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
{
int i;
int fcnt = 0;
rt_kprintf("page table@%p\n", ptb);
for (i = 0; i < 1024*4; i++)
{
rt_uint32_t pte1 = ptb[i];
if ((pte1 & 0x3) == 0)
{
rt_kprintf("%03x: ", i);
fcnt++;
if (fcnt == 16)
{
rt_kprintf("fault\n");
fcnt = 0;
}
continue;
}
if (fcnt != 0)
{
rt_kprintf("fault\n");
fcnt = 0;
}
rt_kprintf("%03x: %08x: ", i, pte1);
if ((pte1 & 0x3) == 0x3)
{
rt_kprintf("LPAE\n");
}
else if ((pte1 & 0x3) == 0x1)
{
rt_kprintf("pte,ns:%d,domain:%d\n",
(pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
/*
*rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
* - 0x80000000 + 0xC0000000));
*/
}
else if (pte1 & (1 << 18))
{
rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
(pte1 >> 19) & 0x1,
((pte1 >> 13) | (pte1 >> 10))& 0xf,
(pte1 >> 4) & 0x1,
((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
}
else
{
rt_kprintf("section,ns:%d,ap:%x,"
"xn:%d,texcb:%02x,domain:%d\n",
(pte1 >> 19) & 0x1,
((pte1 >> 13) | (pte1 >> 10))& 0xf,
(pte1 >> 4) & 0x1,
(((pte1 & (0x7 << 12)) >> 10) |
((pte1 & 0x0c) >> 2)) & 0x1f,
(pte1 >> 5) & 0xf);
}
}
}
/* level1 page table, each entry for 1MB memory. */
volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
rt_uint32_t vaddrEnd,
rt_uint32_t paddrStart,
rt_uint32_t attr)
{
volatile rt_uint32_t *pTT;
volatile int i, nSec;
pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
for (i = 0; i <= nSec; i++)
{
*pTT = attr | (((paddrStart >> 20) + i) << 20);
pTT++;
}
}
unsigned long rt_hw_set_domain_register(unsigned long domain_val)
{
unsigned long old_domain;
asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
return old_domain;
}
void rt_hw_init_mmu_table()
{
/* set page table */
/* 4G 1:1 memory */
rt_hw_mmu_setmtt(0x00000000, 0x3effffff, 0x00000000, NORMAL_MEM);
/* IO memory region */
rt_hw_mmu_setmtt(0x3f000000, 0x40010000, 0x3f000000, DEVICE_MEM);
}
void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
rt_uint32_t size,
rt_uint32_t paddrStart, rt_uint32_t attr)
{
rt_hw_mmu_setmtt(vaddrStart, vaddrStart+size-1, paddrStart, attr);
#ifndef RT_USING_SMP
rt_cpu_dcache_clean_flush();
rt_cpu_icache_flush();
#endif
}
void rt_hw_mmu_init(void)
{
rt_cpu_dcache_clean_flush();
rt_cpu_icache_flush();
rt_hw_cpu_dcache_disable();
rt_hw_cpu_icache_disable();
rt_cpu_mmu_disable();
/*rt_hw_cpu_dump_page_table(MMUTable);*/
rt_hw_set_domain_register(0x55555555);
rt_cpu_tlb_set(MMUTable);
rt_cpu_mmu_enable();
rt_hw_cpu_icache_enable();
rt_hw_cpu_dcache_enable();
}
+51
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@@ -0,0 +1,51 @@
#ifndef MMU_H__
#define MMU_H__
#include <rtthread.h>
#include <rthw.h>
#include <board.h>
#include "cp15.h"
#define DESC_SEC (0x2)
#define CB (3 << 2) //cache_on, write_back
#define CNB (2 << 2) //cache_on, write_through
#define NCB (1 << 2) //cache_off,WR_BUF on
#define NCNB (0 << 2) //cache_off,WR_BUF off
#define AP_RW (3 << 10) //supervisor=RW, user=RW
#define AP_RO (2 << 10) //supervisor=RW, user=RO
#define XN (1 << 4) // eXecute Never
#define SHARED (1 << 16) /* shareable */
#define SHAREDEVICE (1 << 2) /* shared device */
#define STRONGORDER (0 << 2) /* strong ordered */
#define MEMWBWA ((1 << 12) | (3 << 2)) /* write back, write allocate */
#define DOMAIN_FAULT (0x0)
#define DOMAIN_CHK (0x1)
#define DOMAIN_NOTCHK (0x3)
#define DOMAIN0 (0x0 << 5)
#define DOMAIN1 (0x1 << 5)
#define DOMAIN0_ATTR (DOMAIN_CHK << 0)
#define DOMAIN1_ATTR (DOMAIN_FAULT << 2)
/* Read/Write, cache, write back */
#define RW_CB (AP_RW | DOMAIN0 | CB | DESC_SEC)
/* Read/Write, cache, write through */
#define RW_CNB (AP_RW | DOMAIN0 | CNB | DESC_SEC)
/* Read/Write without cache and write buffer */
#define RW_NCNB (AP_RW | DOMAIN0 | NCNB | DESC_SEC)
/* Read/Write without cache and write buffer, no execute */
#define RW_NCNBXN (AP_RW | DOMAIN0 | NCNB | DESC_SEC | XN)
/* Read/Write without cache and write buffer */
#define RW_FAULT (AP_RW | DOMAIN1 | NCNB | DESC_SEC)
/* device mapping type */
#define DEVICE_MEM (SHARED | SHAREDEVICE | RW_NCNBXN)
/* normal memory mapping type */
#define NORMAL_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC)
#define STRONG_ORDER_MEM (SHARED | AP_RO | XN | DESC_SEC)
#define BUS_ADDRESS(phys) (((phys) & ~0xC0000000) | 0xC0000000)
void rt_hw_change_mmu_table(rt_uint32_t vaddrStart,
rt_uint32_t size,
rt_uint32_t paddrStart, rt_uint32_t attr);
#endif
+72
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@@ -0,0 +1,72 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-23 Bernard the first version
* 2011-10-05 Bernard add thumb mode
*/
#include <rtthread.h>
#include <board.h>
#include <armv7.h>
/**
* @addtogroup AM33xx
*/
/*@{*/
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
stack_addr += sizeof(rt_uint32_t);
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint32_t *)stack_addr;
*(--stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */
*(--stk) = 0xdeadbeef; /* r12 */
*(--stk) = 0xdeadbeef; /* r11 */
*(--stk) = 0xdeadbeef; /* r10 */
*(--stk) = 0xdeadbeef; /* r9 */
*(--stk) = 0xdeadbeef; /* r8 */
*(--stk) = 0xdeadbeef; /* r7 */
*(--stk) = 0xdeadbeef; /* r6 */
*(--stk) = 0xdeadbeef; /* r5 */
*(--stk) = 0xdeadbeef; /* r4 */
*(--stk) = 0xdeadbeef; /* r3 */
*(--stk) = 0xdeadbeef; /* r2 */
*(--stk) = 0xdeadbeef; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
/* cpsr */
if ((rt_uint32_t)tentry & 0x01)
*(--stk) = SVCMODE | 0x20; /* thumb mode */
else
*(--stk) = SVCMODE; /* arm mode */
#ifdef RT_USING_LWP
*(--stk) = 0; /* user lr */
*(--stk) = 0; /* user sp*/
#endif
#ifdef RT_USING_FPU
*(--stk) = 0; /* not use fpu*/
#endif
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,51 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.section .vectors, "ax"
.code 32
.globl system_vectors
system_vectors:
ldr pc, _vector_reset
ldr pc, _vector_undef
ldr pc, _vector_swi
ldr pc, _vector_pabt
ldr pc, _vector_dabt
ldr pc, _vector_resv
ldr pc, _vector_irq
ldr pc, _vector_fiq
.globl _reset
.globl vector_undef
.globl vector_swi
.globl vector_pabt
.globl vector_dabt
.globl vector_resv
.globl vector_irq
.globl vector_fiq
_vector_reset:
.word _reset
_vector_undef:
.word vector_undef
_vector_swi:
.word vector_swi
_vector_pabt:
.word vector_pabt
_vector_dabt:
.word vector_dabt
_vector_resv:
.word vector_resv
_vector_irq:
.word vector_irq
_vector_fiq:
.word vector_fiq
.balignl 16,0xdeadbeef
+103
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@@ -0,0 +1,103 @@
menu "Hardware Drivers Config"
menu "BCM Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Using UART"
select RT_USING_SERIAL
default y
if BSP_USING_UART
config RT_USING_UART0
bool "Enabel UART 0"
default y
config RT_USING_UART1
bool "Enabel UART 1"
default n
endif
config BSP_USING_PIN
bool "Using PIN"
select RT_USING_PIN
default y
menuconfig BSP_USING_SYSTIMER
bool "Enable SYSTIMER"
select RT_USING_HWTIMER
default n
if BSP_USING_SYSTIMER
config RT_USING_SYSTIMER1
bool "Enable sys timer1"
default n
config RT_USING_SYSTIMER3
bool "Enable sys timer3"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C"
select RT_USING_I2C
default n
if BSP_USING_I2C
config BSP_USING_I2C0
bool "Enable I2C0"
default n
config BSP_USING_I2C1
bool "Enable I2C1"
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI0_BUS
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI0_DEVICE0
bool "Enable SPI0 DEVICE0"
select BSP_USING_SPI0_BUS
default n
config BSP_USING_SPI0_DEVICE1
bool "Enable SPI0 DEVICE1"
select BSP_USING_SPI0_BUS
default n
endif
config BSP_USING_WDT
bool "Enable WDT"
select RT_USING_WDT
default n
menuconfig BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_RTC
config BSP_USING_ALARM
bool "Enable Alarm"
select RT_USING_ALARM
default n
endif
menuconfig BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
default n
if BSP_USING_SDIO
config BSP_USING_SDIO0
bool "Enable SDIO0"
select RT_USING_SDIO
default n
endif
menuconfig BSP_USING_HDMI
bool "Enable HDMI"
select BSP_USING_SPI
default n
endmenu
endmenu
@@ -0,0 +1,31 @@
# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Split('''
board.c
drv_uart.c
mbox.c
''')
CPPPATH = [cwd]
if GetDepend('BSP_USING_SYSTIMER'):
src += ['drv_timer.c']
if GetDepend('BSP_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('BSP_USING_I2C'):
src += ['drv_i2c.c']
if GetDepend('BSP_USING_WDT'):
src += ['drv_wdt.c']
if GetDepend('BSP_USING_SPI'):
src += ['drv_spi.c']
if GetDepend('BSP_USING_SDIO'):
src += ['drv_sdio.c']
if GetDepend('BSP_USING_RTC'):
src += ['drv_rtc.c']
if GetDepend('BSP_USING_HDMI'):
src += ['drv_fb.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
+182
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@@ -0,0 +1,182 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
#include "drv_timer.h"
#include "cp15.h"
#ifdef RT_USING_SMP
unsigned int cntfrq;
#endif
void rt_hw_timer_isr(int vector, void *parameter)
{
rt_tick_increase();
#ifndef RT_USING_SMP
ARM_TIMER_IRQCLR = 0;
#else
mask_cntv();
__DSB();
write_cntv_tval(cntfrq);
__DSB();
unmask_cntv();
__DSB();
#endif
}
int rt_hw_timer_init()
{
#ifndef RT_USING_SMP
/* timer_clock = apb_clock/(pre_divider + 1) */
ARM_TIMER_PREDIV = (250 - 1);
ARM_TIMER_RELOAD = 0;
ARM_TIMER_LOAD = 0;
ARM_TIMER_IRQCLR = 0;
ARM_TIMER_CTRL = 0;
ARM_TIMER_RELOAD = 10000;
ARM_TIMER_LOAD = 10000;
/* 23-bit counter, enable interrupt, enable timer */
ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
#else
__DSB();
cntfrq = 35000;
write_cntv_tval(cntfrq);
enable_cntv();
__DSB();
enable_cpu_timer_intr(rt_hw_cpu_id());
#endif
rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
rt_hw_interrupt_umask(IRQ_ARM_TIMER);
return 0;
}
#ifdef RT_USING_SMP
extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
void ipi_handler()
{
rt_scheduler_ipi_handler(0,RT_NULL);
}
#endif
void vector_copy(void)
{
rt_memcpy((void*)0x0, (void*)0x8000, 64);
}
void idle_wfi(void)
{
asm volatile ("wfi");
}
void rt_hw_board_init(void)
{
/* initialize hardware interrupt */
rt_hw_interrupt_init();
vector_copy();
rt_hw_vector_init();
/* initialize uart */
rt_hw_uart_init();
/* initialize timer for os tick */
rt_hw_timer_init();
rt_thread_idle_sethook(idle_wfi);
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif /* RT_USING_CONSOLE */
#ifdef RT_USING_HEAP
/* initialize memory system */
rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
#ifdef RT_USING_SMP
/* install IPI handle */
rt_hw_ipi_handler_install(IRQ_ARM_MAILBOX, ipi_handler);
rt_hw_interrupt_umask(IRQ_ARM_MAILBOX);
enable_cpu_ipi_intr(0);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}
void _reset(void);
void secondary_cpu_start(void);
#ifdef RT_USING_SMP
void rt_hw_secondary_cpu_up(void)
{
int i;
int retry,val;
rt_cpu_dcache_clean_flush();
rt_cpu_icache_flush();
/*TODO maybe, there is some bug */
for (i = RT_CPUS_NR - 1; i>0; i-- )
{
rt_kprintf("boot cpu:%d\n", i);
setup_bootstrap_addr(i, (int)_reset);
__SEV();
__DSB();
__ISB();
retry = 10;
rt_thread_delay(RT_TICK_PER_SECOND/1000);
do
{
val = CORE_MAILBOX3_CLEAR(i);
if (val == 0)
{
rt_kprintf("start OK: CPU %d \n",i);
break;
}
rt_thread_delay(RT_TICK_PER_SECOND);
retry --;
if (retry <= 0)
{
rt_kprintf("can't start for CPU %d \n",i);
break;
}
} while (1);
}
__DSB();
__SEV();
}
void secondary_cpu_c_start(void)
{
uint32_t id;
id = rt_hw_cpu_id();
rt_kprintf("cpu = 0x%08x\n",id);
rt_hw_timer_init();
rt_kprintf("cpu %d startup.\n",id);
rt_hw_vector_init();
enable_cpu_ipi_intr(id);
rt_hw_spin_lock(&_cpus_lock);
rt_system_scheduler_start();
}
void rt_hw_secondary_cpu_idle_exec(void)
{
__WFE();
}
#endif
+29
View File
@@ -0,0 +1,29 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <stdint.h>
#include <rthw.h>
#include "raspi.h"
#define __REG32 HWREG32
extern unsigned char __bss_start;
extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 4 * 1024 * 1024)
void rt_hw_board_init(void);
#endif
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,60 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-08-29 zdzn first version
*/
#ifndef __DRV_FB_H__
#define __DRV_FB_H__
#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
#define COLOR_BLACK RGB(0, 0, 0)
#define COLOR_GREEN RGB(0, 255, 0)
#define COLOR_CYAN RGB(0, 255, 255)
#define COLOR_RED RGB(255, 0, 0)
#define COLOR_YELLOW RGB(255, 255, 0)
#define COLOR_WHITE RGB(255, 255, 255)
#define CONSOLE_WHITE COLOR_WHITE
#define CONSOLE_BLACK COLOR_BLACK
#define CONSOLE_GREEN COLOR_GREEN
#define CONSOLE_CYAN COLOR_CYAN
#define CONSOLE_RED COLOR_RED
#define CONSOLE_YELLOW COLOR_YELLOW
typedef struct
{
rt_uint32_t width;
rt_uint32_t height;
rt_uint32_t vwidth;
rt_uint32_t vheight;
rt_uint32_t pitch;
rt_uint32_t depth;
rt_uint32_t fore;
rt_uint32_t back;
rt_uint32_t x;
rt_uint32_t y;
rt_uint32_t addr;
rt_uint32_t size;
} fb_t;
struct rt_hdmi_fb_device
{
struct rt_device parent;
fb_t fb;
};
fb_t fb_info;
void print_fb_info();
void hdmi_fb_init();
#endif/* __DRV_FB_H__ */
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "interrupt.h"
#include "board.h"
#define GPIO_IRQ_NUM 3
#define IRQ_GPIO0 49
#define IRQ_GPIO1 50
#define IRQ_GPIO2 51
#define IRQ_GPIO3 52
struct gpio_irq_def
{
void *irq_arg[32];
void (*irq_cb[32])(void *param);
rt_uint8_t irq_type[32];
};
enum gpio_irq_clock
{
GPIO_IRQ_LOSC_32KHZ = 0,
GPIO_IRQ_HOSC_24MHZ
};
int rt_hw_gpio_init(void);
#endif /* __DRV_GPIO_H__ */
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,43 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#ifndef __DRV_I2C_H__
#define __DRV_I2C_H__
#include <rtdevice.h>
#include <rtthread.h>
#include "board.h"
struct raspi_master_config_t
{
rt_uint8_t sdl_pin;
rt_uint8_t scl_pin;
rt_uint8_t sdl_pin_mode;
rt_uint8_t scl_pin_mode;
rt_uint8_t slave_address;
rt_uint32_t bsc_base;
rt_uint16_t clk_div;
};
struct raspi_i2c_bus
{
struct rt_i2c_bus_device device;
struct rt_i2c_msg *msg;
rt_uint32_t msg_cnt;
volatile rt_uint32_t msg_ptr;
volatile rt_uint32_t dptr;
char *device_name;
struct raspi_master_config_t *cfg;
};
int rt_hw_i2c_init(void);
#endif
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,21 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#ifndef __DRV_RTC_H__
#define __DRV_RTC_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
int rt_hw_rtc_init(void);
#endif
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
+102
View File
@@ -0,0 +1,102 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rtthread.h>
#include <rtdevice.h>
//#include <drivers/spi.h>
#include "board.h"
#define SPI0_BASE_ADDR (PER_BASE + BCM283X_SPI0_BASE)
static rt_uint8_t raspi_byte_reverse_table[] =
{
0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
};
#define SPI_CORE_CLK 250000000U
#define SPI_CS 0x00
#define SPI_CS_LEN_LONG (1 << 25)
#define SPI_CS_DMA_LEN (1 << 24)
#define SPI_CS_CSPOL2 (1 << 23)
#define SPI_CS_CSPOL1 (1 << 22)
#define SPI_CS_CSPOL0 (1 << 21)
#define SPI_CS_RXF (1 << 20)
#define SPI_CS_RXR (1 << 19)
#define SPI_CS_TXD (1 << 18)
#define SPI_CS_RXD (1 << 17)
#define SPI_CS_DONE (1 << 16)
#define SPI_CS_LEN (1 << 13)
#define SPI_CS_REN (1 << 12)
#define SPI_CS_ADCS (1 << 11)
#define SPI_CS_INTR (1 << 10)
#define SPI_CS_INTD (1 << 9)
#define SPI_CS_DMAEN (1 << 8)
#define SPI_CS_TA (1 << 7)
#define SPI_CS_CSPOL (1 << 6)
#define SPI_CS_CLEAR_RXFIFO (1 << 5)
#define SPI_CS_CLEAR_TXFIFO (1 << 4)
#define SPI_CS_CPOL (1 << 3)
#define SPI_CS_CPHA (1 << 2)
#define SPI_CS_MASK 0x3
#define SPI_FIFO 0x04
#define SPI_CLK 0x08
#define SPI_CLK_MASK 0xffff
#define SPI_DLEN 0x0c
#define SPI_DLEN_MASK 0xffff
#define SPI_LTOH 0x10
#define SPI_LTOH_MASK 0xf
#define SPI_DC 0x14
#define SPI_DC_RPANIC_SHIFT 24
#define SPI_DC_RPANIC_MASK (0xff << SPI_DC_RPANIC_SHIFT)
#define SPI_DC_RDREQ_SHIFT 16
#define SPI_DC_RDREQ_MASK (0xff << SPI_DC_RDREQ_SHIFT)
#define SPI_DC_TPANIC_SHIFT 8
#define SPI_DC_TPANIC_MASK (0xff << SPI_DC_TPANIC_SHIFT)
#define SPI_DC_TDREQ_SHIFT 0
#define SPI_DC_TDREQ_MASK 0xff
int rt_hw_spi_init(void);
#endif
@@ -0,0 +1,154 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#include "drv_timer.h"
#ifdef BSP_USING_SYSTIMER
static void raspi_systimer_init(rt_hwtimer_t *hwtimer, rt_uint32_t state)
{
if (state == 0)
hwtimer->ops->stop(hwtimer);
}
static rt_err_t raspi_systimer_start(rt_hwtimer_t *hwtimer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
{
rt_err_t result = RT_EOK;
rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
int timer_id = timer->timer_id;
if (mode == HWTIMER_MODE_PERIOD)
timer->cnt = cnt;
else
timer->cnt = 0;
__sync_synchronize();
if (timer_id == 1)
{
rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
STIMER_C1 = STIMER_CLO + cnt;
}
else if (timer_id == 3)
{
rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
STIMER_C3 = STIMER_CLO + cnt;
}
else
result = -RT_ERROR;
__sync_synchronize();
return result;
}
static void raspi_systimer_stop(rt_hwtimer_t *hwtimer)
{
rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
int timer_id = timer->timer_id;
if (timer_id == 1)
rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_1);
else if (timer_id == 3)
rt_hw_interrupt_mask(IRQ_SYSTEM_TIMER_3);
}
static rt_err_t raspi_systimer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
{
/* The frequency value is an immutable value. */
if (cmd == HWTIMER_CTRL_FREQ_SET)
{
return RT_EOK;
}
else
{
return -RT_ENOSYS;
}
}
void rt_device_systimer_isr(int vector, void *param)
{
rt_hwtimer_t *hwtimer = (rt_hwtimer_t *) param;
rt_systimer_t *timer = (rt_systimer_t *)hwtimer->parent.user_data;
RT_ASSERT(timer != RT_NULL);
int timer_id = timer->timer_id;
__sync_synchronize();
if (timer_id == 1)
{
STIMER_CS = 0x2;
STIMER_C1 = STIMER_CLO + timer->cnt;
}
else if (timer_id == 3)
{
STIMER_CS = 0x8;
STIMER_C3 = STIMER_CLO + timer->cnt;
}
__sync_synchronize();
rt_device_hwtimer_isr(hwtimer);
}
static struct rt_hwtimer_device _hwtimer1;
static struct rt_hwtimer_device _hwtimer3;
static rt_systimer_t _systimer1;
static rt_systimer_t _systimer3;
const static struct rt_hwtimer_ops systimer_ops =
{
raspi_systimer_init,
raspi_systimer_start,
raspi_systimer_stop,
RT_NULL,
raspi_systimer_ctrl
};
static const struct rt_hwtimer_info _info =
{
1000000, /* the maxinum count frequency can be set */
1000000, /* the maxinum count frequency can be set */
0xFFFFFFFF, /* the maximum counter value */
HWTIMER_CNTMODE_UP /* count mode (inc/dec) */
};
#endif
int rt_hw_systimer_init(void)
{
#ifdef BSP_USING_SYSTIMER
#ifdef RT_USING_SYSTIMER1
_systimer1.timer_id =1;
_hwtimer1.ops = &systimer_ops;
_hwtimer1.info = &_info;
rt_device_hwtimer_register(&_hwtimer1, "timer1",&_systimer1);
rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_1, rt_device_systimer_isr, &_hwtimer1, "systimer1");
rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_1);
#endif
#ifdef RT_USING_SYSTIMER3
_systimer3.timer_id =3;
_hwtimer3.ops = &systimer_ops;
_hwtimer3.info = &_info;
rt_device_hwtimer_register(&_hwtimer3, "timer3",&_systimer3);
rt_hw_interrupt_install(IRQ_SYSTEM_TIMER_3, rt_device_systimer_isr, &_hwtimer3, "systimer3");
rt_hw_interrupt_umask(IRQ_SYSTEM_TIMER_3);
#endif
#endif
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_systimer_init);
@@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#ifndef __DRV_TIMER_H__
#define __DRV_TIMER_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
typedef struct rt_systimer_device
{
int timer_id;
rt_uint32_t cnt;
} rt_systimer_t;
int rt_hw_systimer_init(void);
#endif
@@ -0,0 +1,183 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/5/5 Bernard The first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_uart.h"
#include <rtdevice.h>
#define AUX_BASE (0x3F000000 + 0x215000)
struct hw_uart_device
{
rt_uint32_t hw_base;
rt_uint32_t irqno;
};
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
if (uart->hw_base == AUX_BASE)
{
rt_uint32_t value;
/* GPIO function set */
value = BCM283X_GPIO_GPFSEL(1);
value &= ~(7 << 12); /* GPIO14 */
value |= 2 << 12 ; /* ALT5 */
value &= ~(7 << 15); /* GPIO15 */
value |= 2 << 15 ; /* ALT5 */
BCM283X_GPIO_GPFSEL(1) = value;
BCM283X_GPIO_GPPUD = 0;
BCM283X_GPIO_GPPUDCLK(0) = (1 << 14) | (1 << 15);
BCM283X_GPIO_GPPUDCLK(0) = 0;
AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */
AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */
AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */
AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */
AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */
AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */
AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */
}
return RT_EOK;
}
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
AUX_MU_IER_REG(uart->hw_base) = 0x0;
rt_hw_interrupt_mask(uart->irqno);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
AUX_MU_IER_REG(uart->hw_base) = 0x1;
rt_hw_interrupt_umask(uart->irqno);
break;
}
return RT_EOK;
}
static int uart_putc(struct rt_serial_device *serial, char c)
{
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
AUX_MU_IO_REG(uart->hw_base) = c;
return 1;
}
static int uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
{
ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
}
return ch;
}
static const struct rt_uart_ops _uart_ops =
{
uart_configure,
uart_control,
uart_putc,
uart_getc,
};
static void rt_hw_uart_isr(int irqno, void *param)
{
struct rt_serial_device *serial = (struct rt_serial_device*)param;
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
#ifdef RT_USING_UART0
/* UART device driver structure */
static struct hw_uart_device _uart0_device =
{
RPI_UART0_BASE,
IRQ_PBA8_UART0,
};
static struct rt_serial_device _serial0;
#endif
#ifdef RT_USING_UART1
/* UART1 device driver structure */
static struct hw_uart_device _uart1_device =
{
AUX_BASE,
IRQ_AUX,
};
static struct rt_serial_device _serial1;
#endif
int rt_hw_uart_init(void)
{
struct hw_uart_device *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef RT_USING_UART0
uart = &_uart0_device;
_serial0.ops = &_uart_ops;
_serial0.config = config;
/* register UART1 device */
rt_hw_serial_register(&_serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
#endif
#ifdef RT_USING_UART1
uart = &_uart1_device;
_serial1.ops = &_uart_ops;
_serial1.config = config;
/* register UART1 device */
rt_hw_serial_register(&_serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
/* enable Rx and Tx of UART */
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1");
#endif
return 0;
}
@@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef DRV_UART_H__
#define DRV_UART_H__
/*
* Auxiliary
*/
#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */
#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */
#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */
#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */
#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */
#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */
#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */
#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */
#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */
#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */
#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */
#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */
#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */
#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */
#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */
#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */
#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */
#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */
#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */
#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */
int rt_hw_uart_init(void);
#endif /* DRV_UART_H__ */
+117
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/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#include "drv_wdt.h"
#ifdef BSP_USING_WDT
#define SECS_TO_WDOG_TICKS(x) ((x) << 16)
#define WDOG_TICKS_TO_SECS(x) ((x) >> 16)
static struct raspi_wdt_driver bcm_wdt;
void raspi_watchdog_init(rt_uint32_t time_init)
{
bcm_wdt.timeout = time_init;
}
void raspi_watchdog_start()
{
volatile rt_uint32_t cur;
PM_WDOG = PM_PASSWORD | (SECS_TO_WDOG_TICKS(bcm_wdt.timeout) & PM_WDOG_TIME_SET);
cur = PM_RSTC;
PM_RSTC = PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
}
void raspi_watchdog_stop()
{
PM_RSTC = PM_PASSWORD | PM_RSTC_RESET;
}
void raspi_watchdog_clr()
{
bcm_wdt.timeout = 0;
}
void raspi_watchdog_set_timeout(rt_uint32_t timeout_us)
{
bcm_wdt.timeout = timeout_us;
}
rt_uint64_t raspi_watchdog_get_timeout()
{
return bcm_wdt.timeout;
}
rt_uint64_t raspi_watchdog_get_timeleft()
{
rt_uint32_t ret = PM_WDOG;
return WDOG_TICKS_TO_SECS(ret & PM_WDOG_TIME_SET);
}
static rt_err_t raspi_wdg_init(rt_watchdog_t *wdt)
{
/*init for 10S*/
raspi_watchdog_init(1000000);
raspi_watchdog_start();
raspi_watchdog_stop();
return RT_EOK;
}
static rt_err_t raspi_wdg_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
rt_uint64_t timeout_us = 0;
switch (cmd)
{
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
timeout_us = *((rt_uint32_t *)arg) * 1000000;
if (timeout_us >= 0xFFFFFFFF)
timeout_us = 0xFFFFFFFF;
raspi_watchdog_set_timeout((rt_uint32_t)timeout_us);
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
timeout_us = raspi_watchdog_get_timeout();
*((rt_uint32_t *)arg) = timeout_us / 1000000;
break;
case RT_DEVICE_CTRL_WDT_GET_TIMELEFT:
timeout_us = raspi_watchdog_get_timeleft();
*((rt_uint32_t *)arg) = timeout_us / 1000000;
break;
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
raspi_watchdog_clr();
break;
case RT_DEVICE_CTRL_WDT_START:
raspi_watchdog_start();
break;
case RT_DEVICE_CTRL_WDT_STOP:
raspi_watchdog_stop();
break;
default:
return RT_EIO;
}
return RT_EOK;
}
static const struct rt_watchdog_ops raspi_wdg_pos =
{
raspi_wdg_init,
raspi_wdg_control,
};
static rt_watchdog_t raspi_wdg;
int rt_hw_wdt_init(void)
{
raspi_wdg.ops = &raspi_wdg_pos;
rt_hw_watchdog_register(&raspi_wdg, "wdg", 0, RT_NULL);
return RT_EOK;
}
INIT_DEVICE_EXPORT(rt_hw_wdt_init);
#endif /*BSP_USING_WDT */
@@ -0,0 +1,26 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#ifndef __DRV_WDT_H__
#define __DRV_WDT_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
struct raspi_wdt_driver
{
rt_uint32_t timeout;
};
int rt_hw_wdt_init(void);
#endif
+54
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@@ -0,0 +1,54 @@
/*
* File : mbox.c
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-08-29 zdzn first version
*/
/* mailbox message buffer */
#include "mbox.h"
#include "mmu.h"
volatile unsigned int *mbox = (volatile unsigned int *) MBOX_ADDR;
/**
* Make a mailbox call. Returns 0 on failure, non-zero on success
*/
void init_mbox_mmu_map()
{
rt_hw_change_mmu_table(MBOX_ADDR, 96, MBOX_ADDR, STRONG_ORDER_MEM);
}
int mbox_call(unsigned char ch, int mmu_enable)
{
unsigned int r = (((MBOX_ADDR)&~0xF) | (ch&0xF));
if (mmu_enable)
r = BUS_ADDRESS(r);
/* wait until we can write to the mailbox */
do
{
asm volatile("nop");
} while (*MBOX_STATUS & MBOX_FULL);
/* write the address of our message to the mailbox with channel identifier */
*MBOX_WRITE = r;
/* now wait for the response */
while (1)
{
/* is there a response? */
do
{
asm volatile("nop");
}
while (*MBOX_STATUS & MBOX_EMPTY);
/* is it a response to our message? */
if (r == *MBOX_READ)
{
/* is it a valid successful response? */
return mbox[1] == MBOX_RESPONSE;
}
}
return 0;
}
+63
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@@ -0,0 +1,63 @@
/*
* File : mbox.h
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-08-29 zdzn first version
*/
#ifndef __MBOX_H__
#define __MBOX_H__
/* a properly aligned buffer */
extern volatile unsigned int* mbox;
#define MBOX_REQUEST 0
/* channels */
#define MBOX_CH_POWER 0
#define MBOX_CH_FB 1
#define MBOX_CH_VUART 2
#define MBOX_CH_VCHIQ 3
#define MBOX_CH_LEDS 4
#define MBOX_CH_BTNS 5
#define MBOX_CH_TOUCH 6
#define MBOX_CH_COUNT 7
#define MBOX_CH_PROP 8
/* tags */
#define MBOX_TAG_SETPOWER 0x28001
#define MBOX_TAG_SETCLKRATE 0x38002
#define MBOX_GET_MAC_ADDRESS 0x10003
#define MBOX_GET_CLOCK_RATE 0x30002
#define MBOX_SET_CLOCK_RATE 0x38002
#define MBOX_TAG_LAST 0
#define MMIO_BASE 0x3F000000
#define VIDEOCORE_MBOX (MMIO_BASE+0x0000B880)
#define MBOX_READ ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0))
#define MBOX_POLL ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10))
#define MBOX_SENDER ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14))
#define MBOX_STATUS ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18))
#define MBOX_CONFIG ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C))
#define MBOX_WRITE ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20))
#define MBOX_RESPONSE 0x80000000
#define MBOX_FULL 0x80000000
#define MBOX_EMPTY 0x40000000
#define DEVICE_ID_SD_CARD 0
#define DEVICE_ID_USB_HCD 3
#define POWER_STATE_OFF (0 << 0)
#define POWER_STATE_ON (1 << 0)
#define POWER_STATE_WAIT (1 << 1)
#define POWER_STATE_NO_DEVICE (1 << 1) // in response
#define MMU_ENABLE 1
#define MMU_DISABLE 0
#define MBOX_ADDR 0xc00000
int mbox_call(unsigned char ch, int mmu_enable);
#endif
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+149
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/*
* File : link.lds
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* 2017-5-30 bernard first version
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SECTIONS
{
. = 0x00008000;
. = ALIGN(4);
.text :
{
*(.vectors)
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
}
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(4);
.bss :
{
PROVIDE(__bss_start = .);
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
PROVIDE(__bss_end = .);
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
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/* DWARF 1.1 and DWARF 2 */
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/* DWARF 2 */
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.debug_varnames 0 : { *(.debug_varnames) }
}
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+52
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@@ -0,0 +1,52 @@
import os
# toolchains options
ARCH ='armv8-a'
CPU ='cortex-a53'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../../..'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
PLATFORM = 'gcc'
EXEC_PATH = r'/usr/bin'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mfloat-abi=softfp -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math'
CFLAGS = DEVICE + ' -Wall'
AFLAGS = ' -c' + ' -march=armv8-a -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n'
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+150
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@@ -0,0 +1,150 @@
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+54
View File
@@ -0,0 +1,54 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>raspi2</name>
<comment />
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
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<triggers>full,incremental,</triggers>
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<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>rt-thread</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>rt-thread/components</name>
<type>2</type>
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/components</locationURI>
</link>
<link>
<name>rt-thread/include</name>
<type>2</type>
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/include</locationURI>
</link>
<link>
<name>rt-thread/libcpu</name>
<type>2</type>
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/libcpu</locationURI>
</link>
<link>
<name>rt-thread/src</name>
<type>2</type>
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/src</locationURI>
</link>
</linkedResources>
</projectDescription>
+29
View File
@@ -0,0 +1,29 @@
mainmenu "RT-Thread Project Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config BCM2836_SOC
bool
select ARCH_ARM_CORTEX_A53
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select ARCH_CPU_64BIT
default y
source "driver/Kconfig"
+100
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@@ -0,0 +1,100 @@
# Raspberry PI 3-64板级支持包说明
## 1. 简介
树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发,莓派3有三个发行版本:
* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz,双核VideoCore IV GPU,1GB内存,100 Base-T Ethernet
* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM, GigaE over USB 2.0
* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM
这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植,树莓派价格便宜, 使用者甚众,是研究和运行RT-Thread的可选平台之一。
## 2. 编译说明
### 2.1 Window上的环境搭建
Windows环境下推荐使用[env工具][1]进行编译。
首先下载Linux上的gcc工具,版本为gcc-arm-8.3选择aarch64-elf就可以。
将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py`
修改路径:
```
EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
```
然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。
### 2.2 Linux上的环境搭建
Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
直接进入`bsp\raspberry-pi\raspi3-64`,输入scons编译即可。
## 3. 执行
### 3.1 下载[raspbian镜像][3],生成可以运行的raspbian SD卡
Windows下,去[etcher.io][4]下载etcher,这是个可以烧写img的工具
解开下载的镜像文件, linux下使用如下的命令
```
unzip 2018-06-27-raspbian-stretch-lite.zip
```
准备一张空SD卡,linux环境下,插入电脑并执行
```
sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
```
**注意: /dev/xxx 要换成真实环境中的SD卡所在设置,千万不要弄错。**
Windows环境下,执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
最后把kernel8.img放入SD boot分区,删除其它 kernel*.img。
### 3.2 准备好串口线
目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出,连线情况如下图所示(图片中的板子是pi2,GPIO引脚是一样的):
![raspi2](figures/raspi_uart.png)
串口参数: 115200 8N1 ,硬件和软件流控为关。
按上面的方法做好SD卡后,插入树莓派,通电可以在串口上看到如下所示的输出信息:
```text
heap: 0x00020b20 - 0x00400000
\ | /
- RT - Thread Operating System
/ | \ 3.1.0 build Aug 23 2019
2006 - 2019 Copyright by rt-thread team
Hello RT-Thread!
msh >
```
## 4. 支持情况
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: |
| UART | 支持 | UART0|
## 5. 联系人信息
维护人:[bernard][5]
[1]: https://www.rt-thread.org/page/download.html
[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
[4]: https://etcher.io
[5]: https://github.com/BernardXiong
+14
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@@ -0,0 +1,14 @@
# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
+30
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@@ -0,0 +1,30 @@
import os
import sys
import rtconfig
from rtconfig import RTT_ROOT
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
env['ASCOM'] = env['ASPPCOM']
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
# make a building
DoBuilding(TARGET, objs)
@@ -0,0 +1,9 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('test/*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
@@ -0,0 +1,19 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 bernard the first version
*/
#include <rtthread.h>
int main(int argc, char** argv)
{
rt_kprintf("Hi, this is RT-Thread!!\n");
return 0;
}
@@ -0,0 +1,16 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 bernard the first version
*/
#include <rtthread.h>
int mnt_init(void)
{
return 0;
}
@@ -0,0 +1,45 @@
/*
* Copyright (C) 2018 bzt (bztsrc@github)
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#define MMIO_BASE 0x3F000000
#define GPFSEL0 ((volatile unsigned int*)(MMIO_BASE+0x00200000))
#define GPFSEL1 ((volatile unsigned int*)(MMIO_BASE+0x00200004))
#define GPFSEL2 ((volatile unsigned int*)(MMIO_BASE+0x00200008))
#define GPFSEL3 ((volatile unsigned int*)(MMIO_BASE+0x0020000C))
#define GPFSEL4 ((volatile unsigned int*)(MMIO_BASE+0x00200010))
#define GPFSEL5 ((volatile unsigned int*)(MMIO_BASE+0x00200014))
#define GPSET0 ((volatile unsigned int*)(MMIO_BASE+0x0020001C))
#define GPSET1 ((volatile unsigned int*)(MMIO_BASE+0x00200020))
#define GPCLR0 ((volatile unsigned int*)(MMIO_BASE+0x00200028))
#define GPLEV0 ((volatile unsigned int*)(MMIO_BASE+0x00200034))
#define GPLEV1 ((volatile unsigned int*)(MMIO_BASE+0x00200038))
#define GPEDS0 ((volatile unsigned int*)(MMIO_BASE+0x00200040))
#define GPEDS1 ((volatile unsigned int*)(MMIO_BASE+0x00200044))
#define GPHEN0 ((volatile unsigned int*)(MMIO_BASE+0x00200064))
#define GPHEN1 ((volatile unsigned int*)(MMIO_BASE+0x00200068))
#define GPPUD ((volatile unsigned int*)(MMIO_BASE+0x00200094))
#define GPPUDCLK0 ((volatile unsigned int*)(MMIO_BASE+0x00200098))
#define GPPUDCLK1 ((volatile unsigned int*)(MMIO_BASE+0x0020009C))
@@ -0,0 +1,103 @@
/*
* Copyright (C) 2018 bzt (bztsrc@github)
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
#include "gpio.h"
/* Auxilary mini UART registers */
#define AUX_ENABLE ((volatile unsigned int*)(MMIO_BASE+0x00215004))
#define AUX_MU_IO ((volatile unsigned int*)(MMIO_BASE+0x00215040))
#define AUX_MU_IER ((volatile unsigned int*)(MMIO_BASE+0x00215044))
#define AUX_MU_IIR ((volatile unsigned int*)(MMIO_BASE+0x00215048))
#define AUX_MU_LCR ((volatile unsigned int*)(MMIO_BASE+0x0021504C))
#define AUX_MU_MCR ((volatile unsigned int*)(MMIO_BASE+0x00215050))
#define AUX_MU_LSR ((volatile unsigned int*)(MMIO_BASE+0x00215054))
#define AUX_MU_MSR ((volatile unsigned int*)(MMIO_BASE+0x00215058))
#define AUX_MU_SCRATCH ((volatile unsigned int*)(MMIO_BASE+0x0021505C))
#define AUX_MU_CNTL ((volatile unsigned int*)(MMIO_BASE+0x00215060))
#define AUX_MU_STAT ((volatile unsigned int*)(MMIO_BASE+0x00215064))
#define AUX_MU_BAUD ((volatile unsigned int*)(MMIO_BASE+0x00215068))
/**
* Set baud rate and characteristics (115200 8N1) and map to GPIO
*/
void uart_init()
{
register unsigned int r;
/* initialize UART */
*AUX_ENABLE |=1; // enable UART1, AUX mini uart
*AUX_MU_CNTL = 0;
*AUX_MU_LCR = 3; // 8 bits
*AUX_MU_MCR = 0;
*AUX_MU_IER = 0;
*AUX_MU_IIR = 0xc6; // disable interrupts
*AUX_MU_BAUD = 270; // 115200 baud
/* map UART1 to GPIO pins */
r=*GPFSEL1;
r&=~((7<<12)|(7<<15)); // gpio14, gpio15
r|=(2<<12)|(2<<15); // alt5
*GPFSEL1 = r;
*GPPUD = 0; // enable pins 14 and 15
r=150; while(r--) { asm volatile("nop"); }
*GPPUDCLK0 = (1<<14)|(1<<15);
r=150; while(r--) { asm volatile("nop"); }
*GPPUDCLK0 = 0; // flush GPIO setup
*AUX_MU_CNTL = 3; // enable Tx, Rx
}
/**
* Send a character
*/
void uart_send(unsigned int c) {
/* wait until we can send */
do{asm volatile("nop");}while(!(*AUX_MU_LSR&0x20));
/* write the character to the buffer */
*AUX_MU_IO=c;
}
/**
* Receive a character
*/
char uart_getc() {
char r;
/* wait until something is in the buffer */
do{asm volatile("nop");}while(!(*AUX_MU_LSR&0x01));
/* read it and return */
r=(char)(*AUX_MU_IO);
/* convert carrige return to newline */
return r=='\r'?'\n':r;
}
/**
* Display a string
*/
void uart_puts(char *s) {
while(*s) {
/* convert newline to carrige return + newline */
if(*s=='\n')
uart_send('\r');
uart_send(*s++);
}
}
@@ -0,0 +1,29 @@
/*
* Copyright (C) 2018 bzt (bztsrc@github)
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
*/
void uart_init();
void uart_send(unsigned int c);
char uart_getc();
void uart_puts(char *s);
+112
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@@ -0,0 +1,112 @@
config BSP_SUPPORT_FPU
bool "Using Float"
default n
menu "Hardware Drivers Config"
menu "BCM Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Using UART"
select RT_USING_SERIAL
default y
if BSP_USING_UART
config RT_USING_UART0
bool "Enabel UART 0"
default y
config RT_USING_UART1
bool "Enabel UART 1"
default n
endif
config BSP_USING_PIN
bool "Using PIN"
select RT_USING_PIN
default y
menuconfig BSP_USING_SYSTIMER
bool "Enable SYSTIMER"
select BSP_USING_SYSTIMER
default n
if BSP_USING_SYSTIMER
config RT_USING_SYSTIMER1
bool "Enable sys timer1"
default n
config RT_USING_SYSTIMER3
bool "Enable sys timer3"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C"
select RT_USING_I2C
default n
if BSP_USING_I2C
config BSP_USING_I2C0
bool "Enable I2C0"
default n
config BSP_USING_I2C1
bool "Enable I2C1"
default n
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0"
default n
config BSP_USING_SPI1
bool "Enable SPI1"
default n
endif
config BSP_USING_WDT
bool "Enable WDT"
select RT_USING_WDT
default n
menuconfig BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
if BSP_USING_RTC
config BSP_USING_ALARM
bool "Enable Alarm"
select RT_USING_ALARM
default n
endif
menuconfig BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
default n
if BSP_USING_SDIO
config BSP_USING_SDIO0
bool "Enable SDIO0"
select RT_USING_SDIO
default n
endif
endmenu
menu "Board Peripheral Drivers"
menuconfig BSP_USING_HDMI
bool "Enable HDMI"
select BSP_USING_SPI
default n
if BSP_USING_HDMI
config BSP_USING_HDMI_DISPLAY
bool "HDMI DISPLAY"
default n
endif
endmenu
endmenu
@@ -0,0 +1,32 @@
# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Split('''
board.c
bcm283x.c
drv_uart.c
mbox.c
''')
CPPPATH = [cwd]
if GetDepend('BSP_USING_SYSTIMER'):
src += ['drv_timer.c']
if GetDepend('BSP_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('BSP_USING_I2C'):
src += ['drv_i2c.c']
if GetDepend('BSP_USING_WDT'):
src += ['drv_wdt.c']
if GetDepend('BSP_USING_SPI'):
src += ['drv_spi.c']
if GetDepend('BSP_USING_SDIO'):
src += ['drv_sdio.c']
if GetDepend('BSP_USING_RTC'):
src += ['drv_rtc.c']
if GetDepend('BSP_USING_HDMI'):
src += ['drv_fb.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
File diff suppressed because it is too large Load Diff
File diff suppressed because it is too large Load Diff
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+29
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@@ -0,0 +1,29 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <stdint.h>
#include <rthw.h>
#include <bcm283x.h>
#define __REG32 HWREG32
extern unsigned char __bss_start;
extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 4 * 1024 * 1024)
void rt_hw_board_init(void);
#endif
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,60 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-08-29 zdzn first version
*/
#ifndef __DRV_FB_H__
#define __DRV_FB_H__
#define RGB(r, g, b) ((((r))<<16) | (((g))<<8) | ((b)))
#define COLOR_BLACK RGB(0, 0, 0)
#define COLOR_GREEN RGB(0, 255, 0)
#define COLOR_CYAN RGB(0, 255, 255)
#define COLOR_RED RGB(255, 0, 0)
#define COLOR_YELLOW RGB(255, 255, 0)
#define COLOR_WHITE RGB(255, 255, 255)
#define CONSOLE_WHITE COLOR_WHITE
#define CONSOLE_BLACK COLOR_BLACK
#define CONSOLE_GREEN COLOR_GREEN
#define CONSOLE_CYAN COLOR_CYAN
#define CONSOLE_RED COLOR_RED
#define CONSOLE_YELLOW COLOR_YELLOW
typedef struct
{
rt_uint32_t width;
rt_uint32_t height;
rt_uint32_t vwidth;
rt_uint32_t vheight;
rt_uint32_t pitch;
rt_uint32_t depth;
rt_uint32_t fore;
rt_uint32_t back;
rt_uint32_t x;
rt_uint32_t y;
rt_uint32_t addr;
rt_uint32_t size;
}fb_t;
struct rt_hdmi_fb_device
{
struct rt_device parent;
fb_t fb;
};
fb_t fb_info;
void print_fb_info();
void hdmi_fb_init();
#endif/* __DRV_FB_H__ */
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <rtdebug.h>
#include <rtdbg.h>
#include "interrupt.h"
#include "bcm283x.h"
#include "raspi.h"
#include "board.h"
#define GPIO_IRQ_NUM 3
struct gpio_irq_def
{
void *irq_arg[32];
void (*irq_cb[32])(void *param);
rt_uint8_t irq_type[32];
};
enum gpio_irq_clock
{
GPIO_IRQ_LOSC_32KHZ = 0,
GPIO_IRQ_HOSC_24MHZ
};
int rt_hw_gpio_init(void);
#endif /* __DRV_GPIO_H__ */
+177
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@@ -0,0 +1,177 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
*/
#include "drv_i2c.h"
#if defined (BSP_USING_I2C0)
#define I2C1BUS_NAME "i2c0"
#endif /*BSP_USING_I2C0*/
#if defined (BSP_USING_I2C1)
#define I2C2BUS_NAME "i2c1"
#endif /*BSP_USING_I2C1*/
static int i2c_byte_wait_us = 0;
#ifdef BSP_USING_I2C0
static struct raspi_i2c_bus raspi_i2c0 =
{
.device_name = I2C1BUS_NAME,
};
static struct raspi_master_config_t raspi_i2c0_cfg =
{
.sdl_pin = BCM_GPIO_PIN_0,
.scl_pin = BCM_GPIO_PIN_1,
.sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
.scl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
.slave_address = 8,
.bsc_base = (PER_BASE + BCM283X_BSC0_BASE),
.clk_div = BCM283X_I2C_CLOCK_DIVIDER_148,
};
#endif /* RT_USING_HW_I2C1 */
#ifdef BSP_USING_I2C1
static struct raspi_i2c_bus raspi_i2c1 =
{
.device_name = I2C2BUS_NAME,
};
static struct raspi_master_config_t raspi_i2c1_cfg =
{
.sdl_pin = BCM_GPIO_PIN_2,
.scl_pin = BCM_GPIO_PIN_3,
.sdl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
.scl_pin_mode = BCM283X_GPIO_FSEL_ALT0,
.slave_address = 9,
.bsc_base = (PER_BASE + BCM283X_BSC1_BASE),
.clk_div = BCM283X_I2C_CLOCK_DIVIDER_148,
};
#endif /* RT_USING_HW_I2C2 */
#if (defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1))
static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num);
static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
rt_uint32_t,
rt_uint32_t);
void i2c_master_init(struct raspi_master_config_t *cfg)
{
volatile rt_uint32_t addr;
rt_uint32_t data;
bcm283x_gpio_fsel(cfg->sdl_pin, cfg->sdl_pin_mode); /* SDA */
bcm283x_gpio_fsel(cfg->scl_pin, cfg->scl_pin_mode); /* SCL */
addr = cfg->bsc_base + BCM283X_BSC_DIV;
data = bcm283x_peri_read(addr);
i2c_byte_wait_us = ( data * 1000000 / BCM283X_CORE_CLK_HZ) * 9;
addr = cfg->bsc_base + BCM283X_BSC_DIV;
bcm283x_peri_write(addr, cfg->clk_div);
//update
i2c_byte_wait_us = (cfg->clk_div * 1000000 * 9 / BCM283X_CORE_CLK_HZ);
}
static rt_size_t raspi_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num)
{
volatile rt_uint32_t addr;
struct raspi_i2c_bus *raspi_i2c;
rt_size_t i;
RT_ASSERT(bus != RT_NULL);
raspi_i2c = (struct raspi_i2c_bus *) bus;
raspi_i2c->msg = msgs;
raspi_i2c->msg_ptr = 0;
raspi_i2c->msg_cnt = num;
raspi_i2c->dptr = 0;
addr = raspi_i2c->cfg->bsc_base + BCM283X_BSC_A;
bcm283x_peri_write(addr, msgs->addr);
for (i = 0; i < num; i++)
{
if ( raspi_i2c->msg[i].flags & RT_I2C_RD )
{
bcm283x_i2c_read(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num);
}
else
{
bcm283x_i2c_write(raspi_i2c->cfg->bsc_base, raspi_i2c->msg->buf, num);
}
}
raspi_i2c->msg = RT_NULL;
raspi_i2c->msg_ptr = 0;
raspi_i2c->msg_cnt = 0;
raspi_i2c->dptr = 0;
return i;
}
static rt_size_t raspi_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
struct rt_i2c_msg msgs[],
rt_uint32_t num)
{
return 0;
}
static rt_err_t raspi_i2c_bus_control(struct rt_i2c_bus_device *bus,
rt_uint32_t cmd,
rt_uint32_t arg)
{
return RT_ERROR;
}
static const struct rt_i2c_bus_device_ops raspi_i2c_ops =
{
.master_xfer = raspi_i2c_mst_xfer,
.slave_xfer = raspi_i2c_slv_xfer,
.i2c_bus_control = raspi_i2c_bus_control,
};
static rt_err_t raspi_i2c_configure(struct raspi_i2c_bus *bus, struct raspi_master_config_t *cfg)
{
RT_ASSERT(bus != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
bus->device.ops = &raspi_i2c_ops;
bus->cfg = cfg;
i2c_master_init(cfg);
return RT_EOK;
}
#endif
int rt_hw_i2c_init(void)
{
#if defined(BSP_USING_I2C0)
raspi_i2c_configure(&raspi_i2c0 , &raspi_i2c0_cfg);
rt_i2c_bus_device_register(&raspi_i2c0.device, raspi_i2c0.device_name);
#endif /* BSP_USING_I2C1 */
#if defined(BSP_USING_I2C1)
raspi_i2c_configure(&raspi_i2c1 , &raspi_i2c1_cfg);
rt_i2c_bus_device_register(&raspi_i2c1.device, raspi_i2c1.device_name);
#endif /* BSP_USING_I2C2 */
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_i2c_init);

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