mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-05-15 11:07:34 +08:00
[BSP] ADD ns800 BSP
This commit is contained in:
rcitach
GitHub
@@ -518,6 +518,13 @@
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"SUB_RTT_BSP": [
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"allwinner/d1s"
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]
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},
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{
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"RTT_BSP": "novosns",
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"RTT_TOOL_CHAIN": "sourcery-arm",
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"SUB_RTT_BSP": [
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"novosns/ns800/ns800rt7p65-nssinepad"
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]
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}
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]
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}
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@@ -0,0 +1,3 @@
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# NS800 BSP 说明
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NS800 系列 BSP 目前支持情况如下表所示：
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@@ -0,0 +1,13 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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import os
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cwd = GetCurrentDir()
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src = ['drv_common.c']
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path = [cwd]
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group = SConscript(os.path.join(cwd, 'drivers', 'SConscript'))
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group = group + DefineGroup('HAL_Driver', src, depend = [''], CPPPATH = path)
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Return('group')
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@@ -0,0 +1 @@
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# comment "HAL_Drivers driver-level patch options are kept minimal; peripheral configs live in board/Kconfig"
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@@ -0,0 +1,24 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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import os
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cwd = GetCurrentDir()
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src = []
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path = [cwd, cwd + '/config']
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if GetDepend(['BSP_USING_GPIO', 'RT_USING_PIN']):
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src += ['drv_gpio.c']
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if GetDepend(['BSP_USING_UART', 'RT_USING_SERIAL']):
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src += ['drv_uart.c']
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if GetDepend(['BSP_USING_CAN', 'RT_USING_CAN']):
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src += ['drv_can.c']
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if GetDepend(['BSP_USING_ECAP']):
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src += ['drv_ecap.c']
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group = DefineGroup('HAL_Drivers', src, depend = [''], CPPPATH = path)
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Return('group')
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@@ -0,0 +1,94 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-06 zylx first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
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{ \
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.Instance = ADC1, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC1_CONFIG */
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#endif /* BSP_USING_ADC1 */
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#ifdef BSP_USING_ADC2
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#ifndef ADC2_CONFIG
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#define ADC2_CONFIG \
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{ \
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.Instance = ADC2, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC2_CONFIG */
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#endif /* BSP_USING_ADC2 */
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#ifdef BSP_USING_ADC3
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#ifndef ADC3_CONFIG
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#define ADC3_CONFIG \
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{ \
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.Instance = ADC3, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC3_CONFIG */
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#endif /* BSP_USING_ADC3 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_CONFIG_H__ */
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@@ -0,0 +1,43 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-06-16 thread-liu first version
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*/
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#ifndef __DAC_CONFIG_H__
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#define __DAC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_DAC1
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#ifndef DAC1_CONFIG
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#define DAC1_CONFIG \
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{ \
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.Instance = DAC1, \
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}
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#endif /* DAC2_CONFIG */
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#endif /* BSP_USING_DAC2 */
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#ifdef BSP_USING_DAC2
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#ifndef DAC2_CONFIG
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#define DAC2_CONFIG \
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{ \
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.Instance = DAC2, \
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}
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#endif /* DAC2_CONFIG */
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#endif /* BSP_USING_DAC2 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DAC_CONFIG_H__ */
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@@ -0,0 +1,152 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-01-02 zylx first version
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* 2019-01-08 SummerGift clean up the code
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* 2020-05-02 whj4674672 support stm32h7 dma1 and dma2
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 stream0 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Stream0
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#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
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#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn
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#endif
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/* DMA1 stream1 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_TX_DMA_INSTANCE DMA1_Stream1
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#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
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#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn
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#endif
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/* DMA1 stream2 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
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#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
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#endif
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/* DMA1 stream3 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
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#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
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#endif
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/* DMA1 stream4 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
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#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
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#endif
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/* DMA1 stream5 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
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#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
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#endif
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/* DMA1 stream6 */
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/* DMA1 stream7 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
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#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
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#endif
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/* DMA2 stream0 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
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#endif
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/* DMA2 stream1 */
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#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
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#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
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#endif
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/* DMA2 stream2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
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#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#endif
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/* DMA2 stream3 */
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#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
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#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
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#endif
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/* DMA2 stream4 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
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#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
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#endif
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/* DMA2 stream5 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
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#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
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#endif
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/* DMA2 stream6 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
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#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
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#endif
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/* DMA2 stream7 */
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#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
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#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define QSPI_DMA_INSTANCE DMA2_Stream7
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#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */
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@@ -0,0 +1,259 @@
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/*
|
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* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-06 Dyyt587 first version
|
||||
* 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG
|
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* 2024-06-23 wdfk-prog Add H7 hard I2C config
|
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*/
|
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#ifndef __I2C_HARD_CONFIG_H__
|
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#define __I2C_HARD_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
|
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|
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#ifdef BSP_USING_HARD_I2C1
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#ifndef I2C1_BUS_CONFIG
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#define I2C1_BUS_CONFIG \
|
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{ \
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.Instance = I2C1, \
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.timing = 0x307075B1, \
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.timeout = 1000, \
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.name = "hwi2c1", \
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.evirq_type = I2C1_EV_IRQn, \
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.erirq_type = I2C1_ER_IRQn, \
|
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}
|
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#endif /* I2C1_BUS_CONFIG */
|
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#endif /* BSP_USING_HARD_I2C1 */
|
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|
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#ifdef BSP_I2C1_TX_USING_DMA
|
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#ifndef I2C1_TX_DMA_CONFIG
|
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#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
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#define I2C1_TX_DMA_CONFIG \
|
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{ \
|
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.dma_rcc = I2C1_TX_DMA_RCC, \
|
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.Instance = I2C1_TX_DMA_INSTANCE, \
|
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.dma_irq = I2C1_TX_DMA_IRQ, \
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.channel = I2C1_TX_DMA_CHANNEL \
|
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}
|
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#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
|
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#define I2C1_TX_DMA_CONFIG \
|
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{ \
|
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.dma_rcc = I2C1_TX_DMA_RCC, \
|
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.Instance = I2C1_TX_DMA_INSTANCE, \
|
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.dma_irq = I2C1_TX_DMA_IRQ, \
|
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.request = DMA_REQUEST_I2C1_TX \
|
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}
|
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#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
|
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#endif /* I2C1_TX_DMA_CONFIG */
|
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#endif /* BSP_I2C1_TX_USING_DMA */
|
||||
|
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#ifdef BSP_I2C1_RX_USING_DMA
|
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#ifndef I2C1_RX_DMA_CONFIG
|
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#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
#define I2C1_RX_DMA_CONFIG \
|
||||
{ \
|
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.dma_rcc = I2C1_RX_DMA_RCC, \
|
||||
.Instance = I2C1_RX_DMA_INSTANCE, \
|
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.dma_irq = I2C1_RX_DMA_IRQ, \
|
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.channel = I2C1_RX_DMA_CHANNEL, \
|
||||
}
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
|
||||
#define I2C1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C1_RX_DMA_RCC, \
|
||||
.Instance = I2C1_RX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C1_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_I2C1_RX \
|
||||
}
|
||||
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
|
||||
#endif /* I2C1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C2
|
||||
#ifndef I2C2_BUS_CONFIG
|
||||
#define I2C2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C2, \
|
||||
.timing = 0x307075B1, \
|
||||
.timeout = 1000, \
|
||||
.name = "hwi2c2", \
|
||||
.evirq_type = I2C2_EV_IRQn, \
|
||||
.erirq_type = I2C2_ER_IRQn, \
|
||||
}
|
||||
#endif /* I2C2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_HARD_I2C2 */
|
||||
|
||||
#ifdef BSP_I2C2_TX_USING_DMA
|
||||
#ifndef I2C2_TX_DMA_CONFIG
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
#define I2C2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C2_TX_DMA_RCC, \
|
||||
.Instance = I2C2_TX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C2_TX_DMA_IRQ, \
|
||||
.channel = I2C2_TX_DMA_CHANNEL, \
|
||||
}
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
|
||||
#define I2C2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C2_TX_DMA_RCC, \
|
||||
.Instance = I2C2_TX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C2_TX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_I2C2_TX \
|
||||
}
|
||||
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
|
||||
#endif /* I2C2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_I2C2_RX_USING_DMA
|
||||
#ifndef I2C2_RX_DMA_CONFIG
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
#define I2C2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C2_RX_DMA_RCC, \
|
||||
.Instance = I2C2_RX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C2_RX_DMA_IRQ, \
|
||||
.channel = I2C2_RX_DMA_CHANNEL, \
|
||||
}
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
|
||||
#define I2C2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C2_RX_DMA_RCC, \
|
||||
.Instance = I2C2_RX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C2_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_I2C2_RX \
|
||||
}
|
||||
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
|
||||
#endif /* I2C2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C2_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C3
|
||||
#ifndef I2C3_BUS_CONFIG
|
||||
#define I2C3_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C3, \
|
||||
.timing = 0x307075B1, \
|
||||
.timeout = 1000, \
|
||||
.name = "hwi2c3", \
|
||||
.evirq_type = I2C3_EV_IRQn, \
|
||||
.erirq_type = I2C3_ER_IRQn, \
|
||||
}
|
||||
#endif /* I2C3_BUS_CONFIG */
|
||||
#endif /* BSP_USING_HARD_I2C3 */
|
||||
|
||||
#ifdef BSP_I2C3_TX_USING_DMA
|
||||
#ifndef I2C3_TX_DMA_CONFIG
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
#define I2C3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C3_TX_DMA_RCC, \
|
||||
.Instance = I2C3_TX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C3_TX_DMA_IRQ, \
|
||||
.channel = I2C3_TX_DMA_CHANNEL, \
|
||||
}
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
|
||||
#define I2C3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C3_TX_DMA_RCC, \
|
||||
.Instance = I2C3_TX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C3_TX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_I2C3_TX \
|
||||
}
|
||||
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
|
||||
#endif /* I2C3_TX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C3_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_I2C3_RX_USING_DMA
|
||||
#ifndef I2C3_RX_DMA_CONFIG
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
#define I2C3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C3_RX_DMA_RCC, \
|
||||
.Instance = I2C3_RX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C3_RX_DMA_IRQ, \
|
||||
.channel = I2C3_RX_DMA_CHANNEL, \
|
||||
}
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
|
||||
#define I2C3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C3_RX_DMA_RCC, \
|
||||
.Instance = I2C3_RX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C3_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_I2C3_RX \
|
||||
}
|
||||
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
|
||||
#endif /* I2C3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C3_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_HARD_I2C4
|
||||
#ifndef I2C4_BUS_CONFIG
|
||||
#define I2C4_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C4, \
|
||||
.timing = 0x307075B1, \
|
||||
.timeout = 1000, \
|
||||
.name = "hwi2c4", \
|
||||
.evirq_type = I2C4_EV_IRQn, \
|
||||
.erirq_type = I2C4_ER_IRQn, \
|
||||
}
|
||||
#endif /* I2C4_BUS_CONFIG */
|
||||
#endif /* BSP_USING_HARD_I2C4 */
|
||||
|
||||
#ifdef BSP_I2C4_TX_USING_DMA
|
||||
#ifndef I2C4_TX_DMA_CONFIG
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
#define I2C4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C4_TX_DMA_RCC, \
|
||||
.Instance = I2C4_TX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C4_TX_DMA_IRQ, \
|
||||
.channel = I2C4_TX_DMA_CHANNEL, \
|
||||
}
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
|
||||
#define I2C4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C4_TX_DMA_RCC, \
|
||||
.Instance = I2C4_TX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C4_TX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_I2C4_TX \
|
||||
}
|
||||
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
|
||||
#endif /* I2C4_TX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C4_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_I2C4_RX_USING_DMA
|
||||
#ifndef I2C4_RX_DMA_CONFIG
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
#define I2C4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C4_RX_DMA_RCC, \
|
||||
.Instance = I2C4_RX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C4_RX_DMA_IRQ, \
|
||||
.channel = I2C4_RX_DMA_CHANNEL, \
|
||||
}
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
|
||||
#define I2C4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = I2C4_RX_DMA_RCC, \
|
||||
.Instance = I2C4_RX_DMA_INSTANCE, \
|
||||
.dma_irq = I2C4_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_I2C4_RX \
|
||||
}
|
||||
#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
|
||||
#endif /* I2C4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C4_RX_USING_DMA */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__I2C_HARD_CONFIG_H__ */
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-07-11 wdfk-prog first version
|
||||
*/
|
||||
|
||||
#ifndef __LPTIM_CONFIG_H__
|
||||
#define __LPTIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef LPTIM_DEV_INFO_CONFIG
|
||||
#define LPTIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 3000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = CLOCK_TIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* TIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_LPTIM1
|
||||
#ifndef LPTIM1_CONFIG
|
||||
#define LPTIM1_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = LPTIM1, \
|
||||
.tim_irqn = LPTIM1_IRQn, \
|
||||
.name = "lptim1", \
|
||||
}
|
||||
#endif /* LPTIM1_CONFIG */
|
||||
#endif /* BSP_USING_LPTIM1 */
|
||||
|
||||
#ifdef BSP_USING_LPTIM2
|
||||
#ifndef LPTIM2_CONFIG
|
||||
#define LPTIM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = LPTIM2, \
|
||||
.tim_irqn = LPTIM2_IRQn, \
|
||||
.name = "lptim2", \
|
||||
}
|
||||
#endif /* LPTIM1_CONFIG */
|
||||
#endif /* BSP_USING_LPTIM1 */
|
||||
|
||||
#ifdef BSP_USING_LPTIM3
|
||||
#ifndef LPTIM3_CONFIG
|
||||
#define LPTIM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = LPTIM3, \
|
||||
.tim_irqn = LPTIM3_IRQn, \
|
||||
.name = "lptim3", \
|
||||
}
|
||||
#endif /* LPTIM3_CONFIG */
|
||||
#endif /* BSP_USING_LPTIM3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPTIM_CONFIG_H__ */
|
||||
|
||||
@@ -0,0 +1,198 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 zylx first version
|
||||
* 2022-04-14 Miaowulue add PWM1
|
||||
* 2023-04-08 Wangyuqiang complete PWM defination
|
||||
*/
|
||||
|
||||
#ifndef __PWM_CONFIG_H__
|
||||
#define __PWM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM1
|
||||
#define PWM1_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM1, \
|
||||
.name = "pwm1", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM1 */
|
||||
|
||||
#ifdef BSP_USING_PWM2
|
||||
#define PWM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM2, \
|
||||
.name = "pwm2", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM2 */
|
||||
|
||||
#ifdef BSP_USING_PWM3
|
||||
#define PWM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.name = "pwm3", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM3 */
|
||||
|
||||
#ifdef BSP_USING_PWM4
|
||||
#define PWM4_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM4, \
|
||||
.name = "pwm4", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM4 */
|
||||
|
||||
#ifdef BSP_USING_PWM5
|
||||
#define PWM5_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM5, \
|
||||
.name = "pwm5", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM5 */
|
||||
|
||||
#ifdef BSP_USING_PWM6
|
||||
#define PWM6_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM6, \
|
||||
.name = "pwm6", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM6 */
|
||||
|
||||
#ifdef BSP_USING_PWM7
|
||||
#define PWM7_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM7, \
|
||||
.name = "pwm7", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM7 */
|
||||
|
||||
#ifdef BSP_USING_PWM8
|
||||
#define PWM8_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM8, \
|
||||
.name = "pwm8", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM8 */
|
||||
|
||||
#ifdef BSP_USING_PWM9
|
||||
#define PWM9_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM9, \
|
||||
.name = "pwm9", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM9 */
|
||||
|
||||
#ifdef BSP_USING_PWM10
|
||||
#define PWM10_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM10, \
|
||||
.name = "pwm10", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM10 */
|
||||
|
||||
#ifdef BSP_USING_PWM11
|
||||
#define PWM11_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM11, \
|
||||
.name = "pwm11", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM11 */
|
||||
|
||||
#ifdef BSP_USING_PWM12
|
||||
#define PWM12_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM12, \
|
||||
.name = "pwm12", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM12 */
|
||||
|
||||
#ifdef BSP_USING_PWM13
|
||||
#define PWM13_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM13, \
|
||||
.name = "pwm13", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM13 */
|
||||
|
||||
#ifdef BSP_USING_PWM14
|
||||
#define PWM14_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM14, \
|
||||
.name = "pwm14", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM14 */
|
||||
|
||||
#ifdef BSP_USING_PWM15
|
||||
#define PWM15_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM15, \
|
||||
.name = "pwm15", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM15 */
|
||||
|
||||
#ifdef BSP_USING_PWM16
|
||||
#define PWM16_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM16, \
|
||||
.name = "pwm16", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM16 */
|
||||
|
||||
#ifdef BSP_USING_PWM17
|
||||
#define PWM17_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM17, \
|
||||
.name = "pwm17", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM17 */
|
||||
|
||||
#ifdef BSP_USING_PWM18
|
||||
#define PWM18_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM18, \
|
||||
.name = "pwm18", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM18 */
|
||||
|
||||
#ifdef BSP_USING_PWM19
|
||||
#define PWM19_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM19, \
|
||||
.name = "pwm19", \
|
||||
.channel = RT_NULL \
|
||||
}
|
||||
#endif /* BSP_USING_PWM19 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PWM_CONFIG_H__ */
|
||||
|
||||
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-22 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __QSPI_CONFIG_H__
|
||||
#define __QSPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_QSPI
|
||||
#ifndef QSPI_BUS_CONFIG
|
||||
#define QSPI_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = QUADSPI, \
|
||||
.Init.FifoThreshold = 4, \
|
||||
.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
|
||||
.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \
|
||||
}
|
||||
#endif /* QSPI_BUS_CONFIG */
|
||||
#endif /* BSP_USING_QSPI */
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
#ifndef QSPI_DMA_CONFIG
|
||||
#define QSPI_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = QSPI_DMA_INSTANCE, \
|
||||
.Init.Channel = QSPI_DMA_CHANNEL, \
|
||||
.Init.Direction = DMA_PERIPH_TO_MEMORY, \
|
||||
.Init.PeriphInc = DMA_PINC_DISABLE, \
|
||||
.Init.MemInc = DMA_MINC_ENABLE, \
|
||||
.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
|
||||
.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \
|
||||
.Init.Mode = DMA_NORMAL, \
|
||||
.Init.Priority = DMA_PRIORITY_LOW \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
|
||||
#define QSPI_IRQn QUADSPI_IRQn
|
||||
#define QSPI_IRQHandler QUADSPI_IRQHandler
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __QSPI_CONFIG_H__ */
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 BalanceTWK first version
|
||||
*/
|
||||
|
||||
#ifndef __SDIO_CONFIG_H__
|
||||
#define __SDIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
/* #include "stm32h7xx_hal.h" */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
#define SDIO_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SDMMC1, \
|
||||
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
|
||||
.dma_rx.Instance = DMA2_Stream3, \
|
||||
.dma_rx.channel = DMA_CHANNEL_4, \
|
||||
.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
|
||||
.dma_tx.Instance = DMA2_Stream6, \
|
||||
.dma_tx.channel = DMA_CHANNEL_4, \
|
||||
.dma_tx.dma_irq = DMA2_Stream6_IRQn, \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SDIO_CONFIG_H__ */
|
||||
|
||||
@@ -0,0 +1,200 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
.irq_type = SPI1_IRQn, \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_TX_DMA_RCC, \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI1_TX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI1_TX \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_RX_DMA_RCC, \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI1_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI1_RX \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
#ifndef SPI2_BUS_CONFIG
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
.irq_type = SPI2_IRQn, \
|
||||
}
|
||||
#endif /* SPI2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI2 */
|
||||
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
#ifndef SPI2_TX_DMA_CONFIG
|
||||
#define SPI2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_TX_DMA_RCC, \
|
||||
.Instance = SPI2_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI2_TX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI2_TX \
|
||||
}
|
||||
#endif /* SPI2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
#ifndef SPI2_RX_DMA_CONFIG
|
||||
#define SPI2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_RX_DMA_RCC, \
|
||||
.Instance = SPI2_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI2_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI2_RX \
|
||||
}
|
||||
#endif /* SPI2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
#ifndef SPI3_BUS_CONFIG
|
||||
#define SPI3_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3, \
|
||||
.bus_name = "spi3", \
|
||||
.irq_type = SPI3_IRQn, \
|
||||
}
|
||||
#endif /* SPI3_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI3 */
|
||||
|
||||
#ifdef BSP_SPI3_TX_USING_DMA
|
||||
#ifndef SPI3_TX_DMA_CONFIG
|
||||
#define SPI3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_TX_DMA_RCC, \
|
||||
.Instance = SPI3_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI3_TX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI3_TX \
|
||||
}
|
||||
#endif /* SPI3_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI3_RX_USING_DMA
|
||||
#ifndef SPI3_RX_DMA_CONFIG
|
||||
#define SPI3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_RX_DMA_RCC, \
|
||||
.Instance = SPI3_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI3_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI3_RX \
|
||||
}
|
||||
#endif /* SPI3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI4
|
||||
#ifndef SPI4_BUS_CONFIG
|
||||
#define SPI4_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI4, \
|
||||
.bus_name = "spi4", \
|
||||
.irq_type = SPI4_IRQn, \
|
||||
}
|
||||
#endif /* SPI4_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI4 */
|
||||
|
||||
#ifdef BSP_SPI4_TX_USING_DMA
|
||||
#ifndef SPI4_TX_DMA_CONFIG
|
||||
#define SPI4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI4_TX_DMA_RCC, \
|
||||
.Instance = SPI4_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI4_TX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI4_TX \
|
||||
}
|
||||
#endif /* SPI4_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI4_RX_USING_DMA
|
||||
#ifndef SPI4_RX_DMA_CONFIG
|
||||
#define SPI4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI4_RX_DMA_RCC, \
|
||||
.Instance = SPI4_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI4_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI4_RX \
|
||||
}
|
||||
#endif /* SPI4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI5
|
||||
#ifndef SPI5_BUS_CONFIG
|
||||
#define SPI5_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5, \
|
||||
.bus_name = "spi5", \
|
||||
.irq_type = SPI5_IRQn, \
|
||||
}
|
||||
#endif /* SPI5_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI5 */
|
||||
|
||||
#ifdef BSP_SPI5_TX_USING_DMA
|
||||
#ifndef SPI5_TX_DMA_CONFIG
|
||||
#define SPI5_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI5_TX_DMA_RCC, \
|
||||
.Instance = SPI5_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI5_TX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI5_TX \
|
||||
}
|
||||
#endif /* SPI5_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI5_RX_USING_DMA
|
||||
#ifndef SPI5_RX_DMA_CONFIG
|
||||
#define SPI5_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI5_RX_DMA_RCC, \
|
||||
.Instance = SPI5_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI5_RX_DMA_IRQ, \
|
||||
.request = DMA_REQUEST_SPI5_RX \
|
||||
}
|
||||
#endif /* SPI5_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-11 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __TIM_CONFIG_H__
|
||||
#define __TIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef TIM_DEV_INFO_CONFIG
|
||||
#define TIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 3000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = CLOCK_TIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* TIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_TIM11
|
||||
#ifndef TIM11_CONFIG
|
||||
#define TIM11_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM11, \
|
||||
.tim_irqn = TIM1_TRG_COM_TIM11_IRQn, \
|
||||
.name = "timer11", \
|
||||
}
|
||||
#endif /* TIM11_CONFIG */
|
||||
#endif /* BSP_USING_TIM11 */
|
||||
|
||||
#ifdef BSP_USING_TIM13
|
||||
#ifndef TIM13_CONFIG
|
||||
#define TIM13_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM13, \
|
||||
.tim_irqn = TIM8_UP_TIM13_IRQn, \
|
||||
.name = "timer13", \
|
||||
}
|
||||
#endif /* TIM13_CONFIG */
|
||||
#endif /* BSP_USING_TIM13 */
|
||||
|
||||
#ifdef BSP_USING_TIM14
|
||||
#ifndef TIM14_CONFIG
|
||||
#define TIM14_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM14, \
|
||||
.tim_irqn = TIM8_TRG_COM_TIM14_IRQn, \
|
||||
.name = "timer14", \
|
||||
}
|
||||
#endif /* TIM14_CONFIG */
|
||||
#endif /* BSP_USING_TIM14 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TIM_CONFIG_H__ */
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = UART1, \
|
||||
.rx_irq_type = UART1_RX_IRQn, \
|
||||
.tx_irq_type = UART1_TX_IRQn, \
|
||||
.irq_handler = UART1_IRQHandler, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = UART2, \
|
||||
.rx_irq_type = UART2_RX_IRQn, \
|
||||
.tx_irq_type = UART2_TX_IRQn, \
|
||||
.irq_handler = UART2_IRQHandler, \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = UART3, \
|
||||
.rx_irq_type = UART3_RX_IRQn, \
|
||||
.tx_irq_type = UART3_TX_IRQn, \
|
||||
.irq_handler = UART3_IRQHandler, \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#ifndef UART4_CONFIG
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = UART4, \
|
||||
.rx_irq_type = UART4_RX_IRQn, \
|
||||
.tx_irq_type = UART4_TX_IRQn, \
|
||||
.irq_handler = UART4_IRQHandler, \
|
||||
}
|
||||
#endif /* UART4_CONFIG */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-08-05 Xeon Xu the first version
|
||||
* 2019-01-22 YLZ port from stm324xx-HAL to bsp stm3210x-HAL
|
||||
* 2019-01-26 YLZ redefine `struct stm32_drv_can` add member `Rx1Message`
|
||||
* 2019-02-19 YLZ port to BSP [stm32]
|
||||
* 2019-06-17 YLZ modify struct stm32_drv_can.
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CAN_H__
|
||||
#define __DRV_CAN_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <board.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define CAN_FILTER_NUM_MAX (16U)
|
||||
|
||||
enum _can_state
|
||||
{
|
||||
StateIdle = 0x0, /*!< MB idle.*/
|
||||
StateRxData = 0x1, /*!< MB receiving.*/
|
||||
StateRxRemote = 0x2, /*!< MB receiving remote reply.*/
|
||||
StateTxData = 0x3, /*!< MB transmitting.*/
|
||||
StateTxRemote = 0x4, /*!< MB transmitting remote request.*/
|
||||
};
|
||||
|
||||
struct ns800rt7_baud_rate_tab
|
||||
{
|
||||
rt_uint32_t baud_rate;
|
||||
rt_uint32_t config_data;
|
||||
};
|
||||
#define BAUD_DATA(NO) (can_baud_rate_tab[NO].config_data)
|
||||
|
||||
|
||||
/* stm32 can device */
|
||||
typedef struct
|
||||
{
|
||||
char *name;
|
||||
FLEXCANDRV_ControllerCfgType CanCfg;
|
||||
IRQn_Type irqn1;
|
||||
IRQn_Type irqn2;
|
||||
FLEXCANDRV_Type CanHandle;
|
||||
FLEXCANDRV_MsgCfgType FilterConfig[CAN_FILTER_NUM_MAX];
|
||||
uint8_t FilterNum;
|
||||
volatile uint8_t mbState[128];
|
||||
struct rt_can_device device; /* inherit from can device */
|
||||
} ns800rt7_can;
|
||||
|
||||
int rt_hw_can_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__DRV_CAN_H__ */
|
||||
|
||||
/************************** end of file ******************/
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(SOC_SERIES_NS800RT7)
|
||||
#include "rt7/uart_config.h"
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-10 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_DMA_H_
|
||||
#define __DRV_DMA_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct dma_config {
|
||||
EDMA_TypeDef *Instance;
|
||||
rt_uint32_t dma_rcc;
|
||||
IRQn_Type dma_irq;
|
||||
rt_uint32_t request;
|
||||
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__DRV_DMA_H_ */
|
||||
|
||||
@@ -0,0 +1,479 @@
|
||||
/**************************************************************************//**
|
||||
*
|
||||
* @copyright (C) 2026 Novosense Technology Corp. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-5-7 Alex-J First version
|
||||
*
|
||||
******************************************************************************/
|
||||
#include <rtconfig.h>
|
||||
#include "drv_ecap.h"
|
||||
|
||||
#if defined(BSP_USING_ECAP)
|
||||
|
||||
#define DBG_TAG "drv.ecap"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
static const struct rt_ecap_config ecap1_config =
|
||||
{
|
||||
.name = "ecap1",
|
||||
.instance = ECAP1,
|
||||
.irq_type = ECAP1_IRQn,
|
||||
.input_xbar = XBAR_INPUT7,
|
||||
.input_source = GPIO_PIN_16,
|
||||
.gpio_port = GPIOA,
|
||||
.gpio_pin = GPIO_PIN_16,
|
||||
.gpio_mux = ALT0_FUNCTION,
|
||||
};
|
||||
|
||||
static struct rt_ecap_device ecap1_dev;
|
||||
|
||||
void ECAP1_IRQHandler (void);
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
static void ecap_gpio_init (const struct rt_ecap_config *config)
|
||||
{
|
||||
RT_ASSERT(config != RT_NULL);
|
||||
|
||||
GPIO_setPinConfig(config->gpio_port, config->gpio_pin, config->gpio_mux);
|
||||
GPIO_setAnalogMode(config->gpio_port, config->gpio_pin, GPIO_ANALOG_DISABLED);
|
||||
GPIO_setPadConfig(config->gpio_port, config->gpio_pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setQualificationMode(config->gpio_port, config->gpio_pin, GPIO_QUAL_SYNC);
|
||||
GPIO_setDirectionMode(config->gpio_port, config->gpio_pin, GPIO_DIR_MODE_IN);
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
static void ecap_xbar_init (const struct rt_ecap_config *config)
|
||||
{
|
||||
RT_ASSERT(config != RT_NULL);
|
||||
|
||||
XBAR_setInputPin(XBAR, config->input_xbar, config->input_source);
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
static void ecap_hw_init (const struct rt_ecap_config *config)
|
||||
{
|
||||
RT_ASSERT(config != RT_NULL);
|
||||
|
||||
/*
|
||||
* Disable and clear all capture flags and interrupts.
|
||||
*/
|
||||
ECAP_disableInterrupt(config->instance, ECAP_ECEINT_CEVT1_M | ECAP_ECEINT_CEVT2_M | ECAP_ECEINT_CEVT3_M |
|
||||
ECAP_ECEINT_CEVT4_M | ECAP_ECEINT_CTROVF_M | ECAP_ECEINT_CTREQPRD_M |
|
||||
ECAP_ECEINT_CTREQCMP_M);
|
||||
|
||||
ECAP_clearInterrupt(config->instance, ECAP_ECCLR_CEVT1_M | ECAP_ECCLR_CEVT2_M | ECAP_ECCLR_CEVT3_M |
|
||||
ECAP_ECCLR_CEVT4_M | ECAP_ECCLR_CTROVF_M | ECAP_ECCLR_CTRPRD_M |
|
||||
ECAP_ECCLR_CTRCMP_M);
|
||||
|
||||
ECAP_disableTimeStampCapture(config->instance);
|
||||
ECAP_stopCounter(config->instance);
|
||||
|
||||
/*
|
||||
* Capture mode:
|
||||
* Event1 falling
|
||||
* Event2 rising
|
||||
* Event3 falling
|
||||
* Event4 rising
|
||||
*/
|
||||
ECAP_enableCaptureMode(config->instance);
|
||||
ECAP_setCaptureMode(config->instance, ECAP_CONTINUOUS_CAPTURE_MODE, ECAP_EVENT_4);
|
||||
ECAP_setEventPrescaler(config->instance, 0U);
|
||||
|
||||
ECAP_setEventPolarity(config->instance, ECAP_EVENT_1, ECAP_EVNT_FALLING_EDGE);
|
||||
ECAP_setEventPolarity(config->instance, ECAP_EVENT_2, ECAP_EVNT_RISING_EDGE);
|
||||
ECAP_setEventPolarity(config->instance, ECAP_EVENT_3, ECAP_EVNT_FALLING_EDGE);
|
||||
ECAP_setEventPolarity(config->instance, ECAP_EVENT_4, ECAP_EVNT_RISING_EDGE);
|
||||
|
||||
ECAP_enableCounterResetOnEvent(config->instance, ECAP_EVENT_1);
|
||||
ECAP_enableCounterResetOnEvent(config->instance, ECAP_EVENT_2);
|
||||
ECAP_enableCounterResetOnEvent(config->instance, ECAP_EVENT_3);
|
||||
ECAP_enableCounterResetOnEvent(config->instance, ECAP_EVENT_4);
|
||||
|
||||
ECAP_selectECAPInput(config->instance, ECAP_INPUT_XBAR_INPUT7);
|
||||
|
||||
ECAP_setPhaseShiftCount(config->instance, 0U);
|
||||
ECAP_enableLoadCounter(config->instance);
|
||||
|
||||
ECAP_setSyncOutMode(config->instance, ECAP_SYNC_OUT_SYNCI);
|
||||
ECAP_setEmulationMode(config->instance, ECAP_EMULATION_STOP);
|
||||
ECAP_setSyncInPulseSource(config->instance, ECAP_SYNC_IN_PULSE_SRC_DISABLE);
|
||||
|
||||
/* ECAP_startCounter(config->instance); */
|
||||
/* ECAP_enableTimeStampCapture(config->instance); */
|
||||
/* ECAP_reArm(config->instance); */
|
||||
|
||||
/*
|
||||
* 当前配置是 Event4 完成后产生中断。
|
||||
*/
|
||||
/* ECAP_enableInterrupt(config->instance, ECAP_ECEINT_CEVT4_M); */
|
||||
}
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
static void ecap_hw_deinit (const struct rt_ecap_config *config)
|
||||
{
|
||||
RT_ASSERT(config != RT_NULL);
|
||||
|
||||
ECAP_disableInterrupt(config->instance, ECAP_ECEINT_CEVT1_M | ECAP_ECEINT_CEVT2_M | ECAP_ECEINT_CEVT3_M |
|
||||
ECAP_ECEINT_CEVT4_M | ECAP_ECEINT_CTROVF_M | ECAP_ECEINT_CTREQPRD_M |
|
||||
ECAP_ECEINT_CTREQCMP_M);
|
||||
|
||||
ECAP_disableTimeStampCapture(config->instance);
|
||||
ECAP_stopCounter(config->instance);
|
||||
}
|
||||
|
||||
static void ecap_hw_clear_flags (const struct rt_ecap_config *config)
|
||||
{
|
||||
RT_ASSERT(config != RT_NULL);
|
||||
|
||||
ECAP_clearInterrupt(config->instance, ECAP_ECCLR_CEVT1_M | ECAP_ECCLR_CEVT2_M | ECAP_ECCLR_CEVT3_M |
|
||||
ECAP_ECCLR_CEVT4_M | ECAP_ECCLR_CTROVF_M | ECAP_ECCLR_CTRPRD_M |
|
||||
ECAP_ECCLR_CTRCMP_M);
|
||||
ECAP_clearGlobalInterrupt(config->instance);
|
||||
}
|
||||
|
||||
static void ecap_hw_rearm (const struct rt_ecap_config *config)
|
||||
{
|
||||
RT_ASSERT(config != RT_NULL);
|
||||
|
||||
ecap_hw_clear_flags(config);
|
||||
ECAP_reArm(config->instance);
|
||||
}
|
||||
|
||||
static void ecap_calc_capture (struct rt_ecap_capture *cap)
|
||||
{
|
||||
RT_ASSERT(cap != RT_NULL);
|
||||
|
||||
/*
|
||||
* 由于当前配置为：
|
||||
* Event1 falling
|
||||
* Event2 rising
|
||||
* Event3 falling
|
||||
* Event4 rising
|
||||
*
|
||||
* 且每个 event 都 reset counter。
|
||||
*
|
||||
* 所以 cap1~cap4 并不是一个自由运行时间轴上的绝对时间戳，
|
||||
* 而是每段边沿之间的间隔计数。
|
||||
*
|
||||
* 这里给一个通用解释：
|
||||
* cap2: falling -> rising
|
||||
* cap3: rising -> falling
|
||||
* cap4: falling -> rising
|
||||
*
|
||||
* 对 PWM 输入来说，需要根据实际输入波形起始边沿判断高低电平。
|
||||
*/
|
||||
cap->period_high = cap->cap2;
|
||||
cap->period_low = cap->cap3;
|
||||
cap->period_total = cap->cap2 + cap->cap3;
|
||||
}
|
||||
|
||||
static rt_err_t rt_ecap_init (rt_device_t dev)
|
||||
{
|
||||
struct rt_ecap_device *ecap;
|
||||
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
|
||||
ecap = (struct rt_ecap_device *)dev;
|
||||
|
||||
ecap_gpio_init(ecap->config);
|
||||
ecap_xbar_init(ecap->config);
|
||||
ecap_hw_init(ecap->config);
|
||||
|
||||
ecap->last_capture.status = ECAP_STATUS_IDLE;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_ecap_open (rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
struct rt_ecap_device *ecap;
|
||||
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
|
||||
ecap = (struct rt_ecap_device *)dev;
|
||||
|
||||
rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER);
|
||||
|
||||
if (ecap->opened == 0U)
|
||||
{
|
||||
ecap_hw_clear_flags(ecap->config);
|
||||
ECAP_startCounter(ecap->config->instance);
|
||||
ECAP_enableTimeStampCapture(ecap->config->instance);
|
||||
ECAP_reArm(ecap->config->instance);
|
||||
ECAP_enableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M);
|
||||
|
||||
Interrupt_register(ecap->config->irq_type, &ECAP1_IRQHandler);
|
||||
Interrupt_enable(ecap->config->irq_type);
|
||||
}
|
||||
|
||||
ecap->opened++;
|
||||
|
||||
rt_mutex_release(&ecap->lock);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_ecap_close (rt_device_t dev)
|
||||
{
|
||||
struct rt_ecap_device *ecap;
|
||||
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
|
||||
ecap = (struct rt_ecap_device *)dev;
|
||||
|
||||
rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER);
|
||||
|
||||
if (ecap->opened > 0U)
|
||||
{
|
||||
ecap->opened--;
|
||||
|
||||
if (ecap->opened == 0U)
|
||||
{
|
||||
ECAP_disableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M);
|
||||
ECAP_disableTimeStampCapture(ecap->config->instance);
|
||||
ECAP_stopCounter(ecap->config->instance);
|
||||
Interrupt_disable(ecap->config->irq_type);
|
||||
}
|
||||
}
|
||||
|
||||
rt_mutex_release(&ecap->lock);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_ssize_t rt_ecap_read (rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
|
||||
{
|
||||
struct rt_ecap_device *ecap;
|
||||
struct rt_ecap_capture *cap;
|
||||
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
RT_ASSERT(buffer != RT_NULL);
|
||||
|
||||
ecap = (struct rt_ecap_device *)dev;
|
||||
|
||||
if (size < sizeof(struct rt_ecap_capture))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* 阻塞等待一次完整 capture。
|
||||
* 如果不希望阻塞，可以改成 RT_WAITING_NO。
|
||||
*/
|
||||
if (rt_sem_take(&ecap->rx_sem, RT_WAITING_FOREVER) != RT_EOK)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER);
|
||||
|
||||
cap = (struct rt_ecap_capture *)buffer;
|
||||
*cap = ecap->last_capture;
|
||||
|
||||
rt_mutex_release(&ecap->lock);
|
||||
|
||||
return sizeof(struct rt_ecap_capture);
|
||||
}
|
||||
|
||||
static rt_err_t rt_ecap_control (rt_device_t dev, int cmd, void *args)
|
||||
{
|
||||
struct rt_ecap_device *ecap;
|
||||
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
|
||||
ecap = (struct rt_ecap_device *)dev;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case ECAP_CMD_ENABLE:
|
||||
ECAP_startCounter(ecap->config->instance);
|
||||
ECAP_enableTimeStampCapture(ecap->config->instance);
|
||||
ECAP_enableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M);
|
||||
break;
|
||||
|
||||
case ECAP_CMD_DISABLE:
|
||||
ECAP_disableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M);
|
||||
ECAP_disableTimeStampCapture(ecap->config->instance);
|
||||
ECAP_stopCounter(ecap->config->instance);
|
||||
break;
|
||||
|
||||
case ECAP_CMD_REARM:
|
||||
ecap_hw_rearm(ecap->config);
|
||||
break;
|
||||
|
||||
case ECAP_CMD_GET_LAST_CAPTURE:
|
||||
if (args == RT_NULL)
|
||||
{
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER);
|
||||
*(struct rt_ecap_capture *)args = ecap->last_capture;
|
||||
rt_mutex_release(&ecap->lock);
|
||||
break;
|
||||
|
||||
case ECAP_CMD_SET_CALLBACK:
|
||||
{
|
||||
struct rt_ecap_callback *cb;
|
||||
|
||||
if (args == RT_NULL)
|
||||
{
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
cb = (struct rt_ecap_callback *)args;
|
||||
|
||||
rt_mutex_take(&ecap->lock, RT_WAITING_FOREVER);
|
||||
ecap->rx_callback = cb->callback;
|
||||
ecap->rx_user_data = cb->user_data;
|
||||
rt_mutex_release(&ecap->lock);
|
||||
break;
|
||||
}
|
||||
|
||||
case ECAP_CMD_CLEAR_FLAGS:
|
||||
ecap_hw_clear_flags(ecap->config);
|
||||
break;
|
||||
|
||||
case ECAP_CMD_ENABLE_IRQ:
|
||||
ECAP_enableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M);
|
||||
Interrupt_register(ecap->config->irq_type, &ECAP1_IRQHandler);
|
||||
Interrupt_enable(ecap->config->irq_type);
|
||||
break;
|
||||
|
||||
case ECAP_CMD_DISABLE_IRQ:
|
||||
ECAP_disableInterrupt(ecap->config->instance, ECAP_ECEINT_CEVT4_M);
|
||||
Interrupt_disable(ecap->config->irq_type);
|
||||
break;
|
||||
|
||||
default:
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
static const struct rt_device_ops ecap_ops =
|
||||
{
|
||||
rt_ecap_init,
|
||||
rt_ecap_open,
|
||||
rt_ecap_close,
|
||||
rt_ecap_read,
|
||||
RT_NULL,
|
||||
rt_ecap_control
|
||||
};
|
||||
#endif
|
||||
|
||||
static rt_err_t rt_hw_ecap_register (struct rt_ecap_device *ecap, const struct rt_ecap_config *config)
|
||||
{
|
||||
struct rt_device *dev;
|
||||
|
||||
RT_ASSERT(ecap != RT_NULL);
|
||||
RT_ASSERT(config != RT_NULL);
|
||||
|
||||
rt_memset(ecap, 0, sizeof(struct rt_ecap_device));
|
||||
|
||||
ecap->config = config;
|
||||
|
||||
rt_mutex_init(&ecap->lock, config->name, RT_IPC_FLAG_PRIO);
|
||||
rt_sem_init(&ecap->rx_sem, config->name, 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
dev = &ecap->parent;
|
||||
|
||||
dev->type = RT_Device_Class_Miscellaneous;
|
||||
dev->rx_indicate = RT_NULL;
|
||||
dev->tx_complete = RT_NULL;
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
dev->ops = &ecap_ops;
|
||||
#else
|
||||
dev->init = rt_ecap_init;
|
||||
dev->open = rt_ecap_open;
|
||||
dev->close = rt_ecap_close;
|
||||
dev->read = rt_ecap_read;
|
||||
dev->write = RT_NULL;
|
||||
dev->control = rt_ecap_control;
|
||||
#endif
|
||||
|
||||
return rt_device_register(dev, config->name, RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_INT_RX);
|
||||
}
|
||||
|
||||
int rt_hw_ecap_init (void)
|
||||
{
|
||||
rt_err_t ret;
|
||||
|
||||
ret = rt_hw_ecap_register(&ecap1_dev, &ecap1_config);
|
||||
|
||||
if (ret != RT_EOK)
|
||||
{
|
||||
LOG_E("register ecap1 failed, ret = %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
LOG_I("ecap1 register done");
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_ecap_init);
|
||||
|
||||
/*
|
||||
*
|
||||
*/
|
||||
void rt_hw_ecap1_isr(void)
|
||||
{
|
||||
struct rt_ecap_device *ecap;
|
||||
struct rt_ecap_capture cap;
|
||||
|
||||
ecap = &ecap1_dev;
|
||||
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_memset(&cap, 0, sizeof(cap));
|
||||
|
||||
cap.cap1 = ECAP_getEventTimeStamp(ecap->config->instance, ECAP_EVENT_1);
|
||||
cap.cap2 = ECAP_getEventTimeStamp(ecap->config->instance, ECAP_EVENT_2);
|
||||
cap.cap3 = ECAP_getEventTimeStamp(ecap->config->instance, ECAP_EVENT_3);
|
||||
cap.cap4 = ECAP_getEventTimeStamp(ecap->config->instance, ECAP_EVENT_4);
|
||||
|
||||
cap.status = ECAP_STATUS_DONE;
|
||||
ecap_calc_capture(&cap);
|
||||
|
||||
ecap->last_capture = cap;
|
||||
|
||||
/*
|
||||
* 当前是 one-shot capture mode，所以一次捕获完成后需要 re-arm。
|
||||
*/
|
||||
ecap_hw_clear_flags(ecap->config);
|
||||
|
||||
rt_sem_release(&ecap->rx_sem);
|
||||
|
||||
if (ecap->rx_callback != RT_NULL)
|
||||
{
|
||||
ecap->rx_callback((struct rt_ecap_capture *)&ecap->last_capture,
|
||||
ecap->rx_user_data);
|
||||
}
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void ECAP1_IRQHandler (void)
|
||||
{
|
||||
rt_hw_ecap1_isr();
|
||||
}
|
||||
|
||||
|
||||
#endif /* #if defined(BSP_USING_ECAP) */
|
||||
|
||||
@@ -0,0 +1,123 @@
|
||||
/**************************************************************************//**
|
||||
*
|
||||
* @copyright (C) 2026 Novosense Technology Corp. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-5-7 Alex-J First version
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __DRV_ECAP_H__
|
||||
#define __DRV_ECAP_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ECAP_DEVICE_NAME_MAX 8U
|
||||
|
||||
/*
|
||||
* control command
|
||||
*/
|
||||
#define ECAP_CMD_ENABLE (0x01)
|
||||
#define ECAP_CMD_DISABLE (0x02)
|
||||
#define ECAP_CMD_REARM (0x03)
|
||||
#define ECAP_CMD_GET_LAST_CAPTURE (0x04)
|
||||
#define ECAP_CMD_SET_CALLBACK (0x05)
|
||||
#define ECAP_CMD_CLEAR_FLAGS (0x06)
|
||||
#define ECAP_CMD_ENABLE_IRQ (0x07)
|
||||
#define ECAP_CMD_DISABLE_IRQ (0x08)
|
||||
|
||||
/*
|
||||
* ECAP capture status
|
||||
*/
|
||||
#define ECAP_STATUS_IDLE (0x00U)
|
||||
#define ECAP_STATUS_DONE (0x01U)
|
||||
#define ECAP_STATUS_OVERFLOW (0x02U)
|
||||
#define ECAP_STATUS_CAPTURE (0x04U)
|
||||
#define ECAP_STATUS_TIMEOUT (0x05U)
|
||||
|
||||
/*
|
||||
* Capture result.
|
||||
*
|
||||
* cap1~cap4 对应 ECAP CEVT1~CEVT4 的捕获值。
|
||||
* period_high / period_low 可根据当前边沿配置计算。
|
||||
*/
|
||||
struct rt_ecap_capture
|
||||
{
|
||||
rt_uint32_t cap1;
|
||||
rt_uint32_t cap2;
|
||||
rt_uint32_t cap3;
|
||||
rt_uint32_t cap4;
|
||||
|
||||
rt_uint32_t period_low;
|
||||
rt_uint32_t period_high;
|
||||
rt_uint32_t period_total;
|
||||
|
||||
rt_uint32_t status;
|
||||
};
|
||||
|
||||
typedef void (*rt_ecap_rx_callback_t)(struct rt_ecap_capture *capture, void *user_data);
|
||||
|
||||
struct rt_ecap_callback
|
||||
{
|
||||
rt_ecap_rx_callback_t callback;
|
||||
void *user_data;
|
||||
};
|
||||
|
||||
/*
|
||||
* Static ECAP hardware configuration.
|
||||
*/
|
||||
struct rt_ecap_config
|
||||
{
|
||||
const char *name;
|
||||
|
||||
ECAP_TypeDef *instance;
|
||||
IRQn_Type irq_type;
|
||||
|
||||
rt_uint32_t input_xbar;
|
||||
rt_uint32_t ecap_input;
|
||||
rt_uint32_t input_source;
|
||||
|
||||
GPIO_TypeDef *gpio_port;
|
||||
GPIO_PinNum gpio_pin;
|
||||
GPIO_AltFunc gpio_mux;
|
||||
void (*irq_handler)(void);
|
||||
};
|
||||
|
||||
/*
|
||||
* ECAP device object.
|
||||
*/
|
||||
struct rt_ecap_device
|
||||
{
|
||||
struct rt_device parent;
|
||||
|
||||
const struct rt_ecap_config *config;
|
||||
|
||||
struct rt_mutex lock;
|
||||
struct rt_semaphore rx_sem;
|
||||
|
||||
volatile struct rt_ecap_capture last_capture;
|
||||
|
||||
rt_ecap_rx_callback_t rx_callback;
|
||||
void *rx_user_data;
|
||||
|
||||
rt_uint8_t opened;
|
||||
};
|
||||
|
||||
int rt_hw_ecap_init(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_USART_H__ */
|
||||
|
||||
@@ -0,0 +1,461 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include "drv_gpio.h"
|
||||
#include "NS800RT7xxx_TI_gpio.h"
|
||||
#include <ctype.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#ifdef BSP_USING_GPIO
|
||||
|
||||
#define PIN_ENTRY(pin_macro) {pin_macro}
|
||||
|
||||
static const rt_pin_info_t pin_map_table[225] = {
|
||||
/* 0-21: 连续 */
|
||||
[0] = PIN_ENTRY(GPIO_0),
|
||||
[1] = PIN_ENTRY(GPIO_1),
|
||||
[2] = PIN_ENTRY(GPIO_2),
|
||||
[3] = PIN_ENTRY(GPIO_3),
|
||||
[4] = PIN_ENTRY(GPIO_4),
|
||||
[5] = PIN_ENTRY(GPIO_5),
|
||||
[6] = PIN_ENTRY(GPIO_6),
|
||||
[7] = PIN_ENTRY(GPIO_7),
|
||||
[8] = PIN_ENTRY(GPIO_8),
|
||||
[9] = PIN_ENTRY(GPIO_9),
|
||||
[10] = PIN_ENTRY(GPIO_10),
|
||||
[11] = PIN_ENTRY(GPIO_11),
|
||||
[12] = PIN_ENTRY(GPIO_12),
|
||||
[13] = PIN_ENTRY(GPIO_13),
|
||||
[14] = PIN_ENTRY(GPIO_14),
|
||||
[15] = PIN_ENTRY(GPIO_15),
|
||||
[16] = PIN_ENTRY(GPIO_16),
|
||||
[17] = PIN_ENTRY(GPIO_17),
|
||||
[18] = PIN_ENTRY(GPIO_18),
|
||||
[19] = PIN_ENTRY(GPIO_19),
|
||||
[20] = PIN_ENTRY(GPIO_20),
|
||||
[21] = PIN_ENTRY(GPIO_21),
|
||||
|
||||
/* 22-32: 不连续 */
|
||||
[22] = PIN_ENTRY(GPIO_22),
|
||||
[23] = PIN_ENTRY(GPIO_23),
|
||||
[24] = PIN_ENTRY(GPIO_24),
|
||||
[25] = PIN_ENTRY(GPIO_25),
|
||||
[26] = PIN_ENTRY(GPIO_26),
|
||||
[27] = PIN_ENTRY(GPIO_27),
|
||||
[28] = PIN_ENTRY(GPIO_28),
|
||||
[29] = PIN_ENTRY(GPIO_29),
|
||||
[30] = PIN_ENTRY(GPIO_30),
|
||||
[31] = PIN_ENTRY(GPIO_31),
|
||||
[32] = PIN_ENTRY(GPIO_32),
|
||||
|
||||
/* 33-63: 连续 */
|
||||
[33] = PIN_ENTRY(GPIO_33),
|
||||
[34] = PIN_ENTRY(GPIO_34),
|
||||
[35] = PIN_ENTRY(GPIO_35),
|
||||
[36] = PIN_ENTRY(GPIO_36),
|
||||
[37] = PIN_ENTRY(GPIO_37),
|
||||
[38] = PIN_ENTRY(GPIO_38),
|
||||
[39] = PIN_ENTRY(GPIO_39),
|
||||
[40] = PIN_ENTRY(GPIO_40),
|
||||
[41] = PIN_ENTRY(GPIO_41),
|
||||
[42] = PIN_ENTRY(GPIO_42),
|
||||
[43] = PIN_ENTRY(GPIO_43),
|
||||
[44] = PIN_ENTRY(GPIO_44),
|
||||
[45] = PIN_ENTRY(GPIO_45),
|
||||
[46] = PIN_ENTRY(GPIO_46),
|
||||
[47] = PIN_ENTRY(GPIO_47),
|
||||
[48] = PIN_ENTRY(GPIO_48),
|
||||
[49] = PIN_ENTRY(GPIO_49),
|
||||
[50] = PIN_ENTRY(GPIO_50),
|
||||
[51] = PIN_ENTRY(GPIO_51),
|
||||
[52] = PIN_ENTRY(GPIO_52),
|
||||
[53] = PIN_ENTRY(GPIO_53),
|
||||
[54] = PIN_ENTRY(GPIO_54),
|
||||
[55] = PIN_ENTRY(GPIO_55),
|
||||
[56] = PIN_ENTRY(GPIO_56),
|
||||
[57] = PIN_ENTRY(GPIO_57),
|
||||
[58] = PIN_ENTRY(GPIO_58),
|
||||
[59] = PIN_ENTRY(GPIO_59),
|
||||
[60] = PIN_ENTRY(GPIO_60),
|
||||
[61] = PIN_ENTRY(GPIO_61),
|
||||
[62] = PIN_ENTRY(GPIO_62),
|
||||
[63] = PIN_ENTRY(GPIO_63),
|
||||
|
||||
/* 64-94: 连续 */
|
||||
[64] = PIN_ENTRY(GPIO_64),
|
||||
[65] = PIN_ENTRY(GPIO_65),
|
||||
[66] = PIN_ENTRY(GPIO_66),
|
||||
[67] = PIN_ENTRY(GPIO_67),
|
||||
[68] = PIN_ENTRY(GPIO_68),
|
||||
[69] = PIN_ENTRY(GPIO_69),
|
||||
[70] = PIN_ENTRY(GPIO_70),
|
||||
[71] = PIN_ENTRY(GPIO_71),
|
||||
[72] = PIN_ENTRY(GPIO_72),
|
||||
[73] = PIN_ENTRY(GPIO_73),
|
||||
[74] = PIN_ENTRY(GPIO_74),
|
||||
[75] = PIN_ENTRY(GPIO_75),
|
||||
[76] = PIN_ENTRY(GPIO_76),
|
||||
[77] = PIN_ENTRY(GPIO_77),
|
||||
[78] = PIN_ENTRY(GPIO_78),
|
||||
[79] = PIN_ENTRY(GPIO_79),
|
||||
[80] = PIN_ENTRY(GPIO_80),
|
||||
[81] = PIN_ENTRY(GPIO_81),
|
||||
[82] = PIN_ENTRY(GPIO_82),
|
||||
[83] = PIN_ENTRY(GPIO_83),
|
||||
[84] = PIN_ENTRY(GPIO_84),
|
||||
[85] = PIN_ENTRY(GPIO_85),
|
||||
[86] = PIN_ENTRY(GPIO_86),
|
||||
[87] = PIN_ENTRY(GPIO_87),
|
||||
[88] = PIN_ENTRY(GPIO_88),
|
||||
[89] = PIN_ENTRY(GPIO_89),
|
||||
[90] = PIN_ENTRY(GPIO_90),
|
||||
[91] = PIN_ENTRY(GPIO_91),
|
||||
[92] = PIN_ENTRY(GPIO_92),
|
||||
[93] = PIN_ENTRY(GPIO_93),
|
||||
[94] = PIN_ENTRY(GPIO_94),
|
||||
|
||||
/* 不连续引脚 */
|
||||
[99] = PIN_ENTRY(GPIO_99),
|
||||
[100] = PIN_ENTRY(GPIO_100),
|
||||
[103] = PIN_ENTRY(GPIO_103),
|
||||
[104] = PIN_ENTRY(GPIO_104),
|
||||
[105] = PIN_ENTRY(GPIO_105),
|
||||
[106] = PIN_ENTRY(GPIO_106),
|
||||
[133] = PIN_ENTRY(GPIO_133),
|
||||
[183] = PIN_ENTRY(GPIO_183),
|
||||
[184] = PIN_ENTRY(GPIO_184),
|
||||
[198] = PIN_ENTRY(GPIO_198),
|
||||
[199] = PIN_ENTRY(GPIO_199),
|
||||
[200] = PIN_ENTRY(GPIO_200),
|
||||
[201] = PIN_ENTRY(GPIO_201),
|
||||
[202] = PIN_ENTRY(GPIO_202),
|
||||
[203] = PIN_ENTRY(GPIO_203),
|
||||
[204] = PIN_ENTRY(GPIO_204),
|
||||
[205] = PIN_ENTRY(GPIO_205),
|
||||
[206] = PIN_ENTRY(GPIO_206),
|
||||
[207] = PIN_ENTRY(GPIO_207),
|
||||
[208] = PIN_ENTRY(GPIO_208),
|
||||
[209] = PIN_ENTRY(GPIO_209),
|
||||
[210] = PIN_ENTRY(GPIO_210),
|
||||
[211] = PIN_ENTRY(GPIO_211),
|
||||
[212] = PIN_ENTRY(GPIO_212),
|
||||
[213] = PIN_ENTRY(GPIO_213),
|
||||
[214] = PIN_ENTRY(GPIO_214),
|
||||
[215] = PIN_ENTRY(GPIO_215),
|
||||
[216] = PIN_ENTRY(GPIO_216),
|
||||
[217] = PIN_ENTRY(GPIO_217),
|
||||
[218] = PIN_ENTRY(GPIO_218),
|
||||
[219] = PIN_ENTRY(GPIO_219),
|
||||
[220] = PIN_ENTRY(GPIO_220),
|
||||
[221] = PIN_ENTRY(GPIO_221),
|
||||
[222] = PIN_ENTRY(GPIO_222),
|
||||
[223] = PIN_ENTRY(GPIO_223),
|
||||
[224] = PIN_ENTRY(GPIO_224),
|
||||
};
|
||||
|
||||
/* 1. PIN_NUM: 从(port, pin)获取引脚编号 */
|
||||
int get_pin_num(GPIO_TypeDef *port, GPIO_PinNum pin)
|
||||
{
|
||||
/* 遍历数组查找匹配 */
|
||||
for (int i = 0; i < 225; i++)
|
||||
{
|
||||
if (pin_map_table[i].port == port &&
|
||||
pin_map_table[i].pin == (uint16_t)pin)
|
||||
{
|
||||
return i; /* 返回引脚编号 */
|
||||
}
|
||||
}
|
||||
return -1; /* 未找到 */
|
||||
}
|
||||
|
||||
/* 2. PIN_PORT: 从引脚编号获取端口索引 */
|
||||
uint8_t get_port_index(GPIO_TypeDef *port)
|
||||
{
|
||||
/* 由于新平台端口地址可能不连续，需要映射 */
|
||||
if (port == GPIOA) return 0;
|
||||
if (port == GPIOB) return 1;
|
||||
if (port == GPIOC) return 2;
|
||||
if (port == GPIOD) return 3;
|
||||
if (port == GPIOE) return 4;
|
||||
if (port == GPIOF) return 5;
|
||||
if (port == GPIOG) return 6;
|
||||
if (port == GPIOH) return 7;
|
||||
/* 如果有更多端口继续添加 */
|
||||
return 0xFF; /* 无效端口 */
|
||||
}
|
||||
|
||||
/* 3. PIN_NO: 从引脚编号获取引脚索引 */
|
||||
uint8_t get_pin_index(uint16_t pin)
|
||||
{
|
||||
/* 提取引脚位的位置 */
|
||||
switch (pin)
|
||||
{
|
||||
case GPIO_PIN_0: return 0;
|
||||
case GPIO_PIN_1: return 1;
|
||||
case GPIO_PIN_2: return 2;
|
||||
case GPIO_PIN_3: return 3;
|
||||
case GPIO_PIN_4: return 4;
|
||||
case GPIO_PIN_5: return 5;
|
||||
case GPIO_PIN_6: return 6;
|
||||
case GPIO_PIN_7: return 7;
|
||||
case GPIO_PIN_8: return 8;
|
||||
case GPIO_PIN_9: return 9;
|
||||
case GPIO_PIN_10: return 10;
|
||||
case GPIO_PIN_11: return 11;
|
||||
case GPIO_PIN_12: return 12;
|
||||
case GPIO_PIN_13: return 13;
|
||||
case GPIO_PIN_14: return 14;
|
||||
case GPIO_PIN_15: return 15;
|
||||
case GPIO_PIN_16: return 16;
|
||||
case GPIO_PIN_17: return 17;
|
||||
case GPIO_PIN_18: return 18;
|
||||
case GPIO_PIN_19: return 19;
|
||||
case GPIO_PIN_20: return 20;
|
||||
case GPIO_PIN_21: return 21;
|
||||
case GPIO_PIN_22: return 22;
|
||||
case GPIO_PIN_23: return 23;
|
||||
case GPIO_PIN_24: return 24;
|
||||
case GPIO_PIN_25: return 25;
|
||||
case GPIO_PIN_26: return 26;
|
||||
case GPIO_PIN_27: return 27;
|
||||
case GPIO_PIN_28: return 28;
|
||||
case GPIO_PIN_29: return 29;
|
||||
case GPIO_PIN_30: return 30;
|
||||
case GPIO_PIN_31: return 31;
|
||||
default: return 0xFF; /* 无效引脚 */
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t get_port_index_by_num(int pin_num)
|
||||
{
|
||||
const rt_pin_info_t *info = get_pin_info(pin_num);
|
||||
|
||||
if (info == RT_NULL)
|
||||
{
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
return get_port_index(info->port);
|
||||
}
|
||||
|
||||
uint8_t get_pin_index_by_num(int pin_num)
|
||||
{
|
||||
const rt_pin_info_t *info = get_pin_info(pin_num);
|
||||
|
||||
if (info == RT_NULL)
|
||||
{
|
||||
return 0xFF;
|
||||
}
|
||||
|
||||
return get_pin_index(info->pin);
|
||||
}
|
||||
|
||||
const rt_pin_info_t* get_pin_info(int pin_num)
|
||||
{
|
||||
if(pin_num < 0 || pin_num >=225)
|
||||
return NULL;
|
||||
|
||||
if(pin_map_table[pin_num].port == NULL)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return &pin_map_table[pin_num];
|
||||
}
|
||||
|
||||
#define PIN_STPORT(pin) (pin_map_table[(pin)].port)
|
||||
#define PIN_STPIN(pin) (pin_map_table[(pin)].pin)
|
||||
|
||||
|
||||
static uint32_t pin_irq_enable_mask = 0;
|
||||
|
||||
#define ITEM_NUM(items) (sizeof(items) / sizeof((items)[0]))
|
||||
|
||||
/* e.g. PE.7 */
|
||||
static rt_base_t ns800_pin_get(const char *name)
|
||||
{
|
||||
char port_name;
|
||||
int pin_index;
|
||||
uint8_t port_index;
|
||||
GPIO_TypeDef *port = RT_NULL;
|
||||
char *endptr;
|
||||
|
||||
if ((name == RT_NULL) || (name[0] == '\0'))
|
||||
{
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((name[0] != 'P') && (name[0] != 'p'))
|
||||
{
|
||||
goto out;
|
||||
}
|
||||
|
||||
port_name = (char)toupper((unsigned char)name[1]);
|
||||
if (name[2] != '.')
|
||||
{
|
||||
goto out;
|
||||
}
|
||||
|
||||
pin_index = (int)strtol(&name[3], &endptr, 10);
|
||||
if ((endptr == &name[3]) || (*endptr != '\0'))
|
||||
{
|
||||
goto out;
|
||||
}
|
||||
|
||||
if ((pin_index < 0) || (pin_index > 31))
|
||||
{
|
||||
goto out;
|
||||
}
|
||||
|
||||
port_index = (uint8_t)(port_name - 'A');
|
||||
switch (port_index)
|
||||
{
|
||||
case 0: port = GPIOA; break;
|
||||
case 1: port = GPIOB; break;
|
||||
case 2: port = GPIOC; break;
|
||||
case 3: port = GPIOD; break;
|
||||
case 4: port = GPIOE; break;
|
||||
case 5: port = GPIOF; break;
|
||||
case 6: port = GPIOG; break;
|
||||
case 7: port = GPIOH; break;
|
||||
default:
|
||||
goto out;
|
||||
}
|
||||
|
||||
return get_pin_num(port, (GPIO_PinNum)pin_index);
|
||||
|
||||
out:
|
||||
rt_kprintf("Px.y x:A~H y:0-31, e.g. PA.0\n");
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
static void ns800rt7_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
|
||||
{
|
||||
const rt_pin_info_t *info = get_pin_info(pin);
|
||||
|
||||
if (info == RT_NULL)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
if(value == 0)
|
||||
{
|
||||
GPIO_clearPin(info->port, info->pin);
|
||||
}
|
||||
else if(value == 1)
|
||||
{
|
||||
GPIO_setPin(info->port, info->pin);
|
||||
}
|
||||
}
|
||||
|
||||
static rt_ssize_t ns800rt7_pin_read(rt_device_t dev, rt_base_t pin)
|
||||
{
|
||||
const rt_pin_info_t *info = get_pin_info(pin);
|
||||
|
||||
if (info == RT_NULL)
|
||||
{
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
return (GPIO_readPin(info->port, info->pin)) ? PIN_HIGH : PIN_LOW;
|
||||
}
|
||||
|
||||
static void ns800rt7_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
|
||||
{
|
||||
const rt_pin_info_t *info = get_pin_info(pin);
|
||||
|
||||
if (info == RT_NULL)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
|
||||
GPIO_setAnalogMode(info->port, info->pin, GPIO_ANALOG_DISABLED);
|
||||
GPIO_setQualificationMode(info->port, info->pin, GPIO_QUAL_SYNC);
|
||||
GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setDriveLevel(info->port, info->pin, GPIO_DRV_MAX);
|
||||
|
||||
if (mode == PIN_MODE_OUTPUT )
|
||||
{
|
||||
GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION);
|
||||
GPIO_clearPin(info->port, info->pin);
|
||||
GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_OUT);
|
||||
}
|
||||
else if (mode == PIN_MODE_INPUT)
|
||||
{
|
||||
GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION);
|
||||
GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_IN);
|
||||
}
|
||||
else if (mode == PIN_MODE_INPUT_PULLUP)
|
||||
{
|
||||
GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_PULLUP);
|
||||
GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION);
|
||||
GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_IN);
|
||||
}
|
||||
else if (mode == PIN_MODE_INPUT_PULLDOWN)
|
||||
{
|
||||
GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_PULLDOWN);
|
||||
GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION);
|
||||
GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_IN);
|
||||
}
|
||||
else if (mode == PIN_MODE_OUTPUT_OD)
|
||||
{
|
||||
GPIO_setPadConfig(info->port, info->pin, GPIO_PIN_TYPE_OD);
|
||||
GPIO_setPinConfig(info->port, info->pin, ALT0_FUNCTION);
|
||||
GPIO_clearPin(info->port, info->pin);
|
||||
GPIO_setDirectionMode(info->port, info->pin, GPIO_DIR_MODE_OUT);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static rt_err_t ns800_pin_attach_irq(struct rt_device *device, rt_base_t pin,
|
||||
rt_uint8_t mode, void (*hdr)(void *args), void *args)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t ns800_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t ns800_pin_irq_enable(struct rt_device *device, rt_base_t pin,
|
||||
rt_uint8_t enabled)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
static const struct rt_pin_ops _ns800rt7_pin_ops =
|
||||
{
|
||||
ns800rt7_pin_mode,
|
||||
ns800rt7_pin_write,
|
||||
ns800rt7_pin_read,
|
||||
ns800_pin_attach_irq,
|
||||
ns800_pin_dettach_irq,
|
||||
ns800_pin_irq_enable,
|
||||
ns800_pin_get,
|
||||
RT_NULL,
|
||||
};
|
||||
|
||||
rt_inline void pin_irq_hdr(int irqno)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
int rt_hw_pin_init(void)
|
||||
{
|
||||
return rt_device_pin_register("pin", &_ns800rt7_pin_ops, RT_NULL);
|
||||
}
|
||||
|
||||
#endif /* BSP_USING_GPIO */
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 balanceTWK first version
|
||||
* 2020-09-01 thread-liu add GPIOZ
|
||||
* 2020-09-18 geniusgogo optimization design pin-index algorithm
|
||||
*/
|
||||
|
||||
#ifndef __DRV_GPIO_H__
|
||||
#define __DRV_GPIO_H__
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
GPIO_TypeDef *port;
|
||||
GPIO_PinNum pin;
|
||||
} rt_pin_info_t;
|
||||
|
||||
|
||||
#define PIN_NUM(...) get_pin_num(__VA_ARGS__)
|
||||
#define PIN_PORT(pin) get_port_index_by_num(pin)
|
||||
#define PIN_NO(pin) get_pin_index_by_num(pin)
|
||||
|
||||
const rt_pin_info_t* get_pin_info(int pin_num);
|
||||
int get_pin_num(GPIO_TypeDef *port, GPIO_PinNum pin);
|
||||
uint8_t get_port_index(GPIO_TypeDef *port);
|
||||
uint8_t get_pin_index(uint16_t pin);
|
||||
uint8_t get_port_index_by_num(int pin_num);
|
||||
uint8_t get_pin_index_by_num(int pin_num);
|
||||
|
||||
int rt_hw_pin_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_GPIO_H__ */
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-15 SummerGift first version
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: DO NOT include this file on the header file.
|
||||
*/
|
||||
|
||||
#ifndef LOG_TAG
|
||||
#define DBG_TAG "drv"
|
||||
#else
|
||||
#define DBG_TAG LOG_TAG
|
||||
#endif /* LOG_TAG */
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
#define DBG_LVL DBG_LOG
|
||||
#else
|
||||
#define DBG_LVL DBG_INFO
|
||||
#endif /* DRV_DEBUG */
|
||||
|
||||
#include <rtdbg.h>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_USART_H__
|
||||
#define __DRV_USART_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#define UART_CTRL_SET_BLOCK_TIMEOUT 0x20
|
||||
|
||||
/* ns800 config class */
|
||||
struct ns800_uart_config
|
||||
{
|
||||
const char *name;
|
||||
UART_TypeDef *Instance;
|
||||
IRQn_Type rx_irq_type;
|
||||
IRQn_Type tx_irq_type;
|
||||
void (*irq_handler)(void);
|
||||
GPIO_TypeDef *rx_port;
|
||||
GPIO_PinNum rx_pin;
|
||||
GPIO_AltFunc rx_mux;
|
||||
rt_uint32_t rx_pad;
|
||||
GPIO_Direction rx_direction;
|
||||
rt_bool_t rx_drive_max;
|
||||
GPIO_TypeDef *tx_port;
|
||||
GPIO_PinNum tx_pin;
|
||||
GPIO_AltFunc tx_mux;
|
||||
rt_uint32_t tx_pad;
|
||||
GPIO_Direction tx_direction;
|
||||
rt_bool_t tx_drive_max;
|
||||
rt_uint32_t tx_block_timeout;
|
||||
rt_uint16_t rx_bufsz;
|
||||
rt_uint16_t tx_bufsz;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
UART_TypeDef *Instance;
|
||||
|
||||
rt_uint32_t baud_rate;
|
||||
|
||||
rt_uint8_t data_bits;
|
||||
rt_uint8_t stop_bits;
|
||||
rt_uint8_t parity;
|
||||
rt_uint8_t bit_order;
|
||||
rt_uint8_t invert;
|
||||
rt_uint8_t bufsz;
|
||||
rt_uint8_t flowcontrol;
|
||||
rt_uint8_t reserved;
|
||||
}UART_HandleTypeDef;
|
||||
|
||||
/* ns800 uart dirver class */
|
||||
struct ns800_uart
|
||||
{
|
||||
UART_HandleTypeDef handle;
|
||||
struct ns800_uart_config *config;
|
||||
rt_uint32_t DR_mask;
|
||||
rt_uint32_t tx_block_timeout;
|
||||
struct rt_serial_device serial;
|
||||
};
|
||||
|
||||
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
#endif /* __DRV_USART_H__ */
|
||||
|
||||
@@ -0,0 +1,217 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*
|
||||
*/
|
||||
|
||||
#include "drv_common.h"
|
||||
#include <board.h>
|
||||
|
||||
#ifdef RT_USING_PIN
|
||||
#include <drv_gpio.h>
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
#ifdef RT_USING_SERIAL_V2
|
||||
#include <drv_usart_v2.h>
|
||||
#else
|
||||
#include <drv_uart.h>
|
||||
#endif /* RT_USING_SERIAL */
|
||||
#endif /* RT_USING_SERIAL_V2 */
|
||||
|
||||
#define DBG_TAG "drv_common"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
static void reboot(uint8_t argc, char **argv)
|
||||
{
|
||||
rt_hw_cpu_reset();
|
||||
}
|
||||
MSH_CMD_EXPORT(reboot, Reboot System);
|
||||
#endif /* RT_USING_FINSH */
|
||||
|
||||
/* SysTick configuration */
|
||||
void rt_hw_systick_init(void)
|
||||
{
|
||||
/* update the system core clock value */
|
||||
SystemCoreClockUpdate();
|
||||
/* initialize systick(base time) */
|
||||
SysTick_Config(SystemCoreClock / SYSTICK_TIME_UNIT);
|
||||
/* systick interrupt control */
|
||||
Systick_setInterrupt(ENABLE);
|
||||
|
||||
NVIC_SetPriority(SysTick_IRQn, 0x0F);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
volatile rt_tick_t g_tick_test;
|
||||
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
g_tick_test = rt_tick_get();
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void _Error_Handler(char *s, int num)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
LOG_E("Error_Handler at file:%s num:%d", s, num);
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler */
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will delay for some us.
|
||||
*
|
||||
* @param us the delay time of us
|
||||
*/
|
||||
void rt_hw_us_delay(rt_uint32_t us)
|
||||
{
|
||||
rt_uint64_t ticks;
|
||||
rt_uint32_t told, tnow, tcnt = 0;
|
||||
rt_uint32_t reload = SysTick->LOAD;
|
||||
|
||||
ticks = us * (reload / (1000000 / RT_TICK_PER_SECOND));
|
||||
told = SysTick->VAL;
|
||||
while (1)
|
||||
{
|
||||
tnow = SysTick->VAL;
|
||||
if (tnow != told)
|
||||
{
|
||||
if (tnow < told)
|
||||
{
|
||||
tcnt += told - tnow;
|
||||
}
|
||||
else
|
||||
{
|
||||
tcnt += reload - tnow + told;
|
||||
}
|
||||
told = tnow;
|
||||
if (tcnt >= ticks)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define BSP_SCB_ENABLE_I_CACHE
|
||||
#define BSP_SCB_ENABLE_D_CACHE
|
||||
/**
|
||||
* This function will initial NS800 board.
|
||||
*/
|
||||
rt_weak void rt_hw_board_init(void)
|
||||
{
|
||||
#ifdef BSP_SCB_ENABLE_I_CACHE
|
||||
/* Enable I-Cache---------------------------------------------------------*/
|
||||
SCB_EnableICache();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_SCB_ENABLE_D_CACHE
|
||||
/* Enable D-Cache---------------------------------------------------------*/
|
||||
SCB_EnableDCache();
|
||||
#endif
|
||||
|
||||
/* Initialize device clock and peripherals */
|
||||
Device_init();
|
||||
/* Disable peripheral register locks */
|
||||
Device_unlockPeriphReg();
|
||||
/* Interrupt initialization. Disable global interrupts. */
|
||||
Interrupt_initModule();
|
||||
Interrupt_initVectorTable();
|
||||
|
||||
rt_hw_systick_init();
|
||||
|
||||
#if defined(RT_USING_HEAP)
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_PIN
|
||||
rt_hw_pin_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
rt_hw_uart_init();
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||||
/* Set the shell console output device */
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO)
|
||||
extern void rt_hw_console_init(void);
|
||||
rt_hw_console_init();
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
/* Board underlying hardware initialization */
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
#ifdef RT_USING_CONSOLE
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
#if defined(__ICCARM__)
|
||||
rt_size_t size = rt_strlen(str);
|
||||
|
||||
__write(0, str, size);
|
||||
#else
|
||||
rt_size_t i = 0, size = 0;
|
||||
char a = '\r';
|
||||
FILE f;
|
||||
|
||||
size = rt_strlen(str);
|
||||
|
||||
for (i = 0; i < size; i++)
|
||||
{
|
||||
if (*(str + i) == '\n')
|
||||
{
|
||||
fputc(a, &f);
|
||||
}
|
||||
fputc(str[i], &f);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
char rt_hw_console_getchar(void)
|
||||
{
|
||||
/* Note: the initial value of ch must < 0 */
|
||||
int ch = -1;
|
||||
|
||||
if (UART1->STAT.BIT.RDRF)
|
||||
{
|
||||
ch = (uint8_t)UART1->DATA.WORDVAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
return ch;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-7 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_COMMON_H__
|
||||
#define __DRV_COMMON_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
#ifdef RT_USING_DEVICE
|
||||
#include <rtdevice.h>
|
||||
#endif /* RT_USING_DEVICE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void _Error_Handler(char *s, int num);
|
||||
|
||||
#ifndef Error_Handler
|
||||
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
|
||||
#endif
|
||||
|
||||
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,42 @@
|
||||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
cconfig.h
|
||||
@@ -0,0 +1,28 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
BSP_DIR := .
|
||||
|
||||
RTT_DIR := ../../../..
|
||||
LIB_DIR := ../libraries/HAL_Drivers
|
||||
PKGS_DIR := packages
|
||||
|
||||
config SOC_SERIES_NS800RT7
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_NS800RT7P6XX
|
||||
bool
|
||||
select SOC_SERIES_NS800RT7
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
config BOARD_NS800RT7P65X
|
||||
bool
|
||||
depends on SOC_NS800RT7P6XX
|
||||
default y
|
||||
|
||||
source "$(RTT_DIR)/Kconfig"
|
||||
osource "$PKGS_DIR/Kconfig"
|
||||
rsource "board/Kconfig"
|
||||
rsource "$(LIB_DIR)/drivers/Kconfig"
|
||||
@@ -0,0 +1,5 @@
|
||||
# NS800RT7P65-NSSinePad BSP Introduction
|
||||
|
||||
[中文](README_zh.md)
|
||||
|
||||
## MCU: NS800RT7P65D @400MHz, 1024KB FLASH, 770KB RAM
|
||||
@@ -0,0 +1,102 @@
|
||||
# NS800RT7P65-NSSinePad 开发板 BSP 说明
|
||||
|
||||
## 简介
|
||||
|
||||
本文档为 tyustli 为 NS800RT7P65-NSSinePad 开发板提供的 BSP (板级支持包) 说明。
|
||||
|
||||
主要内容如下：
|
||||
|
||||
- 开发板资源介绍
|
||||
- BSP 快速上手
|
||||
- 进阶使用方法
|
||||
|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
|
||||
|
||||
## 开发板介绍
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| :----------------- | :----------: | :------------------------------------- |
|
||||
| USB 转串口 | 支持 |
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| GPIO | 支持 | |
|
||||
| UART | 支持 | UART1 |
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
**请注意！！！**
|
||||
|
||||
在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的HAL库及CMSIS库，否则无法通过编译）：
|
||||
|
||||
```bash
|
||||
pkgs --update
|
||||
```
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用数据线连接开发板到 PC，打开电源开关。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用 ST_LINK 仿真器下载程序，在通过 ST_LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，LED闪烁。
|
||||
|
||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.0.1 build Mar 5 2019
|
||||
2006 - 2019 Copyright by rt-thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
|
||||
|
||||
本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
|
||||
|
||||
## 注意事项
|
||||
|
||||
- 调试串口为串口1 映射说明
|
||||
|
||||
PD8 ------> USART1_TX
|
||||
|
||||
PD9 ------> USART1_RX
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [tyustli](https://github.com/tyustli)
|
||||
@@ -0,0 +1,15 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('env')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,73 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
def bsp_pkg_check():
|
||||
import subprocess
|
||||
|
||||
check_paths = [
|
||||
os.path.join("packages", "CMSIS-Core-latest"),
|
||||
os.path.join("packages", "novosns-series-latest"),
|
||||
]
|
||||
|
||||
need_update = not all(os.path.exists(p) for p in check_paths)
|
||||
|
||||
if need_update:
|
||||
print("\n===============================================================================")
|
||||
print("Dependency packages missing, please running 'pkgs --update'...")
|
||||
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
|
||||
print("===============================================================================")
|
||||
exit(1)
|
||||
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
|
||||
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
|
||||
|
||||
Export('env')
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
rtconfig.BSP_LIBRARY_TYPE = None
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'),variant_dir='build/libraries/HAL_Drivers', duplicate=0))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,15 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-05-06 Jiawei.Deng first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED1 pin: GPIO_68 = PC4 */
|
||||
#define LED1_PIN PIN_NUM(GPIO_68)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
/* rt_kprintf("\r\n led1_thread_entry running! \r\n"); */
|
||||
rt_pin_write(LED1_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(1000);
|
||||
rt_pin_write(LED1_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,126 @@
|
||||
menu "On-chip Peripheral Drivers"
|
||||
menuconfig BOARD_CLK_CONF
|
||||
bool "Clock Configuration"
|
||||
default y
|
||||
if BOARD_CLK_CONF
|
||||
config SYSCLK_USE_PLL
|
||||
bool "Use PLL as system clock source"
|
||||
default y
|
||||
|
||||
config SYSCLK_SOURCE_USE_HXTL
|
||||
bool "Use High-Speed Crystal Oscillator (HXTL) as system clock source"
|
||||
default y
|
||||
depends on SYSCLK_USE_PLL
|
||||
|
||||
config PLLCLK_SOURCE_USE_HXTL
|
||||
bool "Use High-Speed Crystal Oscillator (HXTL) as PLL clock source"
|
||||
default y
|
||||
depends on SYSCLK_USE_PLL
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
if BSP_USING_GPIO
|
||||
config BSP_GPIO_PIN_IRQ
|
||||
bool "Enable GPIO pin IRQ hooks"
|
||||
default n
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_NS800_UART_TX_TIMEOUT
|
||||
int "UART TX timeout"
|
||||
default 6000
|
||||
depends on !RT_USING_SERIAL_V2
|
||||
|
||||
menuconfig BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
if BSP_USING_UART1
|
||||
config BSP_UART1_RX_BUFSIZE
|
||||
int "UART1 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART1_TX_BUFSIZE
|
||||
int "UART1 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART2
|
||||
bool "Enable UART2"
|
||||
default n
|
||||
if BSP_USING_UART2
|
||||
config BSP_UART2_RX_BUFSIZE
|
||||
int "UART2 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART2_TX_BUFSIZE
|
||||
int "UART2 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART3
|
||||
bool "Enable UART3"
|
||||
default n
|
||||
if BSP_USING_UART3
|
||||
config BSP_UART3_RX_BUFSIZE
|
||||
int "UART3 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART3_TX_BUFSIZE
|
||||
int "UART3 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_UART4
|
||||
bool "Enable UART4"
|
||||
default n
|
||||
if BSP_USING_UART4
|
||||
config BSP_UART4_RX_BUFSIZE
|
||||
int "UART4 RX buffer size"
|
||||
range 64 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 256
|
||||
|
||||
config BSP_UART4_TX_BUFSIZE
|
||||
int "UART4 TX buffer size"
|
||||
range 0 65535
|
||||
depends on RT_USING_SERIAL_V2
|
||||
default 0
|
||||
endif
|
||||
endif
|
||||
|
||||
menuconfig BSP_USING_ECAP
|
||||
bool "Enable ECAP"
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_CAN
|
||||
bool "Enable CAN"
|
||||
select RT_USING_CAN
|
||||
default n
|
||||
if BSP_USING_CAN
|
||||
config BSP_USING_CANFD1
|
||||
bool "Enable CANFD1"
|
||||
select RT_CAN_USING_CANFD
|
||||
default n
|
||||
|
||||
endif
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,24 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Glob('board.c')
|
||||
pkg_root = os.path.join(cwd, '..', 'packages', 'novosns-series', 'NS800RT7XXX')
|
||||
path = [
|
||||
cwd,
|
||||
os.path.join(pkg_root, 'Device', 'Inc'),
|
||||
os.path.join(pkg_root, 'StdDriver', 'Inc'),
|
||||
os.path.join(pkg_root, 'StdDriver', 'Inc', 'ti'),
|
||||
os.path.join(cwd, '..', 'libraries', 'HAL_Drivers'),
|
||||
os.path.join(cwd, '..', 'libraries', 'HAL_Drivers', 'drivers'),
|
||||
]
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,356 @@
|
||||
/**
|
||||
* @file board.c
|
||||
* @author Haven-X
|
||||
* @brief Board setup for NS800RTxxx examples.
|
||||
*
|
||||
* @note Board Configurations
|
||||
* Initializes the rest of the modules.
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2025 Novosense Limited.
|
||||
* All rights reserved.</center></h2>
|
||||
*/
|
||||
#include "board.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Functions
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Board Initialization.
|
||||
* @note Call this function in your application if you wish to do all module
|
||||
* initialization.
|
||||
* If you wish to not use some of the initializations, instead of the
|
||||
* Board_init use the individual Module_inits.
|
||||
*/
|
||||
void Board_init (void)
|
||||
{
|
||||
PinMux_init();
|
||||
SerialCOM_init();
|
||||
LED_init();
|
||||
Switch_init();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PinMux Initialization.
|
||||
* @note Call this function in your application if you want all
|
||||
* PinMux initialization to be done.
|
||||
*/
|
||||
void PinMux_init (void)
|
||||
{
|
||||
/* Configure GPIO pins for SCI_COM. */
|
||||
GPIO_setPinConfig(GPIO_12_SCIA_TX);
|
||||
GPIO_setPinConfig(GPIO_13_SCIA_RX);
|
||||
|
||||
/* Configure GPIO pins for LED1 and LED2. */
|
||||
GPIO_setPinConfig(GPIO_68_GPIO68);
|
||||
GPIO_setPinConfig(GPIO_69_GPIO69);
|
||||
|
||||
/* Configure GPIO pins for KEY. */
|
||||
GPIO_setPinConfig(GPIO_41_GPIO41);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Board Serial Communication Interface Initialization.
|
||||
* @note Call this function in the application to initialize the SCI serial port
|
||||
* on the board for outputting debugging information.
|
||||
*/
|
||||
void SerialCOM_init(void)
|
||||
{
|
||||
/* uart1 rx control */
|
||||
GPIO_setAnalogMode(BOARD_SERIALCOM_RX_PIN, GPIO_ANALOG_DISABLED);
|
||||
GPIO_setPadConfig(BOARD_SERIALCOM_RX_PIN, GPIO_PIN_TYPE_PULLUP);
|
||||
GPIO_setQualificationMode(BOARD_SERIALCOM_RX_PIN, GPIO_QUAL_SYNC);
|
||||
GPIO_setQualificationPeriod(BOARD_SERIALCOM_RX_PIN, GPIO_SMP_SYSCLK_DIV_1);
|
||||
GPIO_setDirectionMode(BOARD_SERIALCOM_RX_PIN, GPIO_DIR_MODE_IN);
|
||||
/* uart1 tx control */
|
||||
GPIO_setAnalogMode(BOARD_SERIALCOM_TX_PIN, GPIO_ANALOG_DISABLED);
|
||||
GPIO_setPadConfig(BOARD_SERIALCOM_TX_PIN, GPIO_PIN_TYPE_STD);
|
||||
GPIO_setDriveLevel(BOARD_SERIALCOM_TX_PIN, GPIO_DRV_LOW);
|
||||
GPIO_setPin(BOARD_SERIALCOM_TX_PIN);
|
||||
GPIO_setDirectionMode(BOARD_SERIALCOM_TX_PIN, GPIO_DIR_MODE_OUT);
|
||||
/* Reset uart before configure it */
|
||||
UART_resetModule(BOARD_SERIALCOM);
|
||||
/* Set baudrate */
|
||||
UART_setBaud(BOARD_SERIALCOM, BOARD_SERIALCOM_BAUDRATE);
|
||||
/* Set the number of stop bits */
|
||||
UART_setStopBitCount(BOARD_SERIALCOM, UART_ONE_STOP_BIT);
|
||||
/* Set MSB bit reverses the order of the bits */
|
||||
UART_setMSB(BOARD_SERIALCOM, false);
|
||||
/* Config tx fifo */
|
||||
UART_enableTxFifo(BOARD_SERIALCOM);
|
||||
UART_resetTxFifo(BOARD_SERIALCOM);
|
||||
UART_setTxFifoWatermark(BOARD_SERIALCOM, UART_FIFO_TX6);
|
||||
|
||||
/* Enable transmitter */
|
||||
UART_enableTxModule(BOARD_SERIALCOM);
|
||||
/* Enable receiver */
|
||||
UART_enableRxModule(BOARD_SERIALCOM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Board LED Initialization.
|
||||
* @note Call this function in the application to initialize the LED
|
||||
* on the board.
|
||||
*/
|
||||
void LED_init (void)
|
||||
{
|
||||
/* led1 initialization */
|
||||
GPIO_setAnalogMode(BOARD_LED1_PIN, GPIO_ANALOG_DISABLED);
|
||||
GPIO_setDriveLevel(BOARD_LED1_PIN, GPIO_DRV_MAX);
|
||||
GPIO_clearPin(BOARD_LED1_PIN);
|
||||
GPIO_setDirectionMode(BOARD_LED1_PIN, GPIO_DIR_MODE_OUT);
|
||||
/* led2 initialization */
|
||||
GPIO_setAnalogMode(BOARD_LED2_PIN, GPIO_ANALOG_DISABLED);
|
||||
GPIO_setDriveLevel(BOARD_LED2_PIN, GPIO_DRV_MAX);
|
||||
GPIO_clearPin(BOARD_LED2_PIN);
|
||||
GPIO_setDirectionMode(BOARD_LED2_PIN, GPIO_DIR_MODE_OUT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Board Switch Initialization.
|
||||
* @note Call this function in the application to initialize the Switch
|
||||
* on the board.
|
||||
*/
|
||||
void Switch_init (void)
|
||||
{
|
||||
/* KEY initialization */
|
||||
GPIO_setAnalogMode(BOARD_KEY_PIN, GPIO_ANALOG_DISABLED);
|
||||
GPIO_setPadConfig(BOARD_KEY_PIN, GPIO_PIN_TYPE_OD);
|
||||
GPIO_setQualificationPeriod(BOARD_KEY_PIN, GPIO_SMP_SYSCLK_DIV_510);
|
||||
GPIO_setQualificationMode(BOARD_KEY_PIN, GPIO_QUAL_6SAMPLE);
|
||||
GPIO_setDirectionMode(BOARD_KEY_PIN, GPIO_DIR_MODE_IN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to initialize the device.
|
||||
* @note Mainly initialize the system clock and enable all peripheral clocks.
|
||||
*/
|
||||
void Device_init(void)
|
||||
{
|
||||
System_setClock();
|
||||
#ifndef RT_USING_SMP
|
||||
Device_enableAllPeripheralsInCpu1();
|
||||
#endif
|
||||
Device_enableAllPeripherals();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set up clock source selection, PLL control, and clock dividers.
|
||||
*/
|
||||
void System_setClock (void)
|
||||
{
|
||||
/* If CPU1 has been configured, do not repeat the configuration for CPU2. */
|
||||
if((MCM->CPUID.WORDVAL & 0x01) == 0x01)
|
||||
{
|
||||
#ifdef SYSCLK_USE_PLL
|
||||
#ifdef SYSCLK_SOURCE_USE_HXTL
|
||||
RCC_configHxtl(HXTL_CONFIG, RCC_HXTL_NORMAL, RCC_FUN_ON);
|
||||
#endif
|
||||
RCC_configPll(PLL_CONFIG, PLL_EXT_CONFIG, RCC_FUN_ON);
|
||||
|
||||
RCC_setClock(RCC_SYSCLKSOURCE_PLL);
|
||||
#else /* !SYSCLK_USE_PLL */
|
||||
#ifdef SYSCLK_SOURCE_USE_HXTL
|
||||
RCC_configHxtl(HXTL_CONFIG, RCC_HXTL_NORMAL, RCC_FUN_ON);
|
||||
RCC_setClock(RCC_SYSCLKSOURCE_HXTL);
|
||||
#endif /* SYSCLK_SOURCE_USE_HXTL */
|
||||
|
||||
#ifdef SYSCLK_SOURCE_USE_MIRC1
|
||||
RCC_setClock(RCC_SYSCLKSOURCE_MIRC1);
|
||||
#endif /* SYSCLK_SOURCE_USE_MIRC1 */
|
||||
|
||||
#ifdef SYSCLK_SOURCE_USE_MIRC2
|
||||
RCC_setClock(RCC_SYSCLKSOURCE_MIRC2);
|
||||
#endif /* SYSCLK_SOURCE_USE_MIRC2 */
|
||||
#endif /* SYSCLK_USE_PLL */
|
||||
RCC_configClockDiv(SYSCLOCK_CFGR_DIV_CONFIG, SYSCLOCK_CFGR2_DIV_CONFIG);
|
||||
}
|
||||
}
|
||||
|
||||
#if (DUAL_CORE_ENABLE == 0)
|
||||
/**
|
||||
* @brief Enable CPU1 for peripherals.
|
||||
*/
|
||||
void Device_enableAllPeripheralsInCpu1 (void)
|
||||
{
|
||||
SYSCON->UNLOCK.WORDVAL = 0x55aa6699;
|
||||
|
||||
WRITE_REG(SYSCON->AHBCPUSEL1.WORDVAL, 0x0);
|
||||
WRITE_REG(SYSCON->AHBCPUSEL2.WORDVAL, 0x0);
|
||||
WRITE_REG(SYSCON->APBCPUSEL1.WORDVAL, 0x0);
|
||||
WRITE_REG(SYSCON->APBCPUSEL2.WORDVAL, 0x0);
|
||||
WRITE_REG(SYSCON->APBCPUSEL3.WORDVAL, 0x0);
|
||||
WRITE_REG(SYSCON->APBCPUSEL5.WORDVAL, 0x0);
|
||||
WRITE_REG(SYSCON->APBCPUSEL6.WORDVAL, 0x0);
|
||||
WRITE_REG(SYSCON->APBCPUSEL8.WORDVAL, 0x0);
|
||||
|
||||
SET_BIT(SYSCON->AHBCPUSELEN1.WORDVAL, 0x00000330);
|
||||
SET_BIT(SYSCON->AHBCPUSELEN2.WORDVAL, 0x00007303);
|
||||
SET_BIT(SYSCON->APBCPUSELEN1.WORDVAL, 0xFF7FFFFF);
|
||||
SET_BIT(SYSCON->APBCPUSELEN2.WORDVAL, 0x07FF800F);
|
||||
SET_BIT(SYSCON->APBCPUSELEN3.WORDVAL, 0x00000300);
|
||||
SET_BIT(SYSCON->APBCPUSELEN5.WORDVAL, 0x01070F0F);
|
||||
SET_BIT(SYSCON->APBCPUSELEN6.WORDVAL, 0x03003F03);
|
||||
SET_BIT(SYSCON->APBCPUSELEN8.WORDVAL, 0x03FF0010);
|
||||
|
||||
SYSCON->UNLOCK.WORDVAL = 0x55aa6698;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable clocks for all peripherals.
|
||||
*/
|
||||
void Device_enableAllPeripherals (void)
|
||||
{
|
||||
RCC_unlockRccRegister();
|
||||
|
||||
RCC_enableAhb1PeripheralClock(RCC_HCLKEN1_UPPEN_M | RCC_HCLKEN1_EMIFEN_M | RCC_HCLKEN1_SEMAEN_M |
|
||||
RCC_HCLKEN1_MUEN_M | RCC_HCLKEN1_GPIOHEN_M | RCC_HCLKEN1_GPIOGEN_M |
|
||||
RCC_HCLKEN1_GPIOFEN_M | RCC_HCLKEN1_GPIOEEN_M | RCC_HCLKEN1_GPIODEN_M |
|
||||
RCC_HCLKEN1_GPIOCEN_M | RCC_HCLKEN1_GPIOBEN_M | RCC_HCLKEN1_GPIOAEN_M |
|
||||
RCC_HCLKEN1_EMATHEN_M | RCC_HCLKEN1_QSPIEN_M | RCC_HCLKEN1_CPUXMMATHEN_M |
|
||||
RCC_HCLKEN1_EDMA2EN_M | RCC_HCLKEN1_EDMA1EN_M | RCC_HCLKEN1_DMAMUX2EN_M |
|
||||
RCC_HCLKEN1_DMAMUX1EN_M | RCC_HCLKEN1_SMPUEN_M | RCC_HCLKEN1_FMUEN_M);
|
||||
|
||||
RCC_enableAhb2PeripheralClock(RCC_HCLKEN2_CANFD2EN_M | RCC_HCLKEN2_CANFD1EN_M | RCC_HCLKEN2_CAN1EN_M |
|
||||
RCC_HCLKEN2_LIN2EN_M | RCC_HCLKEN2_LIN1EN_M | RCC_HCLKEN2_BGCRC2EN_M |
|
||||
RCC_HCLKEN2_BGCRC1EN_M | RCC_HCLKEN2_CRC2EN_M | RCC_HCLKEN2_CRC1EN_M |
|
||||
RCC_HCLKEN2_AESHASHEN_M | RCC_HCLKEN2_TRNGEN_M);
|
||||
|
||||
RCC_enableApb1PeripheralClock(RCC_PCLKEN1_EPWM18EN_M | RCC_PCLKEN1_EPWM17EN_M | RCC_PCLKEN1_EQEP6EN_M |
|
||||
RCC_PCLKEN1_EQEP5EN_M | RCC_PCLKEN1_EQEP4EN_M | RCC_PCLKEN1_EQEP3EN_M |
|
||||
RCC_PCLKEN1_EQEP2EN_M | RCC_PCLKEN1_EQEP1EN_M | RCC_PCLKEN1_ECAP7EN_M |
|
||||
RCC_PCLKEN1_ECAP6EN_M | RCC_PCLKEN1_ECAP5EN_M | RCC_PCLKEN1_ECAP4EN_M |
|
||||
RCC_PCLKEN1_ECAP3EN_M | RCC_PCLKEN1_ECAP2EN_M | RCC_PCLKEN1_ECAP1EN_M |
|
||||
RCC_PCLKEN1_EPWM16EN_M | RCC_PCLKEN1_EPWM15EN_M | RCC_PCLKEN1_EPWM14EN_M |
|
||||
RCC_PCLKEN1_EPWM13EN_M | RCC_PCLKEN1_EPWM12EN_M | RCC_PCLKEN1_EPWM11EN_M |
|
||||
RCC_PCLKEN1_EPWM10EN_M | RCC_PCLKEN1_EPWM9EN_M | RCC_PCLKEN1_EPWM8EN_M |
|
||||
RCC_PCLKEN1_EPWM7EN_M | RCC_PCLKEN1_EPWM6EN_M | RCC_PCLKEN1_EPWM5EN_M |
|
||||
RCC_PCLKEN1_EPWM4EN_M | RCC_PCLKEN1_EPWM3EN_M | RCC_PCLKEN1_EPWM2EN_M |
|
||||
RCC_PCLKEN1_EPWM1EN_M);
|
||||
|
||||
RCC_enableApb2PeripheralClock(RCC_PCLKEN2_CMPSS11EN_M | RCC_PCLKEN2_CMPSS10EN_M | RCC_PCLKEN2_CMPSS9EN_M |
|
||||
RCC_PCLKEN2_SDFM1EN_M | RCC_PCLKEN2_CMPSS8EN_M | RCC_PCLKEN2_CMPSS7EN_M |
|
||||
RCC_PCLKEN2_CMPSS6EN_M | RCC_PCLKEN2_CMPSS5EN_M | RCC_PCLKEN2_CMPSS4EN_M |
|
||||
RCC_PCLKEN2_CMPSS3EN_M | RCC_PCLKEN2_CMPSS2EN_M | RCC_PCLKEN2_CMPSS1EN_M |
|
||||
RCC_PCLKEN2_XBAREN_M | RCC_PCLKEN2_ADCDEN_M | RCC_PCLKEN2_ADCCEN_M |
|
||||
RCC_PCLKEN2_ADCBEN_M | RCC_PCLKEN2_ADCAEN_M | RCC_PCLKEN2_SDFM4EN_M |
|
||||
RCC_PCLKEN2_SDFM3EN_M | RCC_PCLKEN2_SDFM2EN_M);
|
||||
|
||||
RCC_enableApb3PeripheralClock(RCC_PCLKEN3_ANALOGSS_M | RCC_PCLKEN3_DAC3EN_M | RCC_PCLKEN3_DAC1EN_M);
|
||||
|
||||
RCC_enableApb5PeripheralClock(RCC_PCLKEN5_DCC1EN_M | RCC_PCLKEN5_CPUXWWDGEN_M | RCC_PCLKEN5_EPGEN_M |
|
||||
RCC_PCLKEN5_PMBUSEN_M | RCC_PCLKEN5_I2C2EN_M | RCC_PCLKEN5_I2C1EN_M |
|
||||
RCC_PCLKEN5_SPI4EN_M | RCC_PCLKEN5_SPI3EN_M | RCC_PCLKEN5_SPI2EN_M |
|
||||
RCC_PCLKEN5_SPI1EN_M | RCC_PCLKEN5_UART4EN_M | RCC_PCLKEN5_UART3EN_M |
|
||||
RCC_PCLKEN5_UART2EN_M | RCC_PCLKEN5_UART1EN_M);
|
||||
|
||||
RCC_enableApb6PeripheralClock(RCC_PCLKEN6_DCC3EN_M | RCC_PCLKEN6_DCC2EN_M | RCC_PCLKEN6_BTIM2EN_M |
|
||||
RCC_PCLKEN6_BTIM1EN_M | RCC_PCLKEN6_CPUXSTIM3EN_M | RCC_PCLKEN6_CPUXSTIM2EN_M |
|
||||
RCC_PCLKEN6_CPUXSTIM1EN_M | RCC_PCLKEN6_CLB6EN_M | RCC_PCLKEN6_CLB5EN_M |
|
||||
RCC_PCLKEN6_CLB4EN_M | RCC_PCLKEN6_CLB3EN_M | RCC_PCLKEN6_CLB2EN_M |
|
||||
RCC_PCLKEN6_CLB1EN_M | RCC_PCLKEN6_TIM2EN_M | RCC_PCLKEN6_TIM1EN_M);
|
||||
|
||||
RCC_enableApb8PeripheralClock(RCC_PCLKEN8_ADCAGG2EN_M | RCC_PCLKEN8_ADCAGG1EN_M | RCC_PCLKEN8_ADCCHK8EN_M |
|
||||
RCC_PCLKEN8_ADCCHK7EN_M | RCC_PCLKEN8_ADCCHK6EN_M | RCC_PCLKEN8_ADCCHK5EN_M |
|
||||
RCC_PCLKEN8_ADCCHK4EN_M | RCC_PCLKEN8_ADCCHK3EN_M | RCC_PCLKEN8_ADCCHK2EN_M |
|
||||
RCC_PCLKEN8_ADCCHK1EN_M | RCC_PCLKEN8_AWKEN_M | RCC_PCLKEN8_LPTIMEN_M |
|
||||
RCC_PCLKEN8_IWDG2EN_M | RCC_PCLKEN8_CPUXIWDG1EN_M | RCC_PCLKEN8_PWREN_M);
|
||||
|
||||
RCC_lockRccRegister();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock all peripheral registers.
|
||||
*/
|
||||
void Device_unlockPeriphReg (void)
|
||||
{
|
||||
/* Enables register writing function about FMU/ECAP/EPWM/XBAR/CMPSS/SDFM/DAC/ANASS/ADC/PGA/GPIO */
|
||||
SYSCON->SYSEALLOW1.WORDVAL = 0x7FFFFFFF;
|
||||
SYSCON->SYSEALLOW2.WORDVAL = 0x7FFFFFFF;
|
||||
SYSCON->SYSEALLOW3.WORDVAL = 0x00003FFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable clocks for all peripherals.
|
||||
*/
|
||||
void Device_disableAllPeripherals (void)
|
||||
{
|
||||
RCC_unlockRccRegister();
|
||||
|
||||
RCC_disableAhb1PeripheralClock(RCC_HCLKEN1_UPPEN_M | RCC_HCLKEN1_EMIFEN_M | RCC_HCLKEN1_SEMAEN_M |
|
||||
RCC_HCLKEN1_MUEN_M | RCC_HCLKEN1_GPIOHEN_M | RCC_HCLKEN1_GPIOGEN_M |
|
||||
RCC_HCLKEN1_GPIOFEN_M | RCC_HCLKEN1_GPIOEEN_M | RCC_HCLKEN1_GPIODEN_M |
|
||||
RCC_HCLKEN1_GPIOCEN_M | RCC_HCLKEN1_GPIOBEN_M | RCC_HCLKEN1_GPIOAEN_M |
|
||||
RCC_HCLKEN1_EMATHEN_M | RCC_HCLKEN1_QSPIEN_M | RCC_HCLKEN1_CPUXMMATHEN_M |
|
||||
RCC_HCLKEN1_EDMA2EN_M | RCC_HCLKEN1_EDMA1EN_M | RCC_HCLKEN1_DMAMUX2EN_M |
|
||||
RCC_HCLKEN1_DMAMUX1EN_M | RCC_HCLKEN1_SMPUEN_M | RCC_HCLKEN1_FMUEN_M);
|
||||
|
||||
RCC_disableAhb2PeripheralClock(RCC_HCLKEN2_CANFD2EN_M | RCC_HCLKEN2_CANFD1EN_M | RCC_HCLKEN2_CAN1EN_M |
|
||||
RCC_HCLKEN2_LIN2EN_M | RCC_HCLKEN2_LIN1EN_M | RCC_HCLKEN2_BGCRC2EN_M |
|
||||
RCC_HCLKEN2_BGCRC1EN_M | RCC_HCLKEN2_CRC2EN_M | RCC_HCLKEN2_CRC1EN_M |
|
||||
RCC_HCLKEN2_AESHASHEN_M |RCC_HCLKEN2_TRNGEN_M);
|
||||
|
||||
RCC_disableApb1PeripheralClock(RCC_PCLKEN1_EPWM18EN_M | RCC_PCLKEN1_EPWM17EN_M | RCC_PCLKEN1_EQEP6EN_M |
|
||||
RCC_PCLKEN1_EQEP5EN_M | RCC_PCLKEN1_EQEP4EN_M | RCC_PCLKEN1_EQEP3EN_M |
|
||||
RCC_PCLKEN1_EQEP2EN_M | RCC_PCLKEN1_EQEP1EN_M | RCC_PCLKEN1_ECAP7EN_M |
|
||||
RCC_PCLKEN1_ECAP6EN_M | RCC_PCLKEN1_ECAP5EN_M | RCC_PCLKEN1_ECAP4EN_M |
|
||||
RCC_PCLKEN1_ECAP3EN_M | RCC_PCLKEN1_ECAP2EN_M | RCC_PCLKEN1_ECAP1EN_M |
|
||||
RCC_PCLKEN1_EPWM16EN_M | RCC_PCLKEN1_EPWM15EN_M | RCC_PCLKEN1_EPWM14EN_M |
|
||||
RCC_PCLKEN1_EPWM13EN_M | RCC_PCLKEN1_EPWM12EN_M | RCC_PCLKEN1_EPWM11EN_M |
|
||||
RCC_PCLKEN1_EPWM10EN_M | RCC_PCLKEN1_EPWM9EN_M | RCC_PCLKEN1_EPWM8EN_M |
|
||||
RCC_PCLKEN1_EPWM7EN_M | RCC_PCLKEN1_EPWM6EN_M | RCC_PCLKEN1_EPWM5EN_M |
|
||||
RCC_PCLKEN1_EPWM4EN_M | RCC_PCLKEN1_EPWM3EN_M | RCC_PCLKEN1_EPWM2EN_M |
|
||||
RCC_PCLKEN1_EPWM1EN_M);
|
||||
|
||||
RCC_disableApb2PeripheralClock(RCC_PCLKEN2_CMPSS11EN_M | RCC_PCLKEN2_CMPSS10EN_M | RCC_PCLKEN2_CMPSS9EN_M |
|
||||
RCC_PCLKEN2_SDFM1EN_M | RCC_PCLKEN2_CMPSS8EN_M | RCC_PCLKEN2_CMPSS7EN_M |
|
||||
RCC_PCLKEN2_CMPSS6EN_M | RCC_PCLKEN2_CMPSS5EN_M | RCC_PCLKEN2_CMPSS4EN_M |
|
||||
RCC_PCLKEN2_CMPSS3EN_M | RCC_PCLKEN2_CMPSS2EN_M | RCC_PCLKEN2_CMPSS1EN_M |
|
||||
RCC_PCLKEN2_XBAREN_M | RCC_PCLKEN2_ADCDEN_M | RCC_PCLKEN2_ADCCEN_M |
|
||||
RCC_PCLKEN2_ADCBEN_M | RCC_PCLKEN2_ADCAEN_M | RCC_PCLKEN2_SDFM4EN_M |
|
||||
RCC_PCLKEN2_SDFM3EN_M | RCC_PCLKEN2_SDFM2EN_M);
|
||||
|
||||
RCC_disableApb3PeripheralClock(RCC_PCLKEN3_ANALOGSS_M | RCC_PCLKEN3_DAC3EN_M | RCC_PCLKEN3_DAC1EN_M);
|
||||
|
||||
RCC_disableApb5PeripheralClock(RCC_PCLKEN5_DCC1EN_M | RCC_PCLKEN5_CPUXWWDGEN_M | RCC_PCLKEN5_EPGEN_M |
|
||||
RCC_PCLKEN5_PMBUSEN_M | RCC_PCLKEN5_I2C2EN_M | RCC_PCLKEN5_I2C1EN_M |
|
||||
RCC_PCLKEN5_SPI4EN_M | RCC_PCLKEN5_SPI3EN_M | RCC_PCLKEN5_SPI2EN_M |
|
||||
RCC_PCLKEN5_SPI1EN_M | RCC_PCLKEN5_UART4EN_M |RCC_PCLKEN5_UART3EN_M |
|
||||
RCC_PCLKEN5_UART2EN_M | RCC_PCLKEN5_UART1EN_M);
|
||||
|
||||
RCC_disableApb6PeripheralClock(RCC_PCLKEN6_DCC3EN_M | RCC_PCLKEN6_DCC2EN_M | RCC_PCLKEN6_BTIM2EN_M |
|
||||
RCC_PCLKEN6_BTIM1EN_M | RCC_PCLKEN6_CPUXSTIM3EN_M | RCC_PCLKEN6_CPUXSTIM2EN_M |
|
||||
RCC_PCLKEN6_CPUXSTIM1EN_M | RCC_PCLKEN6_CLB6EN_M | RCC_PCLKEN6_CLB5EN_M |
|
||||
RCC_PCLKEN6_CLB4EN_M | RCC_PCLKEN6_CLB3EN_M | RCC_PCLKEN6_CLB2EN_M |
|
||||
RCC_PCLKEN6_CLB1EN_M | RCC_PCLKEN6_TIM2EN_M | RCC_PCLKEN6_TIM1EN_M);
|
||||
|
||||
RCC_disableApb8PeripheralClock(RCC_PCLKEN8_ADCAGG2EN_M | RCC_PCLKEN8_ADCAGG1EN_M | RCC_PCLKEN8_ADCCHK8EN_M |
|
||||
RCC_PCLKEN8_ADCCHK7EN_M | RCC_PCLKEN8_ADCCHK6EN_M | RCC_PCLKEN8_ADCCHK5EN_M |
|
||||
RCC_PCLKEN8_ADCCHK4EN_M | RCC_PCLKEN8_ADCCHK3EN_M | RCC_PCLKEN8_ADCCHK2EN_M |
|
||||
RCC_PCLKEN8_ADCCHK1EN_M | RCC_PCLKEN8_AWKEN_M | RCC_PCLKEN8_LPTIMEN_M |
|
||||
RCC_PCLKEN8_IWDG2EN_M | RCC_PCLKEN8_CPUXIWDG1EN_M | RCC_PCLKEN8_PWREN_M);
|
||||
RCC_lockRccRegister();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock all peripheral registers.
|
||||
*/
|
||||
void Device_lockPeriphReg (void)
|
||||
{
|
||||
/* Enables register writing function about FMU/ECAP/EPWM/XBAR/CMPSS/SDFM/DAC/ANASS/ADC/PGA/GPIO */
|
||||
SYSCON->SYSEALLOW1.WORDVAL = 0x00000000;
|
||||
SYSCON->SYSEALLOW2.WORDVAL = 0x00000000;
|
||||
SYSCON->SYSEALLOW3.WORDVAL = 0x00000000;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,288 @@
|
||||
/**
|
||||
* @file board.h
|
||||
* @author Haven-X
|
||||
* @brief Header file of board.c
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2025 Novosense Limited.
|
||||
* All rights reserved.</center></h2>
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "NS800RTxxxx.h"
|
||||
#include "drv_common.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define NS800_FLASH_START_ADRESS ((uint32_t)0x08000000)
|
||||
#define NS800_FLASH_SIZE (512 * 1024)
|
||||
#define NS800_FLASH_END_ADDRESS ((uint32_t)(NS800_FLASH_START_ADRESS + NS800_FLASH_SIZE))
|
||||
|
||||
#define NS800RT7P65_SRAM_SIZE (256)
|
||||
|
||||
extern int Image$$RW_RT_HEAD$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_RT_HEAD$$Limit)
|
||||
#define HEAP_END ((uint32_t)&Image$$RW_RT_HEAD$$Limit + 0x4000)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup BOARD_LEDx_PIN Board LEDx PIN
|
||||
* @{
|
||||
* @brief Defines configuration macros for board ledx pin.
|
||||
*/
|
||||
#define BOARD_LED1_PIN GPIO_68 /* reserve */
|
||||
#define BOARD_LED2_PIN GPIO_69 /* reserve */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BOARD_SWITCHx_PIN Board SWITCHx PIN
|
||||
* @{
|
||||
* @brief Defines configuration macros for board switchx pin.
|
||||
*/
|
||||
#define BOARD_KEY_PIN GPIO_41
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SERIAL_COM_PIN Serial Com port Pins
|
||||
* @{
|
||||
* @brief Defines configuration macros for serial com port pin.
|
||||
*/
|
||||
#define BOARD_SERIALCOM_TX_PIN GPIO_12
|
||||
#define BOARD_SERIALCOM_RX_PIN GPIO_13
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define BOARD_SERIALCOM_BAUDRATE (115200UL)
|
||||
#define BOARD_SERIALCOM UART1
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/** @defgroup HXTL_CONFIG High-Speed Crystal Oscillator (HXTL) Configuration
|
||||
* @{
|
||||
* @brief Defines configuration macros for the High-Speed Crystal Oscillator (HXTL).
|
||||
*/
|
||||
#ifdef SYSCLK_SOURCE_USE_HXTL
|
||||
#define HXTL_CONFIG ((RCC_HXTL_FILT_ENABLE << 15) | \
|
||||
(RCC_HXTL_FEEDBACK_RES_0_8M << 13) | \
|
||||
(RCC_HXTL_FEEDBACK_ENABLE << 12) | \
|
||||
(RCC_HXTL_STARTUP_16384 << 8) | \
|
||||
RCC_HXTL_24M_AGC_DISABLE)
|
||||
|
||||
#else
|
||||
#define HXTL_CONFIG 0U
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PLL_CONFIG PLL Configuration
|
||||
* @{
|
||||
* @brief Defines configuration macros for the Phase-Locked Loop (PLL).
|
||||
* @note Will configure the clock as follows:
|
||||
* PLL_SYSCLK = PLLSOURCE * PLLM / ( (PLLN+1) * (2 * (PLLP+1)))
|
||||
*
|
||||
* PLLSOURCE optional: \b HXTL_FREQ_VALUE
|
||||
* \b MIRC1_FREQ_VALUE
|
||||
* \b MIRC2_FREQ_VALUE
|
||||
* Example:
|
||||
* if PLLSOURCE = HXTL_FREQ_VALUE = 20Mhz, PLLM_40, PLLN_DIV1, PLLP_DIV2,
|
||||
*
|
||||
* PLL_SYSCLK = 20Mhz * 40 / ( (0+1) * (2 * (0+1)) ) = 400MHz
|
||||
*/
|
||||
#ifdef SYSCLK_USE_PLL
|
||||
#ifdef PLLCLK_SOURCE_USE_HXTL
|
||||
#define PLL_CONFIG ((RCC_PLLM_40 << 8) | \
|
||||
(RCC_PLLN_DIV1 << 4) | \
|
||||
(RCC_PLLP_DIV2 << 17) | \
|
||||
(RCC_PLLSOURCE_HXTL))
|
||||
#else /* ndef PLLCLK_SOURCE_USE_HXTL */
|
||||
#ifdef PLLCLK_SOURCE_USE_MIRC2
|
||||
#define PLL_CONFIG ((RCC_PLLM_80 << 8) | \
|
||||
(RCC_PLLN_DIV1 << 4) | \
|
||||
(RCC_PLLP_DIV2 << 17) | \
|
||||
(RCC_PLLSOURCE_MIRC2))
|
||||
#else /* ndef PLLCLK_SOURCE_USE_MIRC2 */
|
||||
#define PLL_CONFIG ((RCC_PLLM_52 << 8) | \
|
||||
(RCC_PLLN_DIV1 << 4) | \
|
||||
(RCC_PLLP_DIV2 << 17) | \
|
||||
(RCC_PLLSOURCE_MIRC1))
|
||||
#endif /* PLLCLK_SOURCE_USE_MIRC2 */
|
||||
#endif /* PLLCLK_SOURCE_USE_HXTL */
|
||||
#else /* ndef SYSCLK_USE_PLL */
|
||||
#define PLL_CONFIG 0U
|
||||
#endif /* SYSCLK_USE_PLL */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup PLL_EXT_CONFIG PLL Extended Configuration
|
||||
* @{
|
||||
* @brief Defines configuration macros for the Phase-Locked Loop (PLL) extended settings.
|
||||
*/
|
||||
#ifdef SYSCLK_USE_PLL
|
||||
#define PLL_EXT_CONFIG ((RCC_PLLQ_DIV8 << 27) | \
|
||||
(RCC_PLLR_DIV8 << 22) | \
|
||||
(RCC_PLL_FORCELK_DISABLE << 18) | \
|
||||
(RCC_PLL_LKDT_SEL_0 << 16) | \
|
||||
(RCC_PLL_LOOP_FILTER_CAP_84PF << 8) | \
|
||||
(RCC_PLL_CHARGE_PUMP_CURRENT_4UA << 4) | \
|
||||
(RCC_PLL_LOOP_FILTER_RES_10K << 2) | \
|
||||
(RCC_PLL_VCO_400_800M))
|
||||
#else
|
||||
#define PLL_EXT_CONFIG 0U
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYS_CLOCK_DIV_CONFIG Systerm Clock Division Configuration
|
||||
* @{
|
||||
* @brief Defines macros for configuring system clock division settings.
|
||||
*/
|
||||
#ifdef SYSCLK_USE_PLL
|
||||
#define SYSCLOCK_CFGR_DIV_CONFIG ((RCC_APB5_HCLK_DIV4 << 28) | \
|
||||
(RCC_APB2_4_HCLK_DIV1 << 24) | \
|
||||
(RCC_APB1_3_HCLK_DIV1 << 20) | \
|
||||
(RCC_HCLKSOURCE_CPUCLK_2 << 12) | \
|
||||
(RCC_SYSCLK_DIV1 << 8))
|
||||
#define SYSCLOCK_CFGR2_DIV_CONFIG ((RCC_FLASH_DIV_2 << 0) | \
|
||||
(RCC_TRACE_DIV_2 << 4) | \
|
||||
(RCC_EMIF_DIV_2 << 8) | \
|
||||
(RCC_EPWM_DIV_1 << 12))
|
||||
|
||||
#else
|
||||
#define SYSCLOCK_CFGR_DIV_CONFIG ((RCC_APB5_HCLK_DIV1 << 28) | \
|
||||
(RCC_APB2_4_HCLK_DIV1 << 24) | \
|
||||
(RCC_APB1_3_HCLK_DIV1 << 20) | \
|
||||
(RCC_HCLKSOURCE_CPUCLK << 12) | \
|
||||
(RCC_SYSCLK_DIV1 << 8))
|
||||
#define SYSCLOCK_CFGR2_DIV_CONFIG ((RCC_FLASH_DIV_1 << 0) | \
|
||||
(RCC_TRACE_DIV_1 << 4) | \
|
||||
(RCC_EMIF_DIV_1 << 8) | \
|
||||
(RCC_EPWM_DIV_1 << 12))
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SYSTICK_TIME_UNIT (1000UL) /*!< Uint: 1M */
|
||||
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Functions
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* \brief Function to initialize the device.
|
||||
* \note Mainly initialize the system clock and enable all peripheral clocks.
|
||||
*/
|
||||
void Device_init(void);
|
||||
|
||||
/**
|
||||
* \brief Set up clock source selection, PLL control, and clock dividers.
|
||||
*/
|
||||
void System_setClock(void);
|
||||
|
||||
/**
|
||||
* \brief Enable clocks for all peripherals.
|
||||
*/
|
||||
void Device_enableAllPeripherals(void);
|
||||
|
||||
/**
|
||||
* \brief Unlock all peripheral registers.
|
||||
*/
|
||||
void Device_unlockPeriphReg (void);
|
||||
|
||||
/**
|
||||
* \brief Disable clocks for all peripherals.
|
||||
*/
|
||||
void Device_disableAllPeripherals (void);
|
||||
|
||||
/**
|
||||
*\@brief Lock all peripheral registers.
|
||||
*/
|
||||
void Device_lockPeriphReg (void);
|
||||
|
||||
/**
|
||||
*\@brief All peripherals are hung on the CUP1
|
||||
*/
|
||||
void Device_enableAllPeripheralsInCpu1 (void);
|
||||
|
||||
|
||||
/**
|
||||
* \brief Board Initialization.
|
||||
* \note Call this function in your application if you wish to do all module
|
||||
* initialization.
|
||||
* If you wish to not use some of the initializations, instead of the
|
||||
* Board_init use the individual Module_inits.
|
||||
*/
|
||||
void Board_init (void);
|
||||
|
||||
/**
|
||||
* \brief PinMux Initialization.
|
||||
* \note Call this function in your application if you want all
|
||||
* PinMux initialization to be done.
|
||||
*/
|
||||
void PinMux_init (void);
|
||||
|
||||
/**
|
||||
* \brief Board Serial Communication Interface Initialization.
|
||||
* \note Call this function in the application to initialize the SCI serial port
|
||||
* on the board for outputting debugging information.
|
||||
*/
|
||||
void SerialCOM_init(void);
|
||||
|
||||
/**
|
||||
* \brief Board LED Initialization.
|
||||
* \note Call this function in the application to initialize the LED
|
||||
* on the board.
|
||||
*/
|
||||
void LED_init (void);
|
||||
|
||||
/**
|
||||
* \brief Board Switch Initialization.
|
||||
* \note Call this function in the application to initialize the Switch
|
||||
* on the board.
|
||||
*/
|
||||
void Switch_init (void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __BOARD_H__ */
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000400;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20011FFF;
|
||||
define symbol __ICFEDIT_region_VTRAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_VTRAM_end__ = 0x200003FF;
|
||||
define symbol __ICFEDIT_region_HEAP_start__ = 0x20012000;
|
||||
define symbol __ICFEDIT_region_HEAP_end__ = 0x20015FFF;
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x20016000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_SRAM1_start__ = 0x20100000;
|
||||
define symbol __ICFEDIT_region_SRAM1_end__ = 0x2011FFFF;
|
||||
define symbol __ICFEDIT_region_SRAM2_start__ = 0x20120000;
|
||||
define symbol __ICFEDIT_region_SRAM2_end__ = 0x2013FFFF;
|
||||
define symbol __ICFEDIT_region_BKPSRAM_start__ = 0x400B7000;
|
||||
define symbol __ICFEDIT_region_BKPSRAM_end__ = 0x400B7FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x0000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region VTRAM_region = mem:[from __ICFEDIT_region_VTRAM_start__ to __ICFEDIT_region_VTRAM_end__];
|
||||
define region HEAP_region = mem:[from __ICFEDIT_region_HEAP_start__ to __ICFEDIT_region_HEAP_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
define region SRAM1_region = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__];
|
||||
define region SRAM2_region = mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
|
||||
define region BKPSRAM_region = mem:[from __ICFEDIT_region_BKPSRAM_start__ to __ICFEDIT_region_BKPSRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit, section .bss.bkupsram };
|
||||
|
||||
define exported symbol Image$$RW_RT_HEAD$$Base = __ICFEDIT_region_HEAP_start__;
|
||||
define exported symbol Image$$RW_RT_HEAD$$Limit = __ICFEDIT_region_HEAP_start__;
|
||||
define exported symbol Image$$RW_RT_HEAD$$End = __ICFEDIT_region_HEAP_end__ + 1;
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, last block CSTACK };
|
||||
place in VTRAM_region { section .vt_dtcm };
|
||||
place in RAM2_region { section .dtcm_ext };
|
||||
place in SRAM1_region { section .sram1 };
|
||||
place in SRAM2_region { section .sram2 };
|
||||
place in BKPSRAM_region { section .bss.bkupsram };
|
||||
@@ -0,0 +1,207 @@
|
||||
/*
|
||||
* GNU ld linker script for NS800RT7P65 (Cortex-M7)
|
||||
*
|
||||
* Memory layout derived from the existing MDK scatter file:
|
||||
* FLASH 0x08000000 512K
|
||||
* VT_DTCM 0x20000000 1K
|
||||
* DTCM 0x20000400 71K (general RW/ZI/stack region)
|
||||
* RT_HEAP 0x20012000 16K (reserved for rt_system_heap_init)
|
||||
* DTCM_EXT 0x20016000 40K (extra named sections only)
|
||||
* SRAM1 0x20100000 128K
|
||||
* SRAM2 0x20120000 128K
|
||||
* BKPSRAM 0x400B7000 4K
|
||||
*/
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
_system_stack_size = 0x1000;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
VT_DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x400
|
||||
DTCM (rwx) : ORIGIN = 0x20000400, LENGTH = 0x11C00
|
||||
RT_HEAP (rwx) : ORIGIN = 0x20012000, LENGTH = 0x4000
|
||||
DTCM_EXT (rwx) : ORIGIN = 0x20016000, LENGTH = 0xA000
|
||||
SRAM1 (rwx) : ORIGIN = 0x20100000, LENGTH = 0x20000
|
||||
SRAM2 (rwx) : ORIGIN = 0x20120000, LENGTH = 0x20000
|
||||
BKPSRAM (rwx) : ORIGIN = 0x400B7000, LENGTH = 0x1000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector))
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
*(.itcm)
|
||||
*(.itcm*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} > FLASH = 0
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
_sidata = .;
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
*(.dtcm)
|
||||
*(.dtcm*)
|
||||
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .;
|
||||
} > DTCM
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > DTCM
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
|
||||
*(.bss.init)
|
||||
} > DTCM
|
||||
__bss_end = .;
|
||||
|
||||
.vt_dtcm (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.vt_dtcm)
|
||||
*(.vt_dtcm*)
|
||||
. = ALIGN(4);
|
||||
} > VT_DTCM
|
||||
|
||||
.sram1 (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.sram1)
|
||||
*(.sram1*)
|
||||
. = ALIGN(4);
|
||||
} > SRAM1
|
||||
|
||||
.sram2 (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.sram2)
|
||||
*(.sram2*)
|
||||
. = ALIGN(4);
|
||||
} > SRAM2
|
||||
|
||||
.bkupsram (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.bss.bkupsram)
|
||||
*(.bss.bkupsram*)
|
||||
. = ALIGN(4);
|
||||
} > BKPSRAM
|
||||
|
||||
.dtcm_ext (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.dtcm_ext)
|
||||
*(.dtcm_ext*)
|
||||
. = ALIGN(4);
|
||||
} > DTCM_EXT
|
||||
|
||||
.rt_heap (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE(Image$$RW_RT_HEAD$$Base = .);
|
||||
PROVIDE(Image$$RW_RT_HEAD$$Limit = .);
|
||||
PROVIDE(__rt_heap_start = .);
|
||||
. = . + LENGTH(RT_HEAP);
|
||||
. = ALIGN(8);
|
||||
PROVIDE(Image$$RW_RT_HEAD$$End = .);
|
||||
PROVIDE(__rt_heap_end = .);
|
||||
} > RT_HEAP
|
||||
|
||||
_end = .;
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
|
||||
RW_ITCM 0x00000000 0x00020000 { ; 128K ITCM -> code in sram
|
||||
.ANY (.itcm)
|
||||
}
|
||||
|
||||
RW_VT_DTCM 0x20000000 0x00000400 { ; 1K VT_DTCM -> Vector Table
|
||||
* (.vt_dtcm)
|
||||
}
|
||||
|
||||
RW_DTCM 0x20000400 0x0001FC00 { ; 127K DTCM -> fast sram
|
||||
.ANY (.dtcm, +RW +ZI)
|
||||
; startup_*.o(STACK)
|
||||
; startup_*.o(HEAP)
|
||||
}
|
||||
|
||||
RW_RT_HEAD 0x20012000 EMPTY 0x4000 {
|
||||
|
||||
}
|
||||
|
||||
; RW_SRAM1 0x20100000 0x00020000 { ; sram with ECC
|
||||
; * (.sram1)
|
||||
; }
|
||||
|
||||
; RW_SRAM2 0x20120000 0x00020000 { ; sram with ECC
|
||||
; * (.sram2)
|
||||
; }
|
||||
|
||||
; RW_SRAMB 0x400B7000 UNINIT 0x00001000 { ; sram with backup
|
||||
; * (.bss.bkupsram)
|
||||
; }
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -0,0 +1,184 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>18</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>6</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ST-LINKIII-KEIL_SWO</Key>
|
||||
<Name>-U0670FF495355878281171423 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32H743ZITx$CMSIS\Flash\STM32H7x_2048.FLM))</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>1</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>10000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,433 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
#define SOC_SERIES_NS800RT7
|
||||
#define SOC_NS800RT7P6XX
|
||||
#define BOARD_NS800RT7P65X
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
/* klibc options */
|
||||
|
||||
/* rt_vsnprintf options */
|
||||
|
||||
/* end of rt_vsnprintf options */
|
||||
|
||||
/* rt_vsscanf options */
|
||||
|
||||
/* end of rt_vsscanf options */
|
||||
|
||||
/* rt_memset options */
|
||||
|
||||
/* end of rt_memset options */
|
||||
|
||||
/* rt_memcpy options */
|
||||
|
||||
/* end of rt_memcpy options */
|
||||
|
||||
/* rt_memmove options */
|
||||
|
||||
/* end of rt_memmove options */
|
||||
|
||||
/* rt_memcmp options */
|
||||
|
||||
/* end of rt_memcmp options */
|
||||
|
||||
/* rt_strstr options */
|
||||
|
||||
/* end of rt_strstr options */
|
||||
|
||||
/* rt_strcasecmp options */
|
||||
|
||||
/* end of rt_strcasecmp options */
|
||||
|
||||
/* rt_strncpy options */
|
||||
|
||||
/* end of rt_strncpy options */
|
||||
|
||||
/* rt_strcpy options */
|
||||
|
||||
/* end of rt_strcpy options */
|
||||
|
||||
/* rt_strncmp options */
|
||||
|
||||
/* end of rt_strncmp options */
|
||||
|
||||
/* rt_strcmp options */
|
||||
|
||||
/* end of rt_strcmp options */
|
||||
|
||||
/* rt_strlen options */
|
||||
|
||||
/* end of rt_strlen options */
|
||||
|
||||
/* rt_strnlen options */
|
||||
|
||||
/* end of rt_strnlen options */
|
||||
/* end of klibc options */
|
||||
#define RT_NAME_MAX 16
|
||||
#define RT_CPUS_NR 1
|
||||
#define RT_ALIGN_SIZE 8
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice options */
|
||||
|
||||
/* end of kservice options */
|
||||
#define RT_USING_DEBUG
|
||||
#define RT_DEBUGING_ASSERT
|
||||
#define RT_DEBUGING_COLOR
|
||||
#define RT_DEBUGING_CONTEXT
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* end of Inter-Thread communication */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_SMALL_MEM
|
||||
#define RT_USING_SMALL_MEM_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
/* end of Memory Management */
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_USING_CONSOLE_OUTPUT_CTL
|
||||
#define RT_VER_NUM 0x50300
|
||||
#define RT_BACKTRACE_LEVEL_MAX_NR 32
|
||||
/* end of RT-Thread Kernel */
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
#define RT_USING_MSH
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
#define FINSH_USING_OPTION_COMPLETION
|
||||
|
||||
/* DFS: device virtual file system */
|
||||
|
||||
/* end of DFS: device virtual file system */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_UNAMED_PIPE_NUMBER 64
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_CAN
|
||||
#define RT_CAN_USING_CANFD
|
||||
#define RT_CANMSG_BOX_SZ 16
|
||||
#define RT_CANSND_BOX_NUM 1
|
||||
#define RT_CANSND_MSG_TIMEOUT 100
|
||||
#define RT_CAN_NB_TX_FIFO_SIZE 256
|
||||
#define RT_USING_PIN
|
||||
/* end of Device Drivers */
|
||||
|
||||
/* C/C++ and POSIX layer */
|
||||
|
||||
/* ISO-ANSI C layer */
|
||||
|
||||
/* Timezone and Daylight Saving Time */
|
||||
|
||||
#define RT_LIBC_USING_LIGHT_TZ_DST
|
||||
#define RT_LIBC_TZ_DEFAULT_HOUR 8
|
||||
#define RT_LIBC_TZ_DEFAULT_MIN 0
|
||||
#define RT_LIBC_TZ_DEFAULT_SEC 0
|
||||
/* end of Timezone and Daylight Saving Time */
|
||||
/* end of ISO-ANSI C layer */
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* end of Interprocess Communication (IPC) */
|
||||
/* end of POSIX (Portable Operating System Interface) layer */
|
||||
/* end of C/C++ and POSIX layer */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* end of Network */
|
||||
|
||||
/* Memory protection */
|
||||
|
||||
/* end of Memory protection */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* end of Utilities */
|
||||
|
||||
/* Using USB legacy version */
|
||||
|
||||
/* end of Using USB legacy version */
|
||||
/* end of RT-Thread Components */
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
/* end of RT-Thread Utestcases */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* end of Marvell WiFi */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* end of Wiced WiFi */
|
||||
|
||||
/* CYW43012 WiFi */
|
||||
|
||||
/* end of CYW43012 WiFi */
|
||||
|
||||
/* BL808 WiFi */
|
||||
|
||||
/* end of BL808 WiFi */
|
||||
|
||||
/* CYW43439 WiFi */
|
||||
|
||||
/* end of CYW43439 WiFi */
|
||||
/* end of Wi-Fi */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* end of IoT Cloud */
|
||||
/* end of IoT - internet of things */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* end of security packages */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
|
||||
|
||||
/* XML: Extensible Markup Language */
|
||||
|
||||
/* end of XML: Extensible Markup Language */
|
||||
/* end of language packages */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* end of LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
/* end of u8g2: a monochrome graphic library */
|
||||
/* end of multimedia packages */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* end of tools packages */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
/* end of enhanced kernel services */
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* end of acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
#define PKG_USING_CMSIS_CORE
|
||||
#define PKG_USING_CMSIS_CORE_LATEST_VERSION
|
||||
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
/* end of Micrium: Micrium software products porting for RT-Thread */
|
||||
/* end of system packages */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* HAL & SDK Drivers */
|
||||
|
||||
/* STM32 HAL & SDK Drivers */
|
||||
|
||||
/* end of STM32 HAL & SDK Drivers */
|
||||
|
||||
/* Infineon HAL Packages */
|
||||
|
||||
/* end of Infineon HAL Packages */
|
||||
|
||||
/* Kendryte SDK */
|
||||
|
||||
/* end of Kendryte SDK */
|
||||
|
||||
/* WCH HAL & SDK Drivers */
|
||||
|
||||
/* end of WCH HAL & SDK Drivers */
|
||||
|
||||
/* AT32 HAL & SDK Drivers */
|
||||
|
||||
/* end of AT32 HAL & SDK Drivers */
|
||||
|
||||
/* HC32 DDL Drivers */
|
||||
|
||||
/* end of HC32 DDL Drivers */
|
||||
|
||||
/* NXP HAL & SDK Drivers */
|
||||
|
||||
/* end of NXP HAL & SDK Drivers */
|
||||
|
||||
/* NUVOTON Drivers */
|
||||
|
||||
/* end of NUVOTON Drivers */
|
||||
|
||||
/* GD32 Drivers */
|
||||
|
||||
/* end of GD32 Drivers */
|
||||
|
||||
/* HPMicro SDK */
|
||||
|
||||
/* end of HPMicro SDK */
|
||||
|
||||
/* FT32 HAL & SDK Drivers */
|
||||
|
||||
/* end of FT32 HAL & SDK Drivers */
|
||||
|
||||
/* NOVOSNS Drivers */
|
||||
|
||||
#define PKG_USING_NOVOSNS_SERIES_DRIVER
|
||||
#define PKG_USING_NOVOSNS_SERIES_DRIVER_LATEST_VERSION
|
||||
/* end of NOVOSNS Drivers */
|
||||
/* end of HAL & SDK Drivers */
|
||||
|
||||
/* sensors drivers */
|
||||
|
||||
/* end of sensors drivers */
|
||||
|
||||
/* touch drivers */
|
||||
|
||||
/* end of touch drivers */
|
||||
/* end of peripheral libraries and drivers */
|
||||
|
||||
/* AI packages */
|
||||
|
||||
/* end of AI packages */
|
||||
|
||||
/* Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* end of Signal Processing and Control Algorithm Packages */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* end of project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
/* end of samples: kernel and components samples */
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
/* end of entertainment: terminal games and other interesting software packages */
|
||||
/* end of miscellaneous packages */
|
||||
|
||||
/* Arduino libraries */
|
||||
|
||||
|
||||
/* Projects and Demos */
|
||||
|
||||
/* end of Projects and Demos */
|
||||
|
||||
/* Sensors */
|
||||
|
||||
/* end of Sensors */
|
||||
|
||||
/* Display */
|
||||
|
||||
/* end of Display */
|
||||
|
||||
/* Timing */
|
||||
|
||||
/* end of Timing */
|
||||
|
||||
/* Data Processing */
|
||||
|
||||
/* end of Data Processing */
|
||||
|
||||
/* Data Storage */
|
||||
|
||||
/* Communication */
|
||||
|
||||
/* end of Communication */
|
||||
|
||||
/* Device Control */
|
||||
|
||||
/* end of Device Control */
|
||||
|
||||
/* Other */
|
||||
|
||||
/* end of Other */
|
||||
|
||||
/* Signal IO */
|
||||
|
||||
/* end of Signal IO */
|
||||
|
||||
/* Uncategorized */
|
||||
|
||||
/* end of Arduino libraries */
|
||||
/* end of RT-Thread online packages */
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BOARD_CLK_CONF
|
||||
#define SYSCLK_USE_PLL
|
||||
#define SYSCLK_SOURCE_USE_HXTL
|
||||
#define PLLCLK_SOURCE_USE_HXTL
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_NS800_UART_TX_TIMEOUT 6000
|
||||
#define BSP_USING_UART1
|
||||
#define BSP_USING_ECAP
|
||||
#define BSP_USING_CAN
|
||||
#define BSP_USING_CANFD1
|
||||
/* end of On-chip Peripheral Drivers */
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user