mirror of
https://github.com/RT-Thread/rt-thread.git
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[bsp][nxp] support qspi flash and filesystem for imxrt1180-evk board
This commit is contained in:
CoreBoxer
GitHub
@@ -27,7 +27,7 @@ CM33对CM7的kick off将在后续版本中支持。
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| **板载外设** | **支持情况** | **备注** |
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| :----------------- | :----------: | :------------------------------------|
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| USB 转串口 | 暂不支持 | |
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| SPI Flash | 暂不支持 | |
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| SPI Flash | 支持 | |
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| 以太网 | 暂不支持 | |
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 暂不支持 | |
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@@ -0,0 +1,11 @@
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scons.args: &scons
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scons_arg:
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- '--strict'
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# ------ component CI ------
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# ------ Peripheral CI ------
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Peripheral.flash_fs:
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<<: *scons
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kconfig:
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- CONFIG_BSP_USING_QSPI_FLASH_FS=y
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@@ -0,0 +1,100 @@
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/*
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* Copyright (c) 2019-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2026-06-02 CoreBoxer add LittleFS on QSPI NOR Flash (IMXRT1180-EVK)
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*/
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#include <rtthread.h>
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/* ====================================================================
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* QSPI NOR Flash LittleFS (controlled by BSP_USING_QSPI_FLASH_FS)
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*
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* Dependencies:
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* - drv_flash.c (Flash read/write/erase driver via ROM API)
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* - FAL framework (partition management)
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* - LittleFS component (RT-Thread package)
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*
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* FAL partition configuration (fal_cfg.h):
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* "filesystem" partition → filesystem area of norflash0
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*
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* Mount procedure:
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* 1. Find FAL partition to confirm correct configuration
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* 2. Create MTD NOR block device
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* 3. Try direct mount (for already formatted filesystem)
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* 4. If failed, perform mkfs then remount (first use or format scenario)
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* ==================================================================== */
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#ifdef BSP_USING_QSPI_FLASH_FS
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#include <dfs_fs.h>
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#include <fal.h>
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#define FS_PARTITION_NAME "filesystem"
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#define FS_TYPE_NAME "lfs"
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#define FS_MOUNT_POINT "/"
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static int _qspi_flash_fs_mount(void)
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{
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struct fal_mtd_nor_device *mtd_dev;
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int ret;
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/* Find FAL partition to confirm configuration is correct */
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if (fal_partition_find(FS_PARTITION_NAME) == RT_NULL)
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{
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rt_kprintf("[qspi_fs] partition '%s' not found, check fal_cfg.h\n",
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FS_PARTITION_NAME);
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return -RT_ERROR;
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}
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/* Create MTD NOR block device for filesystem partition */
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mtd_dev = (struct fal_mtd_nor_device *)fal_mtd_nor_device_create(FS_PARTITION_NAME);
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if (mtd_dev == RT_NULL)
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{
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rt_kprintf("[qspi_fs] failed to create MTD NOR device for '%s'\n",
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FS_PARTITION_NAME);
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return -RT_ERROR;
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}
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/* Try direct mount (for already formatted flash) */
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ret = dfs_mount(FS_PARTITION_NAME, FS_MOUNT_POINT, FS_TYPE_NAME, 0, 0);
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if (ret == 0)
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{
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rt_kprintf("[qspi_fs] '%s' mounted at '%s'\n",
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FS_PARTITION_NAME, FS_MOUNT_POINT);
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return RT_EOK;
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}
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/* Mount failed, indicating flash is not formatted (first use scenario), perform mkfs */
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rt_kprintf("[qspi_fs] mount failed (ret=%d), formatting '%s'...\n",
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ret, FS_PARTITION_NAME);
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ret = dfs_mkfs(FS_TYPE_NAME, FS_PARTITION_NAME);
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if (ret != 0)
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{
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rt_kprintf("[qspi_fs] mkfs failed (ret=%d)\n", ret);
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return -RT_ERROR;
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}
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/* Remount after successful mkfs */
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ret = dfs_mount(FS_PARTITION_NAME, FS_MOUNT_POINT, FS_TYPE_NAME, 0, 0);
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if (ret != 0)
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{
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rt_kprintf("[qspi_fs] mount failed after mkfs (ret=%d)\n", ret);
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return -RT_ERROR;
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}
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rt_kprintf("[qspi_fs] '%s' formatted and mounted at '%s'\n",
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FS_PARTITION_NAME, FS_MOUNT_POINT);
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return RT_EOK;
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}
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INIT_APP_EXPORT(_qspi_flash_fs_mount);
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/*
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* FAL initialization registered as INIT_COMPONENT_EXPORT:
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* after Flash driver (INIT_DEVICE_EXPORT)
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* before filesystem mount (INIT_APP_EXPORT)
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*/
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INIT_COMPONENT_EXPORT(fal_init);
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#endif /* BSP_USING_QSPI_FLASH_FS */
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@@ -229,6 +229,16 @@ menu "Onboard Peripheral Drivers"
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select BSP_USING_SDIO
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select RT_USING_DFS_ELMFAT
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default n
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config BSP_USING_QSPI_FLASH_FS
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bool "Enable QSPI Flash (LittleFS)"
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select BSP_USING_FLEXSPI
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select BSP_USING_FLEXSPI1
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select RT_USING_FAL
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select FAL_PART_HAS_TABLE_CFG
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select RT_USING_MTD_NOR
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select PKG_USING_LITTLEFS
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default n
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endif
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endmenu
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@@ -12,6 +12,9 @@ MCUX_Config/clock_config.c
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MCUX_Config/pin_mux.c
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""")
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if GetDepend(['BSP_USING_QSPI_FLASH_FS']):
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src += ['ports/drv_flexspi_nor_flash.c', 'ports/fal_flash_port.c']
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CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
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CPPDEFINES = ['CPU_MIMXRT1189CVM8C_cm33', 'MCUXPRESSO_SDK', 'MCUX_META_BUILD', 'MIMXRT1189_cm33_SERIES', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'XIP_EXTERNAL_FLASH=1', 'ARM_MATH_CM33']
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@@ -173,6 +173,7 @@ LR_m_text m_text_start m_text_size
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ER_m_QuickAccessCode m_qacode_start m_qacode_size
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{
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fsl_flexspi.o (+RO-CODE)
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.ANY (CodeQuickAccess)
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,59 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-06-03 CoreBoxer support IMXRT1180-EVK
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*/
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#ifndef __DRV_FLEXSPI_NOR_FLASH_H__
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#define __DRV_FLEXSPI_NOR_FLASH_H__
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#include <rtthread.h>
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/* ============================================================
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* Flash Physical Parameters
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* Source: SDK example app.h
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* FLASH_SIZE = 0x4000 (Unit: KB) = 16MB
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* FlexSPI1_AMBA_BASE = 0x28000000
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* ============================================================ */
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#define QSPI_FLASH_BASE FlexSPI1_AMBA_BASE /* 0x28000000 */
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#define QSPI_FLASH_SIZE (0x4000U * 1024U) /* 16MB (0x4000 KB) */
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#define QSPI_SECTOR_SIZE 0x00001000U /* 4KB */
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#define QSPI_PAGE_SIZE 256U /* 256B */
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/*
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* Partition Plan (Total 16MB):
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* 0x00000000 ~ 0x007FFFFF: Application Code Area (8MB, limited by Scatter)
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* 0x00800000 ~ 0x00FFFFFF: File System Area (8MB, LittleFS)
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*/
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#define QSPI_FS_OFFSET 0x00800000U
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#define QSPI_FS_SIZE 0x00800000U
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/* ============================================================
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* RAM Code Section Attributes
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* Write/Erase functions placed in CodeQuickAccess (ITCM),
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* CPU can safely fetch instructions during FlexSPI IP command execution.
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* ============================================================ */
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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#define QSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline))
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#elif defined(__GNUC__)
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#define QSPI_RAM_CODE __attribute__((section(".itcm.text"), noinline))
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#elif defined(__ICCARM__)
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#define QSPI_RAM_CODE __ramfunc
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#else
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#define QSPI_RAM_CODE
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#endif
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/* ============================================================
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* External APIs
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* ============================================================ */
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int rt_qspi_flash_init(void);
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int rt_qspi_flash_read(uint32_t offset, uint8_t *buf, size_t size);
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int rt_qspi_flash_write(uint32_t offset, const uint8_t *buf, size_t size);
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int rt_qspi_flash_erase(uint32_t offset, size_t size);
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void *rt_qspi_flash_mmap(uint32_t offset, size_t size);
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#endif /* __DRV_FLEXSPI_NOR_FLASH_H__ */
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@@ -0,0 +1,37 @@
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/*
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* Copyright (c) 2006-2024, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-01-01 RT-Thread first version
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*/
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#ifndef __FAL_CFG_H__
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#define __FAL_CFG_H__
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#include <rtthread.h>
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#include <board.h>
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extern const struct fal_flash_dev imxrt1180_nor_flash;
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/* flash device table */
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#define FAL_FLASH_DEV_TABLE \
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{ \
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&imxrt1180_nor_flash, \
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}
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/* ====================== Partition Configuration ========================== */
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#ifdef FAL_PART_HAS_TABLE_CFG
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/* partition table */
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#define FAL_PART_TABLE \
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{ \
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{FAL_PART_MAGIC_WROD, "app", "norflash0", 0, 8*1024*1024, 0}, \
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{FAL_PART_MAGIC_WROD, "filesystem", "norflash0", 8*1024*1024, 8*1024*1024, 0}, \
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}
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#endif /* FAL_PART_HAS_TABLE_CFG */
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#endif /* __FAL_CFG_H__ */
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@@ -0,0 +1,57 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2026-06-03 CoreBoxer support IMXRT1180-EVK
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <fal.h>
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#include "drv_flexspi_nor_flash.h"
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/*
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* Logging configuration
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*/
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#define LOG_TAG "fal.flash"
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#define LOG_LVL LOG_LVL_INFO
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#include <rtdbg.h>
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/* FAL ops bridge */
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#ifdef RT_USING_FAL
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static int _fal_init(void)
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{
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return rt_qspi_flash_init();
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}
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static int _fal_read(long offset, rt_uint8_t *buf, size_t size)
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{
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return rt_qspi_flash_read((rt_uint32_t)offset, buf, size);
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}
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QSPI_RAM_CODE static int _fal_write(long offset, const rt_uint8_t *buf, size_t size)
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{
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return rt_qspi_flash_write((rt_uint32_t)offset, buf, size);
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}
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QSPI_RAM_CODE static int _fal_erase(long offset, size_t size)
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{
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return rt_qspi_flash_erase((rt_uint32_t)offset, size);
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}
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const struct fal_flash_dev imxrt1180_nor_flash =
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{
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.name = "norflash0",
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.addr = QSPI_FLASH_BASE,
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.len = QSPI_FLASH_SIZE,
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.blk_size = QSPI_SECTOR_SIZE,
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.ops = { _fal_init, _fal_read, _fal_write, _fal_erase },
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.write_gran = QSPI_PAGE_SIZE,
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};
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#endif /* RT_USING_FAL */
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@@ -0,0 +1,62 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-08-15 xjy198903 The first version for rt1170
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* 2026-06-03 CoreBoxer support IMXRT1180-EVK
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*/
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#ifndef FLEXSPI_PORT_H__
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#define FLEXSPI_PORT_H__
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/* parameters for flexpsi peripheral */
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#define FLEXSPI1_CONTROL_BASE FLEXSPI1
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#define FLEXSPI2_CONTROL_BASE FLEXSPI2
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#define FLEXSPI_ROOT_CLK (12000000U) /* serial root clk: 12MHz*/
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#define FLASH_SIZE (16 * 1024) /* device size 16*1024(KB) = 16MB */
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#define ARD_SEQ_NUMBER 1 /* Sequence number for AHB read command */
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#define ARD_SEQ_INDEX 0 /* Sequence ID for AHB read command */
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#define AWR_SEQ_NUMBER 0 /* Sequence number for AHB write command */
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#define AWR_SEQ_INDEX 0 /* Sequence ID for AHB write command */
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#define ARD_SEQ_CMD 0xBB /* cmd for read */
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#define AWR_SEQ_CMD 0xAA /* cmd for write */
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#define FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad
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#define FLASH_PORT kFLEXSPI_PortA1
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#define CLOCK_SRC kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc24M
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#define CLOCK_DIV 2U
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#define CUSTOM_LUT_LENGTH 60U
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#define FLEXSPI1_AHB_DATA_ADDRESS (0x28000000U)
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#define FLEXSPI2_AHB_DATA_ADDRESS (0x60000000U)
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#define COMBINATION_MODE 0U
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#define FREE_RUNNING_MODE 0U
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#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI1_AMBA_BASE
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#define FLASH_PAGE_SIZE 256
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#define SECTOR_SIZE 0x1000 /* 4K */
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#define EXAMPLE_FLEXSPI_CLOCK kCLOCK_Flexspi1
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#define FLASH_PORT kFLEXSPI_PortA1
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#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4
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#define NOR_CMD_LUT_SEQ_IDX_READID 8
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#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9
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#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
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#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12
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#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5
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#define FLASH_QUAD_ENABLE 0x40
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#define FLASH_BUSY_STATUS_POL 1
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#define FLASH_BUSY_STATUS_OFFSET 0
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#endif /* FLEXSPI_PORT_H__ */
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@@ -6,10 +6,12 @@
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* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-09-14 xjy198903 the first version for 1170
|
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* 2026-06-03 CoreBoxer support IMXRT1180-EVK
|
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*/
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#include <rtthread.h>
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#ifdef BSP_USING_FLEXSPI
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#if defined(BSP_USING_FLEXSPI) && \
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(defined(SOC_IMXRT1170_SERIES) || defined(SOC_IMXRT1180_SERIES))
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#include "board.h"
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#include <rtdevice.h>
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@@ -17,16 +19,23 @@
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#include <finsh.h>
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#endif
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#include "drv_flexspi.h"
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#include "flexspi_port.h"
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#include "fsl_flexspi.h"
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#ifndef COMBINATION_MODE
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#define COMBINATION_MODE 1U
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#endif
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#ifndef FREE_RUNNING_MODE
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#define FREE_RUNNING_MODE 1U
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#endif
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#define FLEXSPI_DEBUG
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#define LOG_TAG "drv.flexspi"
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#include <drv_log.h>
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#if defined(SOC_IMXRT1170_SERIES)
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static flexspi_device_config_t deviceconfig = {
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.flexspiRootClk = 12000000,
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.flashSize = FLASH_SIZE,
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@@ -50,6 +59,114 @@ const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
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[4 * ARD_SEQ_INDEX] =
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FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_8PAD, 0),
|
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};
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#elif defined(SOC_IMXRT1180_SERIES)
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static flexspi_device_config_t deviceconfig = {
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.flexspiRootClk = 12000000,
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.flashSize = FLASH_SIZE,
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.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
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.CSInterval = 2,
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.CSHoldTime = 3,
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.CSSetupTime = 3,
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.dataValidTime = 0,
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.columnspace = 0,
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.enableWordAddress = 0,
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.AWRSeqIndex = AWR_SEQ_INDEX,
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.AWRSeqNumber = AWR_SEQ_NUMBER,
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.ARDSeqIndex = ARD_SEQ_INDEX,
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.ARDSeqNumber = ARD_SEQ_NUMBER,
|
||||
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
|
||||
.AHBWriteWaitInterval = 0,
|
||||
};
|
||||
|
||||
const uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
|
||||
/* Normal read mode - SDR */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03,
|
||||
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04,
|
||||
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
|
||||
|
||||
/* Fast read mode - SDR */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B,
|
||||
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08,
|
||||
kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
|
||||
|
||||
/* Fast read quad mode - SDR */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB,
|
||||
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18),
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06,
|
||||
kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04),
|
||||
|
||||
/* Write Enable */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06,
|
||||
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
|
||||
|
||||
/* Erase Sector */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20,
|
||||
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
|
||||
|
||||
/* Page Program - single mode */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02,
|
||||
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
|
||||
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
|
||||
|
||||
/* Page Program - quad mode */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32,
|
||||
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04,
|
||||
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
|
||||
|
||||
/* Read ID */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READID] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F,
|
||||
kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
|
||||
|
||||
/* Write Status Register */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01,
|
||||
kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04),
|
||||
|
||||
/* Read status register */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05,
|
||||
kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04),
|
||||
|
||||
/* Erase whole chip */
|
||||
[4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7,
|
||||
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
|
||||
};
|
||||
#else
|
||||
#error "Unsupported SOC for drv_flexspi"
|
||||
#endif
|
||||
|
||||
/* --------------------------------------------------------------------------
|
||||
* Internal handle
|
||||
* -------------------------------------------------------------------------- */
|
||||
static imxrt_flexspi_handle_t s_flexspi_handle =
|
||||
{
|
||||
.base = FLEXSPI1_CONTROL_BASE,
|
||||
.port = FLASH_PORT,
|
||||
.ahb_base = FLEXSPI1_AHB_DATA_ADDRESS
|
||||
};
|
||||
|
||||
imxrt_flexspi_handle_t *imxrt_flexspi_get_handle(void)
|
||||
{
|
||||
return &s_flexspi_handle;
|
||||
}
|
||||
|
||||
static void flexspi_clock_init(clock_root_t root, uint8_t src, uint8_t div)
|
||||
{
|
||||
@@ -58,19 +175,26 @@ static void flexspi_clock_init(clock_root_t root, uint8_t src, uint8_t div)
|
||||
CLOCK_SetRootClockMux(root, src);
|
||||
}
|
||||
|
||||
static int rt_hw_imxrt_flexspi_init(void)
|
||||
FLEXSPI_RAM_CODE static int rt_hw_imxrt_flexspi_init(void)
|
||||
{
|
||||
flexspi_config_t config;
|
||||
FLEXSPI_Type *base;
|
||||
|
||||
#ifdef BSP_USING_FLEXSPI1
|
||||
base = FLEXSPI1_CONTROL_BASE;
|
||||
#else
|
||||
base = FLEXSPI2_CONTROL_BASE;
|
||||
#endif
|
||||
|
||||
s_flexspi_handle.base = FLEXSPI1_CONTROL_BASE;
|
||||
s_flexspi_handle.port = FLASH_PORT;
|
||||
s_flexspi_handle.ahb_base = FLEXSPI1_AHB_DATA_ADDRESS;
|
||||
//Set root clk 80MHz
|
||||
flexspi_clock_init(kCLOCK_Root_Flexspi1, CLOCK_SRC, CLOCK_DIV);
|
||||
#else
|
||||
base = FLEXSPI2_CONTROL_BASE;
|
||||
s_flexspi_handle.base = FLEXSPI2_CONTROL_BASE;
|
||||
s_flexspi_handle.port = FLASH_PORT;
|
||||
s_flexspi_handle.ahb_base = FLEXSPI2_AHB_DATA_ADDRESS;
|
||||
flexspi_clock_init(kCLOCK_Root_Flexspi2, CLOCK_SRC, CLOCK_DIV);
|
||||
#endif
|
||||
|
||||
|
||||
/*Get FLEXSPI default settings and configure the flexspi. */
|
||||
FLEXSPI_GetDefaultConfig(&config);
|
||||
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-06-03 CoreBoxer support IMXRT1180-EVK
|
||||
*/
|
||||
|
||||
#ifndef __DRV_FLEXSPI_H__
|
||||
#define __DRV_FLEXSPI_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "fsl_flexspi.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Put critical transfer code into ITCM (Code TCM) */
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
#define FLEXSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline))
|
||||
#elif defined(__GNUC__)
|
||||
#define FLEXSPI_RAM_CODE __attribute__((section("CodeQuickAccess"), noinline))
|
||||
#elif defined(__ICCARM__)
|
||||
#define FLEXSPI_RAM_CODE __ramfunc
|
||||
#else
|
||||
#define FLEXSPI_RAM_CODE
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
FLEXSPI_Type *base;
|
||||
flexspi_port_t port;
|
||||
uint32_t ahb_base;
|
||||
} imxrt_flexspi_handle_t;
|
||||
|
||||
/* Get initialized FlexSPI handle (FlexSPI1 or FlexSPI2 decided by BSP config) */
|
||||
imxrt_flexspi_handle_t *imxrt_flexspi_get_handle(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_FLEXSPI_H__ */
|
||||
Reference in New Issue
Block a user