[bsp][rdk s100] Add the RDC S100 BSP (#11406)

* 添加 rdk_s100 bsp

* 添加 CI 看护

.github/ALL_BSP_COMPILE.json

@@ -525,6 +525,13 @@
       "SUB_RTT_BSP": [
         "novosns/ns800/ns800rt7p65-nssinepad"
       ]
+    },
+    {
+      "RTT_BSP": "RDK",
+      "RTT_TOOL_CHAIN": "sourcery-arm",
+      "SUB_RTT_BSP": [
+        "rdk/s100"
+      ]
     }
   ]
 }

bsp/rdk/s100/Kconfig

@@ -0,0 +1,37 @@
+mainmenu "RT-Thread Configuration"
+
+BSP_DIR := .
+
+# you can change the RTT_ROOT default "rt-thread"
+# example : default "F:/git_repositories/rt-thread"
+
+PKGS_DIR := packages
+
+ENV_DIR := /
+
+config SOC_S100
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "S100 BSP Options"
+
+config RT_USING_FPU
+    bool "Enable Cortex-R52 VFP/FPU support"
+    default y
+    help
+        Enable hardware floating-point support for the S100 BSP.
+
+        When enabled, the BSP builds with hard-float ABI and enables
+        the VFP context save/restore path.
+
+        When disabled, the BSP switches to a soft-float build so O2 can
+        remain enabled without generating VFP instructions.
+
+endmenu
+
+source "$(RTT_DIR)/Kconfig"
+osource "$PKGS_DIR/Kconfig"
+# rsource "$(BSP_DIR)/board/Kconfig"
+source "$(BSP_DIR)/drivers/Kconfig"

bsp/rdk/s100/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+group = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        group = group + SConscript(os.path.join(d, 'SConscript'))
+
+Return('group')

bsp/rdk/s100/SConstruct

@@ -0,0 +1,78 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS   = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC   = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX  = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR   = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+def _replace_cortex_r52_with_startup(objects):
+    startup_dir = os.path.join(Dir('#').abspath, 'startup')
+    startup_names = set(
+        name for name in os.listdir(startup_dir)
+        if os.path.isfile(os.path.join(startup_dir, name))
+    )
+    cpu_dir = os.path.abspath(os.path.join(RTT_ROOT, 'libcpu', rtconfig.ARCH, rtconfig.CPU))
+
+    def _source_path(node):
+        for attr in ('srcnode', 'rfile'):
+            if hasattr(node, attr):
+                source = getattr(node, attr)()
+                if hasattr(source, 'abspath'):
+                    return os.path.abspath(source.abspath)
+        if hasattr(node, 'abspath'):
+            return os.path.abspath(node.abspath)
+        return None
+
+    def _filter(items):
+        filtered = []
+        for item in items:
+            if isinstance(item, list):
+                filtered.append(_filter(item))
+                continue
+
+            if not hasattr(item, 'abspath'):
+                filtered.append(item)
+                continue
+
+            item_path = _source_path(item)
+            if item_path is None:
+                filtered.append(item)
+                continue
+
+            item_name = os.path.basename(item_path)
+            if item_name in startup_names and item_path.startswith(cpu_dir + os.sep):
+                continue
+
+            filtered.append(item)
+
+        return filtered
+
+    return _filter(objects)
+
+objs = _replace_cortex_r52_with_startup(objs)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/rdk/s100/applications/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/rdk/s100/applications/main.c

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2026, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2026-04-20     rcitach      first version
+ */
+#include <rtthread.h>
+
+int main(void)
+{
+    rt_kprintf("Hi, RT-Thread!\n");
+    return 0;
+}
+

bsp/rdk/s100/board/SConscript

@@ -0,0 +1,10 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+CPPPATH = [cwd]
+src = Glob('*.c')
+
+objs = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH)
+Return('objs')

bsp/rdk/s100/board/board.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2026, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2026-04-20     rcitach      first version
+ */
+
+#include <rtthread.h>
+#include "board.h"
+
+
+void rt_hw_board_init(void)
+{
+    /* initialize interrupt */
+    rt_hw_interrupt_init();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+

bsp/rdk/s100/board/board.h

@@ -0,0 +1,107 @@
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtdef.h>
+#include <rthw.h>
+#include <cp15.h>
+
+#ifdef __GNUC__
+extern char OS_HEAP_START_ADDR;
+extern char OS_HEAP_END_ADDR;
+#define HEAP_BEGIN ((void *)&OS_HEAP_START_ADDR)
+#define HEAP_END   ((void *)&OS_HEAP_END_ADDR)
+#else
+#error "GCC support only!"
+#endif
+
+#ifndef __DSB
+#define __DSB() __asm volatile ("dsb" : : : "memory")
+#endif
+
+#ifndef __ISB
+#define __ISB() __asm volatile ("isb" : : : "memory")
+#endif
+
+/***********************************************************************************************************************
+ * GIC definitions
+ **********************************************************************************************************************/
+#define S100_GICD_BASE          0x22000000UL
+#define S100_GICR0_OFFSET       0x100000UL
+
+#define GIC_IRQ_START   0
+#define GIC_ACK_INTID_MASK  (0x000003FFU)
+
+/* number of interrupts on board */
+#define ARM_GIC_NR_IRQS     (448)
+#define MAX_HANDLERS ARM_GIC_NR_IRQS
+/* only one GIC available */
+#define ARM_GIC_MAX_NR      1
+/*  end defined */
+
+#define GICV3_DISTRIBUTOR_BASE_ADDR     (S100_GICD_BASE)
+#define GICV3_REDISTRIBUTOR_BASE_ADDR   (S100_GICD_BASE + S100_GICR0_OFFSET)
+
+/*
+ * Board-level IRQ description used by the S100 BSP.
+ *
+ * Reason:
+ * The SoC GIC can see many more interrupt IDs than this RT-Thread board
+ * actually uses. MCU0 already occupies part of the required interrupt
+ * resources, so this board only maintains the IRQs used by the current
+ * port. We keep a board whitelist so GICv3 only configures and controls
+ * the interrupts that belong to the current board port, which avoids
+ * touching unrelated SPI lines and reduces the risk of conflicting with
+ * the interrupts used by MCU0.
+ *
+ * Fields:
+ * irq_number: GIC interrupt ID used by the board.
+ * enable: whether this IRQ is expected to be enabled by board-level init.
+ * name: short readable name for debug and dump output.
+ */
+typedef struct
+{
+    int irq_number;
+    rt_bool_t enable;
+    const char *name;
+} s100_rt_irq_config_t;
+
+/*
+ * Board-supported external IRQ whitelist.
+ *
+ * s100_mcu1_rt_irq_configs records the SPI interrupts currently owned by this
+ * board port. GICv3 uses this table to decide which external interrupts may be
+ * initialized, enabled, masked, dumped, or otherwise managed.
+ * The main purpose is to maintain only the interrupts actually used by this
+ * side, so we do not accidentally configure or disturb interrupt lines that
+ * are already required by MCU0.
+ *
+ * Private interrupts (SGI/PPI, INTID 0-31) are not listed here because they
+ * are CPU-local resources and are handled separately.
+ */
+extern const s100_rt_irq_config_t s100_mcu1_rt_irq_configs[];
+extern const rt_size_t s100_mcu1_rt_irq_configs_count;
+
+/* Returns RT_TRUE only for IRQs that are managed by the current board port. */
+rt_bool_t s100_board_irq_is_supported(int irq);
+
+/* the basic constants and interfaces needed by gic */
+rt_inline rt_uint32_t platform_get_gic_dist_base(void)
+{
+    return GICV3_DISTRIBUTOR_BASE_ADDR;
+}
+
+rt_inline rt_uint32_t platform_get_gic_redist_base(void)
+{
+    return GICV3_REDISTRIBUTOR_BASE_ADDR;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

bsp/rdk/s100/board/rsc_table.c

@@ -0,0 +1,74 @@
+
+#include "rsc_table.h"
+
+extern uint32_t OS_HEAP_START_ADDR;
+extern uint32_t OS_HEAP_SIZE;
+extern uint32_t MCU_LOG_START_ADDR;
+extern uint32_t MCU_LOG_SIZE;
+extern uint32_t __SCMI_IPC_START_ADDR;
+extern uint32_t __SCMI_IPC_SIZE;
+extern uint32_t ATCM_START_ADDR;
+extern uint32_t ATCM_SIZE;
+extern uint32_t CAN_START_ADDR;
+extern uint32_t FLASH_SEC_ADDR;
+extern uint32_t FLASH_STARTUP_LEN;
+
+#define NUM_TABLE_ENTRIES               (7)
+#define HB_SECTION_T(S)                 __attribute__((__section__(#S)))
+#define HB_RESOURCE                     HB_SECTION_T(.resource_table)
+#define MCU_FLASH_START_BASE_ADDR       (0x0CAA5000)
+#define MCU_FLASH_BASE_ADDR             (0x0CAA5400)
+#define MCU_FREERTOS_HEAP_BASE_ADDR     ((uint32_t)&OS_HEAP_START_ADDR)
+#define MCU_LOG_BASE_ADDR               ((uint32_t)&MCU_LOG_START_ADDR)
+#define MCU_SCMI_BASE_ADDR              ((uint32_t)&__SCMI_IPC_START_ADDR)
+#define MCU_ATCM_ADDR                   ((uint32_t)&ATCM_START_ADDR)
+#define MCU_FLASH_START_DDR_ADDR        (0x0CAB0000)
+#define MCU_FLASH_DDR_ADDR              ((uint32_t)&FLASH_SEC_ADDR)
+#define MCU_FREERTOS_HEAP_DDR_ADDR      ((uint32_t)&OS_HEAP_START_ADDR)
+#define MCU_LOG_DDR_ADDR                ((uint32_t)&MCU_LOG_START_ADDR)
+#define MCU_SCMI_DDR_ADDR               ((uint32_t)&__SCMI_IPC_START_ADDR)
+#define MCU_BTCM_ADDR                   ((uint32_t)&CAN_START_ADDR)
+#define MCU_FLASH_START_SIZE            ((uint32_t)&FLASH_STARTUP_LEN)
+#define MCU_FLASH_SIZE                  (0x2AAC00)
+#define MCU_RTTHREAD_HEAP_ADDR          ((uint32_t)&OS_HEAP_START_ADDR)
+#define MCU_RTTHREAD_HEAP_SIZE          ((uint32_t)&OS_HEAP_SIZE)
+#define MCU_LOG_SIZE                    ((uint32_t)&MCU_LOG_SIZE)
+#define MCU_SCMI_SIZE                   ((uint32_t)&__SCMI_IPC_SIZE)
+#define MCU_ATCM_SIZE                   ((uint32_t)&ATCM_SIZE)
+
+const struct remote_resource_table HB_RESOURCE resources = {
+    /* Version */
+    1,
+
+    /* NUmber of table entries */
+    NUM_TABLE_ENTRIES,
+    /* reserved fields */
+    {0x0, 0x0,},
+
+    /* Offsets of rsc entries */
+    {
+        /* offsetof(struct remote_resource_table, rproc_version), */
+        /* offsetof(struct remote_resource_table, fw_chksum), */
+        /* offsetof(struct remote_resource_table, ddr_devmem), */
+        /* offsetof(struct remote_resource_table, tcm_devmem), */
+        /* offsetof(struct remote_resource_table, rpmsg_vdev), */
+        offsetof(struct remote_resource_table, fw_version),
+        offsetof(struct remote_resource_table, startup_devmem),
+        offsetof(struct remote_resource_table, flash_devmem),
+        offsetof(struct remote_resource_table, freertos_heap_devmem),
+        offsetof(struct remote_resource_table, log_devmem),
+        offsetof(struct remote_resource_table, scmi_devmem),
+        offsetof(struct remote_resource_table, atcm_devmem),
+    },
+
+    {(uint32_t)RSC_VERSION, {0}, {0}, {0}},
+    /* flash_start_mem entry */
+    {(uint32_t)RSC_DEVMEM, MCU_FLASH_START_DDR_ADDR, MCU_FLASH_START_DDR_ADDR, MCU_FLASH_START_SIZE, 0, 0, "startup devmem"},
+    {(uint32_t)RSC_DEVMEM, MCU_FLASH_DDR_ADDR, MCU_FLASH_DDR_ADDR, MCU_FLASH_SIZE, 0, 0, "flash devmem"},
+    {(uint32_t)RSC_DEVMEM, MCU_RTTHREAD_HEAP_ADDR, MCU_RTTHREAD_HEAP_ADDR, MCU_RTTHREAD_HEAP_SIZE, 0, 0, "rtthread_heap devmem"},
+    {(uint32_t)RSC_DEVMEM, MCU_LOG_DDR_ADDR, MCU_LOG_DDR_ADDR, MCU_LOG_SIZE, 0, 0, "log devmem"},
+    {(uint32_t)RSC_DEVMEM, MCU_SCMI_DDR_ADDR, MCU_SCMI_DDR_ADDR, MCU_SCMI_SIZE, 0, 0, "scmi devmem"},
+    {(uint32_t)RSC_DEVMEM, MCU_ATCM_ADDR, MCU_BTCM_ADDR, MCU_ATCM_SIZE, 0, 0, "atcm devmem"},
+
+};
+

bsp/rdk/s100/board/rsc_table.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2014, Mentor Graphics Corporation
+ * All rights reserved.
+ *
+ * Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+ * Copyright (C) 2023, Horizon Robotics
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of Mentor Graphics Corporation nor the names of its
+ *    contributors may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* This file populates resource table for BM remote
+ * for use by the Linux Master */
+#ifndef HB_RSC_TABLE_H
+#define HB_RSC_TABLE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+struct fw_rsc_version_with_type {
+    uint32_t typefw_rsc_version;
+    uint8_t version[48];
+    uint8_t compile_time[16];
+    uint8_t git_hash_id[40];
+};
+
+enum fw_resource_type {
+    RSC_CARVEOUT        = 0,
+    RSC_DEVMEM      = 1,
+    RSC_TRACE       = 2,
+    RSC_VDEV        = 3,
+    RSC_RPROC_MEM   = 4U,
+    RSC_FW_CHKSUM   = 5U,
+    RSC_VERSION     = 6U,
+    RSC_LAST        = 7U,
+    RSC_VENDOR_START    = 128,
+    RSC_VENDOR_END      = 512,
+};
+
+struct fw_rsc_devmem_with_type {
+    uint32_t typefw_rsc_devmem;
+    uint32_t da;
+    uint32_t pa;
+    uint32_t len;
+    uint32_t flags;
+    uint32_t reserved;
+    uint8_t name[32];
+};
+
+#define NO_RESOURCE_ENTRIES         (7U)
+
+/* Resource table for the given remote */
+struct remote_resource_table {
+    uint32_t version;
+    uint32_t num;
+    uint32_t reserved[2];
+    uint32_t offset[NO_RESOURCE_ENTRIES];
+    struct fw_rsc_version_with_type fw_version; /*PRQA S ALL*/
+    struct fw_rsc_devmem_with_type startup_devmem;
+    struct fw_rsc_devmem_with_type flash_devmem;
+    struct fw_rsc_devmem_with_type freertos_heap_devmem;
+    struct fw_rsc_devmem_with_type log_devmem;
+    struct fw_rsc_devmem_with_type scmi_devmem;
+    struct fw_rsc_devmem_with_type atcm_devmem;
+}__attribute__((packed, aligned(0x100)));
+
+extern const struct remote_resource_table resources;
+
+#endif /* RSC_TABLE_H_ */
+

bsp/rdk/s100/drivers/Kconfig

@@ -0,0 +1,111 @@
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_PINMUX
+        bool "Enable pinmux helper driver"
+        default y
+        help
+            Enable the S100 pinmux and pin configuration helper APIs.
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO/pin driver"
+        default y
+        select RT_USING_PIN
+        help
+            Register the RT-Thread pin device and GPIO interrupt dispatch.
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN (S100 FlexCAN)"
+        default y
+        select RT_USING_CAN
+        help
+            Enable the S100 FlexCAN driver using RT-Thread CAN framework.
+
+    if BSP_USING_CAN
+
+    config BSP_USING_CAN5
+        bool "Enable CAN5"
+        default y
+
+    config BSP_USING_CAN6
+        bool "Enable CAN6"
+        default y
+
+    config BSP_USING_CAN7
+        bool "Enable CAN7"
+        default y
+
+    config BSP_USING_CAN8
+        bool "Enable CAN8"
+        default y
+
+    config BSP_USING_CAN9
+        bool "Enable CAN9"
+        default y
+
+    endif
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        depends on RT_USING_SERIAL
+        depends on RT_USING_SERIAL_V2
+
+    if BSP_USING_UART
+
+    config BSP_USING_UART4
+        bool "Enable UART4 (Debugger)"
+        default y
+
+    if BSP_USING_UART4
+
+    config BSP_UART4_RX_BUFSIZE
+        int "Set UART4 RX buffer size"
+        range 64 65535
+        default 1024
+
+    config BSP_UART4_TX_BUFSIZE
+        int "Set UART4 TX buffer size"
+        range 0 65535
+        default 0
+
+    endif
+
+    config BSP_USING_UART5
+        bool "Enable UART5"
+        default n
+
+    if BSP_USING_UART5
+
+    config BSP_UART5_RX_BUFSIZE
+        int "Set UART5 RX buffer size"
+        range 64 65535
+        default 1024
+
+    config BSP_UART5_TX_BUFSIZE
+        int "Set UART5 TX buffer size"
+        range 0 65535
+        default 0
+
+    endif
+
+    config BSP_USING_UART6
+        bool "Enable UART6"
+        default n
+
+    if BSP_USING_UART6
+
+    config BSP_UART6_RX_BUFSIZE
+        int "Set UART6 RX buffer size"
+        range 64 65535
+        default 1024
+
+    config BSP_UART6_TX_BUFSIZE
+        int "Set UART6 TX buffer size"
+        range 0 65535
+        default 0
+
+    endif
+
+    endif
+
+endmenu

bsp/rdk/s100/drivers/SConscript

@@ -0,0 +1,28 @@
+from building import *
+
+cwd = GetCurrentDir()
+list = os.listdir(cwd)
+src = []
+
+src += ['drv_timer.c']
+
+if GetDepend('BSP_USING_UART'):
+    src += ['drv_uart_v2.c']
+
+if GetDepend('BSP_USING_PINMUX'):
+    src += ['drv_pinmux.c']
+
+if GetDepend('BSP_USING_GPIO'):
+    src += ['drv_gpio.c']
+
+if GetDepend('BSP_USING_CAN'):
+    src += ['drv_can.c']
+
+objs = DefineGroup('drivers', src, depend=[''], CPPPATH=[cwd])
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/rdk/s100/drivers/drv_gpio.h

@@ -0,0 +1,31 @@
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+#include "drv_pinmux.h"
+
+/*
+ * MCU GPIO access layer used by both the RT-Thread pin device and simple
+ * board-level helpers.
+ */
+typedef enum
+{
+    S100_PIN_DIR_IN = 0,
+    S100_PIN_DIR_OUT,
+    S100_PIN_DIR_HIGH_Z,
+} s100_pin_direction_t;
+
+typedef enum
+{
+    S100_PIN_LEVEL_LOW = 0,
+    S100_PIN_LEVEL_HIGH,
+} s100_pin_level_t;
+
+rt_err_t s100_gpio_set_direction(s100_pin_t pin, s100_pin_direction_t direction);
+rt_err_t s100_gpio_write_pin(s100_pin_t pin, s100_pin_level_t level);
+rt_err_t s100_gpio_read_pin(s100_pin_t pin, s100_pin_level_t *level);
+
+void s100_gpio_write(rt_uint8_t pin, rt_uint8_t value);
+rt_uint8_t s100_gpio_read(rt_uint8_t pin);
+
+#endif
+

bsp/rdk/s100/drivers/drv_pinmux.c

@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2006-2026, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2026-04-20     rcitach      first version
+ */
+
+#include "drv_pinmux.h"
+
+#define S100_PIN_MUX_REG_BASE            0x234C0060U
+#define S100_PIN_CONFIG_REG_BASE         0x234D0010U
+
+#define S100_PORT_IP_NUM                         2
+#define S100_PORT_LLD_IP_NUM                     6
+#define S100_PORT_PIN_NUM                        (uint8_t)124U
+#define S100_PORT_MCU_PIN_NUM                    (uint8_t)88U
+#define S100_PORT_AON_PIN_NUM                    (uint8_t)18U
+
+#define AON_PIN_NUM(aon_gpio_idx) ((aon_gpio_idx) + (S100_PORT_MCU_PIN_NUM))
+/*
+ * Keep the same MCU GPIO blacklist as the SDK Port subsystem.
+ * These pins are reserved for power/debug or other board-critical uses
+ * and must not be reconfigured as generic GPIO from RT-Thread.
+ *
+ * Note:
+ * The SDK also blacklists a few AON pins. The current cpu1_rtthread BSP
+ * driver only manages MCU GPIO pins, so only the MCU-side blacklist is
+ * enforced here.
+ */
+static const s100_pin_t s100_gpio_blacklist[] =
+{
+    0,  /* S100 Power related pins */
+    5,  /* S100 debug uart tx */
+    38, /* S100 Power related pins */
+    15, /* S100 Power related pins */
+    68, /* S100 Power related pins */
+    69, /* S100 Power related pins */
+    71, /* S100 Power related pins */
+    80, /* S100 Power related pins */
+    81, /* S100 Power related pins */
+    82, /* S100 Power related pins */
+    83, /* S100 Power related pins */
+    AON_PIN_NUM(0),  /* S100 debug uart rx */
+    AON_PIN_NUM(12), /* S100 Power related pins */
+};
+
+typedef struct
+{
+    volatile rt_uint32_t reg_pin_mux_func;
+} s100_pin_mux_reg_t;
+
+typedef union
+{
+    struct
+    {
+        volatile rt_uint32_t ds  : 4;
+        volatile rt_uint32_t ie  : 1;
+        volatile rt_uint32_t pd  : 1;
+        volatile rt_uint32_t pu  : 1;
+        volatile rt_uint32_t st  : 1;
+        volatile rt_uint32_t rsvd: 24;
+    } type0;
+    volatile rt_uint32_t value;
+} s100_pin_cfg_reg_t;
+
+static s100_pin_mux_reg_t *const s100_pin_mux_regs =
+    (s100_pin_mux_reg_t *)S100_PIN_MUX_REG_BASE;
+static s100_pin_cfg_reg_t *const s100_pin_cfg_regs =
+    (s100_pin_cfg_reg_t *)S100_PIN_CONFIG_REG_BASE;
+
+static rt_bool_t s100_pin_is_blacklisted(s100_pin_t pin)
+{
+    rt_size_t i;
+
+    for (i = 0; i < sizeof(s100_gpio_blacklist) / sizeof(s100_gpio_blacklist[0]); i++)
+    {
+        if (pin == s100_gpio_blacklist[i])
+        {
+            return RT_TRUE;
+        }
+    }
+
+    return RT_FALSE;
+}
+
+rt_bool_t s100_pin_is_valid(s100_pin_t pin)
+{
+    if (pin >= S100_GPIO_PIN_COUNT)
+    {
+        return RT_FALSE;
+    }
+
+    /* Pin 79 is a hole in the MCU GPIO numbering and must be skipped. */
+    if (pin == 79U)
+    {
+        return RT_FALSE;
+    }
+
+    if (s100_pin_is_blacklisted(pin) == RT_TRUE)
+    {
+        return RT_FALSE;
+    }
+
+    return RT_TRUE;
+}
+
+rt_err_t s100_pin_set_function(s100_pin_t pin, s100_pin_function_t function)
+{
+    if (!s100_pin_is_valid(pin))
+    {
+        return -RT_EINVAL;
+    }
+
+    s100_pin_mux_regs[pin].reg_pin_mux_func = (rt_uint32_t)function & 0x3U;
+    return RT_EOK;
+}
+
+rt_err_t s100_pin_set_pull(s100_pin_t pin, s100_pin_pull_t pull)
+{
+    s100_pin_cfg_reg_t cfg;
+
+    if (!s100_pin_is_valid(pin))
+    {
+        return -RT_EINVAL;
+    }
+
+    cfg = s100_pin_cfg_regs[pin];
+    cfg.type0.ie = 1U;
+    cfg.type0.st = 1U;
+    cfg.type0.pu = 0U;
+    cfg.type0.pd = 0U;
+
+    if (pull == S100_PIN_PULL_UP)
+    {
+        cfg.type0.pu = 1U;
+    }
+    else if (pull == S100_PIN_PULL_DOWN)
+    {
+        cfg.type0.pd = 1U;
+    }
+
+    s100_pin_cfg_regs[pin].value = cfg.value;
+    return RT_EOK;
+}
+

bsp/rdk/s100/drivers/drv_pinmux.h

@@ -0,0 +1,38 @@
+#ifndef DRV_PINMUX_H__
+#define DRV_PINMUX_H__
+
+#include <rtthread.h>
+
+/*
+ * Shared S100 pinctrl helpers.
+ *
+ * GPIO, UART, SPI and other MCU-side drivers can reuse this layer to switch
+ * mux function and electrical attributes without duplicating pin register
+ * knowledge in every peripheral driver.
+ */
+typedef rt_uint8_t s100_pin_t;
+
+typedef enum
+{
+    S100_PIN_PULL_NONE = 0,
+    S100_PIN_PULL_DOWN,
+    S100_PIN_PULL_UP,
+} s100_pin_pull_t;
+
+typedef enum
+{
+    S100_PIN_FUNC0 = 0,
+    S100_PIN_FUNC1,
+    S100_PIN_FUNC2,
+    S100_PIN_FUNC_GPIO,
+} s100_pin_function_t;
+
+#define S100_GPIO_PIN_COUNT 88U
+
+/* Returns RT_FALSE for reserved/unsupported pins, including the SDK blacklist. */
+rt_bool_t s100_pin_is_valid(s100_pin_t pin);
+rt_err_t s100_pin_set_function(s100_pin_t pin, s100_pin_function_t function);
+rt_err_t s100_pin_set_pull(s100_pin_t pin, s100_pin_pull_t pull);
+
+#endif
+

bsp/rdk/s100/drivers/drv_timer.c

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2026, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2026-04-20     rcitach      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <stdint.h>
+
+#include "board.h"
+
+#define S100_SYSCNT_BASE                 0x23110000U
+#define S100_SYSCNT_CTRL_OSCON_MASK      (0x1U)
+#define S100_SYSCNT_CLK_HZ               (40000000U)
+#define S100_GENERIC_TIMER_PPI           30
+
+#define CNTP_CTL_ENABLE                  (1U << 0)
+
+struct s100_syscnt
+{
+    volatile rt_uint32_t ctrl;
+    volatile rt_uint32_t stat;
+    volatile rt_uint32_t cntcvl;
+    volatile rt_uint32_t cntcvu;
+    rt_uint8_t reserved[16];
+    volatile rt_uint32_t cntfid0;
+};
+
+static volatile struct s100_syscnt *const s100_syscnt =
+    (volatile struct s100_syscnt *)S100_SYSCNT_BASE;
+
+static rt_uint32_t s100_tick_interval;
+static rt_uint64_t s100_read_cntpct(void)
+{
+    rt_uint32_t low;
+    rt_uint32_t high;
+
+    __asm volatile ("mrrc p15, 0, %0, %1, c14" : "=r"(low), "=r"(high));
+
+    return (((rt_uint64_t)high) << 32) | low;
+}
+
+static void s100_write_cntp_cval(rt_uint64_t value)
+{
+    rt_uint32_t low = (rt_uint32_t)value;
+    rt_uint32_t high = (rt_uint32_t)(value >> 32);
+
+    __asm volatile ("mcrr p15, 2, %0, %1, c14" :: "r"(low), "r"(high));
+}
+
+static void s100_write_cntp_ctl(rt_uint32_t value)
+{
+    __asm volatile ("mcr p15, 0, %0, c14, c2, 1" :: "r"(value));
+}
+
+static void s100_program_next_tick(rt_uint32_t delta)
+{
+    s100_write_cntp_cval(s100_read_cntpct() + delta);
+}
+
+static void rt_hw_timer_isr(int vector, void *param)
+{
+    RT_UNUSED(vector);
+    RT_UNUSED(param);
+
+    s100_program_next_tick(s100_tick_interval);
+    rt_tick_increase();
+}
+
+int rt_hw_timer_init(void)
+{
+    s100_tick_interval = S100_SYSCNT_CLK_HZ / RT_TICK_PER_SECOND;
+    RT_ASSERT(s100_tick_interval > 0U);
+
+    s100_syscnt->cntfid0 = S100_SYSCNT_CLK_HZ;
+    s100_syscnt->ctrl |= S100_SYSCNT_CTRL_OSCON_MASK;
+
+    s100_write_cntp_ctl(0U);
+    s100_program_next_tick(s100_tick_interval);
+    s100_write_cntp_ctl(CNTP_CTL_ENABLE);
+
+    rt_hw_interrupt_install(S100_GENERIC_TIMER_PPI, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(S100_GENERIC_TIMER_PPI);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_timer_init);
+

bsp/rdk/s100/drivers/utest/SConscript

@@ -0,0 +1,16 @@
+from building import *
+
+src = []
+
+if GetDepend('BSP_USING_GPIO'):
+    src += ['test_gpio.c']
+
+if GetDepend('BSP_USING_CAN5') or GetDepend('BSP_USING_CAN6') or GetDepend('BSP_USING_CAN7') or GetDepend('BSP_USING_CAN8') or GetDepend('BSP_USING_CAN9'):
+    src += ['test_can.c']
+
+if GetDepend('BSP_USING_UART'):
+    src += ['test_uart.c']
+
+group = DefineGroup('utestcases', src, depend = ['RT_UTEST_DRIVERS_CORE'])
+
+Return('group')

bsp/rdk/s100/rtconfig.py

@@ -0,0 +1,83 @@
+import os
+import sys
+
+
+def _config_enabled(symbol, default=False):
+    config_path = os.path.join(os.path.dirname(__file__), '.config')
+
+    try:
+        with open(config_path, 'r', encoding='utf-8') as cfg:
+            text = cfg.read()
+            if f'CONFIG_{symbol}=y' in text:
+                return True
+            if f'# CONFIG_{symbol} is not set' in text:
+                return False
+            return default
+    except OSError:
+        return default
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-r52'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/toolchain/gcc-arm-none-eabi-10.3-2021.10/bin'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+# BUILD = 'debug'
+BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    NM = PREFIX + 'nm'
+
+    if _config_enabled('RT_USING_FPU', default=True):
+        DEVICE = ' -mcpu=cortex-r52 -marm -mfloat-abi=hard -mfpu=vfpv3-d16 -mlittle-endian'
+    else:
+        DEVICE = ' -mcpu=cortex-r52 -marm -mfloat-abi=soft -mgeneral-regs-only -mlittle-endian'
+    COMMON_CFLAGS = (
+        ' -fno-inline'
+        ' -ffunction-sections'
+        ' -fdata-sections'
+        ' -fdiagnostics-parseable-fixits'
+        ' -fmessage-length=0'
+        ' -funsigned-char'
+        ' -funsigned-bitfields'
+        ' -fno-common'
+        ' -fno-strict-aliasing'
+        ' -funwind-tables'
+        ' -Dgcc'
+    )
+
+    CFLAGS = DEVICE + COMMON_CFLAGS
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vector -lgcc -T link.lds'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -Og -ggdb3 -gdwarf-4'
+        AFLAGS += ' -ggdb3 -gdwarf-4'
+    else:
+        CFLAGS += ' -O2'
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

bsp/rdk/s100/startup/SConscript

@@ -0,0 +1,13 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('startup', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/rdk/s100/startup/stack.c

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2011-2026, Shanghai Real-Thread Electronic Technology Co.,Ltd
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-08-29     RT-Thread    first version
+ */
+
+#include "armv8.h"
+#include <rtthread.h>
+/* #include <board.h> */
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+
+    stack_addr += sizeof(rt_uint32_t);
+    stack_addr  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk      = (rt_uint32_t *)stack_addr;
+    *(--stk) = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0xdeadbeef;                  /* r12 */
+    *(--stk) = 0xdeadbeef;                  /* r11 */
+    *(--stk) = 0xdeadbeef;                  /* r10 */
+    *(--stk) = 0xdeadbeef;                  /* r9 */
+    *(--stk) = 0xdeadbeef;                  /* r8 */
+    *(--stk) = 0xdeadbeef;                  /* r7 */
+    *(--stk) = 0xdeadbeef;                  /* r6 */
+    *(--stk) = 0xdeadbeef;                  /* r5 */
+    *(--stk) = 0xdeadbeef;                  /* r4 */
+    *(--stk) = 0xdeadbeef;                  /* r3 */
+    *(--stk) = 0xdeadbeef;                  /* r2 */
+    *(--stk) = 0xdeadbeef;                  /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+#ifdef RT_USING_OSA
+    *(--stk) = 0;       /* user lr */
+    *(--stk) = 0;       /* user sp*/
+#endif
+#ifdef RT_USING_FPU
+    rt_uint32_t i;
+
+    for (i = 0; i < 32; i++)
+    {
+        *(--stk) = 0;   /* d0-d15 initial state */
+    }
+    *(--stk) = 0;           /* fpscr */
+    *(--stk) = 0x40000000;  /* eager-enable FPU for every new thread */
+#endif
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
+/*@}*/
+

bsp/rdk/s100/startup/system.c

@@ -0,0 +1,136 @@
+#include <rtthread.h>
+#include "board.h"
+#include "gicv3.h"
+
+/* MCU1 interrupt numbers extracted from the original SDK configuration. */
+
+#define Os_IntChannel_PDMA0_Ch0Isr          213U
+#define Os_IntChannel_Pps_IcuRtcIsr         221U
+#define Os_IntChannel_Pps_IcuEthIsr         229U
+#define Os_IntChannel_Spi0_Isr              171U
+#define Os_IntChannel_Spi1_Isr              172U
+#define Os_IntChannel_Spi2_Isr              173U
+#define Os_IntChannel_Spi3_Isr              174U
+#define Os_IntChannel_Uart4_Isr             45U
+#define Os_IntChannel_Uart5_Isr             46U
+#define Os_IntChannel_Adc_Ch0WdIsr          48U
+#define Os_IntChannel_Adc_Ch1WdIsr          49U
+#define Os_IntChannel_Adc_Ch2WdIsr          50U
+#define Os_IntChannel_Adc_Ch3WdIsr          51U
+#define Os_IntChannel_Adc_Ch4WdIsr          52U
+#define Os_IntChannel_Adc_Ch5WdIsr          53U
+#define Os_IntChannel_Adc_Ch6WdIsr          54U
+#define Os_IntChannel_Adc_Ch7WdIsr          55U
+#define Os_IntChannel_Adc_Ch8WdIsr          56U
+#define Os_IntChannel_Adc_Ch9WdIsr          57U
+#define Os_IntChannel_Adc_Ch10WdIsr         58U
+#define Os_IntChannel_Adc_Ch11WdIsr         59U
+#define Os_IntChannel_Adc_Ch12WdIsr         60U
+#define Os_IntChannel_Adc_Ch13WdIsr         61U
+#define Os_IntChannel_Adc_InjIsr            62U
+#define Os_IntChannel_Adc_NorIsr            63U
+#define Os_IntChannel_I2c0_Isr              64U
+#define Os_IntChannel_I2c1_Isr              65U
+#define Os_IntChannel_I2c2_Isr              66U
+#define Os_IntChannel_I2c3_Isr              67U
+#define Os_IntChannel_Gpio_Icu0ExtIsr       68U
+#define Os_IntChannel_Gpio_Icu1ExtIsr       69U
+#define Os_IntChannel_Gpio_Icu2ExtIsr       70U
+#define Os_IntChannel_Mdma1_Ch1Isr          212U
+#define Os_IntChannel_Ipc_CpuIpc0Ch0Isr     254U
+#define Os_IntChannel_Ipc_CpuIpc0Ch4Isr     258U
+#define Os_IntChannel_Ipc_CpuIpc0Ch7Isr     261U
+#define Os_IntChannel_Ipc_CpuIpc0Ch10Isr    264U
+#define Os_Cross_Core_Ins0_Isr              237U
+#define Os_Cross_Core_Ins1_Isr              238U
+#define Os_Cross_Core_Ins2_Isr              239U
+#define Os_Cross_Core_Ins3_Isr              234U
+#define Os_Cross_Core_Ins4_Isr              235U
+#define Os_Cross_Core_Ins5_Isr              236U
+#define Os_IntChannel_Can5_DataIsr          136U
+#define Os_IntChannel_Can6_DataIsr          140U
+#define Os_IntChannel_Can7_DataIsr          144U
+#define Os_IntChannel_Can8_DataIsr          148U
+#define Os_IntChannel_Can9_DataIsr          152U
+
+/*
+ * MCU1 interrupt whitelist extracted from the original SDK interrupt map.
+ * The current BSP only manages these SPI IDs; everything else is treated as
+ * out-of-scope to avoid colliding with resources still owned by MCU0.
+ */
+
+const s100_rt_irq_config_t s100_mcu1_rt_irq_configs[] =
+{
+    {Os_IntChannel_PDMA0_Ch0Isr,      RT_TRUE, "PDMA0_Ch0"},
+    {Os_IntChannel_Pps_IcuRtcIsr,     RT_TRUE, "Pps_IcuRtc"},
+    {Os_IntChannel_Pps_IcuEthIsr,     RT_TRUE, "Pps_IcuEth"},
+    {Os_IntChannel_Spi0_Isr,          RT_TRUE, "Spi0"},
+    {Os_IntChannel_Spi1_Isr,          RT_TRUE, "Spi1"},
+    {Os_IntChannel_Spi2_Isr,          RT_TRUE, "Spi2"},
+    {Os_IntChannel_Spi3_Isr,          RT_TRUE, "Spi3"},
+    {Os_IntChannel_Uart4_Isr,         RT_TRUE, "Uart4"},
+    {Os_IntChannel_Uart5_Isr,         RT_TRUE, "Uart5"},
+    {Os_IntChannel_Adc_Ch0WdIsr,      RT_TRUE, "Adc_Ch0Wd"},
+    {Os_IntChannel_Adc_Ch1WdIsr,      RT_TRUE, "Adc_Ch1Wd"},
+    {Os_IntChannel_Adc_Ch2WdIsr,      RT_TRUE, "Adc_Ch2Wd"},
+    {Os_IntChannel_Adc_Ch3WdIsr,      RT_TRUE, "Adc_Ch3Wd"},
+    {Os_IntChannel_Adc_Ch4WdIsr,      RT_TRUE, "Adc_Ch4Wd"},
+    {Os_IntChannel_Adc_Ch5WdIsr,      RT_TRUE, "Adc_Ch5Wd"},
+    {Os_IntChannel_Adc_Ch6WdIsr,      RT_TRUE, "Adc_Ch6Wd"},
+    {Os_IntChannel_Adc_Ch7WdIsr,      RT_TRUE, "Adc_Ch7Wd"},
+    {Os_IntChannel_Adc_Ch8WdIsr,      RT_TRUE, "Adc_Ch8Wd"},
+    {Os_IntChannel_Adc_Ch9WdIsr,      RT_TRUE, "Adc_Ch9Wd"},
+    {Os_IntChannel_Adc_Ch10WdIsr,     RT_TRUE, "Adc_Ch10Wd"},
+    {Os_IntChannel_Adc_Ch11WdIsr,     RT_TRUE, "Adc_Ch11Wd"},
+    {Os_IntChannel_Adc_Ch12WdIsr,     RT_TRUE, "Adc_Ch12Wd"},
+    {Os_IntChannel_Adc_Ch13WdIsr,     RT_TRUE, "Adc_Ch13Wd"},
+    {Os_IntChannel_Adc_InjIsr,        RT_TRUE, "Adc_Inj"},
+    {Os_IntChannel_Adc_NorIsr,        RT_TRUE, "Adc_Nor"},
+    {Os_IntChannel_I2c0_Isr,          RT_TRUE, "I2c0"},
+    {Os_IntChannel_I2c1_Isr,          RT_TRUE, "I2c1"},
+    {Os_IntChannel_I2c2_Isr,          RT_TRUE, "I2c2"},
+    {Os_IntChannel_I2c3_Isr,          RT_TRUE, "I2c3"},
+    {Os_IntChannel_Gpio_Icu0ExtIsr,   RT_TRUE, "Gpio_Icu0Ext"},
+    {Os_IntChannel_Gpio_Icu1ExtIsr,   RT_TRUE, "Gpio_Icu1Ext"},
+    {Os_IntChannel_Gpio_Icu2ExtIsr,   RT_TRUE, "Gpio_Icu2Ext"},
+    {Os_IntChannel_Mdma1_Ch1Isr,      RT_TRUE, "Mdma1_Ch1"},
+    {Os_IntChannel_Ipc_CpuIpc0Ch0Isr, RT_TRUE, "Ipc_CpuIpc0Ch0"},
+    {Os_IntChannel_Ipc_CpuIpc0Ch4Isr, RT_TRUE, "Ipc_CpuIpc0Ch4"},
+    {Os_IntChannel_Ipc_CpuIpc0Ch7Isr, RT_TRUE, "Ipc_CpuIpc0Ch7"},
+    {Os_IntChannel_Ipc_CpuIpc0Ch10Isr, RT_TRUE, "Ipc_CpuIpc0Ch10"},
+    {Os_Cross_Core_Ins0_Isr,          RT_TRUE, "Cross_Core_Ins0"},
+    {Os_Cross_Core_Ins1_Isr,          RT_TRUE, "Cross_Core_Ins1"},
+    {Os_Cross_Core_Ins2_Isr,          RT_TRUE, "Cross_Core_Ins2"},
+    {Os_Cross_Core_Ins3_Isr,          RT_TRUE, "Cross_Core_Ins3"},
+    {Os_Cross_Core_Ins4_Isr,          RT_TRUE, "Cross_Core_Ins4"},
+    {Os_Cross_Core_Ins5_Isr,          RT_TRUE, "Cross_Core_Ins5"},
+    {Os_IntChannel_Can5_DataIsr,      RT_TRUE, "Can5_Data"},
+    {Os_IntChannel_Can6_DataIsr,      RT_TRUE, "Can6_Data"},
+    {Os_IntChannel_Can7_DataIsr,      RT_TRUE, "Can7_Data"},
+    {Os_IntChannel_Can8_DataIsr,      RT_TRUE, "Can8_Data"},
+    {Os_IntChannel_Can9_DataIsr,      RT_TRUE, "Can9_Data"},
+};
+
+const rt_size_t s100_mcu1_rt_irq_configs_count =
+    sizeof(s100_mcu1_rt_irq_configs) / sizeof(s100_mcu1_rt_irq_configs[0]);
+
+rt_bool_t s100_board_irq_is_supported(int irq)
+{
+    rt_size_t i;
+
+    if ((irq >= 0) && (irq < 32))
+    {
+        return RT_TRUE;
+    }
+
+    for (i = 0; i < s100_mcu1_rt_irq_configs_count; i++)
+    {
+        if (s100_mcu1_rt_irq_configs[i].irq_number == irq)
+        {
+            return RT_TRUE;
+        }
+    }
+
+    return RT_FALSE;
+}
+

bsp/rdk/s100/startup/vector_gcc.S

@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+ 
+.macro push_svc_reg pc_adjust
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    sub     r5, lr, #\pc_adjust
+    str     r5, [r0, #15*4]         @/* Push fault PC                   */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #0x13                   @/* Switch to SVC mode               */
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+/*
+    * EL2 exceptions are unexpected in the normal RT-Thread runtime because
+    * the core has already descended into EL1. Keep the SDK policy simple:
+    * capture a minimal register frame for diagnostics, then stop.
+    */
+.macro push_hyp_reg pc_adjust
+    mov     r7, sp
+    sub     sp, sp, #17 * 4
+    stmia   sp, {r0 - r12}
+    mov     r0, sp
+    str     r7, [r0, #13*4]
+    str     lr, [r0, #14*4]
+    sub     r6, lr, #\pc_adjust
+    str     r6, [r0, #15*4]
+    mrs     r6, spsr
+    str     r6, [r0, #16*4]
+.endm
+
+.globl SWI_Handler
+SWI_Handler:
+    push_svc_reg 4
+    bl      rt_hw_trap_swi
+    b       .
+
+.globl Undefined_Handler
+Undefined_Handler:
+    push_svc_reg 4
+	bl	rt_hw_trap_undef
+    b   .
+
+.globl SVC_Handler
+SVC_Handler:
+	push_svc_reg 4
+	b	rt_hw_trap_svc
+    b   .
+
+.globl Prefetch_Handler
+Prefetch_Handler:
+    push_svc_reg 4
+	b	rt_hw_trap_pabt
+    b   .
+
+.globl Abort_Handler
+Abort_Handler:
+    push_svc_reg 8
+	b	rt_hw_trap_dabt
+    b   .
+
+.globl Reserved_Handler
+Reserved_Handler:
+    push_svc_reg 4
+	b	rt_hw_trap_resv
+    b   .
+
+.globl FIQ_Handler
+FIQ_Handler:
+    stmdb   sp!, {r0-r12, lr}
+
+#ifdef RT_USING_FPU
+    vmrs    r0, fpexc
+    tst     r0, #0x40000000
+    beq     __no_vfp_frame_str_fiq
+    vstmdb  sp!, {d0-d15}
+    vmrs    r1, fpscr
+    stmdb   sp!, {r1}
+__no_vfp_frame_str_fiq:
+    stmdb   sp!, {r0}
+#endif
+
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_fiq
+    bl      rt_interrupt_leave
+
+#ifdef RT_USING_FPU
+    ldmia   sp!, {r0}
+    vmsr    fpexc, r0
+    tst     r0, #0x40000000
+    beq     __no_vfp_frame_ldr_fiq
+    ldmia   sp!, {r1}
+    vmsr    fpscr, r1
+    vldmia  sp!, {d0-d15}
+__no_vfp_frame_ldr_fiq:
+#endif
+
+    ldmia   sp!, {r0-r12, lr}
+    subs    pc, lr, #4
+
+.globl EL2_Undefined_Handler
+EL2_Undefined_Handler:
+    push_hyp_reg 4
+    mov r1, #0
+    b   .
+
+.globl EL2_Prefetch_Handler
+EL2_Prefetch_Handler:
+    push_hyp_reg 4
+    mov r1, #1
+    b   .
+
+.globl EL2_Abort_Handler
+EL2_Abort_Handler:
+    push_hyp_reg 8
+    mov r1, #2
+    b   .
+
+.globl EL2_IRQ_Handler
+EL2_IRQ_Handler:
+    push_hyp_reg 4
+    mov r1, #3
+    b   .
+
+.globl EL2_FIQ_Handler
+EL2_FIQ_Handler:
+    push_hyp_reg 4
+    mov r1, #4
+    b   .
+
+.globl  EL2_HVC_Handler
+EL2_HVC_Handler:
+    push_hyp_reg 4
+    mov r1, #5
+    b   .
+
+.globl  EL2_Trap_Handler
+EL2_Trap_Handler:
+    push_hyp_reg 4
+    mov r1, #6
+    b   .