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raspi4 spi0 driver can run

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This commit is contained in:
bigamgic
2020-07-04 22:32:02 +08:00
parent 7e5373e733
commit f333dcabe3
9 changed files with 470 additions and 26 deletions
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bsp/raspberry-pi/raspi4-32/.config
+11 -1
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@@ -134,13 +134,19 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
@@ -475,6 +481,10 @@ CONFIG_BSP_USING_GIC=y
CONFIG_BSP_USING_GIC400=y
# CONFIG_BSP_USING_GIC500 is not set
CONFIG_BSP_USING_PIN=y
CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI0_BUS=y
CONFIG_BSP_USING_SPI0_DEVICE0=y
# CONFIG_BSP_USING_SPI0_DEVICE1 is not set
CONFIG_BSP_USING_CORETIMER=y
# CONFIG_BSP_USING_SYSTIMER is not set
# CONFIG_BSP_USING_WDT is not set
bsp/raspberry-pi/raspi4-32/driver/Kconfig
+19
View File
@@ -50,6 +50,25 @@ menu "Hardware Drivers Config"
select RT_USING_PIN
default y
menuconfig BSP_USING_SPI
bool "Enable SPI"
select RT_USING_SPI
default n
if BSP_USING_SPI
config BSP_USING_SPI0_BUS
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI0_DEVICE0
bool "Enable SPI0 DEVICE0"
select BSP_USING_SPI0_BUS
default n
config BSP_USING_SPI0_DEVICE1
bool "Enable SPI0 DEVICE1"
select BSP_USING_SPI0_BUS
default n
endif
config BSP_USING_CORETIMER
bool "Using core timer"
select RT_USING_CORETIMER
bsp/raspberry-pi/raspi4-32/driver/SConscript
+11 -1
View File
@@ -4,6 +4,16 @@ cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
group = DefineGroup('driver', src, depend = [''], CPPPATH = CPPPATH)
# build for sub-directory
list = os.listdir(cwd)
objs = []
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
group = group + objs
Return('group')
bsp/raspberry-pi/raspi4-32/driver/drv_gpio.c
+29 -24
View File
@@ -120,6 +120,34 @@ void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode)
raspi_set_pin_state(fselnum, gpfsel);
}
void prev_raspi_pin_write(GPIO_PIN pin, int pin_value)
{
uint32_t num = pin / 32;
if(num == 0)
{
if(pin_value == 1)
{
GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
}
else
{
GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
}
}
else
{
if(pin_value == 1)
{
GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
}
else
{
GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
}
}
}
static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
{
GPIO_FUNC raspi_mode = OUTPUT;
@@ -149,30 +177,7 @@ static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
{
uint32_t num = pin / 32;
if(num == 0)
{
if(value == 0)
{
GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
}
else
{
GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
}
}
else
{
if(value == 0)
{
GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
}
else
{
GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
}
}
prev_raspi_pin_write(pin, value);
}
static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
bsp/raspberry-pi/raspi4-32/driver/drv_gpio.h
+1
View File
@@ -134,6 +134,7 @@ typedef enum {
} GPIO_PUPD_FUNC;
void prev_raspi_pin_mode(GPIO_PIN pin, GPIO_FUNC mode);
void prev_raspi_pin_write(GPIO_PIN pin, int pin_value);
int rt_hw_gpio_init(void);
#endif /* __DRV_GPIO_H__ */
bsp/raspberry-pi/raspi4-32/driver/drv_spi.c
+296
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File diff suppressed because it is too large Load Diff
bsp/raspberry-pi/raspi4-32/driver/drv_spi.h
+87
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@@ -0,0 +1,87 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-06-16 bigmagic first version
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include "drv_gpio.h"
#define SPI_REG_CS(BASE) HWREG32(BASE + 0x00)
#define SPI_REG_FIFO(BASE) HWREG32(BASE + 0x04)
#define SPI_REG_CLK(BASE) HWREG32(BASE + 0x08)
#define SPI_REG_DLEN(BASE) HWREG32(BASE + 0x0C)
#define SPI_REG_LTOH(BASE) HWREG32(BASE + 0x10)
#define SPI_REG_DC(BASE) HWREG32(BASE + 0x14)
/* CS Register */
#define SPI_CS_LOSSI_LONG_32BIT (1 << 25)
#define SPI_CS_LOSSI_DMA_MODE (1 << 24)
#define SPI_CS_CSPOL2 (1 << 23)
#define SPI_CS_CSPOL1 (1 << 22)
#define SPI_CS_CSPOL0 (1 << 21)
#define SPI_CS_RX_FIFO_FULL (1 << 20)
#define SPI_CS_RX_FIFO_3_QUARTER (1 << 19)
#define SPI_CS_TX_DATA (1 << 18)
#define SPI_CS_RX_DATA (1 << 17)
#define SPI_CS_DONE (1 << 16)
#define SPI_CS_LOSSI_EN (1 << 13)
#define SPI_CS_READ_EN (1 << 12)
#define SPI_CS_AUTO_CS (1 << 11)
#define SPI_CS_INTR_RXR (1 << 10)
#define SPI_CS_INTR_DONE (1 << 9)
#define SPI_CS_DMA_EN (1 << 8)
#define SPI_CS_TA (1 << 7)
#define SPI_CS_CSPOL_HIGH (1 << 6)
#define SPI_CS_CLEAR_RX (2 << 4)
#define SPI_CS_CLEAR_TX (1 << 4)
#define SPI_CS_CPOL (1 << 3)
#define SPI_CS_CPHA (1 << 2)
#define SPI_CS_CHIP_SELECT_2 (2 << 0)
#define SPI_CS_CHIP_SELECT_1 (1 << 0)
#define SPI_CS_CHIP_SELECT_0 (0 << 0)
struct raspi_spi_hw_config
{
rt_uint8_t spi_num;
GPIO_PIN sclk_pin;
GPIO_FUNC sclk_mode;
GPIO_PIN mosi_pin;
GPIO_FUNC mosi_mode;
GPIO_PIN miso_pin;
GPIO_FUNC miso_mode;
#if defined (BSP_USING_SPI0_DEVICE0) || defined (BSP_USING_SPI1_DEVICE0)
GPIO_PIN ce0_pin;
GPIO_FUNC ce0_mode;
#endif
#if defined (BSP_USING_SPI0_DEVICE1) || defined (BSP_USING_SPI1_DEVICE1)
GPIO_PIN ce1_pin;
GPIO_FUNC ce1_mode;
#endif
#if defined (BSP_USING_SPI1_DEVICE2)
GPIO_PIN ce2_pin;
GPIO_FUNC ce2_mode;
#endif
rt_ubase_t hw_base;
};
struct raspi_spi_device
{
char *device_name;
struct rt_spi_bus *spi_bus;
struct rt_spi_device *spi_device;
struct raspi_spi_hw_config *spi_hw_config;
GPIO_PIN cs_pin;
};
int rt_hw_spi_init(void);
#endif
bsp/raspberry-pi/raspi4-32/driver/raspi4.h
+12
View File
@@ -61,6 +61,18 @@
#define AUX_BASE (PER_BASE + AUX_BASE_OFFSET)
#define IRQ_PL011 (96 + 57)
/* SPI */
#define SPI_0_BASE_OFFSET (0x00204000)
#define SPI_3_BASE_OFFSET (0x00204600)
#define SPI_4_BASE_OFFSET (0x00204800)
#define SPI_5_BASE_OFFSET (0x00204A00)
#define SPI_6_BASE_OFFSET (0x00204C00)
#define SPI_0_BASE (PER_BASE + SPI_0_BASE_OFFSET)
#define SPI_3_BASE (PER_BASE + SPI_3_BASE_OFFSET)
#define SPI_4_BASE (PER_BASE + SPI_4_BASE_OFFSET)
#define SPI_5_BASE (PER_BASE + SPI_5_BASE_OFFSET)
#define SPI_6_BASE (PER_BASE + SPI_6_BASE_OFFSET)
/* Peripheral IRQ OR-ing */
#define PACTL_CS HWREG32((PER_BASE + PACTL_CS_OFFSET))
typedef enum {
bsp/raspberry-pi/raspi4-32/rtconfig.h
+4
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@@ -86,6 +86,7 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_SPI
/* Using USB */
@@ -173,6 +174,9 @@
#define BSP_USING_GIC
#define BSP_USING_GIC400
#define BSP_USING_PIN
#define BSP_USING_SPI
#define BSP_USING_SPI0_BUS
#define BSP_USING_SPI0_DEVICE0
#define BSP_USING_CORETIMER
/* Board Peripheral Drivers */