mirror of
https://github.com/RT-Thread/rt-thread.git
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[bsp/n32]n32h760zil7-stb bsp修复完善，添加 n32h497zgl7-evb和n32h487zgl7-evb bsp (#11627)
1、修改n32\n32gxx_lxx\n32g4frml-stb中的GCC启动文件bl entry 2、修复完善n32h760zil7-stb bsp，支持GCC环境、支持更多外设 3、添加n32h487zgl7-evb初版BSP 4、添加n32h497zgl7-evb初版BSP 5、删除n32g452xx这个bsp --------- Co-authored-by: OnlyoutzZ <OnlyoutzZ+github[bot]@noreply.github.com>
This commit is contained in:
Onlyou_tzZ
OnlyoutzZ
@@ -342,8 +342,9 @@
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"n32/n32gxx_lxx/n32l43xrl-stb",
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"n32/n32gxx_lxx/n32l436-evb",
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"n32/n32gxx_lxx/n32wb45xl-evb",
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"n32g452xx/n32g452xx-mini-system",
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"n32/n32hxxx/n32h760zil7-stb",
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"n32/n32hxxx/n32h760zil7-stb",
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"n32/n32hxxx/n32h487zgl7-evb",
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"n32/n32hxxx/n32h497zgl7-evb",
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"apm32/apm32f103xe-minibroard",
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"apm32/apm32f407ig-minibroard",
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"apm32/apm32f407zg-evalboard",
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+17
-19
@@ -317,21 +317,24 @@ This document is based on the RT-Thread mainline repository and categorizes the
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#### 🟡 N32
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| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT |
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| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | PWM |ENCODER | LPTIM | NAND | ETH | ON-Chip FLASH |
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|----------|------|------|-----|-----|-----|---------|-----|-----|-----|-----|
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| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
|
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| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
|
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| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
|
||||
| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
|
||||
| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | - |
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| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
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| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
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| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
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#### 🟡 NRF5x
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@@ -420,11 +423,6 @@ This document is based on the RT-Thread mainline repository and categorizes the
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| [swm320-mini](synwit/swm320-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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| [swm341-mini](synwit/swm341-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
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#### ⚪ N32G452xx
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| BSP Name | GPIO | UART | ADC | CAN | DAC | Flash | HWTimer | I2C | PWM | RTC | SDIO | SPI | WDT |
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|----------|------|------|-----|-----|-----|-------|---------|-----|-----|-----|------|-----|-----|
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| [n32g452xx-mini-system](n32g452xx/n32g452xx-mini-system) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ |
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#### ⚪ W60x
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| BSP Name | GPIO | UART | ADC | Crypto | Flash | HWTimer | WDT | PWM | I2C | SPI |
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|----------|------|------|-----|--------|-------|---------|-----|-----|-----|-----|
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+1
-1
@@ -72,7 +72,7 @@ LoopFillZerobss:
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/* Call static constructors */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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bl entry
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bx lr
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.size Reset_Handler, .-Reset_Handler
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@@ -5,8 +5,5 @@
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# 从 .ignore_format.yml 迁移的规则
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/n32h760zil7-stb/board/Cube_Config/
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/n32h760zil7-stb/board/Cube_Config/data/
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/n32h760zil7-stb/board/Cube_Config/Driver/
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/n32h760zil7-stb/board/Cube_Config/MDK-ARM/
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/n32h760zil7-stb/board/Cube_Config/startup/
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/n32h760zil7-stb/board/Cube_Config/USER/
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/n32h487zgl7-evb/board/Cube_Config/
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/n32h497zgl7-evb/board/Cube_Config/
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@@ -6,4 +6,14 @@ config SOC_SERIES_N32H7xx
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select ARCH_ARM_CORTEX_M7
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select SOC_FAMILY_N32
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config SOC_SERIES_N32H47x_48x
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bool
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select ARCH_ARM_CORTEX_M4
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select SOC_FAMILY_N32
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config SOC_SERIES_N32H49x
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bool
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select ARCH_ARM_CORTEX_M4
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select SOC_FAMILY_N32
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@@ -12,24 +12,87 @@ if GetDepend(['RT_USING_PIN']):
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src += ['drv_gpio.c']
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if GetDepend(['RT_USING_SERIAL']):
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src += ['drv_usart.c']
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if GetDepend(['RT_USING_SERIAL_V2']):
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src += ['drv_usart_v2.c']
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else:
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src += ['drv_usart.c']
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if GetDepend(['BSP_USING_CLOCK_TIMER']):
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src += ['drv_tim.c']
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if GetDepend(['BSP_USING_PWM']):
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src += ['drv_pwm.c', 'drv_tim.c']
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if GetDepend(['RT_USING_SPI']):
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src += ['drv_spi.c']
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if GetDepend(['RT_USING_QSPI']):
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src += ['drv_qspi.c']
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if GetDepend(['RT_USING_I2C']):
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if GetDepend('BSP_USING_HARD_I2C1') or GetDepend('BSP_USING_HARD_I2C2') or GetDepend('BSP_USING_HARD_I2C3') or GetDepend('BSP_USING_HARD_I2C4') or GetDepend('BSP_USING_HARD_I2C5') or GetDepend('BSP_USING_HARD_I2C6') or GetDepend('BSP_USING_HARD_I2C7') or GetDepend('BSP_USING_HARD_I2C8') or GetDepend('BSP_USING_HARD_I2C9') or GetDepend('BSP_USING_HARD_I2C10'):
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src += ['drv_hard_i2c.c']
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if GetDepend('BSP_USING_ONCHIP_RTC'):
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src += ['drv_rtc.c']
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if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
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src += ['drv_eth.c']
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if GetDepend(['RT_USING_ADC']):
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src += ['drv_adc.c']
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if GetDepend(['RT_USING_DAC']):
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src += ['drv_dac.c']
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if GetDepend(['RT_USING_CAN']):
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if GetDepend(['SOC_SERIES_N32H7xx']) or GetDepend(['SOC_SERIES_N32H47x_48x']) or GetDepend(['SOC_SERIES_N32H49x']):
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src += ['drv_fdcan.c']
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else:
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src += ['drv_can.c']
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if GetDepend(['RT_USING_PM']):
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src += ['drv_pm.c']
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if GetDepend(['BSP_USING_LPTIM']):
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src += ['drv_lptim.c']
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if GetDepend('BSP_USING_SDRAM'):
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src += ['drv_sdram.c']
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if GetDepend(['BSP_USING_NAND']):
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src += ['drv_nand.c']
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if GetDepend('BSP_USING_LCD'):
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src += ['drv_lcd.c']
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if GetDepend('BSP_USING_ONCHIP_RTC'):
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src += ['drv_rtc.c']
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if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H49x']):
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src += [os.path.join('drv_flash', 'drv_flash_h49x.c')]
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if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H47x_48x']):
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src += [os.path.join('drv_flash', 'drv_flash_h47x_48x.c')]
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if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H7xx']):
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src += [os.path.join('drv_flash', 'drv_flash_h7xx.c')]
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if GetDepend(['BSP_USING_WDT']):
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src += ['drv_wdt.c']
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|
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if GetDepend(['BSP_USING_SDIO']):
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if GetDepend('SOC_SERIES_N32H7xx'):
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src += ['drv_sdmmc.c']
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else:
|
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src += ['drv_sdio.c']
|
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|
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if GetDepend(['BSP_USING_PULSE_ENCODER']):
|
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src += ['drv_pulse_encoder.c', 'drv_tim.c']
|
||||
|
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|
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path += [os.path.join(cwd, 'config')]
|
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|
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if GetDepend('BSP_USING_ON_CHIP_FLASH'):
|
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path += [os.path.join(cwd, 'drv_flash')]
|
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|
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
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|
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Return('group')
|
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|
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+54
-54
@@ -19,72 +19,72 @@ extern "C" {
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|
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
|
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{ \
|
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.ADCx = ADC1, \
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.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \
|
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.EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \
|
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.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
|
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.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
|
||||
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
|
||||
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
|
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.Init.MultiChEn = DISABLE, \
|
||||
.Init.ContinueConvEn = DISABLE, \
|
||||
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
|
||||
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
|
||||
.Init.DatAlign = ADC_DAT_ALIGN_R, \
|
||||
.Init.ChsNumber = 1U, \
|
||||
.Init.Resolution = ADC_DATA_RES_12BIT, \
|
||||
.Rank = 1U, \
|
||||
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
|
||||
#define ADC1_CONFIG \
|
||||
{ \
|
||||
.ADCx = ADC1, \
|
||||
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \
|
||||
.EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \
|
||||
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
|
||||
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
|
||||
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
|
||||
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
|
||||
.Init.MultiChEn = DISABLE, \
|
||||
.Init.ContinueConvEn = DISABLE, \
|
||||
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
|
||||
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
|
||||
.Init.DatAlign = ADC_DAT_ALIGN_R, \
|
||||
.Init.ChsNumber = 1U, \
|
||||
.Init.Resolution = ADC_DATA_RES_12BIT, \
|
||||
.Rank = 1U, \
|
||||
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
|
||||
}
|
||||
#endif /* ADC1_CONFIG */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_CONFIG
|
||||
#define ADC2_CONFIG \
|
||||
{ \
|
||||
.ADCx = ADC2, \
|
||||
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \
|
||||
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
|
||||
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
|
||||
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
|
||||
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
|
||||
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
|
||||
.Init.MultiChEn = DISABLE, \
|
||||
.Init.ContinueConvEn = DISABLE, \
|
||||
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
|
||||
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
|
||||
.Init.DatAlign = ADC_DAT_ALIGN_R, \
|
||||
.Init.ChsNumber = 1U, \
|
||||
.Init.Resolution = ADC_DATA_RES_12BIT, \
|
||||
.Rank = 1U, \
|
||||
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
|
||||
#define ADC2_CONFIG \
|
||||
{ \
|
||||
.ADCx = ADC2, \
|
||||
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \
|
||||
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
|
||||
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
|
||||
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
|
||||
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
|
||||
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
|
||||
.Init.MultiChEn = DISABLE, \
|
||||
.Init.ContinueConvEn = DISABLE, \
|
||||
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
|
||||
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
|
||||
.Init.DatAlign = ADC_DAT_ALIGN_R, \
|
||||
.Init.ChsNumber = 1U, \
|
||||
.Init.Resolution = ADC_DATA_RES_12BIT, \
|
||||
.Rank = 1U, \
|
||||
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
|
||||
}
|
||||
#endif /* ADC2_CONFIG */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_CONFIG
|
||||
#define ADC3_CONFIG \
|
||||
{ \
|
||||
.ADCx = ADC3, \
|
||||
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \
|
||||
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
|
||||
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
|
||||
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
|
||||
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
|
||||
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
|
||||
.Init.MultiChEn = DISABLE, \
|
||||
.Init.ContinueConvEn = DISABLE, \
|
||||
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
|
||||
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
|
||||
.Init.DatAlign = ADC_DAT_ALIGN_R, \
|
||||
.Init.ChsNumber = 1U, \
|
||||
.Init.Resolution = ADC_DATA_RES_12BIT, \
|
||||
.Rank = 1U, \
|
||||
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
|
||||
#define ADC3_CONFIG \
|
||||
{ \
|
||||
.ADCx = ADC3, \
|
||||
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \
|
||||
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
|
||||
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
|
||||
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
|
||||
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
|
||||
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
|
||||
.Init.MultiChEn = DISABLE, \
|
||||
.Init.ContinueConvEn = DISABLE, \
|
||||
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
|
||||
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
|
||||
.Init.DatAlign = ADC_DAT_ALIGN_R, \
|
||||
.Init.ChsNumber = 1U, \
|
||||
.Init.Resolution = ADC_DATA_RES_12BIT, \
|
||||
.Rank = 1U, \
|
||||
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
|
||||
}
|
||||
#endif /* ADC3_CONFIG */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
@@ -0,0 +1,126 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-06-22 lin.qi first version
|
||||
*/
|
||||
|
||||
#ifndef __CAN_CONFIG_H__
|
||||
#define __CAN_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "n32h7xx_fdcan.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
*\*\name n32_fdcan_config.
|
||||
*\*\brief FDCAN instance configuration structure.
|
||||
*\*\note Clock and GPIO initialization are handled by CubeMX-generated code
|
||||
*\*\ in n32h7xx_cfg.c (from Cube.ntfx). NVIC interrupt vector numbers
|
||||
*\*\ are hardcoded in drv_fdcan.c per instance.
|
||||
*/
|
||||
struct n32_fdcan_config
|
||||
{
|
||||
const char *name; /**< device name */
|
||||
FDCAN_Module *Instance; /**< FDCAN peripheral base address */
|
||||
};
|
||||
|
||||
/*
|
||||
* Hardware connection pairs on N32H760ZIL7-STB:
|
||||
* FDCAN1 <-> FDCAN2
|
||||
* FDCAN3 <-> FDCAN4
|
||||
* FDCAN5 <-> FDCAN6
|
||||
* FDCAN7 <-> FDCAN8
|
||||
*/
|
||||
|
||||
#if defined(BSP_USING_FDCAN1)
|
||||
#ifndef FDCAN1_CONFIG
|
||||
#define FDCAN1_CONFIG \
|
||||
{ \
|
||||
.name = "fdcan1", \
|
||||
.Instance = FDCAN1, \
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_USING_FDCAN1 */
|
||||
|
||||
#if defined(BSP_USING_FDCAN2)
|
||||
#ifndef FDCAN2_CONFIG
|
||||
#define FDCAN2_CONFIG \
|
||||
{ \
|
||||
.name = "fdcan2", \
|
||||
.Instance = FDCAN2, \
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_USING_FDCAN2 */
|
||||
|
||||
#if defined(BSP_USING_FDCAN3)
|
||||
#ifndef FDCAN3_CONFIG
|
||||
#define FDCAN3_CONFIG \
|
||||
{ \
|
||||
.name = "fdcan3", \
|
||||
.Instance = FDCAN3, \
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_USING_FDCAN3 */
|
||||
|
||||
#if defined(BSP_USING_FDCAN4)
|
||||
#ifndef FDCAN4_CONFIG
|
||||
#define FDCAN4_CONFIG \
|
||||
{ \
|
||||
.name = "fdcan4", \
|
||||
.Instance = FDCAN4, \
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_USING_FDCAN4 */
|
||||
|
||||
#if defined(BSP_USING_FDCAN5)
|
||||
#ifndef FDCAN5_CONFIG
|
||||
#define FDCAN5_CONFIG \
|
||||
{ \
|
||||
.name = "fdcan5", \
|
||||
.Instance = FDCAN5, \
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_USING_FDCAN5 */
|
||||
|
||||
#if defined(BSP_USING_FDCAN6)
|
||||
#ifndef FDCAN6_CONFIG
|
||||
#define FDCAN6_CONFIG \
|
||||
{ \
|
||||
.name = "fdcan6", \
|
||||
.Instance = FDCAN6, \
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_USING_FDCAN6 */
|
||||
|
||||
#if defined(BSP_USING_FDCAN7)
|
||||
#ifndef FDCAN7_CONFIG
|
||||
#define FDCAN7_CONFIG \
|
||||
{ \
|
||||
.name = "fdcan7", \
|
||||
.Instance = FDCAN7, \
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_USING_FDCAN7 */
|
||||
|
||||
#if defined(BSP_USING_FDCAN8)
|
||||
#ifndef FDCAN8_CONFIG
|
||||
#define FDCAN8_CONFIG \
|
||||
{ \
|
||||
.name = "fdcan8", \
|
||||
.Instance = FDCAN8, \
|
||||
}
|
||||
#endif
|
||||
#endif /* BSP_USING_FDCAN8 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CAN_CONFIG_H__ */
|
||||
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-06-09 li.mengmeng first version
|
||||
*/
|
||||
|
||||
#ifndef __DAC_CONFIG_H__
|
||||
#define __DAC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_DAC1
|
||||
#ifndef DAC1_CONFIG
|
||||
#define DAC1_CONFIG \
|
||||
{ \
|
||||
.DACx = DAC1, \
|
||||
.DAC_Module = DAC12, \
|
||||
.periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \
|
||||
.EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \
|
||||
.DAC_clk_pres = 150, \
|
||||
.Init.DAC_Trigger = DAC_Trigger_Software, \
|
||||
.Init.DAC_Trigger2 = DAC_Trigger2_Software, \
|
||||
.Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \
|
||||
.Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \
|
||||
.Init.DAC_OutputBuffer = DISABLE, \
|
||||
.Init.DAC_TriggerEnable = ENABLE, \
|
||||
.Init.DAC_ConnectOnChipPeripheral = DISABLE, \
|
||||
.Init.DAC_ConnectExternalPin = ENABLE, \
|
||||
.Init.DAC_DMADoubleDataMode = DISABLE, \
|
||||
.Init.DAC_SignedFormat = DISABLE, \
|
||||
}
|
||||
#endif /* DAC1_CONFIG */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
#ifdef BSP_USING_DAC2
|
||||
#ifndef DAC2_CONFIG
|
||||
#define DAC2_CONFIG \
|
||||
{ \
|
||||
.DACx = DAC2, \
|
||||
.DAC_Module = DAC12, \
|
||||
.periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \
|
||||
.EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \
|
||||
.DAC_clk_pres = 150, \
|
||||
.Init.DAC_Trigger = DAC_Trigger_Software, \
|
||||
.Init.DAC_Trigger2 = DAC_Trigger2_Software, \
|
||||
.Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \
|
||||
.Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \
|
||||
.Init.DAC_OutputBuffer = DISABLE, \
|
||||
.Init.DAC_TriggerEnable = ENABLE, \
|
||||
.Init.DAC_ConnectOnChipPeripheral = DISABLE, \
|
||||
.Init.DAC_ConnectExternalPin = ENABLE, \
|
||||
.Init.DAC_DMADoubleDataMode = DISABLE, \
|
||||
.Init.DAC_SignedFormat = DISABLE, \
|
||||
}
|
||||
#endif /* DAC2_CONFIG */
|
||||
#endif /* BSP_USING_DAC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DAC_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
+179
-187
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-06-23 ox-horse first version
|
||||
*/
|
||||
|
||||
#ifndef __LPTIM_CONFIG_H__
|
||||
#define __LPTIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef LPTIM_DEV_INFO_CONFIG
|
||||
#define LPTIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 3000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = CLOCK_TIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* LPTIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_LPTIM1
|
||||
#ifndef LPTIM1_CONFIG
|
||||
#define LPTIM1_CONFIG \
|
||||
{ \
|
||||
.timer = LPTIM1, \
|
||||
.tim_irqn = LPTIM1_WKUP_IRQn, \
|
||||
.name = "lptim1", \
|
||||
}
|
||||
#endif /* LPTIM1_CONFIG */
|
||||
#endif /* BSP_USING_LPTIM1 */
|
||||
|
||||
#ifdef BSP_USING_LPTIM2
|
||||
#ifndef LPTIM2_CONFIG
|
||||
#define LPTIM2_CONFIG \
|
||||
{ \
|
||||
.timer = LPTIM2, \
|
||||
.tim_irqn = LPTIM2_WKUP_IRQn, \
|
||||
.name = "lptim2", \
|
||||
}
|
||||
#endif /* LPTIM2_CONFIG */
|
||||
#endif /* BSP_USING_LPTIM2 */
|
||||
|
||||
#ifdef BSP_USING_LPTIM3
|
||||
#ifndef LPTIM3_CONFIG
|
||||
#define LPTIM3_CONFIG \
|
||||
{ \
|
||||
.timer = LPTIM3, \
|
||||
.tim_irqn = LPTIM3_WKUP_IRQn, \
|
||||
.name = "lptim3", \
|
||||
}
|
||||
#endif /* LPTIM3_CONFIG */
|
||||
#endif /* BSP_USING_LPTIM3 */
|
||||
|
||||
#ifdef BSP_USING_LPTIM4
|
||||
#ifndef LPTIM4_CONFIG
|
||||
#define LPTIM4_CONFIG \
|
||||
{ \
|
||||
.timer = LPTIM4, \
|
||||
.tim_irqn = LPTIM4_WKUP_IRQn, \
|
||||
.name = "lptim4", \
|
||||
}
|
||||
#endif /* LPTIM4_CONFIG */
|
||||
#endif /* BSP_USING_LPTIM4 */
|
||||
|
||||
#ifdef BSP_USING_LPTIM5
|
||||
#ifndef LPTIM5_CONFIG
|
||||
#define LPTIM5_CONFIG \
|
||||
{ \
|
||||
.timer = LPTIM5, \
|
||||
.tim_irqn = LPTIM5_WKUP_IRQn, \
|
||||
.name = "lptim5", \
|
||||
}
|
||||
#endif /* LPTIM5_CONFIG */
|
||||
#endif /* BSP_USING_LPTIM5 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LPTIM_CONFIG_H__ */
|
||||
@@ -0,0 +1,178 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-07-06 ox-horse first version
|
||||
*/
|
||||
|
||||
#ifndef __PULSE_ENCODER_CONFIG_H__
|
||||
#define __PULSE_ENCODER_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER1
|
||||
#ifndef PULSE_ENCODER1_CONFIG
|
||||
#define PULSE_ENCODER1_CONFIG \
|
||||
{ \
|
||||
.timer = ATIM1, \
|
||||
.tim_irqn = ATIM1_UP_IRQn, \
|
||||
.name = "pulse1", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER1_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER1 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER2
|
||||
#ifndef PULSE_ENCODER2_CONFIG
|
||||
#define PULSE_ENCODER2_CONFIG \
|
||||
{ \
|
||||
.timer = ATIM2, \
|
||||
.tim_irqn = ATIM2_UP_IRQn, \
|
||||
.name = "pulse2", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER2_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER2 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER3
|
||||
#ifndef PULSE_ENCODER3_CONFIG
|
||||
#define PULSE_ENCODER3_CONFIG \
|
||||
{ \
|
||||
.timer = ATIM3, \
|
||||
.tim_irqn = ATIM3_UP_IRQn, \
|
||||
.name = "pulse3", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER3_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER3 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER4
|
||||
#ifndef PULSE_ENCODER4_CONFIG
|
||||
#define PULSE_ENCODER4_CONFIG \
|
||||
{ \
|
||||
.timer = ATIM4, \
|
||||
.tim_irqn = ATIM4_UP_IRQn, \
|
||||
.name = "pulse4", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER4_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER4 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER5
|
||||
#ifndef PULSE_ENCODER5_CONFIG
|
||||
#define PULSE_ENCODER5_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA1, \
|
||||
.tim_irqn = GTIMA1_IRQn, \
|
||||
.name = "pulse5", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER5_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER5 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER6
|
||||
#ifndef PULSE_ENCODER6_CONFIG
|
||||
#define PULSE_ENCODER6_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA2, \
|
||||
.tim_irqn = GTIMA2_IRQn, \
|
||||
.name = "pulse6", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER6_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER6 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER7
|
||||
#ifndef PULSE_ENCODER7_CONFIG
|
||||
#define PULSE_ENCODER7_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA3, \
|
||||
.tim_irqn = GTIMA3_IRQn, \
|
||||
.name = "pulse7", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER7_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER7 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER8
|
||||
#ifndef PULSE_ENCODER8_CONFIG
|
||||
#define PULSE_ENCODER8_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA4, \
|
||||
.tim_irqn = GTIMA4_IRQn, \
|
||||
.name = "pulse8", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER8_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER8 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER9
|
||||
#ifndef PULSE_ENCODER9_CONFIG
|
||||
#define PULSE_ENCODER9_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA5, \
|
||||
.tim_irqn = GTIMA5_IRQn, \
|
||||
.name = "pulse9", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER9_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER9 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER10
|
||||
#ifndef PULSE_ENCODER10_CONFIG
|
||||
#define PULSE_ENCODER10_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA6, \
|
||||
.tim_irqn = GTIMA6_IRQn, \
|
||||
.name = "pulse10", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER10_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER10 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER11
|
||||
#ifndef PULSE_ENCODER11_CONFIG
|
||||
#define PULSE_ENCODER11_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA7, \
|
||||
.tim_irqn = GTIMA7_IRQn, \
|
||||
.name = "pulse11", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER11_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER11 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER12
|
||||
#ifndef PULSE_ENCODER12_CONFIG
|
||||
#define PULSE_ENCODER12_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMB1, \
|
||||
.tim_irqn = GTIMB1_IRQn, \
|
||||
.name = "pulse12", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER12_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER12 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER13
|
||||
#ifndef PULSE_ENCODER13_CONFIG
|
||||
#define PULSE_ENCODER13_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMB2, \
|
||||
.tim_irqn = GTIMB2_IRQn, \
|
||||
.name = "pulse13", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER13_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER13 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER14
|
||||
#ifndef PULSE_ENCODER14_CONFIG
|
||||
#define PULSE_ENCODER14_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMB3, \
|
||||
.tim_irqn = GTIMB3_IRQn, \
|
||||
.name = "pulse14", \
|
||||
}
|
||||
#endif /* PULSE_ENCODER14_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER14 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PULSE_ENCODER_CONFIG_H__ */
|
||||
@@ -0,0 +1,178 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-06-23 ox-horse first version
|
||||
*/
|
||||
|
||||
#ifndef __PWM_CONFIG_H__
|
||||
#define __PWM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM1
|
||||
#ifndef PWM1_CONFIG
|
||||
#define PWM1_CONFIG \
|
||||
{ \
|
||||
.timer = ATIM1, \
|
||||
.name = "pwm1", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM1_CONFIG */
|
||||
#endif /* BSP_USING_PWM1 */
|
||||
|
||||
#ifdef BSP_USING_PWM2
|
||||
#ifndef PWM2_CONFIG
|
||||
#define PWM2_CONFIG \
|
||||
{ \
|
||||
.timer = ATIM2, \
|
||||
.name = "pwm2", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM2_CONFIG */
|
||||
#endif /* BSP_USING_PWM2 */
|
||||
|
||||
#ifdef BSP_USING_PWM3
|
||||
#ifndef PWM3_CONFIG
|
||||
#define PWM3_CONFIG \
|
||||
{ \
|
||||
.timer = ATIM3, \
|
||||
.name = "pwm3", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM3_CONFIG */
|
||||
#endif /* BSP_USING_PWM3 */
|
||||
|
||||
#ifdef BSP_USING_PWM4
|
||||
#ifndef PWM4_CONFIG
|
||||
#define PWM4_CONFIG \
|
||||
{ \
|
||||
.timer = ATIM4, \
|
||||
.name = "pwm4", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM4_CONFIG */
|
||||
#endif /* BSP_USING_PWM4 */
|
||||
|
||||
#ifdef BSP_USING_PWM5
|
||||
#ifndef PWM5_CONFIG
|
||||
#define PWM5_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA1, \
|
||||
.name = "pwm5", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM5_CONFIG */
|
||||
#endif /* BSP_USING_PWM5 */
|
||||
|
||||
#ifdef BSP_USING_PWM6
|
||||
#ifndef PWM6_CONFIG
|
||||
#define PWM6_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA2, \
|
||||
.name = "pwm6", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM6_CONFIG */
|
||||
#endif /* BSP_USING_PWM6 */
|
||||
|
||||
#ifdef BSP_USING_PWM7
|
||||
#ifndef PWM7_CONFIG
|
||||
#define PWM7_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA3, \
|
||||
.name = "pwm7", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM7_CONFIG */
|
||||
#endif /* BSP_USING_PWM7 */
|
||||
|
||||
#ifdef BSP_USING_PWM8
|
||||
#ifndef PWM8_CONFIG
|
||||
#define PWM8_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA4, \
|
||||
.name = "pwm8", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM8_CONFIG */
|
||||
#endif /* BSP_USING_PWM8 */
|
||||
|
||||
#ifdef BSP_USING_PWM9
|
||||
#ifndef PWM9_CONFIG
|
||||
#define PWM9_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA5, \
|
||||
.name = "pwm9", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM9_CONFIG */
|
||||
#endif /* BSP_USING_PWM9 */
|
||||
|
||||
#ifdef BSP_USING_PWM10
|
||||
#ifndef PWM10_CONFIG
|
||||
#define PWM10_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA6, \
|
||||
.name = "pwm10", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM10_CONFIG */
|
||||
#endif /* BSP_USING_PWM10 */
|
||||
|
||||
#ifdef BSP_USING_PWM11
|
||||
#ifndef PWM11_CONFIG
|
||||
#define PWM11_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMA7, \
|
||||
.name = "pwm11", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM11_CONFIG */
|
||||
#endif /* BSP_USING_PWM11 */
|
||||
|
||||
#ifdef BSP_USING_PWM12
|
||||
#ifndef PWM12_CONFIG
|
||||
#define PWM12_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMB1, \
|
||||
.name = "pwm12", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM12_CONFIG */
|
||||
#endif /* BSP_USING_PWM12 */
|
||||
|
||||
#ifdef BSP_USING_PWM13
|
||||
#ifndef PWM13_CONFIG
|
||||
#define PWM13_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMB2, \
|
||||
.name = "pwm13", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM13_CONFIG */
|
||||
#endif /* BSP_USING_PWM13 */
|
||||
|
||||
#ifdef BSP_USING_PWM14
|
||||
#ifndef PWM14_CONFIG
|
||||
#define PWM14_CONFIG \
|
||||
{ \
|
||||
.timer = GTIMB3, \
|
||||
.name = "pwm14", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM14_CONFIG */
|
||||
#endif /* BSP_USING_PWM14 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PWM_CONFIG_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -20,11 +20,23 @@ extern "C" {
|
||||
|
||||
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
#include "h7/dma_config.h"
|
||||
#include "h7/uart_config.h"
|
||||
#include "h7/i2c_hard_config.h"
|
||||
#include "h7/adc_config.h"
|
||||
#include "h7/spi_config.h"
|
||||
#include "h7xx/dma_config.h"
|
||||
#include "h7xx/uart_config.h"
|
||||
#include "h7xx/i2c_hard_config.h"
|
||||
#include "h7xx/adc_config.h"
|
||||
#include "h7xx/spi_config.h"
|
||||
#include "h7xx/tim_config.h"
|
||||
#include "h7xx/dac_config.h"
|
||||
#include "h7xx/can_config.h"
|
||||
#include "h7xx/pwm_config.h"
|
||||
#include "h7xx/pulse_encoder_config.h"
|
||||
#include "h7xx/lptim_config.h"
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
#include "h49x/dma_config.h"
|
||||
#include "h49x/uart_config.h"
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
#include "h47x_48x/dma_config.h"
|
||||
#include "h47x_48x/uart_config.h"
|
||||
#endif /* defined(SOC_SERIES_N32H7xx) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-01-24 ox-horse first version
|
||||
* 2026-06-09 li.mengmeng port for N32H7xx
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
|
||||
|
||||
#include "n32h7xx_rcc.h"
|
||||
#include "n32h7xx_dac.h"
|
||||
#include "drv_config.h"
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.dac"
|
||||
#include <drv_log.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
DACX DACx;
|
||||
DAC_Module *DAC_Module;
|
||||
uint32_t periph_clk;
|
||||
void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd);
|
||||
uint32_t DAC_clk_pres;
|
||||
|
||||
GPIO_Module *GPIOx;
|
||||
uint16_t GPIO_Pin;
|
||||
uint32_t GPIO_RCC;
|
||||
|
||||
DAC_InitType Init;
|
||||
} DAC_InitInfo_t;
|
||||
|
||||
static DAC_InitInfo_t dac_config[] = {
|
||||
#ifdef BSP_USING_DAC1
|
||||
DAC1_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_DAC2
|
||||
DAC2_CONFIG,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
static struct n32_dac n32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
|
||||
|
||||
struct n32_dac
|
||||
{
|
||||
DAC_InitInfo_t DAC_Info;
|
||||
struct rt_dac_device n32_dac_device;
|
||||
};
|
||||
|
||||
static rt_err_t n32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
|
||||
{
|
||||
DAC_InitInfo_t *n32_dac_info;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
n32_dac_info = device->parent.user_data;
|
||||
|
||||
/* Enable DAC */
|
||||
DAC_Enable(n32_dac_info->DACx, ENABLE);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t n32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
|
||||
{
|
||||
DAC_InitInfo_t *n32_dac_info;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
n32_dac_info = device->parent.user_data;
|
||||
|
||||
/* Disable DAC */
|
||||
DAC_Enable(n32_dac_info->DACx, DISABLE);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_uint8_t n32_dac_get_resolution(struct rt_dac_device *device)
|
||||
{
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
/* N32H7xx DAC supports 12-bit resolution */
|
||||
return 12;
|
||||
}
|
||||
|
||||
static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
|
||||
{
|
||||
rt_uint16_t set_value;
|
||||
DAC_InitInfo_t *n32_dac_info;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(value != RT_NULL);
|
||||
|
||||
n32_dac_info = device->parent.user_data;
|
||||
|
||||
set_value = (rt_uint16_t)(*value);
|
||||
if (set_value > 4095)
|
||||
{
|
||||
set_value = 4095;
|
||||
}
|
||||
|
||||
/* Set DAC output data (12-bit right-aligned) */
|
||||
DAC_SetData(n32_dac_info->DACx, DAC_ALIGN_R_12BIT, set_value);
|
||||
|
||||
/* Trigger software conversion */
|
||||
DAC_SoftTrgEnable(n32_dac_info->DACx, ENABLE);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_dac_ops n32_dac_ops = {
|
||||
.disabled = n32_dac_disabled,
|
||||
.enabled = n32_dac_enabled,
|
||||
.convert = n32_set_dac_value,
|
||||
.get_resolution = n32_dac_get_resolution,
|
||||
};
|
||||
|
||||
static int n32_dac_init(void)
|
||||
{
|
||||
int result = RT_EOK;
|
||||
char name_buf[5] = { 'd', 'a', 'c', '0', 0 };
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++)
|
||||
{
|
||||
n32_dac_obj[i].DAC_Info = dac_config[i];
|
||||
|
||||
/* Set device name */
|
||||
name_buf[3] = '0';
|
||||
if (n32_dac_obj[i].DAC_Info.DACx == DAC1)
|
||||
name_buf[3] = '1';
|
||||
else if (n32_dac_obj[i].DAC_Info.DACx == DAC2)
|
||||
name_buf[3] = '2';
|
||||
|
||||
/* Enable DAC peripheral clock */
|
||||
n32_dac_obj[i].DAC_Info.EnablePeriphClk(n32_dac_obj[i].DAC_Info.periph_clk, ENABLE);
|
||||
/* Config DAC12 prescaler factor,DAC_CLK = 1M*/
|
||||
DAC_ConfigClkPrescaler(n32_dac_obj[i].DAC_Info.DAC_Module, n32_dac_obj[i].DAC_Info.DAC_clk_pres);
|
||||
|
||||
DAC_SetHighFrequencyMode(n32_dac_obj[i].DAC_Info.DAC_Module, DAC_HIGH_FREQ_MODE_BELOW_160M);
|
||||
/* Initialize DAC */
|
||||
DAC_Init(n32_dac_obj[i].DAC_Info.DACx, &n32_dac_obj[i].DAC_Info.Init);
|
||||
|
||||
/* Register DAC device */
|
||||
if (rt_hw_dac_register(&n32_dac_obj[i].n32_dac_device, name_buf, &n32_dac_ops, &n32_dac_obj[i].DAC_Info) == RT_EOK)
|
||||
{
|
||||
LOG_D("%s init success", name_buf);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("%s register failed", name_buf);
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(n32_dac_init);
|
||||
|
||||
#endif /* BSP_USING_DACx */
|
||||
|
||||
@@ -18,7 +18,8 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DMA_BLOCK_SIZE (4095)
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
#define DMA_BLOCK_SIZE (4095)
|
||||
|
||||
struct dma_config
|
||||
{
|
||||
@@ -30,6 +31,18 @@ struct dma_config
|
||||
rt_uint32_t dmamux_channel;
|
||||
rt_uint32_t dmamux_request;
|
||||
};
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
struct dma_config
|
||||
{
|
||||
DMA_Module *DMAy;
|
||||
DMA_ChannelType *DMAChx;
|
||||
IRQn_Type dma_irq;
|
||||
rt_uint32_t dma_rcc;
|
||||
rt_uint32_t request;
|
||||
rt_uint32_t channel;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-06-22 ox-horse first version - N32H7xx FDCAN driver
|
||||
*/
|
||||
|
||||
#ifndef __DRV_FDCAN_H__
|
||||
#define __DRV_FDCAN_H__
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
*\*\name n32_fdcan_arb_timing.
|
||||
*\*\brief FDCAN arbitration segment (nominal) baud rate timing entry.
|
||||
*/
|
||||
struct n32_fdcan_arb_timing
|
||||
{
|
||||
uint32_t baud_rate; /**< baud rate in bps */
|
||||
uint16_t prescaler; /**< prescaler (1~512) */
|
||||
uint8_t sjw; /**< synchronization jump width (1~128) */
|
||||
uint16_t tseg1; /**< time segment 1 (2~256) */
|
||||
uint8_t tseg2; /**< time segment 2 (2~128) */
|
||||
};
|
||||
|
||||
/**
|
||||
*\*\name n32_fdcan_data_timing.
|
||||
*\*\brief FDCAN data segment baud rate timing entry (for CAN FD with BRS).
|
||||
*/
|
||||
struct n32_fdcan_data_timing
|
||||
{
|
||||
uint32_t baud_rate; /**< data phase baud rate in bps */
|
||||
uint16_t prescaler; /**< data phase prescaler (1~32) */
|
||||
uint8_t sjw; /**< data phase synchronization jump width (1~16) */
|
||||
uint16_t tseg1; /**< data phase time segment 1 (1~32) */
|
||||
uint8_t tseg2; /**< data phase time segment 2 (1~16) */
|
||||
};
|
||||
|
||||
/**
|
||||
*\*\name n32_fdcan.
|
||||
*\*\brief N32 FDCAN device structure.
|
||||
*\*\note GPIO pin initialization is handled by CubeMX-generated code
|
||||
*\*\ in n32h7xx_cfg.c. This driver only handles peripheral configuration.
|
||||
*/
|
||||
struct n32_fdcan
|
||||
{
|
||||
const char *name; /**< device name */
|
||||
FDCAN_Module *fdcan_x; /**< FDCAN peripheral base address (FDCAN1~FDCAN8) */
|
||||
FDCAN_InitType init_struct; /**< FDCAN init parameters */
|
||||
FDCAN_MsgRamType msg_ram; /**< Message RAM block config */
|
||||
FDCAN_FilterType filter_cfg; /**< default filter configuration */
|
||||
FDCAN_TxHeaderType tx_header; /**< TX header cache */
|
||||
FDCAN_RxHeaderType rx_header; /**< RX header cache */
|
||||
rt_uint32_t tx_pending_mask; /**< software mask of TX buffers with a pending request
|
||||
(FDCAN_TX_BUFFER0<<i). Cleared when the ISR detects
|
||||
TXBRP has gone to zero for that buffer, i.e. the
|
||||
hardware finished/cancelled the transmission. */
|
||||
struct rt_can_device device; /**< RT-Thread CAN device base */
|
||||
};
|
||||
|
||||
int rt_hw_fdcan_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_FDCAN_H__ */
|
||||
+43
-76
File diff suppressed because it is too large
Load Diff
+8
-6
@@ -1,19 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-20 breo.com first version
|
||||
* Date Author Notes
|
||||
* 2026-01-24 ox-horse first version
|
||||
* 2026-06-16 li.mengmeng implement for N32H7xx
|
||||
*/
|
||||
|
||||
#ifndef __DRV_FLASH_H__
|
||||
#define __DRV_FLASH_H__
|
||||
#ifndef __DRV_FLASH_H7XX_H__
|
||||
#define __DRV_FLASH_H7XX_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -27,4 +29,4 @@ int n32_flash_erase(rt_uint32_t addr, size_t size);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_FLASH_H__ */
|
||||
#endif /* __DRV_FLASH_H7XX_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -262,8 +262,8 @@ static rt_err_t n32_i2c_init(struct n32_i2c *i2c_drv)
|
||||
I2C_Configuration();
|
||||
/* Disable IIC */
|
||||
I2C_Enable(cfg->Instance, DISABLE);
|
||||
/* Get IIC BUSTIM Register value */
|
||||
BusTim_Reg = cfg->Instance->BUSTIM;
|
||||
/* Get IIC BUSTM Register value */
|
||||
BusTim_Reg = cfg->Instance->BUSTM;
|
||||
|
||||
if (BusTim_Reg == 0U)
|
||||
{
|
||||
|
||||
@@ -13,15 +13,15 @@
|
||||
*/
|
||||
|
||||
#ifndef LOG_TAG
|
||||
#define DBG_TAG "drv"
|
||||
#define DBG_TAG "drv"
|
||||
#else
|
||||
#define DBG_TAG LOG_TAG
|
||||
#define DBG_TAG LOG_TAG
|
||||
#endif /* LOG_TAG */
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
#define DBG_LVL DBG_LOG
|
||||
#define DBG_LVL DBG_LOG
|
||||
#else
|
||||
#define DBG_LVL DBG_INFO
|
||||
#define DBG_LVL DBG_INFO
|
||||
#endif /* DRV_DEBUG */
|
||||
|
||||
#include <rtdbg.h>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025 RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-06-23 ox-horse first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_LPTIM_H__
|
||||
#define __DRV_LPTIM_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/* 0x20 - 0x3F udevice control commands */
|
||||
typedef enum
|
||||
{
|
||||
DRV_HW_LPTIMER_CTRL_GET_TICK_MAX = 0x20, /* get the maximum tick value */
|
||||
DRV_HW_LPTIMER_CTRL_GET_FREQ = 0X21, /* get the timer frequency */
|
||||
DRV_HW_LPTIMER_CTRL_START = 0X22, /* set the timeout value */
|
||||
DRV_HW_LPTIMER_CTRL_GET_COUNT = 0X23, /* get the current count value */
|
||||
} drv_hw_lptimer_ctrl_t;
|
||||
|
||||
#endif /* __DRV_LPTIM_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2023, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-02-26 ox-horse first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_TIM_H__
|
||||
#define __DRV_TIM_H__
|
||||
|
||||
#include <rtdef.h>
|
||||
#include <board.h>
|
||||
|
||||
void n32_tim_ahbx_div_get(TIM_Module *timer, rt_uint32_t *div);
|
||||
void n32_tim_enable_clock(TIM_Module *timer);
|
||||
|
||||
#endif /* __DRV_TIM_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -19,8 +19,16 @@
|
||||
|
||||
int rt_hw_usart_init(void);
|
||||
|
||||
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
|
||||
#define UART_RX_DMA_IT_BLOCK_TC_FLAG 0x01
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
|
||||
#define UART_RX_DMA_IT_BLOCK_TC_FLAG 0x01
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
|
||||
#define UART_RX_DMA_IT_HT_FLAG 0x01
|
||||
#define UART_RX_DMA_IT_TC_FLAG 0x02
|
||||
|
||||
#define UART_CTRL_SET_BLOCK_TIMEOUT 0x20
|
||||
#endif
|
||||
|
||||
/* n32 config class */
|
||||
struct n32_uart_config
|
||||
@@ -39,8 +47,10 @@ struct n32_uart
|
||||
{
|
||||
struct n32_uart_config *config;
|
||||
rt_uint32_t DR_mask;
|
||||
rt_uint32_t tx_block_timeout;
|
||||
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
struct
|
||||
{
|
||||
rt_bool_t DMA_Tx_Init;
|
||||
@@ -69,8 +79,29 @@ struct n32_uart
|
||||
} rx_dma;
|
||||
|
||||
} dma;
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
struct
|
||||
{
|
||||
DMA_InitType TX_DMA_ChInitStr;
|
||||
struct
|
||||
{
|
||||
rt_size_t total_length;
|
||||
rt_uint8_t *buf;
|
||||
} tx_dma;
|
||||
|
||||
#endif
|
||||
rt_bool_t tx_dma_inited;
|
||||
|
||||
DMA_InitType RX_DMA_ChInitStr;
|
||||
struct
|
||||
{
|
||||
rt_size_t remaining_cnt;
|
||||
} rx_dma;
|
||||
|
||||
rt_bool_t rx_dma_inited;
|
||||
|
||||
} dma;
|
||||
#endif /* SOC_SERIES_N32H7xx */
|
||||
#endif /* RT_SERIAL_USING_DMA */
|
||||
rt_uint16_t uart_dma_flag;
|
||||
struct rt_serial_device serial;
|
||||
};
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2025, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-02-24 ox-horse first version
|
||||
* 2026-06-16 li.mengmeng fix issues and add stop handler
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef RT_USING_WDT
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.wdt"
|
||||
#include <drv_log.h>
|
||||
|
||||
struct n32_wdt_obj
|
||||
{
|
||||
rt_watchdog_t watchdog;
|
||||
IWDG_Module *IWDGx;
|
||||
uint32_t IWDG_Clk;
|
||||
void (*IWDGX_ClkCmd)(uint32_t periph, FunctionalState Cmd);
|
||||
|
||||
rt_uint32_t current_threshold_s;
|
||||
rt_uint32_t Reload;
|
||||
rt_uint16_t Prescaler;
|
||||
rt_uint16_t is_start;
|
||||
};
|
||||
|
||||
static struct n32_wdt_obj n32_wdt;
|
||||
static struct rt_watchdog_ops ops;
|
||||
|
||||
static rt_uint32_t wdt_get_prescaler_factor(rt_uint16_t prescaler)
|
||||
{
|
||||
switch (prescaler)
|
||||
{
|
||||
case IWDG_PRESCALER_DIV4:
|
||||
return 4;
|
||||
case IWDG_PRESCALER_DIV8:
|
||||
return 8;
|
||||
case IWDG_PRESCALER_DIV16:
|
||||
return 16;
|
||||
case IWDG_PRESCALER_DIV32:
|
||||
return 32;
|
||||
case IWDG_PRESCALER_DIV64:
|
||||
return 64;
|
||||
case IWDG_PRESCALER_DIV128:
|
||||
return 128;
|
||||
case IWDG_PRESCALER_DIV256:
|
||||
default:
|
||||
return 256;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t wdt_init(rt_watchdog_t *wdt)
|
||||
{
|
||||
n32_wdt.IWDGX_ClkCmd(n32_wdt.IWDG_Clk, ENABLE);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
|
||||
{
|
||||
rt_uint32_t reload_value;
|
||||
rt_uint32_t max_threshold_s;
|
||||
rt_uint32_t prescaler_factor;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
/* feed the watchdog */
|
||||
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
|
||||
IWDG_ReloadKey(n32_wdt.IWDGx);
|
||||
break;
|
||||
|
||||
/* set watchdog timeout */
|
||||
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
|
||||
#if defined(LSI_VALUE)
|
||||
if (n32_wdt.is_start)
|
||||
{
|
||||
LOG_W("IWDG is already running, cannot change timeout\n");
|
||||
return -RT_EBUSY;
|
||||
}
|
||||
|
||||
reload_value = (*(rt_uint32_t *)arg);
|
||||
prescaler_factor = wdt_get_prescaler_factor(n32_wdt.Prescaler);
|
||||
|
||||
if (LSI_VALUE)
|
||||
{
|
||||
max_threshold_s = ((n32_wdt.Reload + 1U) * prescaler_factor) / LSI_VALUE;
|
||||
|
||||
if (reload_value > max_threshold_s)
|
||||
{
|
||||
LOG_W("wdg set timeout parameter too large, please less than %d-s\n", max_threshold_s);
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
n32_wdt.current_threshold_s = reload_value;
|
||||
/* Calculate Reload Value */
|
||||
reload_value = (reload_value * (LSI_VALUE / prescaler_factor)) - 1U;
|
||||
|
||||
/* Enable write access to IWDG_PR and IWDG_RLR registers */
|
||||
IWDG_WriteConfig(n32_wdt.IWDGx, IWDG_WRITE_ENABLE);
|
||||
/* Set IWDG PREDIV */
|
||||
IWDG_SetPrescalerDiv(n32_wdt.IWDGx, n32_wdt.Prescaler);
|
||||
/* Set Counter Reload Value */
|
||||
IWDG_CntReload(n32_wdt.IWDGx, (uint16_t)reload_value);
|
||||
/* Reload IWDG counter */
|
||||
IWDG_ReloadKey(n32_wdt.IWDGx);
|
||||
|
||||
/* Disable write access to IWDG_PR and IWDG_RLR registers */
|
||||
IWDG_WriteConfig(n32_wdt.IWDGx, IWDG_WRITE_DISABLE);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Please define the value of LSI_VALUE!");
|
||||
}
|
||||
#else
|
||||
#error "Please define the value of LSI_VALUE!"
|
||||
#endif
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
|
||||
*(rt_uint32_t *)arg = n32_wdt.current_threshold_s;
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_WDT_START:
|
||||
if (n32_wdt.is_start)
|
||||
{
|
||||
LOG_W("IWDG is already started\n");
|
||||
return RT_EOK;
|
||||
}
|
||||
IWDG_Enable(n32_wdt.IWDGx);
|
||||
n32_wdt.is_start = 1;
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_WDT_STOP:
|
||||
LOG_W("IWDG cannot be stopped once started\n");
|
||||
return -RT_ENOSYS;
|
||||
|
||||
default:
|
||||
LOG_W("This command is not supported.");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
int rt_wdt_init(void)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
n32_wdt.IWDGx = IWDG1;
|
||||
n32_wdt.IWDG_Clk = (RCC_APB5_PERIPHEN_IWDG1PCLK | RCC_APB5_PERIPHEN_IWDG1PCLKLP);
|
||||
n32_wdt.IWDGX_ClkCmd = RCC_EnableAPB5PeriphClk2;
|
||||
#endif
|
||||
|
||||
n32_wdt.Prescaler = IWDG_PRESCALER_DIV256;
|
||||
n32_wdt.Reload = 0xFFFU;
|
||||
n32_wdt.is_start = 0U;
|
||||
|
||||
ops.init = &wdt_init;
|
||||
ops.control = &wdt_control;
|
||||
n32_wdt.watchdog.ops = &ops;
|
||||
|
||||
/* register watchdog device */
|
||||
if (rt_hw_watchdog_register(&n32_wdt.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
|
||||
{
|
||||
LOG_E("wdt device register failed.");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
LOG_D("wdt device register success.");
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_wdt_init);
|
||||
|
||||
#endif /* RT_USING_WDT */
|
||||
@@ -42,13 +42,21 @@ static uint32_t _systick_ms = 1;
|
||||
/* SysTick configuration */
|
||||
void rt_hw_systick_init(void)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_ClocksTypeDef RCC_Clocks = { 0 };
|
||||
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
|
||||
RCC_ClocksType RCC_Clocks = { 0 };
|
||||
#endif
|
||||
|
||||
/* Get clock frequency */
|
||||
RCC_GetClocksFreqValue(&RCC_Clocks);
|
||||
|
||||
/* Set Systick */
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
SysTick_Config(RCC_Clocks.M7ClkFreq / RT_TICK_PER_SECOND);
|
||||
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
|
||||
SysTick_Config(RCC_Clocks.SysclkFreq / RT_TICK_PER_SECOND);
|
||||
#endif
|
||||
|
||||
NVIC_SetPriorityGrouping(SCB_AIRCR_PRIGROUP3);
|
||||
NVIC_SetPriority(SysTick_IRQn, 0xFF);
|
||||
|
||||
@@ -12,82 +12,152 @@
|
||||
#include <rtthread.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
|
||||
static USART_Module* USARTx;
|
||||
static USART_Module *USARTx;
|
||||
|
||||
void rt_hw_console_init(void)
|
||||
{
|
||||
USART_InitType USART_InitStructure;
|
||||
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
|
||||
#endif
|
||||
|
||||
#ifdef USART1
|
||||
if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart1") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART1, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART1, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE);
|
||||
#endif
|
||||
USARTx = USART1;
|
||||
}
|
||||
#endif /* USART1 */
|
||||
#ifdef USART2
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart2") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART2, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_USART2, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE);
|
||||
#endif
|
||||
USARTx = USART2;
|
||||
}
|
||||
#endif /* USART2 */
|
||||
#ifdef USART3
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart3") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART3, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_USART3, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE);
|
||||
#endif
|
||||
USARTx = USART3;
|
||||
}
|
||||
#endif /* USART3 */
|
||||
#ifdef USART4
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart4") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART4, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART4, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART4, ENABLE);
|
||||
#endif
|
||||
USARTx = USART4;
|
||||
}
|
||||
#endif /* USART4 */
|
||||
#ifdef USART5
|
||||
#if defined(USART5) || defined(UART5)
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart5") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART5, ENABLE);
|
||||
USARTx = USART5;
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_UART5, ENABLE);
|
||||
USARTx = UART5;
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE);
|
||||
USARTx = UART5;
|
||||
#endif
|
||||
}
|
||||
#endif /* USART5 */
|
||||
#ifdef USART6
|
||||
#endif /* defined(USART5) || defined(UART5) */
|
||||
#if defined(USART6) || defined(UART6)
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart6") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART6, ENABLE);
|
||||
USARTx = USART6;
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART6, ENABLE);
|
||||
USARTx = UART6;
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART6, ENABLE);
|
||||
USARTx = UART6;
|
||||
#endif
|
||||
}
|
||||
#endif /* USART6 */
|
||||
#ifdef USART7
|
||||
#endif /* defined(USART6) || defined(UART6) */
|
||||
#if defined(USART7) || defined(UART7)
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart7") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART7, ENABLE);
|
||||
USARTx = USART7;
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART7, ENABLE);
|
||||
USARTx = UART7;
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART7, ENABLE);
|
||||
USARTx = UART7;
|
||||
#endif
|
||||
}
|
||||
#endif /* USART7 */
|
||||
#ifdef USART8
|
||||
#endif /* defined(USART7) || defined(UART7) */
|
||||
#if defined(USART8) || defined(UART8)
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart8") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART8, ENABLE);
|
||||
USARTx = USART8;
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_UART8, ENABLE);
|
||||
USARTx = UART8;
|
||||
#elif defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART8, ENABLE);
|
||||
USARTx = UART8;
|
||||
#endif
|
||||
}
|
||||
#endif /* USART8 */
|
||||
#ifdef UART9
|
||||
#endif /* defined(USART8) || defined(UART8) */
|
||||
#if defined(USART9) || defined(UART9)
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart9") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART9, ENABLE);
|
||||
USARTx = UART9;
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART9, ENABLE);
|
||||
USARTx = USART9;
|
||||
#endif
|
||||
}
|
||||
#endif /* UART9 */
|
||||
#endif /* defined(USART9) || defined(UART9) */
|
||||
#ifdef UART10
|
||||
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart10") == 0)
|
||||
{
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART10, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x)
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART10, ENABLE);
|
||||
#endif
|
||||
USARTx = UART10;
|
||||
}
|
||||
#endif /* UART10 */
|
||||
@@ -161,7 +231,7 @@ void rt_hw_console_output(const char *str)
|
||||
|
||||
while (USART_GetFlagStatus(USARTx, USART_FLAG_TXC) == RESET);
|
||||
|
||||
USART_SendData(USARTx, (uint8_t )(*(str + i)));
|
||||
USART_SendData(USARTx, (uint8_t)(*(str + i)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -25,56 +25,88 @@ void rt_pin_mode(rt_uint64_t pin, rt_uint8_t mode)
|
||||
mode == PIN_MODE_INPUT_PULLUP || mode == PIN_MODE_INPUT_PULLDOWN ||
|
||||
mode == PIN_MODE_OUTPUT_OD);
|
||||
|
||||
switch((rt_ubase_t)GPIOx)
|
||||
switch ((rt_ubase_t)GPIOx)
|
||||
{
|
||||
case (rt_ubase_t)GPIOA:
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOB:
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOB, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOC:
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOC, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOA:
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA, ENABLE);
|
||||
#endif
|
||||
break;
|
||||
case (rt_ubase_t)GPIOB:
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOB, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOB, ENABLE);
|
||||
#endif
|
||||
break;
|
||||
case (rt_ubase_t)GPIOC:
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOC, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOC, ENABLE);
|
||||
#endif
|
||||
break;
|
||||
#ifdef GPIOD
|
||||
case (rt_ubase_t)GPIOD:
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOD, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOD:
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOD, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOD, ENABLE);
|
||||
#endif
|
||||
break;
|
||||
#endif /* GPIOD */
|
||||
#ifdef GPIOE
|
||||
case (rt_ubase_t)GPIOE:
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOE, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOE:
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOE, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOE, ENABLE);
|
||||
#endif
|
||||
break;
|
||||
#endif /* GPIOE */
|
||||
#ifdef GPIOF
|
||||
case (rt_ubase_t)GPIOF:
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOF, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOF:
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOF, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOF, ENABLE);
|
||||
#endif
|
||||
break;
|
||||
#endif /* GPIOF */
|
||||
#ifdef GPIOG
|
||||
case (rt_ubase_t)GPIOG:
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOG, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOG:
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOG, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOG, ENABLE);
|
||||
#endif
|
||||
break;
|
||||
#endif /* GPIOG */
|
||||
#ifdef GPIOH
|
||||
case (rt_ubase_t)GPIOH:
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOH:
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE);
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOH, ENABLE);
|
||||
#endif
|
||||
break;
|
||||
#endif /* GPIOH */
|
||||
#ifdef GPIOI
|
||||
case (rt_ubase_t)GPIOI:
|
||||
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOI, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOI:
|
||||
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOI, ENABLE);
|
||||
break;
|
||||
#endif /* GPIOI */
|
||||
#ifdef GPIOj
|
||||
case (rt_ubase_t)GPIOj:
|
||||
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOJ, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOj:
|
||||
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOJ, ENABLE);
|
||||
break;
|
||||
#endif /* GPIOj */
|
||||
#ifdef GPIOk
|
||||
case (rt_ubase_t)GPIOk:
|
||||
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOK, ENABLE);
|
||||
break;
|
||||
case (rt_ubase_t)GPIOk:
|
||||
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOK, ENABLE);
|
||||
break;
|
||||
#endif /* GPIOk */
|
||||
}
|
||||
|
||||
@@ -122,7 +154,11 @@ void rt_pin_write(rt_uint64_t pin, rt_uint8_t value)
|
||||
|
||||
RT_ASSERT(value == PIN_LOW || value == PIN_HIGH);
|
||||
|
||||
#if defined(SOC_SERIES_N32H7xx)
|
||||
GPIO_WriteBit(GPIOx, GPIO_Pin, ((value == PIN_LOW) ? Bit_RESET : Bit_SET));
|
||||
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
|
||||
GPIO_WriteBits(GPIOx, GPIO_Pin, ((value == PIN_LOW) ? Bit_RESET : Bit_SET));
|
||||
#endif
|
||||
}
|
||||
|
||||
rt_int8_t rt_pin_read(rt_uint64_t pin)
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
scons.args: &scons
|
||||
scons_arg:
|
||||
- '--strict'
|
||||
|
||||
# ------ nano ------
|
||||
nano:
|
||||
<<: *scons
|
||||
kconfig:
|
||||
- CONFIG_RT_USING_NANO=y
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,41 @@
|
||||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
cconfig.h
|
||||
@@ -0,0 +1,22 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
BSP_DIR := .
|
||||
|
||||
RTT_DIR := ../../../..
|
||||
|
||||
PKGS_DIR := packages
|
||||
|
||||
config SOC_N32H488ZEL7
|
||||
bool
|
||||
select SOC_SERIES_N32H47x_48x
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
source "$(RTT_DIR)/Kconfig"
|
||||
osource "$PKGS_DIR/Kconfig"
|
||||
rsource "../libraries/Kconfig"
|
||||
|
||||
if !RT_USING_NANO
|
||||
rsource "board/Kconfig"
|
||||
endif
|
||||
@@ -0,0 +1,116 @@
|
||||
# N32H488ZEL7 开发板 BSP 说明
|
||||
|
||||
## 简介
|
||||
|
||||
本文档为 RT-Thread 开发团队为 N32H488ZEL7 开发板提供的 BSP (板级支持包) 说明。
|
||||
|
||||
主要内容如下：
|
||||
|
||||
- 开发板资源介绍
|
||||
- BSP 快速上手
|
||||
- 进阶使用方法
|
||||
|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
|
||||
|
||||
## 开发板介绍
|
||||
|
||||
N32H488ZEL7_EVB V1.1 是 Nsing 推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 240Mhz，该开发板具有丰富的板载资源，可以充分发挥 N32H488 的芯片性能。
|
||||
|
||||
开发板外观如下图所示：
|
||||
|
||||
|
||||
|
||||
该开发板常用 **板载资源** 如下：
|
||||
|
||||
- MCU：N32H488ZEL7，主频 240MHz，512KB FLASH ，160KB RAM
|
||||
- 外部 PSRAM：IS66WV51216EBLL（FEMC）
|
||||
- 外部 EEROM：AT24C02
|
||||
- 外部 FLASH：W25Q128JVSIQTR（SPI）、P25Q40HA-SSH-IT（XSPI）、IS34ML01G081-TLI（FEMC-NAND）
|
||||
- 常用外设
|
||||
- LED：3个，LED1（PA3），LED2（PB4），LED3（PA8）
|
||||
- 按键：4个，WKUP（兼具唤醒功能，PA0），KEY1（PC13），KEY2（PA15），KEY3（PC8）
|
||||
- 常用接口：USB 转串口、CAN 接口、RS485 接口、LIN 接口、以太网接口
|
||||
- 调试接口，标准 JTAG/SWD
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| GPIO | 支持 | PA0, PA1... PH6 ---> PIN: 0, 1...118 |
|
||||
| UART | 支持 | UART1/2/3, 如需使用该外设，请使用 Cube 重新配 |
|
||||
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
**请注意！！！**
|
||||
|
||||
在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的 STD 库及 CMSIS 库，否则无法通过编译）：
|
||||
|
||||
```bash
|
||||
pkgs --update
|
||||
```
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用数据线连接开发板到 PC，打开电源开关。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 USB 线连接开发板的基础上，点击下载按钮即可下载程序到开发板
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察开发板上 LED1 的运行效果，LED1 会周期性闪烁。
|
||||
|
||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.3.0 build Jul 16 2026 11:18:41
|
||||
2006 - 2024 Copyright by RT-Thread team
|
||||
msh >
|
||||
```
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
|
||||
- 调试串口为串口 1 映射说明
|
||||
|
||||
PA9 ------> USART1_TX
|
||||
|
||||
PA10 ------> USART1_RX
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [OnlyoutzZ](https://github.com/OnlyoutzZ)
|
||||
Executable → Regular
+3
@@ -1,12 +1,15 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
Import('env')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
env.Append(CPPDEFINES = ['N32H488'])
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
@@ -0,0 +1,74 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
def bsp_pkg_check():
|
||||
import subprocess
|
||||
|
||||
check_paths = [
|
||||
os.path.join("packages", "CMSIS-Core-latest"),
|
||||
os.path.join("packages", "n32h47x_48x_cmsis_driver-latest"),
|
||||
os.path.join("packages", "n32h47x_48x_std_driver-latest")
|
||||
]
|
||||
|
||||
need_update = not all(os.path.exists(p) for p in check_paths)
|
||||
|
||||
if need_update:
|
||||
print("\n===============================================================================")
|
||||
print("Dependency packages missing, please running 'pkgs --update'...")
|
||||
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
|
||||
print("===============================================================================")
|
||||
exit(1)
|
||||
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
|
||||
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
|
||||
|
||||
Export('env')
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
rtconfig.BSP_LIBRARY_TYPE = None
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'N32_Drivers', 'SConscript'),variant_dir='build/libraries/N32_Drivers', duplicate=0))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
Executable → Regular
+2
-2
@@ -1,9 +1,9 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
cwd = GetCurrentDir()
|
||||
CPPPATH = [cwd]
|
||||
src = ['main.c']
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-07-15 ox-horse first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
#include <drv_gpio.h>
|
||||
#ifndef RT_USING_NANO
|
||||
#include <rtdevice.h>
|
||||
#endif /* RT_USING_NANO */
|
||||
|
||||
/* defined the LED1 pin: PA3 */
|
||||
#define LED1_PIN GET_PIN(A, 3)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED1 pin mode to output */
|
||||
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED1_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED1_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
Binary file not shown.
@@ -0,0 +1,33 @@
|
||||
/**
|
||||
* @file n32h47x_48x_cfg.h
|
||||
* @author N32cube
|
||||
*/
|
||||
#ifndef __N32H47X_48X_CFG_H__
|
||||
#define __N32H47X_48X_CFG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* NTFx CODE START INCLUDE*/
|
||||
#include "n32h47x_48x.h"
|
||||
#include "n32h47x_48x_conf.h"
|
||||
/* NTFx CODE END INCLUDE*/
|
||||
|
||||
/* NTFx CODE START Extern*/
|
||||
extern void SysTick_Delayms(uint32_t Delayms);
|
||||
extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize);
|
||||
extern bool RCC_Configuration(void);
|
||||
extern bool GPIO_Configuration(void);
|
||||
extern bool NVIC_Configuration(void);
|
||||
extern bool DMA_Configuration(void);
|
||||
extern bool USART_Configuration(void);
|
||||
/* NTFx CODE END Extern*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32H47X_48X_CFG_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,71 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
|
||||
config BSP_UART1_RX_USING_DMA
|
||||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART1_TX_USING_DMA
|
||||
bool "Enable UART1 TX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "Enable UART2"
|
||||
default n
|
||||
|
||||
config BSP_UART2_RX_USING_DMA
|
||||
bool "Enable UART2 RX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART2_TX_USING_DMA
|
||||
bool "Enable UART2 TX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART3
|
||||
bool "Enable UART3"
|
||||
default n
|
||||
|
||||
config BSP_UART3_RX_USING_DMA
|
||||
bool "Enable UART3 RX DMA"
|
||||
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART3_TX_USING_DMA
|
||||
bool "Enable UART3 TX DMA"
|
||||
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
endif
|
||||
|
||||
source "$BSP_DIR/../libraries/N32_Drivers/drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,27 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
Cube_Config/USER/src/n32h47x_48x_cfg.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
path += [os.path.join(cwd, 'Cube_Config', 'USER', 'inc')]
|
||||
|
||||
CPPDEFINES = ['N32H488', 'CORE_CM4']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
# if os.path.isfile(os.path.join(cwd, "ports", 'SConscript')):
|
||||
# group = group + SConscript(os.path.join("ports", 'SConscript'))
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-03 ox-horse first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/**
|
||||
* @brief System_Initialize
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void System_Initialize(void)
|
||||
{
|
||||
/* Initialize system clock and enable Peripheral clock */
|
||||
RCC_Configuration();
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
|
||||
/* Config Peripheral GPIO */
|
||||
GPIO_Configuration();
|
||||
}
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-03 ox-horse first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "n32h47x_48x_cfg.h"
|
||||
#include "drv_common.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define N32_FLASH_START_ADRESS ((uint32_t)0x08000000)
|
||||
#define N32_FLASH_SIZE (512 * 1024)
|
||||
#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE))
|
||||
|
||||
#define N32_SRAM_SIZE (160)
|
||||
#define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024)
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section = "CSTACK"
|
||||
#define HEAP_BEGIN (__segment_end("CSTACK"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END N32_SRAM_END
|
||||
|
||||
void System_Initialize(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM1_end__ = 0x20028000;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x0400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM1_region { readwrite, last block CSTACK };
|
||||
Executable → Regular
+14
-8
@@ -1,16 +1,15 @@
|
||||
/*
|
||||
* linker script for N32G452xx with GNU ld
|
||||
* bernard.xiong 2009-10-14
|
||||
* linker script for N32H48X with GNU ld
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */
|
||||
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 64k /* 64KB sram */
|
||||
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */
|
||||
RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 160k /* 160K sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x200;
|
||||
_system_stack_size = 0x400;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
@@ -29,6 +28,12 @@ SECTIONS
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for utest */
|
||||
. = ALIGN(4);
|
||||
__rt_utest_tc_tab_start = .;
|
||||
KEEP(*(UtestTcTab))
|
||||
__rt_utest_tc_tab_end = .;
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
@@ -54,6 +59,7 @@ SECTIONS
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
_etext = .;
|
||||
} > CODE = 0
|
||||
|
||||
@@ -88,7 +94,7 @@ SECTIONS
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >DATA
|
||||
} >RAM1
|
||||
|
||||
.stack :
|
||||
{
|
||||
@@ -97,7 +103,7 @@ SECTIONS
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >DATA
|
||||
} >RAM1
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
@@ -115,7 +121,7 @@ SECTIONS
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > DATA
|
||||
} > RAM1
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
Executable → Regular
+3
-3
@@ -2,13 +2,13 @@
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00040000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00040000 { ; load address = execution address
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00014000 { ; RW data
|
||||
RW_IRAM1 0x20000000 0x00028000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,19 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
objs = []
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = []
|
||||
path = [cwd]
|
||||
|
||||
CPPDEFINES = ['']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 4.6 MiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Executable → Regular
+43
-30
@@ -1,7 +1,5 @@
|
||||
import os
|
||||
|
||||
print(os.path.abspath(__file__))
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
@@ -14,25 +12,21 @@ if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if ('EXEC_PATH' in dir()) == False:
|
||||
EXEC_PATH = r'/opt/gcc-arm-none-eabi-6_2-2016q4/bin'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
if ('EXEC_PATH' in dir()) == False:
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iccarm'
|
||||
if ('EXEC_PATH' in dir()) == False:
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
@@ -63,7 +57,8 @@ if PLATFORM == 'gcc':
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
@@ -94,6 +89,40 @@ elif PLATFORM == 'armcc':
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'armclang':
|
||||
# toolchains
|
||||
CC = 'armclang'
|
||||
CXX = 'armclang'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 '
|
||||
CFLAGS += ' -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 '
|
||||
CFLAGS += ' -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar '
|
||||
CFLAGS += ' -gdwarf-3 -ffunction-sections '
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers '
|
||||
LFLAGS += ' --list rt-thread.map '
|
||||
LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" '
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib'
|
||||
|
||||
EXEC_PATH += '/ARM/ARMCLANG/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O1' # armclang recommend
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
@@ -144,7 +173,7 @@ elif PLATFORM == 'iccarm':
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
@@ -154,19 +183,3 @@ def dist_handle(BSP_ROOT, dist_dir):
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
|
||||
print('ARCH =[%s]' %(ARCH ))
|
||||
print('CPU =[%s]' %(CPU ))
|
||||
print('CROSS_TOOL =[%s]' %(CROSS_TOOL))
|
||||
print('RTT_ROOT =[%s]' %(RTT_ROOT ))
|
||||
print('PLATFORM =[%s]' %(PLATFORM ))
|
||||
print('EXEC_PATH =[%s]' %(EXEC_PATH ))
|
||||
print('CC =[%s]' %(CC ))
|
||||
print('AS =[%s]' %(AS ))
|
||||
print('AR =[%s]' %(AR ))
|
||||
print('LINK =[%s]' %(LINK ))
|
||||
print('TARGET_EXT =[%s]' %(TARGET_EXT))
|
||||
print('DEVICE =[%s]' %(DEVICE ))
|
||||
print('CFLAGS =[%s]' %(CFLAGS ))
|
||||
print('AFLAGS =[%s]' %(AFLAGS ))
|
||||
print('LFLAGS =[%s]' %(LFLAGS ))
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\template.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
@@ -0,0 +1,190 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC3000 -FN1 -FF0N32H48x_512 -FS08000000 -FL080000 -FP0($$Device:N32H488ZE$Flash\N32H48x_512.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC3000 -FD20000000 -FF0N32H48x_512 -FL080000 -FS08000000 -FP0($$Device:N32H488ZE$Flash\N32H48x_512.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>JL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC3000 -FD20000000 -FF0N32H48x_512 -FL080000 -FS08000000 -FP0($$Device:N32H488ZE$Flash\N32H48x_512.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
Executable → Regular
+24
-27
@@ -7,22 +7,23 @@
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rtthread-n32</TargetName>
|
||||
<TargetName>rt-thread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>5060960::V5.06 update 7 (build 960)::.\ARMCC</pCCUsed>
|
||||
<uAC6>0</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>N32G452RCL7</Device>
|
||||
<Device>N32H488ZE</Device>
|
||||
<Vendor>Nationstech</Vendor>
|
||||
<PackID>Nationstech.N32G45x_DFP.1.0.1</PackID>
|
||||
<PackID>Nationstech.N32H48x_DFP.1.2.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x24000) IROM(0x08000000,0x40000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<Cpu>IRAM(0x20000000,0x30000) IROM(0x08000000,0x80000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0N32G45x -FS08000000 -FL040000 -FP0($$Device:N32G452RCL7$Flash\N32G45x.FLM))</FlashDriverDll>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC3000 -FN1 -FF0N32H48x_512 -FS08000000 -FL080000 -FP0($$Device:N32H488ZE$Flash\N32H48x_512.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:N32G452RCL7$firmware\CMSIS\device\n32g45x.h</RegisterFile>
|
||||
<RegisterFile>$$Device:N32H488ZE$firmware\CMSIS\device\n32h48x.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
@@ -32,7 +33,7 @@
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:N32G452RCL7$svd\N32G452.svd</SFDFile>
|
||||
<SFDFile>$$Device:N32H488ZE$svd\N32H488.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
@@ -47,14 +48,14 @@
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rt-thread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>0</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
@@ -245,12 +246,12 @@
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x24000</Size>
|
||||
<Size>0x30000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
@@ -275,7 +276,7 @@
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
@@ -300,7 +301,7 @@
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x24000</Size>
|
||||
<Size>0x30000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
@@ -315,13 +316,13 @@
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
@@ -351,7 +352,7 @@
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>1</ClangAsOpt>
|
||||
<ClangAsOpt>4</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
@@ -378,6 +379,11 @@
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source Group 1</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
@@ -387,13 +393,4 @@
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName>template</LayName>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
</LayerInfo>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,10 @@
|
||||
scons.args: &scons
|
||||
scons_arg:
|
||||
- '--strict'
|
||||
|
||||
# ------ nano ------
|
||||
nano:
|
||||
<<: *scons
|
||||
kconfig:
|
||||
- CONFIG_RT_USING_NANO=y
|
||||
|
||||
+84
-49
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,41 @@
|
||||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
cconfig.h
|
||||
@@ -0,0 +1,22 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
BSP_DIR := .
|
||||
|
||||
RTT_DIR := ../../../..
|
||||
|
||||
PKGS_DIR := packages
|
||||
|
||||
config SOC_N32H497ZGL7
|
||||
bool
|
||||
select SOC_SERIES_N32H49x
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
source "$(RTT_DIR)/Kconfig"
|
||||
osource "$PKGS_DIR/Kconfig"
|
||||
rsource "../libraries/Kconfig"
|
||||
|
||||
if !RT_USING_NANO
|
||||
rsource "board/Kconfig"
|
||||
endif
|
||||
@@ -0,0 +1,121 @@
|
||||
# N32H497ZGL7 开发板 BSP 说明
|
||||
|
||||
## 简介
|
||||
|
||||
本文档为 RT-Thread 开发团队为 N32H497ZGL7 开发板提供的 BSP (板级支持包) 说明。
|
||||
|
||||
主要内容如下：
|
||||
|
||||
- 开发板资源介绍
|
||||
- BSP 快速上手
|
||||
- 进阶使用方法
|
||||
|
||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
|
||||
|
||||
## 开发板介绍
|
||||
|
||||
N32H497ZGL7_EVB V1.0 是 Nsing 推出的一款基于 ARM Cortex-M4 内核的开发板，最高主频为 240Mhz，该开发板具有丰富的板载资源，可以充分发挥 N32H497 的芯片性能。
|
||||
|
||||
开发板外观如下图所示：
|
||||
|
||||
|
||||
|
||||
该开发板常用 **板载资源** 如下：
|
||||
|
||||
- MCU：N32H497ZGL7，主频 240MHz，1024KB FLASH ，448KB RAM
|
||||
- 外部 PSRAM：APS1604M-3SQR-SN（XSPI-PSRAM）
|
||||
- 外部 SDRAM：M12L64164A-5TG2C
|
||||
- 外部 EEROM：AT24C02
|
||||
- 外部 FLASH：W25Q128JVSIQTR（SPI）、P25Q40HA-SSH-IT（XSPI）
|
||||
- 常用外设
|
||||
- LED：3个，LED1（PA3），LED2（PB3），LED3（PA8）
|
||||
- 按键：4个，WKUP（兼具唤醒功能，PA0），KEY1（PC13），KEY2（PA15），KEY3
|
||||
- 常用接口：USB 转串口、CAN 接口、RS485 接口、LIN 接口、以太网接口
|
||||
- 调试接口，标准 JTAG/SWD
|
||||
|
||||
## 外设支持
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| GPIO | 支持 | PA0, PA1... PH5 ---> PIN: 0, 1...117 |
|
||||
| UART | 支持 | UART1/2/3, 如需使用该外设，请使用 Cube 重新配 |
|
||||
|
||||
|
||||
## 使用说明
|
||||
|
||||
使用说明分为如下两个章节：
|
||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
|
||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
|
||||
|
||||
|
||||
### 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
**请注意！！！**
|
||||
|
||||
在执行编译工作前请先打开ENV执行以下指令（该指令用于拉取必要的 STD 库及 CMSIS 库，否则无法通过编译）：
|
||||
|
||||
```bash
|
||||
pkgs --update
|
||||
```
|
||||
|
||||
#### 硬件连接
|
||||
|
||||
使用数据线连接开发板到 PC，打开电源开关。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用 CMSIS-DAP 下载程序，在通过 USB 线连接开发板的基础上，点击下载按钮即可下载程序到开发板
|
||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察开发板上 LED1 的运行效果，LED1 会周期性闪烁。
|
||||
|
||||
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.3.0 build Jul 16 2026 11:18:41
|
||||
2006 - 2024 Copyright by RT-Thread team
|
||||
msh >
|
||||
```
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
|
||||
- 调试串口为串口 1 映射说明
|
||||
|
||||
PA9 ------> USART1_TX
|
||||
|
||||
PA10 ------> USART1_RX
|
||||
|
||||
- 按键 KEY3 说明
|
||||
|
||||
若需要使用按键 KEY3，需要拔了 J43 跳线帽，使用杜邦线连接到 PB4
|
||||
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [OnlyoutzZ](https://github.com/OnlyoutzZ)
|
||||
@@ -0,0 +1,18 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
Import('env')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
env.Append(CPPDEFINES = ['N32H49x'])
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,74 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
def bsp_pkg_check():
|
||||
import subprocess
|
||||
|
||||
check_paths = [
|
||||
os.path.join("packages", "CMSIS-Core-latest"),
|
||||
os.path.join("packages", "n32h49x_cmsis_driver-latest"),
|
||||
os.path.join("packages", "n32h49x_std_driver-latest")
|
||||
]
|
||||
|
||||
need_update = not all(os.path.exists(p) for p in check_paths)
|
||||
|
||||
if need_update:
|
||||
print("\n===============================================================================")
|
||||
print("Dependency packages missing, please running 'pkgs --update'...")
|
||||
print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...")
|
||||
print("===============================================================================")
|
||||
exit(1)
|
||||
|
||||
RegisterPreBuildingAction(bsp_pkg_check)
|
||||
|
||||
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
|
||||
|
||||
Export('env')
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
rtconfig.BSP_LIBRARY_TYPE = None
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'N32_Drivers', 'SConscript'),variant_dir='build/libraries/N32_Drivers', duplicate=0))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -0,0 +1,15 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
CPPPATH = [cwd]
|
||||
src = ['main.c']
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-07-15 ox-horse first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
#include <drv_gpio.h>
|
||||
#ifndef RT_USING_NANO
|
||||
#include <rtdevice.h>
|
||||
#endif /* RT_USING_NANO */
|
||||
|
||||
/* defined the LED1 pin: PA3 */
|
||||
#define LED1_PIN GET_PIN(A, 3)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED1 pin mode to output */
|
||||
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED1_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED1_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
Binary file not shown.
+15
-15
@@ -1,32 +1,32 @@
|
||||
|
||||
/**
|
||||
* @file n32h76x_78x_cfg.h
|
||||
* @file n32h49x_cfg.h
|
||||
* @author N32cube
|
||||
*/
|
||||
#ifndef __N32H76X_78X_CFG_H__
|
||||
#define __N32H76X_78X_CFG_H__
|
||||
#ifndef __N32H49X_CFG_H__
|
||||
#define __N32H49X_CFG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* NTFx CODE START INCLUDE*/
|
||||
#include "n32h76x_78x.h"
|
||||
#include "n32h76x_78x_rcc.h"
|
||||
#include "n32h49x.h"
|
||||
#include "n32h49x_dbg.h"
|
||||
#include "n32h49x_vrefbuf.h"
|
||||
#include "n32h49x_flash.h"
|
||||
#include "n32h49x_rcc.h"
|
||||
#include "misc.h"
|
||||
#include "n32h76x_78x_dma.h"
|
||||
#include "n32h76x_78x_gpio.h"
|
||||
#include "n32h76x_78x_usart.h"
|
||||
#include "n32h76x_78x_pwr.h"
|
||||
#include "n32h76x_78x_dmamux.h"
|
||||
#include "n32h76x_78x_mdma.h"
|
||||
#include "n32h49x_dma.h"
|
||||
#include "n32h49x_gpio.h"
|
||||
#include "n32h49x_usart.h"
|
||||
/* NTFx CODE END INCLUDE*/
|
||||
|
||||
/* NTFx CODE START Extern*/
|
||||
extern void SysTick_Delayms(uint32_t Delayms);
|
||||
extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr,uint32_t memAddr,uint32_t bufSize );
|
||||
extern void DMA_SetPerMemAddr(DMA_ChannelType* DMAChx, uint32_t periphAddr, uint32_t memAddr, uint32_t bufSize);
|
||||
extern bool RCC_Configuration(void);
|
||||
extern bool GPIO_Configuration(void);
|
||||
extern bool NVIC_Configuration(void);
|
||||
extern bool DMA_Configuration(void);
|
||||
extern bool GPIO_Configuration(void);
|
||||
extern bool USART_Configuration(void);
|
||||
/* NTFx CODE END Extern*/
|
||||
|
||||
@@ -34,7 +34,7 @@ extern bool USART_Configuration(void);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MAIN_H__ */
|
||||
#endif /* __N32H49X_CFG_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,71 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
|
||||
config BSP_UART1_RX_USING_DMA
|
||||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART1_TX_USING_DMA
|
||||
bool "Enable UART1 TX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "Enable UART2"
|
||||
default n
|
||||
|
||||
config BSP_UART2_RX_USING_DMA
|
||||
bool "Enable UART2 RX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART2_TX_USING_DMA
|
||||
bool "Enable UART2 TX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART3
|
||||
bool "Enable UART3"
|
||||
default n
|
||||
|
||||
config BSP_UART3_RX_USING_DMA
|
||||
bool "Enable UART3 RX DMA"
|
||||
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_UART3_TX_USING_DMA
|
||||
bool "Enable UART3 TX DMA"
|
||||
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
endif
|
||||
|
||||
source "$BSP_DIR/../libraries/N32_Drivers/drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,27 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
Cube_Config/USER/src/n32h49x_cfg.c
|
||||
''')
|
||||
|
||||
path = [cwd]
|
||||
path += [os.path.join(cwd, 'Cube_Config', 'USER', 'inc')]
|
||||
|
||||
CPPDEFINES = ['N32H49x', 'CORE_CM4']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
# if os.path.isfile(os.path.join(cwd, "ports", 'SConscript')):
|
||||
# group = group + SConscript(os.path.join("ports", 'SConscript'))
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-03 ox-horse first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
/**
|
||||
* @brief System_Initialize
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void System_Initialize(void)
|
||||
{
|
||||
/* Initialize system clock and enable Peripheral clock */
|
||||
RCC_Configuration();
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
|
||||
|
||||
/* Config Peripheral GPIO */
|
||||
GPIO_Configuration();
|
||||
}
|
||||
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2026, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2026-04-03 ox-horse first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "n32h49x_cfg.h"
|
||||
#include "n32h49x_exti.h"
|
||||
#include "misc.h"
|
||||
#include "n32h49x_dma.h"
|
||||
#include "n32h49x_pwr.h"
|
||||
#include "n32h49x_dbg.h"
|
||||
#include "n32h49x_flash.h"
|
||||
#include "drv_common.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define N32_FLASH_START_ADRESS ((uint32_t)0x08000000)
|
||||
#define N32_FLASH_SIZE (1024 * 1024)
|
||||
#define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE))
|
||||
|
||||
#define N32_SRAM_SIZE (448)
|
||||
#define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024)
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section = "CSTACK"
|
||||
#define HEAP_BEGIN (__segment_end("CSTACK"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END N32_SRAM_END
|
||||
|
||||
void System_Initialize(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user