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[bsp/n32]n32h760zil7-stb bsp修复完善，添加 n32h497zgl7-evb和n32h487zgl7-evb bsp (#11627)

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1、修改n32\n32gxx_lxx\n32g4frml-stb中的GCC启动文件bl entry
2、修复完善n32h760zil7-stb bsp，支持GCC环境、支持更多外设
3、添加n32h487zgl7-evb初版BSP
4、添加n32h497zgl7-evb初版BSP
5、删除n32g452xx这个bsp

---------

Co-authored-by: OnlyoutzZ <OnlyoutzZ+github[bot]@noreply.github.com>
This commit is contained in:
Onlyou_tzZ
2026-07-22 17:06:34 +08:00
committed by GitHub
co-authored by OnlyoutzZ <OnlyoutzZ+github[bot]@noreply.github.com>
parent 622c55248c
commit f08217a883
505 changed files with 45982 additions and 292468 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.github/ALL_BSP_COMPILE.json
+3 -2
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@@ -342,8 +342,9 @@
"n32/n32gxx_lxx/n32l43xrl-stb",
"n32/n32gxx_lxx/n32l436-evb",
"n32/n32gxx_lxx/n32wb45xl-evb",
"n32g452xx/n32g452xx-mini-system",
"n32/n32hxxx/n32h760zil7-stb",
"n32/n32hxxx/n32h760zil7-stb",
"n32/n32hxxx/n32h487zgl7-evb",
"n32/n32hxxx/n32h497zgl7-evb",
"apm32/apm32f103xe-minibroard",
"apm32/apm32f407ig-minibroard",
"apm32/apm32f407zg-evalboard",
bsp/README.md
+17 -19
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@@ -317,21 +317,24 @@ This document is based on the RT-Thread mainline repository and categorizes the
#### 🟡 N32
| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT |
| BSP Name | GPIO | UART | ADC | CAN | DAC | HWTimer | I2C | RTC | SPI | WDT | PWM |ENCODER | LPTIM | NAND | ETH | ON-Chip FLASH |
|----------|------|------|-----|-----|-----|---------|-----|-----|-----|-----|
| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | - | - | - | ✅ | ✅ | ✅ | - |
| [n32g43xcl-stb](n32/n32gxx_lxx/n32g43xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g457gel-stb](n32/n32gxx_lxx/n32g457gel-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g45xcl-stb](n32/n32gxx_lxx/n32g45xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g45xml-stb](n32/n32gxx_lxx/n32g45xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g45xrl-stb](n32/n32gxx_lxx/n32g45xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g45xvl-stb](n32/n32gxx_lxx/n32g45xvl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32g47rml-stb](n32/n32gxx_lxx/n32g47rml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32l40xcl-stb](n32/n32gxx_lxx/n32l40xcl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32l436-evb](n32/n32gxx_lxx/n32l436-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32l43xml-stb](n32/n32gxx_lxx/n32l43xml-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32l43xrl-stb](n32/n32gxx_lxx/n32l43xrl-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32wb45xl-evb](n32/n32gxx_lxx/n32wb45xl-evb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | - | - | - | - |
| [n32h760zil7-stb](n32/n32hxxx/n32h760zil7-stb) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [n32h497zgl7-evb](n32/n32hxxx/n32h497zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
| [n32h487zgl7-evb](n32/n32hxxx/n32h487zgl7-evb) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
#### 🟡 NRF5x
@@ -420,11 +423,6 @@ This document is based on the RT-Thread mainline repository and categorizes the
| [swm320-mini](synwit/swm320-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
| [swm341-mini](synwit/swm341-mini) | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ |
#### ⚪ N32G452xx
| BSP Name | GPIO | UART | ADC | CAN | DAC | Flash | HWTimer | I2C | PWM | RTC | SDIO | SPI | WDT |
|----------|------|------|-----|-----|-----|-------|---------|-----|-----|-----|------|-----|-----|
| [n32g452xx-mini-system](n32g452xx/n32g452xx-mini-system) | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ |
#### ⚪ W60x
| BSP Name | GPIO | UART | ADC | Crypto | Flash | HWTimer | WDT | PWM | I2C | SPI |
|----------|------|------|-----|--------|-------|---------|-----|-----|-----|-----|
bsp/n32/n32gxx_lxx/libraries/N32G4FR_Firmware_Library/CMSIS/device/startup/startup_n32g4fr_gcc.s
+1 -1
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@@ -72,7 +72,7 @@ LoopFillZerobss:
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler
bsp/n32/n32hxxx/.clang-format-ignore
+2 -5
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@@ -5,8 +5,5 @@
# 从 .ignore_format.yml 迁移的规则
/n32h760zil7-stb/board/Cube_Config/
/n32h760zil7-stb/board/Cube_Config/data/
/n32h760zil7-stb/board/Cube_Config/Driver/
/n32h760zil7-stb/board/Cube_Config/MDK-ARM/
/n32h760zil7-stb/board/Cube_Config/startup/
/n32h760zil7-stb/board/Cube_Config/USER/
/n32h487zgl7-evb/board/Cube_Config/
/n32h497zgl7-evb/board/Cube_Config/
bsp/n32/n32hxxx/libraries/Kconfig
+10
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@@ -6,4 +6,14 @@ config SOC_SERIES_N32H7xx
select ARCH_ARM_CORTEX_M7
select SOC_FAMILY_N32
config SOC_SERIES_N32H47x_48x
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_N32
config SOC_SERIES_N32H49x
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_N32
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/SConscript
+66 -3
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@@ -12,24 +12,87 @@ if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_usart.c']
if GetDepend(['RT_USING_SERIAL_V2']):
src += ['drv_usart_v2.c']
else:
src += ['drv_usart.c']
if GetDepend(['BSP_USING_CLOCK_TIMER']):
src += ['drv_tim.c']
if GetDepend(['BSP_USING_PWM']):
src += ['drv_pwm.c', 'drv_tim.c']
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_QSPI']):
src += ['drv_qspi.c']
if GetDepend(['RT_USING_I2C']):
if GetDepend('BSP_USING_HARD_I2C1') or GetDepend('BSP_USING_HARD_I2C2') or GetDepend('BSP_USING_HARD_I2C3') or GetDepend('BSP_USING_HARD_I2C4') or GetDepend('BSP_USING_HARD_I2C5') or GetDepend('BSP_USING_HARD_I2C6') or GetDepend('BSP_USING_HARD_I2C7') or GetDepend('BSP_USING_HARD_I2C8') or GetDepend('BSP_USING_HARD_I2C9') or GetDepend('BSP_USING_HARD_I2C10'):
src += ['drv_hard_i2c.c']
if GetDepend('BSP_USING_ONCHIP_RTC'):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
src += ['drv_eth.c']
if GetDepend(['RT_USING_ADC']):
src += ['drv_adc.c']
if GetDepend(['RT_USING_DAC']):
src += ['drv_dac.c']
if GetDepend(['RT_USING_CAN']):
if GetDepend(['SOC_SERIES_N32H7xx']) or GetDepend(['SOC_SERIES_N32H47x_48x']) or GetDepend(['SOC_SERIES_N32H49x']):
src += ['drv_fdcan.c']
else:
src += ['drv_can.c']
if GetDepend(['RT_USING_PM']):
src += ['drv_pm.c']
if GetDepend(['BSP_USING_LPTIM']):
src += ['drv_lptim.c']
if GetDepend('BSP_USING_SDRAM'):
src += ['drv_sdram.c']
if GetDepend(['BSP_USING_NAND']):
src += ['drv_nand.c']
if GetDepend('BSP_USING_LCD'):
src += ['drv_lcd.c']
if GetDepend('BSP_USING_ONCHIP_RTC'):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H49x']):
src += [os.path.join('drv_flash', 'drv_flash_h49x.c')]
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H47x_48x']):
src += [os.path.join('drv_flash', 'drv_flash_h47x_48x.c')]
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_N32H7xx']):
src += [os.path.join('drv_flash', 'drv_flash_h7xx.c')]
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_SDIO']):
if GetDepend('SOC_SERIES_N32H7xx'):
src += ['drv_sdmmc.c']
else:
src += ['drv_sdio.c']
if GetDepend(['BSP_USING_PULSE_ENCODER']):
src += ['drv_pulse_encoder.c', 'drv_tim.c']
path += [os.path.join(cwd, 'config')]
if GetDepend('BSP_USING_ON_CHIP_FLASH'):
path += [os.path.join(cwd, 'drv_flash')]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/dma_config.h
+201
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@@ -0,0 +1,201 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-07 ox-horse first version
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel1 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA)
#define UART1_RX_DMA DMA1
#define UART1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define UART1_RX_DMA_CHType DMA1_CH1
#define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn
#define UART1_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART1_RX_DMA_REQUEST DMA_REMAP_USART1_RX
#define UART1_RX_DMA_CHANNEL 1U
#endif
/* DMA1 channel2 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA)
#define UART2_RX_DMA DMA1
#define UART2_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define UART2_RX_DMA_CHType DMA1_CH2
#define UART2_RX_DMA_IRQ DMA1_Channel2_IRQn
#define UART2_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART2_RX_DMA_REQUEST DMA_REMAP_USART2_RX
#define UART2_RX_DMA_CHANNEL 2U
#endif
/* DMA1 channel3 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA)
#define UART3_RX_DMA DMA1
#define UART3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define UART3_RX_DMA_CHType DMA1_CH3
#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
#define UART3_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART3_RX_DMA_REQUEST DMA_REMAP_USART3_RX
#define UART3_RX_DMA_CHANNEL 3U
#endif
/* DMA1 channel4 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA)
#define UART4_RX_DMA DMA1
#define UART4_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define UART4_RX_DMA_CHType DMA1_CH4
#define UART4_RX_DMA_IRQ DMA1_Channel4_IRQn
#define UART4_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART4_RX_DMA_REQUEST DMA_REMAP_USART4_RX
#define UART4_RX_DMA_CHANNEL 4U
#endif
/* DMA1 channel5 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA)
#define UART5_RX_DMA DMA1
#define UART5_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART5_RX_DMA_CHType DMA1_CH5
#define UART5_RX_DMA_IRQ DMA1_Channel5_IRQn
#define UART5_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART5_RX_DMA_REQUEST DMA_REMAP_UART5_RX
#define UART5_RX_DMA_CHANNEL 5U
#endif
/* DMA1 channel6 */
#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA)
#define UART6_RX_DMA DMA1
#define UART6_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART6_RX_DMA_CHType DMA1_CH6
#define UART6_RX_DMA_IRQ DMA1_Channel6_IRQn
#define UART6_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART6_RX_DMA_REQUEST DMA_REMAP_UART6_RX
#define UART6_RX_DMA_CHANNEL 6U
#endif
/* DMA1 channel7 */
#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA)
#define UART7_RX_DMA DMA1
#define UART7_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART7_RX_DMA_CHType DMA1_CH7
#define UART7_RX_DMA_IRQ DMA1_Channel7_IRQn
#define UART7_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART7_RX_DMA_REQUEST DMA_REMAP_UART7_RX
#define UART7_RX_DMA_CHANNEL 7U
#endif
/* DMA1 channel8 */
#if defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA)
#define UART8_RX_DMA DMA1
#define UART8_RX_DMA_IRQHandler DMA1_Channel8_IRQHandler
#define UART8_RX_DMA_CHType DMA1_CH8
#define UART8_RX_DMA_IRQ DMA1_Channel8_IRQn
#define UART8_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART8_RX_DMA_REQUEST DMA_REMAP_UART8_RX
#define UART8_RX_DMA_CHANNEL 8U
#endif
/* DMA2 channel1 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA)
#define UART1_TX_DMA DMA2
#define UART1_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define UART1_TX_DMA_CHType DMA2_CH1
#define UART1_TX_DMA_IRQ DMA2_Channel1_IRQn
#define UART1_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART1_TX_DMA_REQUEST DMA_REMAP_USART1_TX
#define UART1_TX_DMA_CHANNEL 1U
#endif
/* DMA2 channel2 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA)
#define UART2_TX_DMA DMA2
#define UART2_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define UART2_TX_DMA_CHType DMA2_CH2
#define UART2_TX_DMA_IRQ DMA2_Channel2_IRQn
#define UART2_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART2_TX_DMA_REQUEST DMA_REMAP_USART2_TX
#define UART2_TX_DMA_CHANNEL 2U
#endif
/* DMA2 channel3 */
#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA)
#define UART3_TX_DMA DMA2
#define I2C10_RX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define UART3_TX_DMA_CHType DMA2_CH3
#define UART3_TX_DMA_IRQ DMA2_Channel3_IRQn
#define UART3_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART3_TX_DMA_REQUEST DMA_REMAP_USART3_TX
#define UART3_TX_DMA_CHANNEL 3U
#endif
/* DMA2 channel4 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA)
#define UART4_TX_DMA DMA2
#define UART4_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define UART4_TX_DMA_CHType DMA2_CH4
#define UART4_TX_DMA_IRQ DMA2_Channel4_IRQn
#define UART4_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART4_TX_DMA_REQUEST DMA_REMAP_USART4_TX
#define UART4_TX_DMA_CHANNEL 4U
#endif
/* DMA2 channel5 */
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA)
#define UART5_TX_DMA DMA2
#define UART5_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define UART5_TX_DMA_CHType DMA2_CH5
#define UART5_TX_DMA_IRQ DMA2_Channel5_IRQn
#define UART5_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART5_TX_DMA_REQUEST DMA_REMAP_UART5_TX
#define UART5_TX_DMA_CHANNEL 5U
#endif
/* DMA2 channel6 */
#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA)
#define UART6_TX_DMA DMA2
#define UART6_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define UART6_TX_DMA_CHType DMA2_CH6
#define UART6_TX_DMA_IRQ DMA2_Channel6_IRQn
#define UART6_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART6_TX_DMA_REQUEST DMA_REMAP_UART6_TX
#define UART6_TX_DMA_CHANNEL 6U
#endif
/* DMA2 channel7 */
#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA)
#define UART7_TX_DMA DMA2
#define UART7_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define UART7_TX_DMA_CHType DMA2_CH7
#define UART7_TX_DMA_IRQ DMA2_Channel7_IRQn
#define UART7_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART7_TX_DMA_REQUEST DMA_REMAP_UART7_TX
#define UART7_TX_DMA_CHANNEL 7U
#endif
/* DMA2 channel8 */
#if defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA)
#define UART8_TX_DMA DMA2
#define UART8_TX_DMA_IRQHandler DMA2_Channel8_IRQHandler
#define UART8_TX_DMA_CHType DMA2_CH8
#define UART8_TX_DMA_IRQ DMA2_Channel8_IRQn
#define UART8_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART8_TX_DMA_REQUEST DMA_REMAP_UART8_TX
#define UART8_TX_DMA_CHANNEL 8U
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h47x_48x/uart_config.h
+401
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-07 ox-horse first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.periph = RCC_APB2_PERIPH_USART1, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#if defined(UART1_RX_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.DMAy = UART1_RX_DMA, \
.DMAChx = UART1_RX_DMA_CHType, \
.dma_irq = UART1_RX_DMA_IRQ, \
.dma_rcc = UART1_RX_DMA_RCC, \
.request = UART1_RX_DMA_REQUEST, \
.channel = UART1_RX_DMA_CHANNEL, \
}
#endif /* UART1_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_RX_DMA */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#if defined(UART1_TX_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.DMAy = UART1_TX_DMA, \
.DMAChx = UART1_TX_DMA_CHType, \
.dma_irq = UART1_TX_DMA_IRQ, \
.dma_rcc = UART1_TX_DMA_RCC, \
.request = UART1_TX_DMA_REQUEST, \
.channel = UART1_TX_DMA_CHANNEL, \
}
#endif /* UART1_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_TX_DMA */
#endif /* BSP_UART1_TX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.periph = RCC_APB1_PERIPH_USART2, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#if defined(UART2_RX_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.DMAy = UART2_RX_DMA, \
.DMAChx = UART2_RX_DMA_CHType, \
.dma_irq = UART2_RX_DMA_IRQ, \
.dma_rcc = UART2_RX_DMA_RCC, \
.request = UART2_RX_DMA_REQUEST, \
.channel = UART2_RX_DMA_CHANNEL, \
}
#endif /* UART2_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_RX_DMA */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#if defined(UART2_TX_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.DMAy = UART2_TX_DMA, \
.DMAChx = UART2_TX_DMA_CHType, \
.dma_irq = UART2_TX_DMA_IRQ, \
.dma_rcc = UART2_TX_DMA_RCC, \
.request = UART2_TX_DMA_REQUEST, \
.channel = UART2_TX_DMA_CHANNEL, \
}
#endif /* UART2_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_TX_DMA */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.periph = RCC_APB1_PERIPH_USART3, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_UART3_RX_USING_DMA)
#if defined(UART3_RX_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.DMAy = UART3_RX_DMA, \
.DMAChx = UART3_RX_DMA_CHType, \
.dma_irq = UART3_RX_DMA_IRQ, \
.dma_rcc = UART3_RX_DMA_RCC, \
.request = UART3_RX_DMA_REQUEST, \
.channel = UART3_RX_DMA_CHANNEL, \
}
#endif /* UART3_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_RX_DMA */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#if defined(UART3_TX_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.DMAy = UART3_TX_DMA, \
.DMAChx = UART3_TX_DMA_CHType, \
.dma_irq = UART3_TX_DMA_IRQ, \
.dma_rcc = UART3_TX_DMA_RCC, \
.request = UART3_TX_DMA_REQUEST, \
.channel = UART3_TX_DMA_CHANNEL, \
}
#endif /* UART3_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_TX_DMA */
#endif /* BSP_UART3_TX_USING_DMA */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = USART4, \
.irq_type = USART4_IRQn, \
.periph = RCC_APB2_PERIPH_USART4, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_UART4_RX_USING_DMA)
#if defined(UART4_RX_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.DMAy = UART4_RX_DMA, \
.DMAChx = UART4_RX_DMA_CHType, \
.dma_irq = UART4_RX_DMA_IRQ, \
.dma_rcc = UART4_RX_DMA_RCC, \
.request = UART4_RX_DMA_REQUEST, \
.channel = UART4_RX_DMA_CHANNEL, \
}
#endif /* UART4_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_RX_DMA */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_UART4_TX_USING_DMA)
#if defined(UART4_TX_DMA)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.DMAy = UART4_TX_DMA, \
.DMAChx = UART4_TX_DMA_CHType, \
.dma_irq = UART4_TX_DMA_IRQ, \
.dma_rcc = UART4_TX_DMA_RCC, \
.request = UART4_TX_DMA_REQUEST, \
.channel = UART4_TX_DMA_CHANNEL, \
}
#endif /* UART4_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_TX_DMA */
#endif /* BSP_UART4_TX_USING_DMA */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.periph = RCC_APB1_PERIPH_UART5, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_UART5_RX_USING_DMA)
#if defined(UART5_RX_DMA)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
{ \
.DMAy = UART5_RX_DMA, \
.DMAChx = UART5_RX_DMA_CHType, \
.dma_irq = UART5_RX_DMA_IRQ, \
.dma_rcc = UART5_RX_DMA_RCC, \
.request = UART5_RX_DMA_REQUEST, \
.channel = UART5_RX_DMA_CHANNEL, \
}
#endif /* UART5_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_RX_DMA */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#if defined(UART5_TX_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
{ \
.DMAy = UART5_TX_DMA, \
.DMAChx = UART5_TX_DMA_CHType, \
.dma_irq = UART5_TX_DMA_IRQ, \
.dma_rcc = UART5_TX_DMA_RCC, \
.request = UART5_TX_DMA_REQUEST, \
.channel = UART5_TX_DMA_CHANNEL, \
}
#endif /* UART5_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_TX_DMA */
#endif /* BSP_UART5_TX_USING_DMA */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = UART6, \
.irq_type = UART6_IRQn, \
.periph = RCC_APB2_PERIPH_UART6, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_UART6_RX_USING_DMA)
#if defined(UART6_RX_DMA)
#ifndef UART6_DMA_RX_CONFIG
#define UART6_DMA_RX_CONFIG \
{ \
.DMAy = UART6_RX_DMA, \
.DMAChx = UART6_RX_DMA_CHType, \
.dma_irq = UART6_RX_DMA_IRQ, \
.dma_rcc = UART6_RX_DMA_RCC, \
.request = UART6_RX_DMA_REQUEST, \
.channel = UART6_RX_DMA_CHANNEL, \
}
#endif /* UART6_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_RX_DMA */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#if defined(UART6_TX_DMA)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
{ \
.DMAy = UART6_TX_DMA, \
.DMAChx = UART6_TX_DMA_CHType, \
.dma_irq = UART6_TX_DMA_IRQ, \
.dma_rcc = UART6_TX_DMA_RCC, \
.request = UART6_TX_DMA_REQUEST, \
.channel = UART6_TX_DMA_CHANNEL, \
}
#endif /* UART6_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_TX_DMA */
#endif /* BSP_UART6_TX_USING_DMA */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.Instance = UART7, \
.irq_type = UART7_IRQn, \
.periph = RCC_APB2_PERIPH_UART7, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_UART7_RX_USING_DMA)
#if defined(UART7_RX_DMA)
#ifndef UART7_DMA_RX_CONFIG
#define UART7_DMA_RX_CONFIG \
{ \
.DMAy = UART7_RX_DMA, \
.DMAChx = UART7_RX_DMA_CHType, \
.dma_irq = UART7_RX_DMA_IRQ, \
.dma_rcc = UART7_RX_DMA_RCC, \
.request = UART7_RX_DMA_REQUEST, \
.channel = UART7_RX_DMA_CHANNEL, \
}
#endif /* UART7_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_RX_DMA */
#endif /* BSP_UART7_RX_USING_DMA */
#if defined(BSP_UART7_TX_USING_DMA)
#if defined(UART7_TX_DMA)
#ifndef UART7_DMA_TX_CONFIG
#define UART7_DMA_TX_CONFIG \
{ \
.DMAy = UART7_TX_DMA, \
.DMAChx = UART7_TX_DMA_CHType, \
.dma_irq = UART7_TX_DMA_IRQ, \
.dma_rcc = UART7_TX_DMA_RCC, \
.request = UART7_TX_DMA_REQUEST, \
.channel = UART7_TX_DMA_CHANNEL, \
}
#endif /* UART7_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_TX_DMA */
#endif /* BSP_UART7_TX_USING_DMA */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.Instance = UART8, \
.irq_type = UART8_IRQn, \
.periph = RCC_APB1_PERIPH_UART8, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_UART8_RX_USING_DMA)
#if defined(UART8_RX_DMA)
#ifndef UART8_DMA_RX_CONFIG
#define UART8_DMA_RX_CONFIG \
{ \
.DMAy = UART8_RX_DMA, \
.DMAChx = UART8_RX_DMA_CHType, \
.dma_irq = UART8_RX_DMA_IRQ, \
.dma_rcc = UART8_RX_DMA_RCC, \
.request = UART8_RX_DMA_REQUEST, \
.channel = UART8_RX_DMA_CHANNEL, \
}
#endif /* UART8_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_RX_DMA */
#endif /* BSP_UART8_RX_USING_DMA */
#if defined(BSP_UART8_TX_USING_DMA)
#if defined(UART8_TX_DMA)
#ifndef UART8_DMA_TX_CONFIG
#define UART8_DMA_TX_CONFIG \
{ \
.DMAy = UART8_TX_DMA, \
.DMAChx = UART8_TX_DMA_CHType, \
.dma_irq = UART8_TX_DMA_IRQ, \
.dma_rcc = UART8_TX_DMA_RCC, \
.request = UART8_TX_DMA_REQUEST, \
.channel = UART8_TX_DMA_CHANNEL, \
}
#endif /* UART8_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_TX_DMA */
#endif /* BSP_UART8_TX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /* __UART_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/dma_config.h
+411
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@@ -0,0 +1,411 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-07 ox-horse first version
*/
#ifndef __DMA_CONFIG_H__
#define __DMA_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
/* DMA1 channel1 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA)
#define UART1_RX_DMA DMA1
#define UART1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
#define UART1_RX_DMA_CHType DMA1_CH1
#define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn
#define UART1_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART1_RX_DMA_REQUEST DMA_REMAP_USART1_RX
#define UART1_RX_DMA_CHANNEL 1U
#endif
/* DMA1 channel2 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA)
#define UART2_RX_DMA DMA1
#define UART2_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define UART2_RX_DMA_CHType DMA1_CH2
#define UART2_RX_DMA_IRQ DMA1_Channel2_IRQn
#define UART2_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART2_RX_DMA_REQUEST DMA_REMAP_USART2_RX
#define UART2_RX_DMA_CHANNEL 2U
#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA)
#define I2C2_RX_DMA DMA1
#define I2C2_RX_DMA_IRQHandler DMA1_Channel2_IRQHandler
#define I2C2_RX_DMA_CHType DMA1_CH2
#define I2C2_RX_DMA_IRQ DMA1_Channel2_IRQn
#define I2C2_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define I2C2_RX_DMA_REQUEST DMA_REMAP_I2C2_RX
#define I2C2_RX_DMA_CHANNEL 2U
#endif
/* DMA1 channel3 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA)
#define UART3_RX_DMA DMA1
#define UART3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define UART3_RX_DMA_CHType DMA1_CH3
#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
#define UART3_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART3_RX_DMA_REQUEST DMA_REMAP_USART3_RX
#define UART3_RX_DMA_CHANNEL 3U
#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA)
#define I2C3_RX_DMA DMA1
#define I2C3_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
#define I2C3_RX_DMA_CHType DMA1_CH3
#define I2C3_RX_DMA_IRQ DMA1_Channel3_IRQn
#define I2C3_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define I2C3_RX_DMA_REQUEST DMA_REMAP_I2C3_RX
#define I2C3_RX_DMA_CHANNEL 3U
#endif
/* DMA1 channel4 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA)
#define UART4_RX_DMA DMA1
#define UART4_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define UART4_RX_DMA_CHType DMA1_CH4
#define UART4_RX_DMA_IRQ DMA1_Channel4_IRQn
#define UART4_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART4_RX_DMA_REQUEST DMA_REMAP_USART4_RX
#define UART4_RX_DMA_CHANNEL 4U
#elif defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA)
#define SPI6_RX_DMA DMA1
#define SPI6_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define SPI6_RX_DMA_CHType DMA1_CH4
#define SPI6_RX_DMA_IRQ DMA1_Channel4_IRQn
#define SPI6_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI6_RX_DMA_REQUEST DMA_REMAP_SPI6_RX
#define SPI6_RX_DMA_CHANNEL 4U
#elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA)
#define I2C4_RX_DMA DMA1
#define I2C4_RX_DMA_IRQHandler DMA1_Channel4_IRQHandler
#define I2C4_RX_DMA_CHType DMA1_CH4
#define I2C4_RX_DMA_IRQ DMA1_Channel4_IRQn
#define I2C4_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define I2C4_RX_DMA_REQUEST DMA_REMAP_I2C4_RX
#define I2C4_RX_DMA_CHANNEL 4U
#endif
/* DMA1 channel5 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA)
#define UART5_RX_DMA DMA1
#define UART5_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART5_RX_DMA_CHType DMA1_CH5
#define UART5_RX_DMA_IRQ DMA1_Channel5_IRQn
#define UART5_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART5_RX_DMA_REQUEST DMA_REMAP_UART5_RX
#define UART5_RX_DMA_CHANNEL 5U
#elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA)
#define UART10_TX_DMA DMA1
#define UART10_TX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define UART10_TX_DMA_CHType DMA1_CH5
#define UART10_TX_DMA_IRQ DMA1_Channel5_IRQn
#define UART10_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART10_TX_DMA_REQUEST DMA_REMAP_UART10_TX
#define UART10_TX_DMA_CHANNEL 5U
#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA)
#define SPI5_RX_DMA DMA1
#define SPI5_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
#define SPI5_RX_DMA_CHType DMA1_CH5
#define SPI5_RX_DMA_IRQ DMA1_Channel5_IRQn
#define SPI5_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI5_RX_DMA_REQUEST DMA_REMAP_SPI5_RX
#define SPI5_RX_DMA_CHANNEL 5U
#endif
/* DMA1 channel6 */
#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA)
#define UART6_RX_DMA DMA1
#define UART6_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART6_RX_DMA_CHType DMA1_CH6
#define UART6_RX_DMA_IRQ DMA1_Channel6_IRQn
#define UART6_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART6_RX_DMA_REQUEST DMA_REMAP_UART6_RX
#define UART6_RX_DMA_CHANNEL 6U
#elif defined(BSP_UART9_TX_USING_DMA) && !defined(UART9_TX_DMA)
#define UART9_TX_DMA DMA1
#define UART9_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define UART9_TX_DMA_CHType DMA1_CH6
#define UART9_TX_DMA_IRQ DMA1_Channel6_IRQn
#define UART9_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART9_TX_DMA_REQUEST DMA_REMAP_USART9_TX
#define UART9_TX_DMA_CHANNEL 6U
#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA)
#define SPI4_RX_DMA DMA1
#define SPI4_RX_DMA_IRQHandler DMA1_Channel6_IRQHandler
#define SPI4_RX_DMA_CHType DMA1_CH6
#define SPI4_RX_DMA_IRQ DMA1_Channel6_IRQn
#define SPI4_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI4_RX_DMA_REQUEST DMA_REMAP_SPI4_RX
#define SPI4_RX_DMA_CHANNEL 6U
#endif
/* DMA1 channel7 */
#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA)
#define UART7_RX_DMA DMA1
#define UART7_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART7_RX_DMA_CHType DMA1_CH7
#define UART7_RX_DMA_IRQ DMA1_Channel7_IRQn
#define UART7_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART7_RX_DMA_REQUEST DMA_REMAP_UART7_RX
#define UART7_RX_DMA_CHANNEL 7U
#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA)
#define UART8_TX_DMA DMA1
#define UART8_TX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define UART8_TX_DMA_CHType DMA1_CH7
#define UART8_TX_DMA_IRQ DMA1_Channel7_IRQn
#define UART8_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART8_TX_DMA_REQUEST DMA_REMAP_UART8_TX
#define UART8_TX_DMA_CHANNEL 7U
#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA)
#define SPI3_RX_DMA DMA1
#define SPI3_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
#define SPI3_RX_DMA_CHType DMA1_CH7
#define SPI3_RX_DMA_IRQ DMA1_Channel7_IRQn
#define SPI3_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI3_RX_DMA_REQUEST DMA_REMAP_SPI3_I2S3_RX
#define SPI3_RX_DMA_CHANNEL 7U
#endif
/* DMA1 channel8 */
#if defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA)
#define UART8_RX_DMA DMA1
#define UART8_RX_DMA_IRQHandler DMA1_Channel8_IRQHandler
#define UART8_RX_DMA_CHType DMA1_CH8
#define UART8_RX_DMA_IRQ DMA1_Channel8_IRQn
#define UART8_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART8_RX_DMA_REQUEST DMA_REMAP_UART8_RX
#define UART8_RX_DMA_CHANNEL 8U
#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA)
#define UART7_TX_DMA DMA1
#define UART7_TX_DMA_IRQHandler DMA1_Channel8_IRQHandler
#define UART7_TX_DMA_CHType DMA1_CH8
#define UART7_TX_DMA_IRQ DMA1_Channel8_IRQn
#define UART7_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define UART7_TX_DMA_REQUEST DMA_REMAP_UART7_TX
#define UART7_TX_DMA_CHANNEL 8U
#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA)
#define SPI2_RX_DMA DMA1
#define SPI2_RX_DMA_IRQHandler DMA1_Channel8_IRQHandler
#define SPI2_RX_DMA_CHType DMA1_CH8
#define SPI2_RX_DMA_IRQ DMA1_Channel8_IRQn
#define SPI2_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA1
#define SPI2_RX_DMA_REQUEST DMA_REMAP_SPI2_I2S2_RX
#define SPI2_RX_DMA_CHANNEL 8U
#endif
/* DMA2 channel1 */
#if defined(BSP_UART9_RX_USING_DMA) && !defined(UART9_RX_DMA)
#define UART9_RX_DMA DMA2
#define UART9_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define UART9_RX_DMA_CHType DMA2_CH1
#define UART9_RX_DMA_IRQ DMA2_Channel1_IRQn
#define UART9_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART9_RX_DMA_REQUEST DMA_REMAP_USART9_RX
#define UART9_RX_DMA_CHANNEL 1U
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA)
#define SPI1_RX_DMA DMA2
#define SPI1_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define SPI1_RX_DMA_CHType DMA2_CH1
#define SPI1_RX_DMA_IRQ DMA2_Channel1_IRQn
#define SPI1_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI1_RX_DMA_REQUEST DMA_REMAP_SPI1_RX
#define SPI1_RX_DMA_CHANNEL 1U
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA)
#define I2C1_RX_DMA DMA2
#define I2C1_RX_DMA_IRQHandler DMA2_Channel1_IRQHandler
#define I2C1_RX_DMA_CHType DMA2_CH1
#define I2C1_RX_DMA_IRQ DMA2_Channel1_IRQn
#define I2C1_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C1_RX_DMA_REQUEST DMA_REMAP_I2C1_RX
#define I2C1_RX_DMA_CHANNEL 1U
#endif
/* DMA2 channel2 */
#if defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA)
#define UART10_RX_DMA DMA2
#define UART10_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define UART10_RX_DMA_CHType DMA2_CH2
#define UART10_RX_DMA_IRQ DMA2_Channel2_IRQn
#define UART10_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART10_RX_DMA_REQUEST DMA_REMAP_UART10_RX
#define UART10_RX_DMA_CHANNEL 2U
#elif defined(BSP_USING_SDIO) && !defined(UART10_RX_DMA)
#define SDIO_RX_DMA DMA2
#define SDIO_TX_DMA DMA2
#define SDIO_RX_TX_DMA_IRQHandler DMA2_Channel2_IRQHandler
#define SDIO_TX_DMA_CHType DMA2_CH2
#define SDIO_RX_DMA_CHType DMA2_CH2
#define SDIO_TX_DMA_IRQ DMA2_Channel2_IRQn
#define SDIO_RX_DMA_IRQ DMA2_Channel2_IRQn
#define SDIO_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SDIO_RX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SDIO_TX_DMA_REQUEST DMA_REMAP_SDIO
#define SDIO_RX_DMA_REQUEST DMA_REMAP_SDIO
#define SDIO_TX_DMA_CHANNEL 2U
#define SDIO_RX_DMA_CHANNEL 2U
#endif
/* DMA2 channel3 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA)
#define UART1_TX_DMA DMA2
#define UART1_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define UART1_TX_DMA_CHType DMA2_CH3
#define UART1_TX_DMA_IRQ DMA2_Channel3_IRQn
#define UART1_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART1_TX_DMA_REQUEST DMA_REMAP_USART1_TX
#define UART1_TX_DMA_CHANNEL 3U
#elif defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA)
#define SPI6_TX_DMA DMA2
#define SPI6_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define SPI6_TX_DMA_CHType DMA2_CH3
#define SPI6_TX_DMA_IRQ DMA2_Channel3_IRQn
#define SPI6_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI6_TX_DMA_REQUEST DMA_REMAP_SPI6_TX
#define SPI6_TX_DMA_CHANNEL 3U
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA)
#define I2C1_TX_DMA DMA2
#define I2C1_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
#define I2C1_TX_DMA_CHType DMA2_CH3
#define I2C1_TX_DMA_IRQ DMA2_Channel3_IRQn
#define I2C1_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C1_TX_DMA_REQUEST DMA_REMAP_I2C1_TX
#define I2C1_TX_DMA_CHANNEL 3U
#endif
/* DMA2 channel4 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA)
#define UART2_TX_DMA DMA2
#define UART2_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define UART2_TX_DMA_CHType DMA2_CH4
#define UART2_TX_DMA_IRQ DMA2_Channel4_IRQn
#define UART2_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART2_TX_DMA_REQUEST DMA_REMAP_USART2_TX
#define UART2_TX_DMA_CHANNEL 4U
#elif defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA)
#define SPI5_TX_DMA DMA2
#define SPI5_TX_DMA_IRQHandler DMA2_Channel4_IRQHandler
#define SPI5_TX_DMA_CHType DMA2_CH4
#define SPI5_TX_DMA_IRQ DMA2_Channel4_IRQn
#define SPI5_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI5_TX_DMA_REQUEST DMA_REMAP_SPI5_TX
#define SPI5_TX_DMA_CHANNEL 4U
#endif
/* DMA2 channel5 */
#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA)
#define UART3_TX_DMA DMA2
#define UART3_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define UART3_TX_DMA_CHType DMA2_CH5
#define UART3_TX_DMA_IRQ DMA2_Channel5_IRQn
#define UART3_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART3_TX_DMA_REQUEST DMA_REMAP_USART3_TX
#define UART3_TX_DMA_CHANNEL 5U
#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA)
#define SPI4_TX_DMA DMA2
#define SPI4_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define SPI4_TX_DMA_CHType DMA2_CH5
#define SPI4_TX_DMA_IRQ DMA2_Channel5_IRQn
#define SPI4_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI4_TX_DMA_REQUEST DMA_REMAP_SPI4_TX
#define SPI4_TX_DMA_CHANNEL 5U
#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA)
#define I2C2_TX_DMA DMA2
#define I2C2_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
#define I2C2_TX_DMA_CHType DMA2_CH5
#define I2C2_TX_DMA_IRQ DMA2_Channel5_IRQn
#define I2C2_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C2_TX_DMA_REQUEST DMA_REMAP_I2C2_TX
#define I2C2_TX_DMA_CHANNEL 5U
#endif
/* DMA2 channel6 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA)
#define UART4_TX_DMA DMA2
#define UART4_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define UART4_TX_DMA_CHType DMA2_CH6
#define UART4_TX_DMA_IRQ DMA2_Channel6_IRQn
#define UART4_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART4_TX_DMA_REQUEST DMA_REMAP_USART4_TX
#define UART4_TX_DMA_CHANNEL 6U
#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA)
#define SPI3_TX_DMA DMA2
#define SPI3_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define SPI3_TX_DMA_CHType DMA2_CH6
#define SPI3_TX_DMA_IRQ DMA2_Channel6_IRQn
#define SPI3_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI3_TX_DMA_REQUEST DMA_REMAP_SPI3_I2S3_TX
#define SPI3_TX_DMA_CHANNEL 6U
#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA)
#define I2C3_TX_DMA DMA2
#define I2C3_TX_DMA_IRQHandler DMA2_Channel6_IRQHandler
#define I2C3_TX_DMA_CHType DMA2_CH6
#define I2C3_TX_DMA_IRQ DMA2_Channel6_IRQn
#define I2C3_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C3_TX_DMA_REQUEST DMA_REMAP_I2C3_TX
#define I2C3_TX_DMA_CHANNEL 6U
#endif
/* DMA2 channel7 */
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA)
#define UART5_TX_DMA DMA2
#define UART5_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define UART5_TX_DMA_CHType DMA2_CH7
#define UART5_TX_DMA_IRQ DMA2_Channel7_IRQn
#define UART5_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART5_TX_DMA_REQUEST DMA_REMAP_UART5_TX
#define UART5_TX_DMA_CHANNEL 7U
#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA)
#define SPI2_TX_DMA DMA2
#define SPI2_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define SPI2_TX_DMA_CHType DMA2_CH7
#define SPI2_TX_DMA_IRQ DMA2_Channel7_IRQn
#define SPI2_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI2_TX_DMA_REQUEST DMA_REMAP_SPI2_I2S2_TX
#define SPI2_TX_DMA_CHANNEL 7U
#elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA)
#define I2C4_TX_DMA DMA2
#define I2C4_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
#define I2C4_TX_DMA_CHType DMA2_CH7
#define I2C4_TX_DMA_IRQ DMA2_Channel7_IRQn
#define I2C4_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define I2C4_TX_DMA_REQUEST DMA_REMAP_I2C4_TX
#define I2C4_TX_DMA_CHANNEL 7U
#endif
/* DMA2 channel8 */
#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA)
#define UART6_TX_DMA DMA2
#define UART6_TX_DMA_IRQHandler DMA2_Channel8_IRQHandler
#define UART6_TX_DMA_CHType DMA2_CH8
#define UART6_TX_DMA_IRQ DMA2_Channel8_IRQn
#define UART6_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define UART6_TX_DMA_REQUEST DMA_REMAP_UART6_TX
#define UART6_TX_DMA_CHANNEL 8U
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA)
#define SPI1_TX_DMA DMA2
#define SPI1_TX_DMA_IRQHandler DMA2_Channel8_IRQHandler
#define SPI1_TX_DMA_CHType DMA2_CH8
#define SPI1_TX_DMA_IRQ DMA2_Channel8_IRQn
#define SPI1_TX_DMA_RCC RCC_AHB_PERIPHEN_DMA2
#define SPI1_TX_DMA_REQUEST DMA_REMAP_SPI1_TX
#define SPI1_TX_DMA_CHANNEL 8U
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DMA_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h49x/uart_config.h
+495
View File
@@ -0,0 +1,495 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-04-07 ox-horse first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.Instance = USART1, \
.irq_type = USART1_IRQn, \
.periph = RCC_APB2_PERIPHEN_USART1, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_UART1_RX_USING_DMA)
#if defined(UART1_RX_DMA)
#ifndef UART1_DMA_RX_CONFIG
#define UART1_DMA_RX_CONFIG \
{ \
.DMAy = UART1_RX_DMA, \
.DMAChx = UART1_RX_DMA_CHType, \
.dma_irq = UART1_RX_DMA_IRQ, \
.dma_rcc = UART1_RX_DMA_RCC, \
.request = UART1_RX_DMA_REQUEST, \
.channel = UART1_RX_DMA_CHANNEL, \
}
#endif /* UART1_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_RX_DMA */
#endif /* BSP_UART1_RX_USING_DMA */
#if defined(BSP_UART1_TX_USING_DMA)
#if defined(UART1_TX_DMA)
#ifndef UART1_DMA_TX_CONFIG
#define UART1_DMA_TX_CONFIG \
{ \
.DMAy = UART1_TX_DMA, \
.DMAChx = UART1_TX_DMA_CHType, \
.dma_irq = UART1_TX_DMA_IRQ, \
.dma_rcc = UART1_TX_DMA_RCC, \
.request = UART1_TX_DMA_REQUEST, \
.channel = UART1_TX_DMA_CHANNEL, \
}
#endif /* UART1_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART1_TX_DMA */
#endif /* BSP_UART1_TX_USING_DMA */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.Instance = USART2, \
.irq_type = USART2_IRQn, \
.periph = RCC_APB1_PERIPHEN_USART2, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_UART2_RX_USING_DMA)
#if defined(UART2_RX_DMA)
#ifndef UART2_DMA_RX_CONFIG
#define UART2_DMA_RX_CONFIG \
{ \
.DMAy = UART2_RX_DMA, \
.DMAChx = UART2_RX_DMA_CHType, \
.dma_irq = UART2_RX_DMA_IRQ, \
.dma_rcc = UART2_RX_DMA_RCC, \
.request = UART2_RX_DMA_REQUEST, \
.channel = UART2_RX_DMA_CHANNEL, \
}
#endif /* UART2_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_RX_DMA */
#endif /* BSP_UART2_RX_USING_DMA */
#if defined(BSP_UART2_TX_USING_DMA)
#if defined(UART2_TX_DMA)
#ifndef UART2_DMA_TX_CONFIG
#define UART2_DMA_TX_CONFIG \
{ \
.DMAy = UART2_TX_DMA, \
.DMAChx = UART2_TX_DMA_CHType, \
.dma_irq = UART2_TX_DMA_IRQ, \
.dma_rcc = UART2_TX_DMA_RCC, \
.request = UART2_TX_DMA_REQUEST, \
.channel = UART2_TX_DMA_CHANNEL, \
}
#endif /* UART2_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART2_TX_DMA */
#endif /* BSP_UART2_TX_USING_DMA */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.Instance = USART3, \
.irq_type = USART3_IRQn, \
.periph = RCC_APB1_PERIPHEN_USART3, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_UART3_RX_USING_DMA)
#if defined(UART3_RX_DMA)
#ifndef UART3_DMA_RX_CONFIG
#define UART3_DMA_RX_CONFIG \
{ \
.DMAy = UART3_RX_DMA, \
.DMAChx = UART3_RX_DMA_CHType, \
.dma_irq = UART3_RX_DMA_IRQ, \
.dma_rcc = UART3_RX_DMA_RCC, \
.request = UART3_RX_DMA_REQUEST, \
.channel = UART3_RX_DMA_CHANNEL, \
}
#endif /* UART3_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_RX_DMA */
#endif /* BSP_UART3_RX_USING_DMA */
#if defined(BSP_UART3_TX_USING_DMA)
#if defined(UART3_TX_DMA)
#ifndef UART3_DMA_TX_CONFIG
#define UART3_DMA_TX_CONFIG \
{ \
.DMAy = UART3_TX_DMA, \
.DMAChx = UART3_TX_DMA_CHType, \
.dma_irq = UART3_TX_DMA_IRQ, \
.dma_rcc = UART3_TX_DMA_RCC, \
.request = UART3_TX_DMA_REQUEST, \
.channel = UART3_TX_DMA_CHANNEL, \
}
#endif /* UART3_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART3_TX_DMA */
#endif /* BSP_UART3_TX_USING_DMA */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.Instance = USART4, \
.irq_type = USART4_IRQn, \
.periph = RCC_APB2_PERIPHEN_USART4, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_UART4_RX_USING_DMA)
#if defined(UART4_RX_DMA)
#ifndef UART4_DMA_RX_CONFIG
#define UART4_DMA_RX_CONFIG \
{ \
.DMAy = UART4_RX_DMA, \
.DMAChx = UART4_RX_DMA_CHType, \
.dma_irq = UART4_RX_DMA_IRQ, \
.dma_rcc = UART4_RX_DMA_RCC, \
.request = UART4_RX_DMA_REQUEST, \
.channel = UART4_RX_DMA_CHANNEL, \
}
#endif /* UART4_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_RX_DMA */
#endif /* BSP_UART4_RX_USING_DMA */
#if defined(BSP_UART4_TX_USING_DMA)
#if defined(UART4_TX_DMA)
#ifndef UART4_DMA_TX_CONFIG
#define UART4_DMA_TX_CONFIG \
{ \
.DMAy = UART4_TX_DMA, \
.DMAChx = UART4_TX_DMA_CHType, \
.dma_irq = UART4_TX_DMA_IRQ, \
.dma_rcc = UART4_TX_DMA_RCC, \
.request = UART4_TX_DMA_REQUEST, \
.channel = UART4_TX_DMA_CHANNEL, \
}
#endif /* UART4_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART4_TX_DMA */
#endif /* BSP_UART4_TX_USING_DMA */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.Instance = UART5, \
.irq_type = UART5_IRQn, \
.periph = RCC_APB1_PERIPHEN_UART5, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_UART5_RX_USING_DMA)
#if defined(UART5_RX_DMA)
#ifndef UART5_DMA_RX_CONFIG
#define UART5_DMA_RX_CONFIG \
{ \
.DMAy = UART5_RX_DMA, \
.DMAChx = UART5_RX_DMA_CHType, \
.dma_irq = UART5_RX_DMA_IRQ, \
.dma_rcc = UART5_RX_DMA_RCC, \
.request = UART5_RX_DMA_REQUEST, \
.channel = UART5_RX_DMA_CHANNEL, \
}
#endif /* UART5_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_RX_DMA */
#endif /* BSP_UART5_RX_USING_DMA */
#if defined(BSP_UART5_TX_USING_DMA)
#if defined(UART5_TX_DMA)
#ifndef UART5_DMA_TX_CONFIG
#define UART5_DMA_TX_CONFIG \
{ \
.DMAy = UART5_TX_DMA, \
.DMAChx = UART5_TX_DMA_CHType, \
.dma_irq = UART5_TX_DMA_IRQ, \
.dma_rcc = UART5_TX_DMA_RCC, \
.request = UART5_TX_DMA_REQUEST, \
.channel = UART5_TX_DMA_CHANNEL, \
}
#endif /* UART5_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART5_TX_DMA */
#endif /* BSP_UART5_TX_USING_DMA */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.Instance = UART6, \
.irq_type = UART6_IRQn, \
.periph = RCC_APB2_PERIPHEN_UART6, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_UART6_RX_USING_DMA)
#if defined(UART6_RX_DMA)
#ifndef UART6_DMA_RX_CONFIG
#define UART6_DMA_RX_CONFIG \
{ \
.DMAy = UART6_RX_DMA, \
.DMAChx = UART6_RX_DMA_CHType, \
.dma_irq = UART6_RX_DMA_IRQ, \
.dma_rcc = UART6_RX_DMA_RCC, \
.request = UART6_RX_DMA_REQUEST, \
.channel = UART6_RX_DMA_CHANNEL, \
}
#endif /* UART6_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_RX_DMA */
#endif /* BSP_UART6_RX_USING_DMA */
#if defined(BSP_UART6_TX_USING_DMA)
#if defined(UART6_TX_DMA)
#ifndef UART6_DMA_TX_CONFIG
#define UART6_DMA_TX_CONFIG \
{ \
.DMAy = UART6_TX_DMA, \
.DMAChx = UART6_TX_DMA_CHType, \
.dma_irq = UART6_TX_DMA_IRQ, \
.dma_rcc = UART6_TX_DMA_RCC, \
.request = UART6_TX_DMA_REQUEST, \
.channel = UART6_TX_DMA_CHANNEL, \
}
#endif /* UART6_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART6_TX_DMA */
#endif /* BSP_UART6_TX_USING_DMA */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.Instance = UART7, \
.irq_type = UART7_IRQn, \
.periph = RCC_APB2_PERIPHEN_UART7, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_UART7_RX_USING_DMA)
#if defined(UART7_RX_DMA)
#ifndef UART7_DMA_RX_CONFIG
#define UART7_DMA_RX_CONFIG \
{ \
.DMAy = UART7_RX_DMA, \
.DMAChx = UART7_RX_DMA_CHType, \
.dma_irq = UART7_RX_DMA_IRQ, \
.dma_rcc = UART7_RX_DMA_RCC, \
.request = UART7_RX_DMA_REQUEST, \
.channel = UART7_RX_DMA_CHANNEL, \
}
#endif /* UART7_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_RX_DMA */
#endif /* BSP_UART7_RX_USING_DMA */
#if defined(BSP_UART7_TX_USING_DMA)
#if defined(UART7_TX_DMA)
#ifndef UART7_DMA_TX_CONFIG
#define UART7_DMA_TX_CONFIG \
{ \
.DMAy = UART7_TX_DMA, \
.DMAChx = UART7_TX_DMA_CHType, \
.dma_irq = UART7_TX_DMA_IRQ, \
.dma_rcc = UART7_TX_DMA_RCC, \
.request = UART7_TX_DMA_REQUEST, \
.channel = UART7_TX_DMA_CHANNEL, \
}
#endif /* UART7_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART7_TX_DMA */
#endif /* BSP_UART7_TX_USING_DMA */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.Instance = UART8, \
.irq_type = UART8_IRQn, \
.periph = RCC_APB1_PERIPHEN_UART8, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_UART8_RX_USING_DMA)
#if defined(UART8_RX_DMA)
#ifndef UART8_DMA_RX_CONFIG
#define UART8_DMA_RX_CONFIG \
{ \
.DMAy = UART8_RX_DMA, \
.DMAChx = UART8_RX_DMA_CHType, \
.dma_irq = UART8_RX_DMA_IRQ, \
.dma_rcc = UART8_RX_DMA_RCC, \
.request = UART8_RX_DMA_REQUEST, \
.channel = UART8_RX_DMA_CHANNEL, \
}
#endif /* UART8_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_RX_DMA */
#endif /* BSP_UART8_RX_USING_DMA */
#if defined(BSP_UART8_TX_USING_DMA)
#if defined(UART8_TX_DMA)
#ifndef UART8_DMA_TX_CONFIG
#define UART8_DMA_TX_CONFIG \
{ \
.DMAy = UART8_TX_DMA, \
.DMAChx = UART8_TX_DMA_CHType, \
.dma_irq = UART8_TX_DMA_IRQ, \
.dma_rcc = UART8_TX_DMA_RCC, \
.request = UART8_TX_DMA_REQUEST, \
.channel = UART8_TX_DMA_CHANNEL, \
}
#endif /* UART8_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART8_TX_DMA */
#endif /* BSP_UART8_TX_USING_DMA */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.Instance = USART9, \
.irq_type = USART9_IRQn, \
.periph = RCC_APB2_PERIPHEN_USART9, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#if defined(BSP_UART9_RX_USING_DMA)
#if defined(UART9_RX_DMA)
#ifndef UART9_DMA_RX_CONFIG
#define UART9_DMA_RX_CONFIG \
{ \
.DMAy = UART9_RX_DMA, \
.DMAChx = UART9_RX_DMA_CHType, \
.dma_irq = UART9_RX_DMA_IRQ, \
.dma_rcc = UART9_RX_DMA_RCC, \
.request = UART9_RX_DMA_REQUEST, \
.channel = UART9_RX_DMA_CHANNEL, \
}
#endif /* UART9_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART9_RX_DMA */
#endif /* BSP_UART9_RX_USING_DMA */
#if defined(BSP_UART9_TX_USING_DMA)
#if defined(UART9_TX_DMA)
#ifndef UART9_DMA_TX_CONFIG
#define UART9_DMA_TX_CONFIG \
{ \
.DMAy = UART9_TX_DMA, \
.DMAChx = UART9_TX_DMA_CHType, \
.dma_irq = UART9_TX_DMA_IRQ, \
.dma_rcc = UART9_TX_DMA_RCC, \
.request = UART9_TX_DMA_REQUEST, \
.channel = UART9_TX_DMA_CHANNEL, \
}
#endif /* UART9_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART9_TX_DMA */
#endif /* BSP_UART9_TX_USING_DMA */
#if defined(BSP_USING_UART10)
#ifndef UART10_CONFIG
#define UART10_CONFIG \
{ \
.name = "uart10", \
.Instance = URT10, \
.irq_type = UART10_IRQn, \
.periph = RCC_APB2_PERIPHEN_UART10, \
.EnablePeriphClk = RCC_EnableAPB2PeriphClk, \
}
#endif /* UART10_CONFIG */
#endif /* BSP_USING_UART10 */
#if defined(BSP_UART10_RX_USING_DMA)
#if defined(UART10_RX_DMA)
#ifndef UART10_DMA_RX_CONFIG
#define UART10_DMA_RX_CONFIG \
{ \
.DMAy = UART10_RX_DMA, \
.DMAChx = UART10_RX_DMA_CHType, \
.dma_irq = UART10_RX_DMA_IRQ, \
.dma_rcc = UART10_RX_DMA_RCC, \
.request = UART10_RX_DMA_REQUEST, \
.channel = UART10_RX_DMA_CHANNEL, \
}
#endif /* UART10_DMA_RX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART10_RX_DMA */
#endif /* BSP_UART10_RX_USING_DMA */
#if defined(BSP_UART10_TX_USING_DMA)
#if defined(UART10_TX_DMA)
#ifndef UART10_DMA_TX_CONFIG
#define UART10_DMA_TX_CONFIG \
{ \
.DMAy = UART10_TX_DMA, \
.DMAChx = UART10_TX_DMA_CHType, \
.dma_irq = UART10_TX_DMA_IRQ, \
.dma_rcc = UART10_TX_DMA_RCC, \
.request = UART10_TX_DMA_REQUEST, \
.channel = UART10_TX_DMA_CHANNEL, \
}
#endif /* UART10_DMA_TX_CONFIG */
#else
#error "The DMA resource is not available."
#endif /* UART10_TX_DMA */
#endif /* BSP_UART10_TX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /* __UART_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/dma_config.h
-710
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/spi_config.h
-310
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@@ -1,310 +0,0 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.SPIx = SPI1, \
.bus_name = "spi1", \
.irq_type = SPI1_IRQn, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.dma_irq = SPI1_TX_DMA_IRQ, \
.HsInterface = SPI1_TX_DMA_HANDSHAK, \
.dma_rcc = SPI1_TX_DMA_DMA_RCC, \
.dma_channel = SPI1_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI1_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI1_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.dma_irq = SPI1_RX_DMA_IRQ, \
.HsInterface = SPI1_RX_DMA_HANDSHAK, \
.dma_rcc = SPI1_RX_DMA_DMA_RCC, \
.dma_channel = SPI1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.SPIx = SPI2, \
.bus_name = "spi2", \
.irq_type = SPI2_IRQn, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.dma_irq = SPI2_TX_DMA_IRQ, \
.HsInterface = SPI2_TX_DMA_HANDSHAK, \
.dma_rcc = SPI2_TX_DMA_DMA_RCC, \
.dma_channel = SPI2_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI2_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI2_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.dma_irq = SPI2_RX_DMA_IRQ, \
.HsInterface = SPI2_RX_DMA_HANDSHAK, \
.dma_rcc = SPI2_RX_DMA_DMA_RCC, \
.dma_channel = SPI2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.SPIx = SPI3, \
.bus_name = "spi3", \
.irq_type = SPI3_IRQn, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.dma_irq = SPI3_TX_DMA_IRQ, \
.HsInterface = SPI3_TX_DMA_HANDSHAK, \
.dma_rcc = SPI3_TX_DMA_DMA_RCC, \
.dma_channel = SPI3_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI3_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI3_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.dma_irq = SPI3_RX_DMA_IRQ, \
.HsInterface = SPI3_RX_DMA_HANDSHAK, \
.dma_rcc = SPI3_RX_DMA_DMA_RCC, \
.dma_channel = SPI3_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI3_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI3_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.SPIx = SPI4, \
.bus_name = "spi4", \
.irq_type = SPI4_IRQn, \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.Instance = SPI4_TX_DMA_INSTANCE, \
.dma_irq = SPI4_TX_DMA_IRQ, \
.HsInterface = SPI4_TX_DMA_HANDSHAK, \
.dma_rcc = SPI4_TX_DMA_DMA_RCC, \
.dma_channel = SPI4_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI4_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI4_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.Instance = SPI4_RX_DMA_INSTANCE, \
.dma_irq = SPI4_RX_DMA_IRQ, \
.HsInterface = SPI4_RX_DMA_HANDSHAK, \
.dma_rcc = SPI4_RX_DMA_DMA_RCC, \
.dma_channel = SPI4_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI4_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI4_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.SPIx = SPI5, \
.bus_name = "spi5", \
.irq_type = SPI5_IRQn, \
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.Instance = SPI5_TX_DMA_INSTANCE, \
.dma_irq = SPI5_TX_DMA_IRQ, \
.HsInterface = SPI5_TX_DMA_HANDSHAK, \
.dma_rcc = SPI5_TX_DMA_DMA_RCC, \
.dma_channel = SPI5_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI5_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI5_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI5_TX_DMA_CONFIG */
#endif /* BSP_SPI5_TX_USING_DMA */
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.Instance = SPI5_RX_DMA_INSTANCE, \
.dma_irq = SPI5_RX_DMA_IRQ, \
.HsInterface = SPI5_RX_DMA_HANDSHAK, \
.dma_rcc = SPI5_RX_DMA_DMA_RCC, \
.dma_channel = SPI5_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI5_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI5_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI5_RX_DMA_CONFIG */
#endif /* BSP_SPI5_RX_USING_DMA */
#ifdef BSP_USING_SPI6
#ifndef SPI6_BUS_CONFIG
#define SPI6_BUS_CONFIG \
{ \
.SPIx = SPI6, \
.bus_name = "spi6", \
.irq_type = SPI6_IRQn, \
}
#endif /* SPI6_BUS_CONFIG */
#endif /* BSP_USING_SPI6 */
#ifdef BSP_SPI6_TX_USING_DMA
#ifndef SPI6_TX_DMA_CONFIG
#define SPI6_TX_DMA_CONFIG \
{ \
.Instance = SPI6_TX_DMA_INSTANCE, \
.dma_irq = SPI6_TX_DMA_IRQ, \
.HsInterface = SPI6_TX_DMA_HANDSHAK, \
.dma_rcc = SPI6_TX_DMA_DMA_RCC, \
.dma_channel = SPI6_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI6_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI6_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI6_TX_DMA_CONFIG */
#endif /* BSP_SPI6_TX_USING_DMA */
#ifdef BSP_SPI6_RX_USING_DMA
#ifndef SPI6_RX_DMA_CONFIG
#define SPI6_RX_DMA_CONFIG \
{ \
.Instance = SPI6_RX_DMA_INSTANCE, \
.dma_irq = SPI6_RX_DMA_IRQ, \
.HsInterface = SPI6_RX_DMA_HANDSHAK, \
.dma_rcc = SPI6_RX_DMA_DMA_RCC, \
.dma_channel = SPI6_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI6_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI6_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI6_RX_DMA_CONFIG */
#endif /* BSP_SPI6_RX_USING_DMA */
#ifdef BSP_USING_SPI7
#ifndef SPI7_BUS_CONFIG
#define SPI7_BUS_CONFIG \
{ \
.SPIx = SPI7, \
.bus_name = "spi7", \
.irq_type = SPI7_IRQn, \
}
#endif /* SPI7_BUS_CONFIG */
#endif /* BSP_USING_SPI7 */
#ifdef BSP_SPI7_TX_USING_DMA
#ifndef SPI7_TX_DMA_CONFIG
#define SPI7_TX_DMA_CONFIG \
{ \
.Instance = SPI7_TX_DMA_INSTANCE, \
.dma_irq = SPI7_TX_DMA_IRQ, \
.HsInterface = SPI7_TX_DMA_HANDSHAK, \
.dma_rcc = SPI7_TX_DMA_DMA_RCC, \
.dma_channel = SPI7_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI7_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI7_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI7_TX_DMA_CONFIG */
#endif /* BSP_SPI7_TX_USING_DMA */
#ifdef BSP_SPI7_RX_USING_DMA
#ifndef SPI7_RX_DMA_CONFIG
#define SPI7_RX_DMA_CONFIG \
{ \
.Instance = SPI7_RX_DMA_INSTANCE, \
.dma_irq = SPI7_RX_DMA_IRQ, \
.HsInterface = SPI7_RX_DMA_HANDSHAK, \
.dma_rcc = SPI7_RX_DMA_DMA_RCC, \
.dma_channel = SPI7_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI7_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI7_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI7_RX_DMA_CONFIG */
#endif /* BSP_SPI7_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/uart_config.h
-832
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/adc_config.h → bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/adc_config.h
+54 -54
View File
@@ -19,72 +19,72 @@ extern "C" {
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.ADCx = ADC1, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
#define ADC1_CONFIG \
{ \
.ADCx = ADC1, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC1SYS | RCC_AHB1_PERIPHEN_M7_ADC1BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk1, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef BSP_USING_ADC2
#ifndef ADC2_CONFIG
#define ADC2_CONFIG \
{ \
.ADCx = ADC2, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
#define ADC2_CONFIG \
{ \
.ADCx = ADC2, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC2SYS | RCC_AHB1_PERIPHEN_M7_ADC2BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
}
#endif /* ADC2_CONFIG */
#endif /* BSP_USING_ADC2 */
#ifdef BSP_USING_ADC3
#ifndef ADC3_CONFIG
#define ADC3_CONFIG \
{ \
.ADCx = ADC3, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
#define ADC3_CONFIG \
{ \
.ADCx = ADC3, \
.AHB_periph = (RCC_AHB1_PERIPHEN_M7_ADC3SYS | RCC_AHB1_PERIPHEN_M7_ADC3BUS), \
.EnablePeriphClk = RCC_EnableAHB1PeriphClk4, \
.ADC_ClkMode = ADC_CTRL3_CKMOD_AHB, \
.Pll_CLK_source = RCC_ADCPLLCLK_SRC_PLL1B, \
.RCC_ADCPrescaler = RCC_AHB1DIV2_ADC1SYSDIV_DIV15, \
.Init.WorkMode = ADC_WORKMODE_INDEPENDENT, \
.Init.MultiChEn = DISABLE, \
.Init.ContinueConvEn = DISABLE, \
.Init.ExtTrigSelect = ADC_EXT_TRIG_REG_CONV_SOFTWARE, \
.Init.DataTransferMode = ADC_REG_DR_TRANSFER, \
.Init.DatAlign = ADC_DAT_ALIGN_R, \
.Init.ChsNumber = 1U, \
.Init.Resolution = ADC_DATA_RES_12BIT, \
.Rank = 1U, \
.ADC_SampleTime = ADC_SAMP_TIME_CYCLES_24, \
}
#endif /* ADC3_CONFIG */
#endif /* BSP_USING_ADC3 */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/can_config.h
+126
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/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-22 lin.qi first version
*/
#ifndef __CAN_CONFIG_H__
#define __CAN_CONFIG_H__
#include <rtthread.h>
#include "n32h7xx_fdcan.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*\*\name n32_fdcan_config.
*\*\brief FDCAN instance configuration structure.
*\*\note Clock and GPIO initialization are handled by CubeMX-generated code
*\*\ in n32h7xx_cfg.c (from Cube.ntfx). NVIC interrupt vector numbers
*\*\ are hardcoded in drv_fdcan.c per instance.
*/
struct n32_fdcan_config
{
const char *name; /**< device name */
FDCAN_Module *Instance; /**< FDCAN peripheral base address */
};
/*
* Hardware connection pairs on N32H760ZIL7-STB:
* FDCAN1 <-> FDCAN2
* FDCAN3 <-> FDCAN4
* FDCAN5 <-> FDCAN6
* FDCAN7 <-> FDCAN8
*/
#if defined(BSP_USING_FDCAN1)
#ifndef FDCAN1_CONFIG
#define FDCAN1_CONFIG \
{ \
.name = "fdcan1", \
.Instance = FDCAN1, \
}
#endif
#endif /* BSP_USING_FDCAN1 */
#if defined(BSP_USING_FDCAN2)
#ifndef FDCAN2_CONFIG
#define FDCAN2_CONFIG \
{ \
.name = "fdcan2", \
.Instance = FDCAN2, \
}
#endif
#endif /* BSP_USING_FDCAN2 */
#if defined(BSP_USING_FDCAN3)
#ifndef FDCAN3_CONFIG
#define FDCAN3_CONFIG \
{ \
.name = "fdcan3", \
.Instance = FDCAN3, \
}
#endif
#endif /* BSP_USING_FDCAN3 */
#if defined(BSP_USING_FDCAN4)
#ifndef FDCAN4_CONFIG
#define FDCAN4_CONFIG \
{ \
.name = "fdcan4", \
.Instance = FDCAN4, \
}
#endif
#endif /* BSP_USING_FDCAN4 */
#if defined(BSP_USING_FDCAN5)
#ifndef FDCAN5_CONFIG
#define FDCAN5_CONFIG \
{ \
.name = "fdcan5", \
.Instance = FDCAN5, \
}
#endif
#endif /* BSP_USING_FDCAN5 */
#if defined(BSP_USING_FDCAN6)
#ifndef FDCAN6_CONFIG
#define FDCAN6_CONFIG \
{ \
.name = "fdcan6", \
.Instance = FDCAN6, \
}
#endif
#endif /* BSP_USING_FDCAN6 */
#if defined(BSP_USING_FDCAN7)
#ifndef FDCAN7_CONFIG
#define FDCAN7_CONFIG \
{ \
.name = "fdcan7", \
.Instance = FDCAN7, \
}
#endif
#endif /* BSP_USING_FDCAN7 */
#if defined(BSP_USING_FDCAN8)
#ifndef FDCAN8_CONFIG
#define FDCAN8_CONFIG \
{ \
.name = "fdcan8", \
.Instance = FDCAN8, \
}
#endif
#endif /* BSP_USING_FDCAN8 */
#ifdef __cplusplus
}
#endif
#endif /* __CAN_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dac_config.h
+70
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@@ -0,0 +1,70 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-09 li.mengmeng first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_DAC1
#ifndef DAC1_CONFIG
#define DAC1_CONFIG \
{ \
.DACx = DAC1, \
.DAC_Module = DAC12, \
.periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \
.DAC_clk_pres = 150, \
.Init.DAC_Trigger = DAC_Trigger_Software, \
.Init.DAC_Trigger2 = DAC_Trigger2_Software, \
.Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \
.Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \
.Init.DAC_OutputBuffer = DISABLE, \
.Init.DAC_TriggerEnable = ENABLE, \
.Init.DAC_ConnectOnChipPeripheral = DISABLE, \
.Init.DAC_ConnectExternalPin = ENABLE, \
.Init.DAC_DMADoubleDataMode = DISABLE, \
.Init.DAC_SignedFormat = DISABLE, \
}
#endif /* DAC1_CONFIG */
#endif /* BSP_USING_DAC1 */
#ifdef BSP_USING_DAC2
#ifndef DAC2_CONFIG
#define DAC2_CONFIG \
{ \
.DACx = DAC2, \
.DAC_Module = DAC12, \
.periph_clk = RCC_APB1_PERIPHEN_M7_DAC12, \
.EnablePeriphClk = RCC_EnableAPB1PeriphClk2, \
.DAC_clk_pres = 150, \
.Init.DAC_Trigger = DAC_Trigger_Software, \
.Init.DAC_Trigger2 = DAC_Trigger2_Software, \
.Init.DAC_WaveGeneration = DAC_WaveGeneration_None, \
.Init.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0, \
.Init.DAC_OutputBuffer = DISABLE, \
.Init.DAC_TriggerEnable = ENABLE, \
.Init.DAC_ConnectOnChipPeripheral = DISABLE, \
.Init.DAC_ConnectExternalPin = ENABLE, \
.Init.DAC_DMADoubleDataMode = DISABLE, \
.Init.DAC_SignedFormat = DISABLE, \
}
#endif /* DAC2_CONFIG */
#endif /* BSP_USING_DAC2 */
#ifdef __cplusplus
}
#endif
#endif /* __DAC_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/dma_config.h
+709
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7/i2c_hard_config.h → bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/i2c_hard_config.h
+179 -187
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/lptim_config.h
+89
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/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#ifndef __LPTIM_CONFIG_H__
#define __LPTIM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef LPTIM_DEV_INFO_CONFIG
#define LPTIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 1000000, \
.minfreq = 3000, \
.maxcnt = 0xFFFF, \
.cntmode = CLOCK_TIMER_CNTMODE_UP, \
}
#endif /* LPTIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_LPTIM1
#ifndef LPTIM1_CONFIG
#define LPTIM1_CONFIG \
{ \
.timer = LPTIM1, \
.tim_irqn = LPTIM1_WKUP_IRQn, \
.name = "lptim1", \
}
#endif /* LPTIM1_CONFIG */
#endif /* BSP_USING_LPTIM1 */
#ifdef BSP_USING_LPTIM2
#ifndef LPTIM2_CONFIG
#define LPTIM2_CONFIG \
{ \
.timer = LPTIM2, \
.tim_irqn = LPTIM2_WKUP_IRQn, \
.name = "lptim2", \
}
#endif /* LPTIM2_CONFIG */
#endif /* BSP_USING_LPTIM2 */
#ifdef BSP_USING_LPTIM3
#ifndef LPTIM3_CONFIG
#define LPTIM3_CONFIG \
{ \
.timer = LPTIM3, \
.tim_irqn = LPTIM3_WKUP_IRQn, \
.name = "lptim3", \
}
#endif /* LPTIM3_CONFIG */
#endif /* BSP_USING_LPTIM3 */
#ifdef BSP_USING_LPTIM4
#ifndef LPTIM4_CONFIG
#define LPTIM4_CONFIG \
{ \
.timer = LPTIM4, \
.tim_irqn = LPTIM4_WKUP_IRQn, \
.name = "lptim4", \
}
#endif /* LPTIM4_CONFIG */
#endif /* BSP_USING_LPTIM4 */
#ifdef BSP_USING_LPTIM5
#ifndef LPTIM5_CONFIG
#define LPTIM5_CONFIG \
{ \
.timer = LPTIM5, \
.tim_irqn = LPTIM5_WKUP_IRQn, \
.name = "lptim5", \
}
#endif /* LPTIM5_CONFIG */
#endif /* BSP_USING_LPTIM5 */
#ifdef __cplusplus
}
#endif
#endif /* __LPTIM_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pulse_encoder_config.h
+178
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@@ -0,0 +1,178 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-07-06 ox-horse first version
*/
#ifndef __PULSE_ENCODER_CONFIG_H__
#define __PULSE_ENCODER_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PULSE_ENCODER1
#ifndef PULSE_ENCODER1_CONFIG
#define PULSE_ENCODER1_CONFIG \
{ \
.timer = ATIM1, \
.tim_irqn = ATIM1_UP_IRQn, \
.name = "pulse1", \
}
#endif /* PULSE_ENCODER1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER1 */
#ifdef BSP_USING_PULSE_ENCODER2
#ifndef PULSE_ENCODER2_CONFIG
#define PULSE_ENCODER2_CONFIG \
{ \
.timer = ATIM2, \
.tim_irqn = ATIM2_UP_IRQn, \
.name = "pulse2", \
}
#endif /* PULSE_ENCODER2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER2 */
#ifdef BSP_USING_PULSE_ENCODER3
#ifndef PULSE_ENCODER3_CONFIG
#define PULSE_ENCODER3_CONFIG \
{ \
.timer = ATIM3, \
.tim_irqn = ATIM3_UP_IRQn, \
.name = "pulse3", \
}
#endif /* PULSE_ENCODER3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER3 */
#ifdef BSP_USING_PULSE_ENCODER4
#ifndef PULSE_ENCODER4_CONFIG
#define PULSE_ENCODER4_CONFIG \
{ \
.timer = ATIM4, \
.tim_irqn = ATIM4_UP_IRQn, \
.name = "pulse4", \
}
#endif /* PULSE_ENCODER4_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER4 */
#ifdef BSP_USING_PULSE_ENCODER5
#ifndef PULSE_ENCODER5_CONFIG
#define PULSE_ENCODER5_CONFIG \
{ \
.timer = GTIMA1, \
.tim_irqn = GTIMA1_IRQn, \
.name = "pulse5", \
}
#endif /* PULSE_ENCODER5_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER5 */
#ifdef BSP_USING_PULSE_ENCODER6
#ifndef PULSE_ENCODER6_CONFIG
#define PULSE_ENCODER6_CONFIG \
{ \
.timer = GTIMA2, \
.tim_irqn = GTIMA2_IRQn, \
.name = "pulse6", \
}
#endif /* PULSE_ENCODER6_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER6 */
#ifdef BSP_USING_PULSE_ENCODER7
#ifndef PULSE_ENCODER7_CONFIG
#define PULSE_ENCODER7_CONFIG \
{ \
.timer = GTIMA3, \
.tim_irqn = GTIMA3_IRQn, \
.name = "pulse7", \
}
#endif /* PULSE_ENCODER7_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER7 */
#ifdef BSP_USING_PULSE_ENCODER8
#ifndef PULSE_ENCODER8_CONFIG
#define PULSE_ENCODER8_CONFIG \
{ \
.timer = GTIMA4, \
.tim_irqn = GTIMA4_IRQn, \
.name = "pulse8", \
}
#endif /* PULSE_ENCODER8_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER8 */
#ifdef BSP_USING_PULSE_ENCODER9
#ifndef PULSE_ENCODER9_CONFIG
#define PULSE_ENCODER9_CONFIG \
{ \
.timer = GTIMA5, \
.tim_irqn = GTIMA5_IRQn, \
.name = "pulse9", \
}
#endif /* PULSE_ENCODER9_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER9 */
#ifdef BSP_USING_PULSE_ENCODER10
#ifndef PULSE_ENCODER10_CONFIG
#define PULSE_ENCODER10_CONFIG \
{ \
.timer = GTIMA6, \
.tim_irqn = GTIMA6_IRQn, \
.name = "pulse10", \
}
#endif /* PULSE_ENCODER10_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER10 */
#ifdef BSP_USING_PULSE_ENCODER11
#ifndef PULSE_ENCODER11_CONFIG
#define PULSE_ENCODER11_CONFIG \
{ \
.timer = GTIMA7, \
.tim_irqn = GTIMA7_IRQn, \
.name = "pulse11", \
}
#endif /* PULSE_ENCODER11_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER11 */
#ifdef BSP_USING_PULSE_ENCODER12
#ifndef PULSE_ENCODER12_CONFIG
#define PULSE_ENCODER12_CONFIG \
{ \
.timer = GTIMB1, \
.tim_irqn = GTIMB1_IRQn, \
.name = "pulse12", \
}
#endif /* PULSE_ENCODER12_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER12 */
#ifdef BSP_USING_PULSE_ENCODER13
#ifndef PULSE_ENCODER13_CONFIG
#define PULSE_ENCODER13_CONFIG \
{ \
.timer = GTIMB2, \
.tim_irqn = GTIMB2_IRQn, \
.name = "pulse13", \
}
#endif /* PULSE_ENCODER13_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER13 */
#ifdef BSP_USING_PULSE_ENCODER14
#ifndef PULSE_ENCODER14_CONFIG
#define PULSE_ENCODER14_CONFIG \
{ \
.timer = GTIMB3, \
.tim_irqn = GTIMB3_IRQn, \
.name = "pulse14", \
}
#endif /* PULSE_ENCODER14_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER14 */
#ifdef __cplusplus
}
#endif
#endif /* __PULSE_ENCODER_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/pwm_config.h
+178
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@@ -0,0 +1,178 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM1
#ifndef PWM1_CONFIG
#define PWM1_CONFIG \
{ \
.timer = ATIM1, \
.name = "pwm1", \
.channel = 0 \
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
{ \
.timer = ATIM2, \
.name = "pwm2", \
.channel = 0 \
}
#endif /* PWM2_CONFIG */
#endif /* BSP_USING_PWM2 */
#ifdef BSP_USING_PWM3
#ifndef PWM3_CONFIG
#define PWM3_CONFIG \
{ \
.timer = ATIM3, \
.name = "pwm3", \
.channel = 0 \
}
#endif /* PWM3_CONFIG */
#endif /* BSP_USING_PWM3 */
#ifdef BSP_USING_PWM4
#ifndef PWM4_CONFIG
#define PWM4_CONFIG \
{ \
.timer = ATIM4, \
.name = "pwm4", \
.channel = 0 \
}
#endif /* PWM4_CONFIG */
#endif /* BSP_USING_PWM4 */
#ifdef BSP_USING_PWM5
#ifndef PWM5_CONFIG
#define PWM5_CONFIG \
{ \
.timer = GTIMA1, \
.name = "pwm5", \
.channel = 0 \
}
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef BSP_USING_PWM6
#ifndef PWM6_CONFIG
#define PWM6_CONFIG \
{ \
.timer = GTIMA2, \
.name = "pwm6", \
.channel = 0 \
}
#endif /* PWM6_CONFIG */
#endif /* BSP_USING_PWM6 */
#ifdef BSP_USING_PWM7
#ifndef PWM7_CONFIG
#define PWM7_CONFIG \
{ \
.timer = GTIMA3, \
.name = "pwm7", \
.channel = 0 \
}
#endif /* PWM7_CONFIG */
#endif /* BSP_USING_PWM7 */
#ifdef BSP_USING_PWM8
#ifndef PWM8_CONFIG
#define PWM8_CONFIG \
{ \
.timer = GTIMA4, \
.name = "pwm8", \
.channel = 0 \
}
#endif /* PWM8_CONFIG */
#endif /* BSP_USING_PWM8 */
#ifdef BSP_USING_PWM9
#ifndef PWM9_CONFIG
#define PWM9_CONFIG \
{ \
.timer = GTIMA5, \
.name = "pwm9", \
.channel = 0 \
}
#endif /* PWM9_CONFIG */
#endif /* BSP_USING_PWM9 */
#ifdef BSP_USING_PWM10
#ifndef PWM10_CONFIG
#define PWM10_CONFIG \
{ \
.timer = GTIMA6, \
.name = "pwm10", \
.channel = 0 \
}
#endif /* PWM10_CONFIG */
#endif /* BSP_USING_PWM10 */
#ifdef BSP_USING_PWM11
#ifndef PWM11_CONFIG
#define PWM11_CONFIG \
{ \
.timer = GTIMA7, \
.name = "pwm11", \
.channel = 0 \
}
#endif /* PWM11_CONFIG */
#endif /* BSP_USING_PWM11 */
#ifdef BSP_USING_PWM12
#ifndef PWM12_CONFIG
#define PWM12_CONFIG \
{ \
.timer = GTIMB1, \
.name = "pwm12", \
.channel = 0 \
}
#endif /* PWM12_CONFIG */
#endif /* BSP_USING_PWM12 */
#ifdef BSP_USING_PWM13
#ifndef PWM13_CONFIG
#define PWM13_CONFIG \
{ \
.timer = GTIMB2, \
.name = "pwm13", \
.channel = 0 \
}
#endif /* PWM13_CONFIG */
#endif /* BSP_USING_PWM13 */
#ifdef BSP_USING_PWM14
#ifndef PWM14_CONFIG
#define PWM14_CONFIG \
{ \
.timer = GTIMB3, \
.name = "pwm14", \
.channel = 0 \
}
#endif /* PWM14_CONFIG */
#endif /* BSP_USING_PWM14 */
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/spi_config.h
+297
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@@ -0,0 +1,297 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
*/
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.SPIx = SPI1, \
.bus_name = "spi1", \
.irq_type = SPI1_IRQn, \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \
{ \
.Instance = SPI1_TX_DMA_INSTANCE, \
.dma_irq = SPI1_TX_DMA_IRQ, \
.HsInterface = SPI1_TX_DMA_HANDSHAK, \
.dma_rcc = SPI1_TX_DMA_DMA_RCC, \
.dma_channel = SPI1_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI1_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI1_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \
{ \
.Instance = SPI1_RX_DMA_INSTANCE, \
.dma_irq = SPI1_RX_DMA_IRQ, \
.HsInterface = SPI1_RX_DMA_HANDSHAK, \
.dma_rcc = SPI1_RX_DMA_DMA_RCC, \
.dma_channel = SPI1_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI1_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI1_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.SPIx = SPI2, \
.bus_name = "spi2", \
.irq_type = SPI2_IRQn, \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_SPI2_TX_USING_DMA
#ifndef SPI2_TX_DMA_CONFIG
#define SPI2_TX_DMA_CONFIG \
{ \
.Instance = SPI2_TX_DMA_INSTANCE, \
.dma_irq = SPI2_TX_DMA_IRQ, \
.HsInterface = SPI2_TX_DMA_HANDSHAK, \
.dma_rcc = SPI2_TX_DMA_DMA_RCC, \
.dma_channel = SPI2_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI2_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI2_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI2_TX_DMA_CONFIG */
#endif /* BSP_SPI2_TX_USING_DMA */
#ifdef BSP_SPI2_RX_USING_DMA
#ifndef SPI2_RX_DMA_CONFIG
#define SPI2_RX_DMA_CONFIG \
{ \
.Instance = SPI2_RX_DMA_INSTANCE, \
.dma_irq = SPI2_RX_DMA_IRQ, \
.HsInterface = SPI2_RX_DMA_HANDSHAK, \
.dma_rcc = SPI2_RX_DMA_DMA_RCC, \
.dma_channel = SPI2_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI2_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI2_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI2_RX_DMA_CONFIG */
#endif /* BSP_SPI2_RX_USING_DMA */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.SPIx = SPI3, \
.bus_name = "spi3", \
.irq_type = SPI3_IRQn, \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef BSP_SPI3_TX_USING_DMA
#ifndef SPI3_TX_DMA_CONFIG
#define SPI3_TX_DMA_CONFIG \
{ \
.Instance = SPI3_TX_DMA_INSTANCE, \
.dma_irq = SPI3_TX_DMA_IRQ, \
.HsInterface = SPI3_TX_DMA_HANDSHAK, \
.dma_rcc = SPI3_TX_DMA_DMA_RCC, \
.dma_channel = SPI3_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI3_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI3_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI3_TX_DMA_CONFIG */
#endif /* BSP_SPI3_TX_USING_DMA */
#ifdef BSP_SPI3_RX_USING_DMA
#ifndef SPI3_RX_DMA_CONFIG
#define SPI3_RX_DMA_CONFIG \
{ \
.Instance = SPI3_RX_DMA_INSTANCE, \
.dma_irq = SPI3_RX_DMA_IRQ, \
.HsInterface = SPI3_RX_DMA_HANDSHAK, \
.dma_rcc = SPI3_RX_DMA_DMA_RCC, \
.dma_channel = SPI3_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI3_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI3_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI3_RX_DMA_CONFIG */
#endif /* BSP_SPI3_RX_USING_DMA */
#ifdef BSP_USING_SPI4
#ifndef SPI4_BUS_CONFIG
#define SPI4_BUS_CONFIG \
{ \
.SPIx = SPI4, \
.bus_name = "spi4", \
.irq_type = SPI4_IRQn, \
}
#endif /* SPI4_BUS_CONFIG */
#endif /* BSP_USING_SPI4 */
#ifdef BSP_SPI4_TX_USING_DMA
#ifndef SPI4_TX_DMA_CONFIG
#define SPI4_TX_DMA_CONFIG \
{ \
.Instance = SPI4_TX_DMA_INSTANCE, \
.dma_irq = SPI4_TX_DMA_IRQ, \
.HsInterface = SPI4_TX_DMA_HANDSHAK, \
.dma_rcc = SPI4_TX_DMA_DMA_RCC, \
.dma_channel = SPI4_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI4_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI4_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI4_TX_DMA_CONFIG */
#endif /* BSP_SPI4_TX_USING_DMA */
#ifdef BSP_SPI4_RX_USING_DMA
#ifndef SPI4_RX_DMA_CONFIG
#define SPI4_RX_DMA_CONFIG \
{ \
.Instance = SPI4_RX_DMA_INSTANCE, \
.dma_irq = SPI4_RX_DMA_IRQ, \
.HsInterface = SPI4_RX_DMA_HANDSHAK, \
.dma_rcc = SPI4_RX_DMA_DMA_RCC, \
.dma_channel = SPI4_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI4_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI4_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI4_RX_DMA_CONFIG */
#endif /* BSP_SPI4_RX_USING_DMA */
#ifdef BSP_USING_SPI5
#ifndef SPI5_BUS_CONFIG
#define SPI5_BUS_CONFIG \
{ \
.SPIx = SPI5, \
.bus_name = "spi5", \
.irq_type = SPI5_IRQn, \
}
#endif /* SPI5_BUS_CONFIG */
#endif /* BSP_USING_SPI5 */
#ifdef BSP_SPI5_TX_USING_DMA
#ifndef SPI5_TX_DMA_CONFIG
#define SPI5_TX_DMA_CONFIG \
{ \
.Instance = SPI5_TX_DMA_INSTANCE, \
.dma_irq = SPI5_TX_DMA_IRQ, \
.HsInterface = SPI5_TX_DMA_HANDSHAK, \
.dma_rcc = SPI5_TX_DMA_DMA_RCC, \
.dma_channel = SPI5_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI5_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI5_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI5_TX_DMA_CONFIG */
#endif /* BSP_SPI5_TX_USING_DMA */
#ifdef BSP_SPI5_RX_USING_DMA
#ifndef SPI5_RX_DMA_CONFIG
#define SPI5_RX_DMA_CONFIG \
{ \
.Instance = SPI5_RX_DMA_INSTANCE, \
.dma_irq = SPI5_RX_DMA_IRQ, \
.HsInterface = SPI5_RX_DMA_HANDSHAK, \
.dma_rcc = SPI5_RX_DMA_DMA_RCC, \
.dma_channel = SPI5_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI5_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI5_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI5_RX_DMA_CONFIG */
#endif /* BSP_SPI5_RX_USING_DMA */
#ifdef BSP_USING_SPI6
#ifndef SPI6_BUS_CONFIG
#define SPI6_BUS_CONFIG \
{ \
.SPIx = SPI6, \
.bus_name = "spi6", \
.irq_type = SPI6_IRQn, \
}
#endif /* SPI6_BUS_CONFIG */
#endif /* BSP_USING_SPI6 */
#ifdef BSP_SPI6_TX_USING_DMA
#ifndef SPI6_TX_DMA_CONFIG
#define SPI6_TX_DMA_CONFIG \
{ \
.Instance = SPI6_TX_DMA_INSTANCE, \
.dma_irq = SPI6_TX_DMA_IRQ, \
.HsInterface = SPI6_TX_DMA_HANDSHAK, \
.dma_rcc = SPI6_TX_DMA_DMA_RCC, \
.dma_channel = SPI6_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI6_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI6_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI6_TX_DMA_CONFIG */
#endif /* BSP_SPI6_TX_USING_DMA */
#ifdef BSP_SPI6_RX_USING_DMA
#ifndef SPI6_RX_DMA_CONFIG
#define SPI6_RX_DMA_CONFIG \
{ \
.Instance = SPI6_RX_DMA_INSTANCE, \
.dma_irq = SPI6_RX_DMA_IRQ, \
.HsInterface = SPI6_RX_DMA_HANDSHAK, \
.dma_rcc = SPI6_RX_DMA_DMA_RCC, \
.dma_channel = SPI6_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI6_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI6_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI6_RX_DMA_CONFIG */
#endif /* BSP_SPI6_RX_USING_DMA */
#ifdef BSP_USING_SPI7
#ifndef SPI7_BUS_CONFIG
#define SPI7_BUS_CONFIG \
{ \
.SPIx = SPI7, \
.bus_name = "spi7", \
.irq_type = SPI7_IRQn, \
}
#endif /* SPI7_BUS_CONFIG */
#endif /* BSP_USING_SPI7 */
#ifdef BSP_SPI7_TX_USING_DMA
#ifndef SPI7_TX_DMA_CONFIG
#define SPI7_TX_DMA_CONFIG \
{ \
.Instance = SPI7_TX_DMA_INSTANCE, \
.dma_irq = SPI7_TX_DMA_IRQ, \
.HsInterface = SPI7_TX_DMA_HANDSHAK, \
.dma_rcc = SPI7_TX_DMA_DMA_RCC, \
.dma_channel = SPI7_TX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI7_TX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI7_TX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI7_TX_DMA_CONFIG */
#endif /* BSP_SPI7_TX_USING_DMA */
#ifdef BSP_SPI7_RX_USING_DMA
#ifndef SPI7_RX_DMA_CONFIG
#define SPI7_RX_DMA_CONFIG \
{ \
.Instance = SPI7_RX_DMA_INSTANCE, \
.dma_irq = SPI7_RX_DMA_IRQ, \
.HsInterface = SPI7_RX_DMA_HANDSHAK, \
.dma_rcc = SPI7_RX_DMA_DMA_RCC, \
.dma_channel = SPI7_RX_DMA_DMA_CHANNEL, \
.dmamux_channel = SPI7_RX_DMA_DMAMUX_CHANNEL, \
.dmamux_request = SPI7_RX_DMA_DMAMUX_REQUEST, \
}
#endif /* SPI7_RX_DMA_CONFIG */
#endif /* BSP_SPI7_RX_USING_DMA */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/tim_config.h
+232
View File
@@ -0,0 +1,232 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-02-26 ox-horse first version
*/
#ifndef __TIM_CONFIG_H__
#define __TIM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 1000000, \
.minfreq = 3000, \
.maxcnt = 0xFFFF, \
.cntmode = CLOCK_TIMER_CNTMODE_UP, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_ATIM1
#ifndef ATIM1_CONFIG
#define ATIM1_CONFIG \
{ \
.timer = ATIM1, \
.tim_irqn = ATIM1_UP_IRQn, \
.name = "timer1", \
}
#endif /* ATIM1_CONFIG */
#endif /* BSP_USING_ATIM1 */
#ifdef BSP_USING_ATIM2
#ifndef ATIM2_CONFIG
#define ATIM2_CONFIG \
{ \
.timer = ATIM2, \
.tim_irqn = ATIM2_UP_IRQn, \
.name = "timer2", \
}
#endif /* ATIM2_CONFIG */
#endif /* BSP_USING_ATIM2 */
#ifdef BSP_USING_ATIM3
#ifndef ATIM3_CONFIG
#define ATIM3_CONFIG \
{ \
.timer = ATIM3, \
.tim_irqn = ATIM3_UP_IRQn, \
.name = "timer3", \
}
#endif /* ATIM3_CONFIG */
#endif /* BSP_USING_ATIM3 */
#ifdef BSP_USING_ATIM4
#ifndef ATIM4_CONFIG
#define ATIM4_CONFIG \
{ \
.timer = ATIM4, \
.tim_irqn = ATIM4_UP_IRQn, \
.name = "timer4", \
}
#endif /* ATIM4_CONFIG */
#endif /* BSP_USING_ATIM4 */
#ifdef BSP_USING_GTIMA1
#ifndef GTIMA1_CONFIG
#define GTIMA1_CONFIG \
{ \
.timer = GTIMA1, \
.tim_irqn = GTIMA1_IRQn, \
.name = "timer5", \
}
#endif /* GTIMA1_CONFIG */
#endif /* BSP_USING_GTIMA1 */
#ifdef BSP_USING_GTIMA2
#ifndef GTIMA2_CONFIG
#define GTIMA2_CONFIG \
{ \
.timer = GTIMA2, \
.tim_irqn = GTIMA2_IRQn, \
.name = "timer6", \
}
#endif /* GTIMA2_CONFIG */
#endif /* BSP_USING_GTIMA2 */
#ifdef BSP_USING_GTIMA3
#ifndef GTIMA3_CONFIG
#define GTIMA3_CONFIG \
{ \
.timer = GTIMA3, \
.tim_irqn = GTIMA3_IRQn, \
.name = "timer7", \
}
#endif /* GTIMA3_CONFIG */
#endif /* BSP_USING_GTIMA3 */
#ifdef BSP_USING_GTIMA4
#ifndef GTIMA4_CONFIG
#define GTIMA4_CONFIG \
{ \
.timer = GTIMA4, \
.tim_irqn = GTIMA4_IRQn, \
.name = "timer8", \
}
#endif /* GTIMA4_CONFIG */
#endif /* BSP_USING_GTIMA4 */
#ifdef BSP_USING_GTIMA5
#ifndef GTIMA5_CONFIG
#define GTIMA5_CONFIG \
{ \
.timer = GTIMA5, \
.tim_irqn = GTIMA5_IRQn, \
.name = "timer9", \
}
#endif /* GTIMA5_CONFIG */
#endif /* BSP_USING_GTIMA5 */
#ifdef BSP_USING_GTIMA6
#ifndef GTIMA6_CONFIG
#define GTIMA6_CONFIG \
{ \
.timer = GTIMA6, \
.tim_irqn = GTIMA6_IRQn, \
.name = "timer10", \
}
#endif /* GTIMA6_CONFIG */
#endif /* BSP_USING_GTIMA6 */
#ifdef BSP_USING_GTIMA7
#ifndef GTIMA7_CONFIG
#define GTIMA7_CONFIG \
{ \
.timer = GTIMA7, \
.tim_irqn = GTIMA7_IRQn, \
.name = "timer11", \
}
#endif /* GTIMA7_CONFIG */
#endif /* BSP_USING_GTIMA7 */
#ifdef BSP_USING_GTIMB1
#ifndef GTIMB1_CONFIG
#define GTIMB1_CONFIG \
{ \
.timer = GTIMB1, \
.tim_irqn = GTIMB1_IRQn, \
.name = "timer12", \
}
#endif /* GTIMB1_CONFIG */
#endif /* BSP_USING_GTIMB1 */
#ifdef BSP_USING_GTIMB2
#ifndef GTIMB2_CONFIG
#define GTIMB2_CONFIG \
{ \
.timer = GTIMB2, \
.tim_irqn = GTIMB2_IRQn, \
.name = "timer13", \
}
#endif /* GTIMB2_CONFIG */
#endif /* BSP_USING_GTIMB2 */
#ifdef BSP_USING_GTIMB3
#ifndef GTIMB3_CONFIG
#define GTIMB3_CONFIG \
{ \
.timer = GTIMB3, \
.tim_irqn = GTIMB3_IRQn, \
.name = "timer14", \
}
#endif /* GTIMB3_CONFIG */
#endif /* BSP_USING_GTIMB3 */
#ifdef BSP_USING_BTIM1
#ifndef BTIM1_CONFIG
#define BTIM1_CONFIG \
{ \
.timer = BTIM1, \
.tim_irqn = BTIM1_IRQn, \
.name = "timer15", \
}
#endif /* BTIM1_CONFIG */
#endif /* BSP_USING_BTIM1 */
#ifdef BSP_USING_BTIM2
#ifndef BTIM2_CONFIG
#define BTIM2_CONFIG \
{ \
.timer = BTIM2, \
.tim_irqn = BTIM2_IRQn, \
.name = "timer16", \
}
#endif /* BTIM2_CONFIG */
#endif /* BSP_USING_BTIM2 */
#ifdef BSP_USING_BTIM3
#ifndef BTIM3_CONFIG
#define BTIM3_CONFIG \
{ \
.timer = BTIM3, \
.tim_irqn = BTIM3_IRQn, \
.name = "timer17", \
}
#endif /* BTIM3_CONFIG */
#endif /* BSP_USING_BTIM3 */
#ifdef BSP_USING_BTIM4
#ifndef BTIM4_CONFIG
#define BTIM4_CONFIG \
{ \
.timer = BTIM4, \
.tim_irqn = BTIM4_IRQn, \
.name = "timer18", \
}
#endif /* BTIM4_CONFIG */
#endif /* BSP_USING_BTIM4 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/config/h7xx/uart_config.h
+814
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_config.h
+17 -5
View File
@@ -20,11 +20,23 @@ extern "C" {
#if defined(SOC_SERIES_N32H7xx)
#include "h7/dma_config.h"
#include "h7/uart_config.h"
#include "h7/i2c_hard_config.h"
#include "h7/adc_config.h"
#include "h7/spi_config.h"
#include "h7xx/dma_config.h"
#include "h7xx/uart_config.h"
#include "h7xx/i2c_hard_config.h"
#include "h7xx/adc_config.h"
#include "h7xx/spi_config.h"
#include "h7xx/tim_config.h"
#include "h7xx/dac_config.h"
#include "h7xx/can_config.h"
#include "h7xx/pwm_config.h"
#include "h7xx/pulse_encoder_config.h"
#include "h7xx/lptim_config.h"
#elif defined(SOC_SERIES_N32H49x)
#include "h49x/dma_config.h"
#include "h49x/uart_config.h"
#elif defined(SOC_SERIES_N32H47x_48x)
#include "h47x_48x/dma_config.h"
#include "h47x_48x/uart_config.h"
#endif /* defined(SOC_SERIES_N32H7xx) */
#ifdef __cplusplus
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dac.c
+168
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@@ -0,0 +1,168 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-06-09 li.mengmeng port for N32H7xx
*/
#include <board.h>
#include <rtthread.h>
#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
#include "n32h7xx_rcc.h"
#include "n32h7xx_dac.h"
#include "drv_config.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.dac"
#include <drv_log.h>
typedef struct
{
DACX DACx;
DAC_Module *DAC_Module;
uint32_t periph_clk;
void (*EnablePeriphClk)(uint32_t periph, FunctionalState cmd);
uint32_t DAC_clk_pres;
GPIO_Module *GPIOx;
uint16_t GPIO_Pin;
uint32_t GPIO_RCC;
DAC_InitType Init;
} DAC_InitInfo_t;
static DAC_InitInfo_t dac_config[] = {
#ifdef BSP_USING_DAC1
DAC1_CONFIG,
#endif
#ifdef BSP_USING_DAC2
DAC2_CONFIG,
#endif
};
static struct n32_dac n32_dac_obj[sizeof(dac_config) / sizeof(dac_config[0])];
struct n32_dac
{
DAC_InitInfo_t DAC_Info;
struct rt_dac_device n32_dac_device;
};
static rt_err_t n32_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
{
DAC_InitInfo_t *n32_dac_info;
RT_ASSERT(device != RT_NULL);
n32_dac_info = device->parent.user_data;
/* Enable DAC */
DAC_Enable(n32_dac_info->DACx, ENABLE);
return RT_EOK;
}
static rt_err_t n32_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
{
DAC_InitInfo_t *n32_dac_info;
RT_ASSERT(device != RT_NULL);
n32_dac_info = device->parent.user_data;
/* Disable DAC */
DAC_Enable(n32_dac_info->DACx, DISABLE);
return RT_EOK;
}
static rt_uint8_t n32_dac_get_resolution(struct rt_dac_device *device)
{
RT_ASSERT(device != RT_NULL);
/* N32H7xx DAC supports 12-bit resolution */
return 12;
}
static rt_err_t n32_set_dac_value(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
rt_uint16_t set_value;
DAC_InitInfo_t *n32_dac_info;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
n32_dac_info = device->parent.user_data;
set_value = (rt_uint16_t)(*value);
if (set_value > 4095)
{
set_value = 4095;
}
/* Set DAC output data (12-bit right-aligned) */
DAC_SetData(n32_dac_info->DACx, DAC_ALIGN_R_12BIT, set_value);
/* Trigger software conversion */
DAC_SoftTrgEnable(n32_dac_info->DACx, ENABLE);
return RT_EOK;
}
static const struct rt_dac_ops n32_dac_ops = {
.disabled = n32_dac_disabled,
.enabled = n32_dac_enabled,
.convert = n32_set_dac_value,
.get_resolution = n32_dac_get_resolution,
};
static int n32_dac_init(void)
{
int result = RT_EOK;
char name_buf[5] = { 'd', 'a', 'c', '0', 0 };
int i = 0;
for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++)
{
n32_dac_obj[i].DAC_Info = dac_config[i];
/* Set device name */
name_buf[3] = '0';
if (n32_dac_obj[i].DAC_Info.DACx == DAC1)
name_buf[3] = '1';
else if (n32_dac_obj[i].DAC_Info.DACx == DAC2)
name_buf[3] = '2';
/* Enable DAC peripheral clock */
n32_dac_obj[i].DAC_Info.EnablePeriphClk(n32_dac_obj[i].DAC_Info.periph_clk, ENABLE);
/* Config DAC12 prescaler factor,DAC_CLK = 1M*/
DAC_ConfigClkPrescaler(n32_dac_obj[i].DAC_Info.DAC_Module, n32_dac_obj[i].DAC_Info.DAC_clk_pres);
DAC_SetHighFrequencyMode(n32_dac_obj[i].DAC_Info.DAC_Module, DAC_HIGH_FREQ_MODE_BELOW_160M);
/* Initialize DAC */
DAC_Init(n32_dac_obj[i].DAC_Info.DACx, &n32_dac_obj[i].DAC_Info.Init);
/* Register DAC device */
if (rt_hw_dac_register(&n32_dac_obj[i].n32_dac_device, name_buf, &n32_dac_ops, &n32_dac_obj[i].DAC_Info) == RT_EOK)
{
LOG_D("%s init success", name_buf);
}
else
{
LOG_E("%s register failed", name_buf);
result = -RT_ERROR;
}
}
return result;
}
INIT_DEVICE_EXPORT(n32_dac_init);
#endif /* BSP_USING_DACx */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_dma.h
+14 -1
View File
@@ -18,7 +18,8 @@
extern "C" {
#endif
#define DMA_BLOCK_SIZE (4095)
#if defined(SOC_SERIES_N32H7xx)
#define DMA_BLOCK_SIZE (4095)
struct dma_config
{
@@ -30,6 +31,18 @@ struct dma_config
rt_uint32_t dmamux_channel;
rt_uint32_t dmamux_request;
};
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
struct dma_config
{
DMA_Module *DMAy;
DMA_ChannelType *DMAChx;
IRQn_Type dma_irq;
rt_uint32_t dma_rcc;
rt_uint32_t request;
rt_uint32_t channel;
};
#endif
#ifdef __cplusplus
}
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.c
+1023
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_eth.h
+204
View File
@@ -0,0 +1,204 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-24 ox-horse first version
*/
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#include "n32h7xx_eth.h"
#include "n32h7xx_rcc.h"
#include "n32h7xx_pwr.h"
#ifdef __cplusplus
extern "C" {
#endif
/* ======================= ETH Instance Selection ======================= */
#if defined(BSP_USING_ETH1)
#define ETH ETH1
#define ETH_RCC_ENABLE_AHB_PERIPHEN_CLK RCC_EnableAHB2PeriphClk2
#define ETH_RCC_AHB_PERIPHEN_CLK RCC_AHB2_PERIPHEN_M7_ETH1CLK
#define ETH_RCC_AHB_PERIPHEN (RCC_AHB2_PERIPHEN_M7_ETH1MAC | \
RCC_AHB2_PERIPHEN_M7_ETH1TX | \
RCC_AHB2_PERIPHEN_M7_ETH1RX)
#define ETH_GLOBAL_IRQ ETH1_IRQn
#define ETH_PWR_CTRL HSC1_ETH1_PWRCTRL
#define ETH_GLOBAL_IRQHANDLER ETH1_IRQHandler
#elif defined(BSP_USING_ETH2)
#define ETH ETH2
#define ETH_RCC_ENABLE_AHB_PERIPHEN_CLK RCC_EnableAHB1PeriphClk2
#define ETH_RCC_AHB_PERIPHEN_CLK RCC_AHB1_PERIPHEN_M7_ETH2CLK
#define ETH_RCC_AHB_PERIPHEN (RCC_AHB1_PERIPHEN_M7_ETH2MAC | \
RCC_AHB1_PERIPHEN_M7_ETH2TX | \
RCC_AHB1_PERIPHEN_M7_ETH2RX)
#define ETH_GLOBAL_IRQ ETH2_IRQn
#define ETH_PWR_CTRL HSC2_ETH2_PWRCTRL
#define ETH_GLOBAL_IRQHANDLER ETH2_IRQHandler
#endif /* BSP_USING_ETH1 / BSP_USING_ETH2 */
/* ======================= Media Interface Selection ======================= */
#if defined(ETH_INTERFACE_USING_GMII)
#define ETH_MEDIA_INTERFACE ETH_GMII_MODE
#elif defined(ETH_INTERFACE_USING_MII)
#define ETH_MEDIA_INTERFACE ETH_MII_MODE
#elif defined(ETH_INTERFACE_USING_RMII)
#define ETH_MEDIA_INTERFACE ETH_RMII_MODE
#else
#define ETH_MEDIA_INTERFACE ETH_GMII_MODE
#endif
/* ======================= Standard IEEE 802.3 PHY Registers ======================= */
#define PHY_BASIC_CONTROL_REG 0x00U
#define PHY_BASIC_STATUS_REG 0x01U
#define PHY_ID1_REG 0x02U
#define PHY_ID2_REG 0x03U
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
#define PHY_AUTONEG_LINK_PARTNER 0x05U
#define PHY_GIGABIT_CONTROL_REG 0x09U /* 1000BASE-T Control Register */
#define PHY_GIGABIT_STATUS_REG 0x0AU /* 1000BASE-T Status Register */
/* Basic Control Register bits */
#define PHY_RESET_MASK (1 << 15)
#define PHY_LOOPBACK_MASK (1 << 14)
#define PHY_AUTO_NEGOTIATION_MASK (1 << 12)
#define PHY_POWER_DOWN_MASK (1 << 11)
#define PHY_RESTART_AUTONEG_MASK (1 << 9)
#define PHY_DUPLEX_MODE_MASK (1 << 8)
/* Basic Status Register bits */
#define PHY_100BASE_T4_MASK (1 << 15)
#define PHY_100BASE_TX_FD_MASK (1 << 14)
#define PHY_100BASE_TX_HD_MASK (1 << 13)
#define PHY_10BASE_T_FD_MASK (1 << 12)
#define PHY_10BASE_T_HD_MASK (1 << 11)
#define PHY_1000BASE_T_FD_MASK (1 << 10)
#define PHY_1000BASE_T_HD_MASK (1 << 9)
#define PHY_LINKED_STATUS_MASK (1 << 2)
#define PHY_AUTONEGO_COMPLETE_MASK (1 << 5)
/* ======================= DM9119INP PHY Specific Registers ======================= */
#ifdef PHY_USING_DM9119INP
/* DM9119INP is a Gigabit PHY supporting GMII/MII/RMII */
#define PHY_DM9119INP_ID1 0x006EU
#define PHY_DM9119INP_ID2 0x3212U
/* DM9119INP PHY Specific Status Register (0x11)
* bit[15:14] = 00 → 10M, 01 → 100M, 10 → 1000M
* bit[13] = 1 → Full-Duplex, 0 → Half-Duplex */
#define PHY_SDSR 0x11U
#define PHY_Status_SPEED_1000M(sr) (((sr) & (1 << 15)) != 0)
#define PHY_Status_SPEED_100M(sr) (((sr) & (1 << 14)) != 0)
#define PHY_Status_SPEED_10M(sr) (!PHY_Status_SPEED_1000M(sr) && !PHY_Status_SPEED_100M(sr))
#define PHY_Status_FULL_DUPLEX(sr) (((sr) & (1 << 13)) != 0)
/* DM9119INP PHY Specific Interrupt Registers
* 0x12 Interrupt Control, 0x13 Interrupt Status */
#define PHY_INTERRUPT_CTRL_REG 0x12U
#define PHY_INTERRUPT_FLAG_REG 0x13U
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 10))
#endif /* PHY_USING_DM9119INP */
/* ======================= YT8522H PHY Specific Registers ======================= */
#ifdef PHY_USING_YT8522H
/* YT8522H is a Fast Ethernet PHY supporting MII/RMII, up to 100M */
#define PHY_YT8522H_ID1 0x4F51U
#define PHY_YT8522H_ID2 0xE928U
/* YT8522H PHY Specific Status Register (0x11)
* bit[15:14] = 00 → 10M, 01 → 100M
* bit[13] = 1 → Full-Duplex, 0 → Half-Duplex */
#define PHY_SDSR 0x11U
#define PHY_Status_SPEED_100M(sr) (((sr) & (1 << 14)) != 0)
#define PHY_Status_SPEED_10M(sr) (!PHY_Status_SPEED_100M(sr))
#define PHY_Status_FULL_DUPLEX(sr) (((sr) & (1 << 13)) != 0)
/* YT8522H PHY Specific Interrupt Registers
* 0x12 Interrupt Control, 0x13 Interrupt Status
* bit15=Auto-Neg Fail, bit14=Speed Change, bit13=Duplex Change,
* bit11=Link Fail, bit10=Link Success */
#define PHY_INTERRUPT_CTRL_REG 0x12U
#define PHY_INTERRUPT_FLAG_REG 0x13U
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10))
#endif /* PHY_USING_YT8522H */
/* ======================= RTL8211EG PHY Specific Registers ======================= */
#ifdef PHY_USING_RTL8211EG
/* RTL8211EG is a Gigabit PHY supporting GMII/MII/RMII */
#define PHY_RTL8211EG_ID1 0x001CU
#define PHY_RTL8211EG_ID2 0xC915U
/* RTL8211EG PHY Specific Status Register (0x11)
* bit[15:14] = 00 → 10M, 01 → 100M, 10 → 1000M
* bit[13] = 1 → Full-Duplex, 0 → Half-Duplex
* No unlock sequence needed — accessible via default register page. */
#define PHY_SDSR 0x11U
#define PHY_Status_SPEED_1000M(sr) (((sr) & (1 << 15)) != 0)
#define PHY_Status_SPEED_100M(sr) (((sr) & (1 << 14)) != 0)
#define PHY_Status_SPEED_10M(sr) (!PHY_Status_SPEED_1000M(sr) && !PHY_Status_SPEED_100M(sr))
#define PHY_Status_FULL_DUPLEX(sr) (((sr) & (1 << 13)) != 0)
/* RTL8211EG Interrupt Registers: 0x12 Control, 0x13 Status
* bit15=Auto-Neg Error, bit11=Auto-Neg Complete, bit10=Link Change */
#define PHY_INTERRUPT_CTRL_REG 0x12U
#define PHY_INTERRUPT_FLAG_REG 0x13U
#define PHY_INTERRUPT_MASK_REG 0x12U
#define PHY_INT_MASK ((1 << 15) | (1 << 11) | (1 << 10))
#endif /* PHY_USING_RTL8211EG */
/* ======================= Buffer & Descriptor Configuration ======================= */
#ifndef ETH_TX_DESC_NUMBER
#define ETH_TX_DESC_NUMBER ((uint32_t)4U)
#endif
#ifndef ETH_RX_DESC_NUMBER
#define ETH_RX_DESC_NUMBER ((uint32_t)4U)
#endif
/* ETH_MAX_PACKET_SIZE is defined in n32h7xx_eth.h (1528U) */
#define ETH_TX_BUF_SIZE (ETH_TX_DESC_NUMBER * ETH_MAX_PACKET_SIZE)
#define ETH_RX_BUF_SIZE (ETH_RX_DESC_NUMBER * ETH_MAX_PACKET_SIZE)
/* ======================= PHY Link Status Flags ======================= */
#define PHY_LINK (1 << 0)
#define PHY_10M (1 << 1)
#define PHY_100M (1 << 2)
#define PHY_1000M (1 << 3)
#define PHY_FULL_DUPLEX (1 << 4)
/* ---- test/monitoring accessors (enabled via DO_ETH_TEST) ---- */
#define DO_ETH_TEST 1
#if DO_ETH_TEST
rt_uint32_t n32_eth_get_speed(void);
rt_uint32_t n32_eth_get_duplex(void);
rt_uint8_t n32_eth_get_phy_addr(void);
void n32_eth_get_mac_addr(rt_uint8_t mac[6]);
const char *n32_eth_get_phy_name(void);
#endif /* DO_ETH_TEST */
#ifdef __cplusplus
}
#endif
#endif /* __DRV_ETH_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.c
+1488
View File
File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_fdcan.h
+76
View File
@@ -0,0 +1,76 @@
/*
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-22 ox-horse first version - N32H7xx FDCAN driver
*/
#ifndef __DRV_FDCAN_H__
#define __DRV_FDCAN_H__
#include <rtdevice.h>
#include <rtthread.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
*\*\name n32_fdcan_arb_timing.
*\*\brief FDCAN arbitration segment (nominal) baud rate timing entry.
*/
struct n32_fdcan_arb_timing
{
uint32_t baud_rate; /**< baud rate in bps */
uint16_t prescaler; /**< prescaler (1~512) */
uint8_t sjw; /**< synchronization jump width (1~128) */
uint16_t tseg1; /**< time segment 1 (2~256) */
uint8_t tseg2; /**< time segment 2 (2~128) */
};
/**
*\*\name n32_fdcan_data_timing.
*\*\brief FDCAN data segment baud rate timing entry (for CAN FD with BRS).
*/
struct n32_fdcan_data_timing
{
uint32_t baud_rate; /**< data phase baud rate in bps */
uint16_t prescaler; /**< data phase prescaler (1~32) */
uint8_t sjw; /**< data phase synchronization jump width (1~16) */
uint16_t tseg1; /**< data phase time segment 1 (1~32) */
uint8_t tseg2; /**< data phase time segment 2 (1~16) */
};
/**
*\*\name n32_fdcan.
*\*\brief N32 FDCAN device structure.
*\*\note GPIO pin initialization is handled by CubeMX-generated code
*\*\ in n32h7xx_cfg.c. This driver only handles peripheral configuration.
*/
struct n32_fdcan
{
const char *name; /**< device name */
FDCAN_Module *fdcan_x; /**< FDCAN peripheral base address (FDCAN1~FDCAN8) */
FDCAN_InitType init_struct; /**< FDCAN init parameters */
FDCAN_MsgRamType msg_ram; /**< Message RAM block config */
FDCAN_FilterType filter_cfg; /**< default filter configuration */
FDCAN_TxHeaderType tx_header; /**< TX header cache */
FDCAN_RxHeaderType rx_header; /**< RX header cache */
rt_uint32_t tx_pending_mask; /**< software mask of TX buffers with a pending request
(FDCAN_TX_BUFFER0<<i). Cleared when the ISR detects
TXBRP has gone to zero for that buffer, i.e. the
hardware finished/cancelled the transmission. */
struct rt_can_device device; /**< RT-Thread CAN device base */
};
int rt_hw_fdcan_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FDCAN_H__ */
bsp/n32g452xx/Libraries/rt_drivers/drv_flash.c → bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h7xx.c
+43 -76
View File
@@ -1,40 +1,42 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 breo.com first version
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-06-16 li.mengmeng implement for N32H7xx
*/
#include <stddef.h>
#include <board.h>
#include <rtthread.h>
#include <rtconfig.h>
#include <rtdef.h>
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_flash.h"
#include "drv_config.h"
#include "drv_flash_h7xx.h"
#include <board.h>
#include "n32h7xx_smu.h"
#if defined(RT_USING_FAL)
#include "fal.h"
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
#define N32_FLASH_SECTOR_SIZE ((rt_uint32_t)0x1000) /* 4KB per erase sector */
#define N32_FLASH_PAGE_SIZE ((rt_uint32_t)0x1000) /* 4KB per page */
/**
* @brief Gets the page of a given address
* @param addr: address of the flash memory
* @param addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static rt_uint32_t get_page(uint32_t addr)
static uint32_t GetPage(uint32_t addr)
{
rt_uint32_t page = 0;
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
return page;
return RT_ALIGN_DOWN(addr, N32_FLASH_PAGE_SIZE);
}
/**
@@ -59,7 +61,7 @@ int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
*buf = *(rt_uint8_t *)addr;
}
return size;
@@ -67,8 +69,7 @@ int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
* @note This operation must after erase. @see n32_flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
@@ -78,14 +79,8 @@ int n32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
*/
int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if (addr % 4 != 0)
{
LOG_E("write addr must be 4-byte alignment");
return -RT_EINVAL;
}
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if ((end_addr) > N32_FLASH_END_ADDRESS)
{
@@ -93,28 +88,15 @@ int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
return -RT_EINVAL;
}
FLASH_Unlock();
while (addr < end_addr)
if (size < 1)
{
if (FLASH_ProgramWord(addr, *((rt_uint32_t *)buf)) == FLASH_COMPL)
{
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
{
result = -RT_ERROR;
break;
}
addr += 4;
buf += 4;
}
else
{
result = -RT_ERROR;
break;
}
return -RT_EINVAL;
}
FLASH_Lock();
if (SMU_WriteFlash(addr, (uint8_t *)buf, size) != FLASH_SUCCESS)
{
result = -RT_ERROR;
}
if (result != RT_EOK)
{
@@ -125,9 +107,9 @@ int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
}
/**
* Erase data on flash .
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
* @note Erase unit is 4KB.
*
* @param addr flash address
* @param size erase bytes size
@@ -136,39 +118,35 @@ int n32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
*/
int n32_flash_erase(rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
rt_uint32_t page_addr = 0;
FLASH_Unlock();
rt_uint32_t erase_addr;
if ((end_addr) > N32_FLASH_END_ADDRESS)
{
LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
while (addr < end_addr)
{
page_addr = get_page(addr);
erase_addr = GetPage(addr);
if (FLASH_EraseOnePage(page_addr) != FLASH_COMPL)
while (erase_addr < end_addr)
{
if (SMU_EraseFlash(erase_addr) != FLASH_SUCCESS)
{
result = -RT_ERROR;
goto __exit;
}
addr += FLASH_PAGE_SIZE;
erase_addr += N32_FLASH_SECTOR_SIZE;
}
FLASH_Lock();
__exit:
if (result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
@@ -178,19 +156,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev n32_onchip_flash =
{
"onchip_flash",
N32_FLASH_START_ADRESS,
N32_FLASH_SIZE,
FLASH_PAGE_SIZE,
{
NULL,
fal_flash_read,
fal_flash_write,
fal_flash_erase
}
};
const struct fal_flash_dev n32_onchip_flash = { "onchip_flash", N32_FLASH_START_ADRESS, N32_FLASH_SIZE, N32_FLASH_SECTOR_SIZE, { NULL, fal_flash_read, fal_flash_write, fal_flash_erase } };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
@@ -207,5 +173,6 @@ static int fal_flash_erase(long offset, size_t size)
return n32_flash_erase(n32_onchip_flash.addr + offset, size);
}
#endif
#endif /* RT_USING_FAL */
#endif /* BSP_USING_ON_CHIP_FLASH */
bsp/n32g452xx/Libraries/rt_drivers/drv_flash.h → bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_flash/drv_flash_h7xx.h
+8 -6
View File
@@ -1,19 +1,21 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 breo.com first version
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-06-16 li.mengmeng implement for N32H7xx
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#ifndef __DRV_FLASH_H7XX_H__
#define __DRV_FLASH_H7XX_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
@@ -27,4 +29,4 @@ int n32_flash_erase(rt_uint32_t addr, size_t size);
}
#endif
#endif /* __DRV_FLASH_H__ */
#endif /* __DRV_FLASH_H7XX_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_gpio.c
+91 -17
View File
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2026-01-24 ox-horse first version
* 2026-04-07 ox-horse Add N32H49X and N32H47X_48X
*/
#include "drv_gpio.h"
@@ -24,13 +25,21 @@
static uint32_t pin_irq_enable_mask = 0;
#if defined(GPIOK)
#define __N32_PORT_MAX 8u
#if defined(SOC_SERIES_N32H7xx)
#define __N32_PORT_MAX 8u
#endif
#elif defined(GPIOJ)
#define __N32_PORT_MAX 16u
#elif defined(GPIOI)
#define __N32_PORT_MAX 16u
#elif defined(GPIOH)
#define __N32_PORT_MAX 16u
#if defined(SOC_SERIES_N32H7xx)
#define __N32_PORT_MAX 16u
#elif defined(SOC_SERIES_N32H49x)
#define __N32_PORT_MAX 6u
#elif defined(SOC_SERIES_N32H47x_48x)
#define __N32_PORT_MAX 7u
#endif
#elif defined(GPIOG)
#define __N32_PORT_MAX 16u
#elif defined(GPIOF)
@@ -362,8 +371,13 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
irqmap = &pin_irq_map[irqindex];
/* EXTI Line Config */
#if defined(SOC_SERIES_N32H7xx)
GPIO_ConfigEXTILine(irqmap->exti_line, (PIN_NO(pin) * 11 + PIN_PORT(pin)));
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
// PA8-->Pin8--> PIN_PORT(1000)=0, PIN_NO(1000)=8
// PB1-->Pin17--> PIN_PORT(10001)=1, PIN_NO(10001)=1
GPIO_ConfigEXTILine(PIN_NO(pin), PIN_PORT(pin), PIN_NO(pin));
#endif
GPIO_InitStruct(&GPIO_InitStructure);
/* Configure GPIO_InitStructure */
GPIO_InitStructure.Pin = PIN_STPIN(pin);
@@ -394,6 +408,9 @@ static rt_err_t n32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_InitPeripheral(&EXTI_InitStructure);
/* Clear spurious pending bit caused by GPIO pull reconfiguration */
EXTI_ClrITPendBit(irqmap->exti_line);
NVIC_SetPriority(irqmap->irqno, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
NVIC_EnableIRQ(irqmap->irqno);
pin_irq_enable_mask |= irqmap->pinbit;
@@ -462,6 +479,7 @@ rt_inline void pin_irq_hdr(int irqno)
void N32_GPIO_EXTI_Callback(uint16_t line_num)
{
#if defined(SOC_SERIES_N32H7xx)
if (pin_irq_hdr_tab[line_num].pin != -1 && EXTI_GetITStatus(line_num) != RESET)
{
/* Clear EXTI line pending bit */
@@ -469,6 +487,18 @@ void N32_GPIO_EXTI_Callback(uint16_t line_num)
pin_irq_hdr(line_num);
}
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
{
rt_int32_t idx = bit2bitno(line_num);
if (idx >= 0 && idx < (rt_int32_t)ITEM_NUM(pin_irq_hdr_tab) && pin_irq_hdr_tab[idx].pin != -1 && EXTI_GetITStatus(line_num) != RESET)
{
/* Clear EXTI line pending bit */
EXTI_ClrITPendBit(line_num);
pin_irq_hdr(idx);
}
}
#endif
}
void EXTI0_IRQHandler(void)
@@ -531,95 +561,139 @@ void EXTI15_10_IRQHandler(void)
int rt_hw_pin_init(void)
{
#ifdef AFIO
#if defined(SOC_SERIES_N32H7xx)
#if defined(AFIO)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_AFIO, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
#endif
#endif /* AFIO */
#if defined(EXTI)
#ifdef EXTI
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB5PeriphClk2(RCC_APB5_PERIPHEN_EXTI, ENABLE);
#endif
#endif /* EXTI */
#if defined(GPIOA)
#ifdef GPIOA
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOA, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOA, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOA, ENABLE);
#endif
#endif /* GPIOA */
#if defined(GPIOB)
#ifdef GPIOB
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOB, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOB, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOB, ENABLE);
#endif
#endif /* GPIOB */
#if defined(GPIOC)
#ifdef GPIOC
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOC, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOC, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOC, ENABLE);
#endif
#endif /* GPIOC */
#if defined(GPIOD)
#ifdef GPIOD
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOD, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOD, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOD, ENABLE);
#endif
#endif /* GPIOD */
#if defined(GPIOE)
#ifdef GPIOE
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOE, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOE, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOE, ENABLE);
#endif
#endif /* GPIOE */
#if defined(GPIOF)
#ifdef GPIOF
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOF, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOF, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOF, ENABLE);
#endif
#endif /* GPIOF */
#if defined(GPIOG)
#ifdef GPIOG
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOG, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOG, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOG, ENABLE);
#endif
#endif /* GPIOG */
#if defined(GPIOH)
#ifdef GPIOH
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M7_GPIOH, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk1(RCC_AHB5_PERIPHEN_M4_GPIOH, ENABLE);
#endif /* SOC_N32H78X */
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAHB1PeriphClk(RCC_AHB_PERIPHEN_GPIOH, ENABLE);
#endif
#endif /* GPIOH */
#if defined(GPIOI)
#ifdef GPIOI
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOI, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOI, ENABLE);
#endif /* SOC_N32H78X */
#endif
#endif /* GPIOI */
#if defined(GPIOJ)
#ifdef GPIOJ
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOJ, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOJ, ENABLE);
#endif /* SOC_N32H78X */
#endif
#endif /* GPIOJ */
#if defined(GPIOK)
#ifdef GPIOK
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_GPIOK, ENABLE);
#if defined(SOC_N32H78X)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M4_GPIOK, ENABLE);
#endif /* SOC_N32H78X */
#endif
#endif /* defined(SOC_SERIES_N32H7xx) */
#endif /* GPIOK */
return rt_device_pin_register("pin", &_n32_pin_ops, RT_NULL);
}
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_hard_i2c.c
+2 -2
View File
@@ -262,8 +262,8 @@ static rt_err_t n32_i2c_init(struct n32_i2c *i2c_drv)
I2C_Configuration();
/* Disable IIC */
I2C_Enable(cfg->Instance, DISABLE);
/* Get IIC BUSTIM Register value */
BusTim_Reg = cfg->Instance->BUSTIM;
/* Get IIC BUSTM Register value */
BusTim_Reg = cfg->Instance->BUSTM;
if (BusTim_Reg == 0U)
{
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_log.h
+4 -4
View File
@@ -13,15 +13,15 @@
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.c
+512
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_lptim.h
+25
View File
@@ -0,0 +1,25 @@
/*
* Copyright (c) 2006-2025 RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#ifndef __DRV_LPTIM_H__
#define __DRV_LPTIM_H__
#include <rtthread.h>
/* 0x20 - 0x3F udevice control commands */
typedef enum
{
DRV_HW_LPTIMER_CTRL_GET_TICK_MAX = 0x20, /* get the maximum tick value */
DRV_HW_LPTIMER_CTRL_GET_FREQ = 0X21, /* get the timer frequency */
DRV_HW_LPTIMER_CTRL_START = 0X22, /* set the timeout value */
DRV_HW_LPTIMER_CTRL_GET_COUNT = 0X23, /* get the current count value */
} drv_hw_lptimer_ctrl_t;
#endif /* __DRV_LPTIM_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_nand.c
+589
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pulse_encoder.c
+473
View File
@@ -0,0 +1,473 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-23 ox-horse first version
*/
#include <board.h>
#include "drv_config.h"
#ifdef RT_USING_PULSE_ENCODER
#include "drv_tim.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.pulse_encoder"
#include <drv_log.h>
/* NOTE: A timer instance must NOT be enabled for both clock-timer (BSP_USING_ATIMx/GTIMx/BTIMx)
* and pulse-encoder (BSP_USING_PULSE_ENCODERx) simultaneously. The Kconfig should enforce
* mutual exclusivity, otherwise ISR symbol conflicts will occur at link time.
*/
#if !defined(BSP_USING_PULSE_ENCODER1) && !defined(BSP_USING_PULSE_ENCODER2) && !defined(BSP_USING_PULSE_ENCODER3) && !defined(BSP_USING_PULSE_ENCODER4) && !defined(BSP_USING_PULSE_ENCODER5) && !defined(BSP_USING_PULSE_ENCODER6) && !defined(BSP_USING_PULSE_ENCODER7) && !defined(BSP_USING_PULSE_ENCODER8) && !defined(BSP_USING_PULSE_ENCODER9) && !defined(BSP_USING_PULSE_ENCODER10) && !defined(BSP_USING_PULSE_ENCODER11) && !defined(BSP_USING_PULSE_ENCODER12) && !defined(BSP_USING_PULSE_ENCODER13) && !defined(BSP_USING_PULSE_ENCODER14)
#error "Please define at least one BSP_USING_PULSE_ENCODERx"
#endif
/* Auto-reload value for encoder mode. Using half of the 16-bit range
* allows for overflow tracking in both directions. */
#define AUTO_RELOAD_VALUE 0x7FFF
/*
* N32H7xx pulse encoder device mapping:
* ATIM1-4 -> pulse_encoder1-4 (advanced, with encoder support)
* GTIMA1-7 -> pulse_encoder5-11 (general purpose, A bus)
* GTIMB1-3 -> pulse_encoder12-14 (general purpose, B bus)
*
* BTIM1-4 (basic timers) do NOT support encoder mode.
*/
enum
{
#ifdef BSP_USING_PULSE_ENCODER1
PULSE_ENCODER1_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER2
PULSE_ENCODER2_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER3
PULSE_ENCODER3_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER4
PULSE_ENCODER4_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER5
PULSE_ENCODER5_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER6
PULSE_ENCODER6_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER7
PULSE_ENCODER7_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER8
PULSE_ENCODER8_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER9
PULSE_ENCODER9_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER10
PULSE_ENCODER10_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER11
PULSE_ENCODER11_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER12
PULSE_ENCODER12_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER13
PULSE_ENCODER13_INDEX,
#endif
#ifdef BSP_USING_PULSE_ENCODER14
PULSE_ENCODER14_INDEX,
#endif
};
struct n32_pulse_encoder_device
{
struct rt_pulse_encoder_device pulse_encoder;
TIM_Module *timer;
IRQn_Type tim_irqn;
rt_int32_t over_under_flowcount;
char *name;
};
static struct n32_pulse_encoder_device n32_pulse_encoder_obj[] = {
#ifdef BSP_USING_PULSE_ENCODER1
PULSE_ENCODER1_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER2
PULSE_ENCODER2_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER3
PULSE_ENCODER3_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER4
PULSE_ENCODER4_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER5
PULSE_ENCODER5_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER6
PULSE_ENCODER6_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER7
PULSE_ENCODER7_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER8
PULSE_ENCODER8_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER9
PULSE_ENCODER9_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER10
PULSE_ENCODER10_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER11
PULSE_ENCODER11_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER12
PULSE_ENCODER12_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER13
PULSE_ENCODER13_CONFIG,
#endif
#ifdef BSP_USING_PULSE_ENCODER14
PULSE_ENCODER14_CONFIG,
#endif
};
/**
* @brief Initialize the pulse encoder hardware.
*/
static rt_err_t pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
{
struct n32_pulse_encoder_device *n32_device;
TIM_TimeBaseInitType TIM_TimeBaseStructure;
n32_device = (struct n32_pulse_encoder_device *)pulse_encoder;
/* Enable timer clock */
n32_tim_enable_clock(n32_device->timer);
/* Configure time base for encoder mode */
TIM_InitTimBaseStruct(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.Prescaler = 0;
TIM_TimeBaseStructure.CounterMode = TIM_CNT_MODE_UP;
TIM_TimeBaseStructure.Period = AUTO_RELOAD_VALUE;
TIM_TimeBaseStructure.ClkDiv = TIM_CLK_DIV1;
TIM_InitTimeBase(n32_device->timer, &TIM_TimeBaseStructure);
/* Limit update interrupt source to counter overflow/underflow only (URS equivalent) */
TIM_ConfigUpdateRequestIntSrc(n32_device->timer, TIM_UPDATE_SRC_REGULAR);
/* Configure encoder interface in quadrature mode (TI1 + TI2) */
TIM_ConfigEncoderInterface(n32_device->timer,
TIM_ENCODE_QUA_MODE_TI12,
TIM_IC_POLARITY_RISING,
TIM_IC_POLARITY_RISING);
/* Configure TI1 and TI2 input capture with filter */
ConfigTI1(n32_device->timer, TIM_IC_POLARITY_RISING, TIM_IC_SELECTION_DIRECTTI, 3);
ConfigTI2(n32_device->timer, TIM_IC_POLARITY_RISING, TIM_IC_SELECTION_DIRECTTI, 3);
/* Configure NVIC for update interrupt (overflow tracking) */
NVIC_SetPriority(n32_device->tim_irqn,
NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 3, 0));
NVIC_EnableIRQ(n32_device->tim_irqn);
/* Clear update flag and enable update interrupt source */
TIM_ClearFlag(n32_device->timer, TIM_FLAG_UPDATE);
TIM_EnableUpdateEvt(n32_device->timer, ENABLE);
LOG_D("%s init success", n32_device->name);
return RT_EOK;
}
/**
* @brief Get the accumulated encoder count (handles 16-bit overflow).
*/
static rt_int32_t pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
{
struct n32_pulse_encoder_device *n32_device;
n32_device = (struct n32_pulse_encoder_device *)pulse_encoder;
return (rt_int32_t)((rt_int16_t)TIM_GetCnt(n32_device->timer) + n32_device->over_under_flowcount * (AUTO_RELOAD_VALUE + 1));
}
/**
* @brief Clear the encoder count and overflow accumulator.
*/
static rt_err_t pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
{
struct n32_pulse_encoder_device *n32_device;
n32_device = (struct n32_pulse_encoder_device *)pulse_encoder;
n32_device->over_under_flowcount = 0;
TIM_SetCnt(n32_device->timer, 0);
return RT_EOK;
}
/**
* @brief Control the pulse encoder (enable/disable).
*/
static rt_err_t pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
{
rt_err_t result;
struct n32_pulse_encoder_device *n32_device;
n32_device = (struct n32_pulse_encoder_device *)pulse_encoder;
result = RT_EOK;
switch (cmd)
{
case PULSE_ENCODER_CMD_ENABLE:
/* Enable update interrupt for overflow tracking */
TIM_ConfigInt(n32_device->timer, TIM_INT_UPDATE, ENABLE);
/* Enable timer counter */
TIM_Enable(n32_device->timer, ENABLE);
break;
case PULSE_ENCODER_CMD_DISABLE:
/* Disable update interrupt */
TIM_ConfigInt(n32_device->timer, TIM_INT_UPDATE, DISABLE);
/* Stop timer counter */
TIM_Enable(n32_device->timer, DISABLE);
break;
default:
result = -RT_ENOSYS;
break;
}
return result;
}
/**
* @brief ISR update handler: track overflow/underflow for 32-bit position accumulation.
*/
static void pulse_encoder_update_isr(struct n32_pulse_encoder_device *device)
{
/* TIM Update event (overflow/underflow) */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_UPDATE) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_UPDATE);
/* Check counting direction */
if (TIM_GetFlagStatus(device->timer, TIM_DOWN_COUNTING) != RESET)
{
device->over_under_flowcount--;
}
else
{
device->over_under_flowcount++;
}
}
/* Capture compare 1 event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_CC1) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_CC1);
}
/* Capture compare 2 event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_CC2) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_CC2);
}
/* Capture compare 3 event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_CC3) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_CC3);
}
/* Capture compare 4 event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_CC4) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_CC4);
}
/* Break input event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_BREAK) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_BREAK);
}
/* Trigger detection event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_TRIG) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_TRIG);
}
/* Commutation event */
if (TIM_GetFlagStatus(device->timer, TIM_FLAG_COM) != RESET)
{
TIM_ClearFlag(device->timer, TIM_FLAG_COM);
}
}
/* ---- ISR Handlers ---- */
#ifdef BSP_USING_PULSE_ENCODER1
void ATIM1_UP_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER1_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER2
void ATIM2_UP_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER2_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER3
void ATIM3_UP_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER3_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER4
void ATIM4_UP_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER4_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER5
void GTIMA1_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER5_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER6
void GTIMA2_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER6_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER7
void GTIMA3_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER7_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER8
void GTIMA4_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER8_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER9
void GTIMA5_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER9_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER10
void GTIMA6_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER10_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER11
void GTIMA7_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER11_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER12
void GTIMB1_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER12_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER13
void GTIMB2_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER13_INDEX]);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_PULSE_ENCODER14
void GTIMB3_IRQHandler(void)
{
rt_interrupt_enter();
pulse_encoder_update_isr(&n32_pulse_encoder_obj[PULSE_ENCODER14_INDEX]);
rt_interrupt_leave();
}
#endif
/* ---- Device Registration ---- */
static const struct rt_pulse_encoder_ops _ops = {
.init = pulse_encoder_init,
.get_count = pulse_encoder_get_count,
.clear_count = pulse_encoder_clear_count,
.control = pulse_encoder_control,
};
static int n32_pulse_encoder_init(void)
{
int i;
int result;
result = RT_EOK;
for (i = 0; i < sizeof(n32_pulse_encoder_obj) / sizeof(n32_pulse_encoder_obj[0]); i++)
{
n32_pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
n32_pulse_encoder_obj[i].pulse_encoder.ops = &_ops;
if (rt_device_pulse_encoder_register(&n32_pulse_encoder_obj[i].pulse_encoder,
n32_pulse_encoder_obj[i].name, RT_NULL) != RT_EOK)
{
LOG_E("%s register failed", n32_pulse_encoder_obj[i].name);
result = -RT_ERROR;
}
else
{
LOG_D("%s register success", n32_pulse_encoder_obj[i].name);
}
}
return result;
}
INIT_BOARD_EXPORT(n32_pulse_encoder_init);
#endif /* RT_USING_PULSE_ENCODER */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_pwm.c
+685
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.c
+892
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_sdio.h
+212
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@@ -0,0 +1,212 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-06-28 ox-horse first version
*/
#ifndef _DRV_SDIO_H
#define _DRV_SDIO_H
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <string.h>
#include "drv_dma.h"
#include "drv_config.h"
#define SDCARD_INSTANCE_TYPE SDIO_Module
#define SDCARD_INSTANCE SDIO
#define SDIO_BUFF_SIZE 4096
#define SDIO_ALIGN_LEN 32
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (12 * 1000 * 1000)
#endif
#ifndef SDIO_BASE_ADDRESS
#define SDIO_BASE_ADDRESS SDIO_BASE
#endif
#ifndef SDIO_CLOCK_FREQ
#define SDIO_CLOCK_FREQ (48U * 1000 * 1000)
#endif
#ifndef SDIO_BUFF_SIZE
#define SDIO_BUFF_SIZE (4096)
#endif
#ifndef SDIO_ALIGN_LEN
#define SDIO_ALIGN_LEN (32)
#endif
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (24 * 1000 * 1000)
#endif
#define HW_SDIO_IT_CCRCFAIL (0x01U << 0)
#define HW_SDIO_IT_DCRCFAIL (0x01U << 1)
#define HW_SDIO_IT_CTIMEOUT (0x01U << 2)
#define HW_SDIO_IT_DTIMEOUT (0x01U << 3)
#define HW_SDIO_IT_TXUNDERR (0x01U << 4)
#define HW_SDIO_IT_RXOVERR (0x01U << 5)
#define HW_SDIO_IT_CMDREND (0x01U << 6)
#define HW_SDIO_IT_CMDSENT (0x01U << 7)
#define HW_SDIO_IT_DATAEND (0x01U << 8)
#define HW_SDIO_IT_STBITERR (0x01U << 9)
#define HW_SDIO_IT_DBCKEND (0x01U << 10)
#define HW_SDIO_IT_CMDACT (0x01U << 11)
#define HW_SDIO_IT_TXACT (0x01U << 12)
#define HW_SDIO_IT_RXACT (0x01U << 13)
#define HW_SDIO_IT_TXFIFOHE (0x01U << 14)
#define HW_SDIO_IT_RXFIFOHF (0x01U << 15)
#define HW_SDIO_IT_TXFIFOF (0x01U << 16)
#define HW_SDIO_IT_RXFIFOF (0x01U << 17)
#define HW_SDIO_IT_TXFIFOE (0x01U << 18)
#define HW_SDIO_IT_RXFIFOE (0x01U << 19)
#define HW_SDIO_IT_TXDAVL (0x01U << 20)
#define HW_SDIO_IT_RXDAVL (0x01U << 21)
#define HW_SDIO_IT_SDIOIT (0x01U << 22)
#define HW_SDIO_ERRORS \
(HW_SDIO_IT_CCRCFAIL | HW_SDIO_IT_CTIMEOUT | \
HW_SDIO_IT_DCRCFAIL | HW_SDIO_IT_DTIMEOUT | \
HW_SDIO_IT_RXOVERR | HW_SDIO_IT_TXUNDERR)
#define HW_SDIO_POWER_OFF (0x00U)
#define HW_SDIO_POWER_UP (0x02U)
#define HW_SDIO_POWER_ON (0x03U)
#define HW_SDIO_FLOW_ENABLE (0x01U << 14)
#define HW_SDIO_BUSWIDE_1B (0x00U << 11)
#define HW_SDIO_BUSWIDE_4B (0x01U << 11)
#define HW_SDIO_BUSWIDE_8B (0x02U << 11)
#define HW_SDIO_BYPASS_ENABLE (0x01U << 10)
#define HW_SDIO_IDLE_ENABLE (0x01U << 9)
#define HW_SDIO_CLK_ENABLE (0x01U << 13)
#define HW_SDIO_SUSPEND_CMD (0x01U << 11)
#define HW_SDIO_CPSM_ENABLE (0x01U << 0)
#define HW_SDIO_WAIT_END (0x01U << 9)
#define HW_SDIO_WAIT_INT (0x01U << 8)
#define HW_SDIO_RESPONSE_NO (0x00U << 14)
#define HW_SDIO_RESPONSE_SHORT (0x01U << 14)
#define HW_SDIO_RESPONSE_LONG (0x03U << 14)
#define HW_SDIO_DATA_LEN_MASK (0x01FFFFFFU)
#define HW_SDIO_IO_ENABLE (0x01U << 11)
#define HW_SDIO_RWMOD_CK (0x01U << 10)
#define HW_SDIO_RWSTOP_ENABLE (0x01U << 9)
#define HW_SDIO_RWSTART_ENABLE (0x01U << 8)
#define HW_SDIO_DBLOCKSIZE_1 (0x00U << 4)
#define HW_SDIO_DBLOCKSIZE_2 (0x01U << 4)
#define HW_SDIO_DBLOCKSIZE_4 (0x02U << 4)
#define HW_SDIO_DBLOCKSIZE_8 (0x03U << 4)
#define HW_SDIO_DBLOCKSIZE_16 (0x04U << 4)
#define HW_SDIO_DBLOCKSIZE_32 (0x05U << 4)
#define HW_SDIO_DBLOCKSIZE_64 (0x06U << 4)
#define HW_SDIO_DBLOCKSIZE_128 (0x07U << 4)
#define HW_SDIO_DBLOCKSIZE_256 (0x08U << 4)
#define HW_SDIO_DBLOCKSIZE_512 (0x09U << 4)
#define HW_SDIO_DBLOCKSIZE_1024 (0x0AU << 4)
#define HW_SDIO_DBLOCKSIZE_2048 (0x0BU << 4)
#define HW_SDIO_DBLOCKSIZE_4096 (0x0CU << 4)
#define HW_SDIO_DBLOCKSIZE_8192 (0x0DU << 4)
#define HW_SDIO_DBLOCKSIZE_16384 (0x0EU << 4)
#define HW_SDIO_DMA_ENABLE (0x01U << 3)
#define HW_SDIO_STREAM_ENABLE (0x01U << 2)
#define HW_SDIO_TO_HOST (0x01U << 2)
#define HW_SDIO_DPSM_ENABLE (0x01U << 0)
#define HW_SDIO_DATATIMEOUT (0xF0000000U)
struct n32_sdio
{
volatile rt_uint32_t power;
volatile rt_uint32_t clkcr;
volatile rt_uint32_t arg;
volatile rt_uint32_t cmd;
volatile rt_uint32_t respcmd;
volatile rt_uint32_t resp1;
volatile rt_uint32_t resp2;
volatile rt_uint32_t resp3;
volatile rt_uint32_t resp4;
volatile rt_uint32_t dtimer;
volatile rt_uint32_t dlen;
volatile rt_uint32_t dctrl;
volatile rt_uint32_t dcount;
volatile rt_uint32_t sta;
volatile rt_uint32_t icr;
volatile rt_uint32_t mask;
volatile rt_uint32_t reserved0[2];
volatile rt_uint32_t fifocnt;
volatile rt_uint32_t reserved1[13];
volatile rt_uint32_t fifo;
};
typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
typedef rt_uint32_t (*sdio_clk_get)(struct n32_sdio *hw_sdio);
struct n32_sdio_des
{
struct n32_sdio *hw_sdio;
dma_txconfig txconfig;
dma_rxconfig rxconfig;
sdio_clk_get clk_get;
};
struct n32_sdio_config
{
SDCARD_INSTANCE_TYPE *sdio_x;
struct dma_config dma_rx, dma_tx;
};
/* n32 sdio dirver class */
struct n32_sdio_class
{
struct n32_sdio_des *des;
const struct n32_sdio_config *cfg;
struct rt_mmcsd_host host;
struct
{
DMA_InitType handle_rx;
DMA_InitType handle_tx;
} dma;
};
extern void n32_mmcsd_change(void);
#if defined(BSP_USING_SDIO)
#ifndef SDIO_BUS_CONFIG
#define SDIO_BUS_CONFIG \
{ \
.sdio_x = SDIO, \
.dma_rx = { \
.DMAy = SDIO_RX_DMA, \
.DMAChx = SDIO_TX_DMA_CHType, \
.dma_irq = SDIO_TX_DMA_IRQ, \
.dma_rcc = SDIO_TX_DMA_RCC, \
.request = SDIO_TX_DMA_REQUEST, \
.channel = SDIO_TX_DMA_CHANNEL \
}, \
.dma_tx = { \
.DMAy = SDIO_TX_DMA, \
.DMAChx = SDIO_RX_DMA_CHType, \
.dma_irq = SDIO_RX_DMA_IRQ, \
.dma_rcc = SDIO_RX_DMA_RCC, \
.request = SDIO_RX_DMA_REQUEST, \
.channel = SDIO_RX_DMA_CHANNEL \
} \
}
#endif
#endif /* SDIO_BUS_CONFIG */
#endif
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.c
+904
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_tim.h
+20
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@@ -0,0 +1,20 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-02-26 ox-horse first version
*/
#ifndef __DRV_TIM_H__
#define __DRV_TIM_H__
#include <rtdef.h>
#include <board.h>
void n32_tim_ahbx_div_get(TIM_Module *timer, rt_uint32_t *div);
void n32_tim_enable_clock(TIM_Module *timer);
#endif /* __DRV_TIM_H__ */
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.c
+505 -31
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File diff suppressed because it is too large Load Diff
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_usart.h
+34 -3
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@@ -19,8 +19,16 @@
int rt_hw_usart_init(void);
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
#define UART_RX_DMA_IT_BLOCK_TC_FLAG 0x01
#if defined(SOC_SERIES_N32H7xx)
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
#define UART_RX_DMA_IT_BLOCK_TC_FLAG 0x01
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
#define UART_RX_DMA_IT_IDLE_FLAG 0x00
#define UART_RX_DMA_IT_HT_FLAG 0x01
#define UART_RX_DMA_IT_TC_FLAG 0x02
#define UART_CTRL_SET_BLOCK_TIMEOUT 0x20
#endif
/* n32 config class */
struct n32_uart_config
@@ -39,8 +47,10 @@ struct n32_uart
{
struct n32_uart_config *config;
rt_uint32_t DR_mask;
rt_uint32_t tx_block_timeout;
#ifdef RT_SERIAL_USING_DMA
#if defined(SOC_SERIES_N32H7xx)
struct
{
rt_bool_t DMA_Tx_Init;
@@ -69,8 +79,29 @@ struct n32_uart
} rx_dma;
} dma;
#elif defined(SOC_SERIES_N32H49x) || defined(SOC_SERIES_N32H47x_48x)
struct
{
DMA_InitType TX_DMA_ChInitStr;
struct
{
rt_size_t total_length;
rt_uint8_t *buf;
} tx_dma;
#endif
rt_bool_t tx_dma_inited;
DMA_InitType RX_DMA_ChInitStr;
struct
{
rt_size_t remaining_cnt;
} rx_dma;
rt_bool_t rx_dma_inited;
} dma;
#endif /* SOC_SERIES_N32H7xx */
#endif /* RT_SERIAL_USING_DMA */
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};
bsp/n32/n32hxxx/libraries/N32_Drivers/drivers/drv_wdt.c
+180
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@@ -0,0 +1,180 @@
/*
* Copyright (c) 2006-2025, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2026-02-24 ox-horse first version
* 2026-06-16 li.mengmeng fix issues and add stop handler
*/
#include <board.h>
#include <rtthread.h>
#ifdef RT_USING_WDT
//#define DRV_DEBUG
#define LOG_TAG "drv.wdt"
#include <drv_log.h>
struct n32_wdt_obj
{
rt_watchdog_t watchdog;
IWDG_Module *IWDGx;
uint32_t IWDG_Clk;
void (*IWDGX_ClkCmd)(uint32_t periph, FunctionalState Cmd);
rt_uint32_t current_threshold_s;
rt_uint32_t Reload;
rt_uint16_t Prescaler;
rt_uint16_t is_start;
};
static struct n32_wdt_obj n32_wdt;
static struct rt_watchdog_ops ops;
static rt_uint32_t wdt_get_prescaler_factor(rt_uint16_t prescaler)
{
switch (prescaler)
{
case IWDG_PRESCALER_DIV4:
return 4;
case IWDG_PRESCALER_DIV8:
return 8;
case IWDG_PRESCALER_DIV16:
return 16;
case IWDG_PRESCALER_DIV32:
return 32;
case IWDG_PRESCALER_DIV64:
return 64;
case IWDG_PRESCALER_DIV128:
return 128;
case IWDG_PRESCALER_DIV256:
default:
return 256;
}
}
static rt_err_t wdt_init(rt_watchdog_t *wdt)
{
n32_wdt.IWDGX_ClkCmd(n32_wdt.IWDG_Clk, ENABLE);
return RT_EOK;
}
static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
rt_uint32_t reload_value;
rt_uint32_t max_threshold_s;
rt_uint32_t prescaler_factor;
switch (cmd)
{
/* feed the watchdog */
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
IWDG_ReloadKey(n32_wdt.IWDGx);
break;
/* set watchdog timeout */
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
#if defined(LSI_VALUE)
if (n32_wdt.is_start)
{
LOG_W("IWDG is already running, cannot change timeout\n");
return -RT_EBUSY;
}
reload_value = (*(rt_uint32_t *)arg);
prescaler_factor = wdt_get_prescaler_factor(n32_wdt.Prescaler);
if (LSI_VALUE)
{
max_threshold_s = ((n32_wdt.Reload + 1U) * prescaler_factor) / LSI_VALUE;
if (reload_value > max_threshold_s)
{
LOG_W("wdg set timeout parameter too large, please less than %d-s\n", max_threshold_s);
return -RT_EINVAL;
}
else
{
n32_wdt.current_threshold_s = reload_value;
/* Calculate Reload Value */
reload_value = (reload_value * (LSI_VALUE / prescaler_factor)) - 1U;
/* Enable write access to IWDG_PR and IWDG_RLR registers */
IWDG_WriteConfig(n32_wdt.IWDGx, IWDG_WRITE_ENABLE);
/* Set IWDG PREDIV */
IWDG_SetPrescalerDiv(n32_wdt.IWDGx, n32_wdt.Prescaler);
/* Set Counter Reload Value */
IWDG_CntReload(n32_wdt.IWDGx, (uint16_t)reload_value);
/* Reload IWDG counter */
IWDG_ReloadKey(n32_wdt.IWDGx);
/* Disable write access to IWDG_PR and IWDG_RLR registers */
IWDG_WriteConfig(n32_wdt.IWDGx, IWDG_WRITE_DISABLE);
}
}
else
{
LOG_E("Please define the value of LSI_VALUE!");
}
#else
#error "Please define the value of LSI_VALUE!"
#endif
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
*(rt_uint32_t *)arg = n32_wdt.current_threshold_s;
break;
case RT_DEVICE_CTRL_WDT_START:
if (n32_wdt.is_start)
{
LOG_W("IWDG is already started\n");
return RT_EOK;
}
IWDG_Enable(n32_wdt.IWDGx);
n32_wdt.is_start = 1;
break;
case RT_DEVICE_CTRL_WDT_STOP:
LOG_W("IWDG cannot be stopped once started\n");
return -RT_ENOSYS;
default:
LOG_W("This command is not supported.");
return -RT_ERROR;
}
return RT_EOK;
}
int rt_wdt_init(void)
{
#if defined(SOC_SERIES_N32H7xx)
n32_wdt.IWDGx = IWDG1;
n32_wdt.IWDG_Clk = (RCC_APB5_PERIPHEN_IWDG1PCLK | RCC_APB5_PERIPHEN_IWDG1PCLKLP);
n32_wdt.IWDGX_ClkCmd = RCC_EnableAPB5PeriphClk2;
#endif
n32_wdt.Prescaler = IWDG_PRESCALER_DIV256;
n32_wdt.Reload = 0xFFFU;
n32_wdt.is_start = 0U;
ops.init = &wdt_init;
ops.control = &wdt_control;
n32_wdt.watchdog.ops = &ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&n32_wdt.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
return -RT_ERROR;
}
LOG_D("wdt device register success.");
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_wdt_init);
#endif /* RT_USING_WDT */
bsp/n32/n32hxxx/libraries/N32_Drivers/drv_common.c
+8
View File
@@ -42,13 +42,21 @@ static uint32_t _systick_ms = 1;
/* SysTick configuration */
void rt_hw_systick_init(void)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_ClocksTypeDef RCC_Clocks = { 0 };
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
RCC_ClocksType RCC_Clocks = { 0 };
#endif
/* Get clock frequency */
RCC_GetClocksFreqValue(&RCC_Clocks);
/* Set Systick */
#if defined(SOC_SERIES_N32H7xx)
SysTick_Config(RCC_Clocks.M7ClkFreq / RT_TICK_PER_SECOND);
#elif defined(SOC_SERIES_N32H47x_48x) || defined(SOC_SERIES_N32H49x)
SysTick_Config(RCC_Clocks.SysclkFreq / RT_TICK_PER_SECOND);
#endif
NVIC_SetPriorityGrouping(SCB_AIRCR_PRIGROUP3);
NVIC_SetPriority(SysTick_IRQn, 0xFF);
bsp/n32/n32hxxx/libraries/N32_Drivers/nano/drv_console.c
+83 -13
View File
@@ -12,82 +12,152 @@
#include <rtthread.h>
#include <drv_common.h>
static USART_Module* USARTx;
static USART_Module *USARTx;
void rt_hw_console_init(void)
{
USART_InitType USART_InitStructure;
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAHB5PeriphClk2(RCC_AHB5_PERIPHEN_M7_AFIO, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_AFIO, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
#endif
#ifdef USART1
if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart1") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART1, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART1, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART1, ENABLE);
#endif
USARTx = USART1;
}
#endif /* USART1 */
#ifdef USART2
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart2") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART2, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_USART2, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART2, ENABLE);
#endif
USARTx = USART2;
}
#endif /* USART2 */
#ifdef USART3
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart3") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART3, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_USART3, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_USART3, ENABLE);
#endif
USARTx = USART3;
}
#endif /* USART3 */
#ifdef USART4
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart4") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_USART4, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART4, ENABLE);
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_USART4, ENABLE);
#endif
USARTx = USART4;
}
#endif /* USART4 */
#ifdef USART5
#if defined(USART5) || defined(UART5)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart5") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART5, ENABLE);
USARTx = USART5;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_UART5, ENABLE);
USARTx = UART5;
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART5, ENABLE);
USARTx = UART5;
#endif
}
#endif /* USART5 */
#ifdef USART6
#endif /* defined(USART5) || defined(UART5) */
#if defined(USART6) || defined(UART6)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart6") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART6, ENABLE);
USARTx = USART6;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART6, ENABLE);
USARTx = UART6;
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART6, ENABLE);
USARTx = UART6;
#endif
}
#endif /* USART6 */
#ifdef USART7
#endif /* defined(USART6) || defined(UART6) */
#if defined(USART7) || defined(UART7)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart7") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART7, ENABLE);
USARTx = USART7;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART7, ENABLE);
USARTx = UART7;
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_UART7, ENABLE);
USARTx = UART7;
#endif
}
#endif /* USART7 */
#ifdef USART8
#endif /* defined(USART7) || defined(UART7) */
#if defined(USART8) || defined(UART8)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart8") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB2PeriphClk3(RCC_APB2_PERIPHEN_M7_USART8, ENABLE);
USARTx = USART8;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPHEN_UART8, ENABLE);
USARTx = UART8;
#elif defined(SOC_SERIES_N32H47x_48x)
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_UART8, ENABLE);
USARTx = UART8;
#endif
}
#endif /* USART8 */
#ifdef UART9
#endif /* defined(USART8) || defined(UART8) */
#if defined(USART9) || defined(UART9)
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart9") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART9, ENABLE);
USARTx = UART9;
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_USART9, ENABLE);
USARTx = USART9;
#endif
}
#endif /* UART9 */
#endif /* defined(USART9) || defined(UART9) */
#ifdef UART10
else if (rt_strcmp(RT_CONSOLE_DEVICE_NAME, "uart10") == 0)
{
#if defined(SOC_SERIES_N32H7xx)
RCC_EnableAPB1PeriphClk3(RCC_APB1_PERIPHEN_M7_UART10, ENABLE);
#elif defined(SOC_SERIES_N32H49x)
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPHEN_UART10, ENABLE);
#endif
USARTx = UART10;
}
#endif /* UART10 */
@@ -161,7 +231,7 @@ void rt_hw_console_output(const char *str)
while (USART_GetFlagStatus(USARTx, USART_FLAG_TXC) == RESET);
USART_SendData(USARTx, (uint8_t )(*(str + i)));
USART_SendData(USARTx, (uint8_t)(*(str + i)));
}
}

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