mirror of
https://github.com/RT-Thread/rt-thread.git
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[add]add gd32350r-eval bsp
This commit is contained in:
RiceChen
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,9 @@
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<?xml version="1.0" encoding="utf-8"?>
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<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
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<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
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<events>
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</events>
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</component_viewer>
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@@ -0,0 +1,37 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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# you can change the RTT_ROOT default: "rt-thread"
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# example : default "F:/git_repositories/rt-thread"
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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config SOC_GD32350R
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bool
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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config BSP_USING_UART0
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bool "using uart0"
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select RT_USING_SERIAL
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default n
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config BSP_USING_UART1
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bool "using uart1"
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select RT_USING_SERIAL
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default n
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@@ -0,0 +1,242 @@
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/*!
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\file gd32f3x0.h
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\brief general definitions for gd32f3x0
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\version 2017-06-06, V1.0.0, firmware for GD32F3x0
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\version 2019-06-01, V2.0.0, firmware for GD32F3x0
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F3X0_H
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#define GD32F3X0_H
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#ifdef cplusplus
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extern "C" {
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#endif
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/* define GD32F3x0 */
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#if !defined (GD32F3x0)
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#define GD32F3x0
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#endif /* define GD32F3x0 */
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#if !defined (GD32F3x0)
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#error "Please select the target GD32F3x0 device used in your application (in gd32f3x0.h file)"
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#endif /* undefine GD32F3x0 tip */
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/* define GD32F3x0 device category */
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#if (!defined (GD32F330))&&(!defined (GD32F350))
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#error "Please select GD32F3x0 device category( GD32F330 or GD32F350 )"
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#endif /* undefine GD32F330 or GD32F350 tip */
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#if (defined (GD32F330))&&(defined (GD32F350))
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#error "Please select one GD32F3x0 device category( GD32F330 or GD32F350 )"
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#endif /* define GD32F330 and GD32F350 tip */
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/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE ((uint32_t)8000000)
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#endif /* high speed crystal oscillator value */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
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#if !defined (IRC8M_VALUE)
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#define IRC8M_VALUE ((uint32_t)8000000)
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#endif /* internal 8MHz RC oscillator value */
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/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
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#if !defined (IRC8M_STARTUP_TIMEOUT)
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#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 8MHz RC oscillator startup timeout */
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/* define value of internal RC oscillator for ADC in Hz */
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#if !defined (IRC28M_VALUE)
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#define IRC28M_VALUE ((uint32_t)28000000)
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#endif /* IRC28M_VALUE */
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#if !defined (IRC48M_VALUE)
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#define IRC48M_VALUE ((uint32_t)48000000)
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#endif /* IRC48M_VALUE */
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/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
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#if !defined (IRC40K_VALUE)
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#define IRC40K_VALUE ((uint32_t)40000)
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#endif /* internal 40KHz RC oscillator value */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* GD32F3x0 firmware library version number V1.0 */
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#define __GD32F3x0_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __GD32F3x0_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
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#define __GD32F3x0_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __GD32F3x0_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __GD32F3x0_STDPERIPH_VERSION ((__GD32F3x0_STDPERIPH_VERSION_MAIN << 24)\
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|(__GD32F3x0_STDPERIPH_VERSION_SUB1 << 16)\
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|(__GD32F3x0_STDPERIPH_VERSION_SUB2 << 8)\
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|(__GD32F3x0_STDPERIPH_VERSION_RC))
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/* configuration of the Cortex-M4 processor and core peripherals */
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#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 0U /*!< GD32F3x0 do not provide MPU */
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#define __NVIC_PRIO_BITS 4U /*!< GD32F3x0 uses 4 bits for the priority levels */
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#define __Vendor_SysTickConfig 0U /*!< set to 1 if different sysTick config is used */
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#define __FPU_PRESENT 1U /*!< FPU present */
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/* define interrupt number */
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typedef enum IRQn
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{
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/* Cortex-M4 processor exceptions numbers */
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NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */
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/* interruput numbers */
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WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
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LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
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RCU_CTC_IRQn = 2, /*!< RTC and CTC interrupt */
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FMC_IRQn = 3, /*!< FMC interrupt */
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RCU_IRQn = 4, /*!< RCU interrupt */
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EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */
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EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */
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EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */
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TSI_IRQn = 8, /*!< TSI Interrupt */
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DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */
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DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */
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DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */
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ADC_CMP_IRQn = 12, /*!< ADC, CMP0 and CMP1 interrupts */
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TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */
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TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */
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TIMER1_IRQn = 15, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 16, /*!< TIMER2 interrupt */
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#ifdef GD32F350
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TIMER5_DAC_IRQn = 17, /*!< TIMER5 and DAC interrupts */
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#endif /* GD32F350 */
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TIMER13_IRQn = 19, /*!< TIMER13 interrupt */
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TIMER14_IRQn = 20, /*!< TIMER14 interrupt */
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TIMER15_IRQn = 21, /*!< TIMER15 interrupt */
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TIMER16_IRQn = 22, /*!< TIMER16 interrupt */
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I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */
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I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */
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SPI0_IRQn = 25, /*!< SPI0 interrupt */
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SPI1_IRQn = 26, /*!< SPI1 interrupt */
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USART0_IRQn = 27, /*!< USART0 interrupt */
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USART1_IRQn = 28, /*!< USART1 interrupt */
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#ifdef GD32F350
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CEC_IRQn = 30, /*!< CEC interrupt */
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#endif /* GD32F350 */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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DMA_Channel5_6_IRQn = 48, /*!< DMA channel 5 and channel 6 interrupts */
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#ifdef GD32F350
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USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
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USBFS_IRQn = 67, /*!< USBFS global interrupt */
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#endif /* GD32F350 */
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} IRQn_Type;
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/* includes */
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#include "core_cm4.h"
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#include "system_gd32f3x0.h"
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#include <stdint.h>
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/* enum definitions */
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
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typedef enum {FALSE = 0, TRUE = !FALSE} bool;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus;
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
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/* bit operations */
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#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
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#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
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#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
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#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
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#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
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#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
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/* main flash and SRAM memory map */
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#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
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#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
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/* SRAM and peripheral base bit-band region */
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#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
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#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
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/* peripheral memory map */
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#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
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#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
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#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
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#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
|
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/* advanced peripheral bus 1 memory map */
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#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
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#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
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#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
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#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
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#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
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#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
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#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
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#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
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#define CEC_BASE (APB1_BUS_BASE + 0x00007800U) /*!< CEC base address */
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||||
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
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/* advanced peripheral bus 2 memory map */
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#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
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#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */
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#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
|
||||
#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
|
||||
#define TSI_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< TSI base address */
|
||||
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE0000U) /*!< USBFS base address */
|
||||
/* advanced high performance bus 2 memory map */
|
||||
#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||||
/* option byte and debug memory map */
|
||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||
|
||||
/* define marco USE_STDPERIPH_DRIVER */
|
||||
#if !defined USE_STDPERIPH_DRIVER
|
||||
#define USE_STDPERIPH_DRIVER
|
||||
#endif
|
||||
#ifdef USE_STDPERIPH_DRIVER
|
||||
#include "gd32f3x0_libopt.h"
|
||||
#endif /* USE_STDPERIPH_DRIVER */
|
||||
|
||||
#ifdef cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,58 @@
|
||||
/*!
|
||||
\file system_gd32f3x0.h
|
||||
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
|
||||
GD32F3x0 Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32F3X0_H
|
||||
#define SYSTEM_GD32F3X0_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit (void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32F3X0_H */
|
||||
@@ -0,0 +1,318 @@
|
||||
;/*!
|
||||
; \file startup_gd32f3x0.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
; \version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
;are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||
; list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
;OF SUCH DAMAGE.
|
||||
;*/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 18:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 19:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 20:RCU and CTC
|
||||
DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
|
||||
DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
|
||||
DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
|
||||
DCD TSI_IRQHandler ; 24:TSI
|
||||
DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
|
||||
DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
|
||||
DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
|
||||
DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator 0-1
|
||||
DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 31:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 32:TIMER2
|
||||
DCD TIMER5_DAC_IRQHandler ; 33:TIMER5 and DAC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER13_IRQHandler ; 35:TIMER13
|
||||
DCD TIMER14_IRQHandler ; 36:TIMER14
|
||||
DCD TIMER15_IRQHandler ; 37:TIMER15
|
||||
DCD TIMER16_IRQHandler ; 38:TIMER16
|
||||
DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
|
||||
DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
|
||||
DCD SPI0_IRQHandler ; 41:SPI0
|
||||
DCD SPI1_IRQHandler ; 42:SPI1
|
||||
DCD USART0_IRQHandler ; 43:USART0
|
||||
DCD USART1_IRQHandler ; 44:USART1
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_IRQHandler ; 46:CEC
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA_Channel5_6_IRQHandler ; 64:DMA Channel5 and Channel6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_15_IRQHandler [WEAK]
|
||||
EXPORT TSI_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel1_2_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel3_4_IRQHandler [WEAK]
|
||||
EXPORT ADC_CMP_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER14_IRQHandler [WEAK]
|
||||
EXPORT TIMER15_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT CEC_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel5_6_IRQHandler [WEAK]
|
||||
EXPORT USBFS_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_1_IRQHandler
|
||||
EXTI2_3_IRQHandler
|
||||
EXTI4_15_IRQHandler
|
||||
TSI_IRQHandler
|
||||
DMA_Channel0_IRQHandler
|
||||
DMA_Channel1_2_IRQHandler
|
||||
DMA_Channel3_4_IRQHandler
|
||||
ADC_CMP_IRQHandler
|
||||
TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER13_IRQHandler
|
||||
TIMER14_IRQHandler
|
||||
TIMER15_IRQHandler
|
||||
TIMER16_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
CEC_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
USBFS_WKUP_IRQHandler
|
||||
DMA_Channel5_6_IRQHandler
|
||||
USBFS_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,366 @@
|
||||
;/*!
|
||||
; \file startup_gd32f3x0.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
; \version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without modification,
|
||||
;are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice, this
|
||||
; list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
;OF SUCH DAMAGE.
|
||||
;*/
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||
|
||||
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; Vector Number 16,Window watchdog timer
|
||||
DCD LVD_IRQHandler ; Vector Number 17,LVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; Vector Number 18,RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; Vector Number 19,FMC
|
||||
DCD RCU_CTC_IRQHandler ; Vector Number 20,RCU and CTC
|
||||
DCD EXTI0_1_IRQHandler ; Vector Number 21,EXTI Line 0 and EXTI Line 1
|
||||
DCD EXTI2_3_IRQHandler ; Vector Number 22,EXTI Line 2 and EXTI Line 3
|
||||
DCD EXTI4_15_IRQHandler ; Vector Number 23,EXTI Line 4 to EXTI Line 15
|
||||
DCD TSI_IRQHandler ; Vector Number 24,TSI
|
||||
DCD DMA_Channel0_IRQHandler ; Vector Number 25,DMA Channel 0
|
||||
DCD DMA_Channel1_2_IRQHandler ; Vector Number 26,DMA Channel 1 and DMA Channel 2
|
||||
DCD DMA_Channel3_4_IRQHandler ; Vector Number 27,DMA Channel 3 and DMA Channel 4
|
||||
DCD ADC_CMP_IRQHandler ; Vector Number 28,ADC and Comparator 1-2
|
||||
DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; Vector Number 29,TIMER0 Break, Update, Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; Vector Number 30,TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; Vector Number 31,TIMER1
|
||||
DCD TIMER2_IRQHandler ; Vector Number 32,TIMER2
|
||||
DCD TIMER5_DAC_IRQHandler ; Vector Number 33,TIMER5 and DAC
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER13_IRQHandler ; Vector Number 35,TIMER13
|
||||
DCD TIMER14_IRQHandler ; Vector Number 36,TIMER14
|
||||
DCD TIMER15_IRQHandler ; Vector Number 37,TIMER15
|
||||
DCD TIMER16_IRQHandler ; Vector Number 38,TIMER16
|
||||
DCD I2C0_EV_IRQHandler ; Vector Number 39,I2C0 Event
|
||||
DCD I2C1_EV_IRQHandler ; Vector Number 40,I2C1 Event
|
||||
DCD SPI0_IRQHandler ; Vector Number 41,SPI0
|
||||
DCD SPI1_IRQHandler ; Vector Number 42,SPI1
|
||||
DCD USART0_IRQHandler ; Vector Number 43,USART0
|
||||
DCD USART1_IRQHandler ; Vector Number 44,USART1
|
||||
DCD 0 ; Reserved
|
||||
DCD CEC_IRQHandler ; Vector Number 46,CEC
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C0_ER_IRQHandler ; Vector Number 48,I2C0 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_ER_IRQHandler ; Vector Number 50,I2C1 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USBFS_WKUP_IRQHandler ; Vector Number 58,USBFS Wakeup
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA_Channel5_6_IRQHandler ; Vector Number 64,DMA Channel5 and Channel6
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD USBFS_IRQHandler ; Vector Number 83,USBFS
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_CTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_CTC_IRQHandler
|
||||
B RCU_CTC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_1_IRQHandler
|
||||
B EXTI0_1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_3_IRQHandler
|
||||
B EXTI2_3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_15_IRQHandler
|
||||
B EXTI4_15_IRQHandler
|
||||
|
||||
PUBWEAK TSI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSI_IRQHandler
|
||||
B TSI_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel0_IRQHandler
|
||||
B DMA_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel1_2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel1_2_IRQHandler
|
||||
B DMA_Channel1_2_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel3_4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel3_4_IRQHandler
|
||||
B DMA_Channel3_4_IRQHandler
|
||||
|
||||
PUBWEAK ADC_CMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_CMP_IRQHandler
|
||||
B ADC_CMP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
B TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_DAC_IRQHandler
|
||||
B TIMER5_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER13_IRQHandler
|
||||
B TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER14_IRQHandler
|
||||
B TIMER14_IRQHandler
|
||||
|
||||
PUBWEAK TIMER15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER15_IRQHandler
|
||||
B TIMER15_IRQHandler
|
||||
|
||||
PUBWEAK TIMER16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER16_IRQHandler
|
||||
B TIMER16_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK CEC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CEC_IRQHandler
|
||||
B CEC_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_WKUP_IRQHandler
|
||||
B USBFS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel5_6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel5_6_IRQHandler
|
||||
B DMA_Channel5_6_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_IRQHandler
|
||||
B USBFS_IRQHandler
|
||||
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,365 @@
|
||||
/*!
|
||||
\file gd32f3x0_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_ADC_H
|
||||
#define GD32F3X0_ADC_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC ADC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT REG32(ADC + 0x00000000U) /*!< ADC status register */
|
||||
#define ADC_CTL0 REG32(ADC + 0x00000004U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1 REG32(ADC + 0x00000008U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0 REG32(ADC + 0x0000000CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1 REG32(ADC + 0x00000010U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0 REG32(ADC + 0x00000014U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1 REG32(ADC + 0x00000018U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2 REG32(ADC + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3 REG32(ADC + 0x00000020U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT REG32(ADC + 0x00000024U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT REG32(ADC + 0x00000028U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0 REG32(ADC + 0x0000002CU) /*!< ADC regular sequence register 0 */
|
||||
#define ADC_RSQ1 REG32(ADC + 0x00000030U) /*!< ADC regular sequence register 1 */
|
||||
#define ADC_RSQ2 REG32(ADC + 0x00000034U) /*!< ADC regular sequence register 2 */
|
||||
#define ADC_ISQ REG32(ADC + 0x00000038U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0 REG32(ADC + 0x0000003CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1 REG32(ADC + 0x00000040U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2 REG32(ADC + 0x00000044U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3 REG32(ADC + 0x00000048U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA REG32(ADC + 0x0000004CU) /*!< ADC regular data register */
|
||||
#define ADC_OVSAMPCTL REG32(ADC + 0x00000080U) /*!< ADC oversampling control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
|
||||
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
|
||||
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
|
||||
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */
|
||||
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
|
||||
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
|
||||
#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */
|
||||
#define ADC_CTL1_VBETEN BIT(24) /*!< VBAT enable */
|
||||
|
||||
/* ADC_SAMPTx x=0,1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..18) sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx x=0..2 */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */
|
||||
|
||||
/* ADC_OVSAMPCTL */
|
||||
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
|
||||
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
|
||||
|
||||
/* constants definitions */
|
||||
/* ADC flag definitions */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */
|
||||
|
||||
/* ADC special function */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* ADC data alignment */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */
|
||||
|
||||
/* external trigger select for regular channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
|
||||
#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
|
||||
|
||||
/* external trigger select for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
|
||||
#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
|
||||
#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
|
||||
|
||||
/* adc_samptx register value */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
|
||||
|
||||
/* ADC data offset for inserted channel x*/
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC analog watchdog high threshold */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC analog watchdog low threshold */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC regular channel group length */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* ADC inserted channel group length */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* ADC resolution definitions */
|
||||
#define CTL0_DRES(regval) (BITS(24,25) & ((regval) << 24)) /*!< ADC resolution */
|
||||
#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
|
||||
|
||||
/* ADC oversampling shift */
|
||||
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
|
||||
|
||||
/* ADC oversampling ratio */
|
||||
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||
|
||||
/* ADC triggered oversampling */
|
||||
#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||
#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */
|
||||
|
||||
/* ADC channel group definitions */
|
||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */
|
||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
|
||||
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
|
||||
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
|
||||
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
|
||||
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
|
||||
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */
|
||||
|
||||
/* ADC interrupt definitions */
|
||||
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ADC */
|
||||
void adc_deinit(void);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(void);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(void);
|
||||
|
||||
/* ADC calibration and reset calibration */
|
||||
void adc_calibration_enable(void);
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(void);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(void);
|
||||
|
||||
/* enable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_enable(void);
|
||||
/* disable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_disable(void);
|
||||
/* enable the vbat channel */
|
||||
void adc_vbat_enable(void);
|
||||
/* disable the vbat channel */
|
||||
void adc_vbat_disable(void);
|
||||
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
|
||||
/* configure ADC special function */
|
||||
void adc_special_function_config(uint32_t function, ControlStatus newvalue);
|
||||
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t data_alignment);
|
||||
/* configure the length of regular channel group or inserted channel group */
|
||||
void adc_channel_length_config(uint8_t channel_group, uint32_t length);
|
||||
/* configure ADC regular channel */
|
||||
void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
|
||||
/* enable ADC external trigger */
|
||||
void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint8_t channel_group);
|
||||
|
||||
/* read ADC regular group data register */
|
||||
uint16_t adc_regular_data_read(void);
|
||||
/* read ADC inserted group data register */
|
||||
uint16_t adc_inserted_data_read(uint8_t inserted_channel);
|
||||
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t flag);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t flag);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
/* configure ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint8_t channel);
|
||||
/* configure ADC analog watchdog group channel */
|
||||
void adc_watchdog_group_channel_enable(uint8_t channel_group);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(void);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
|
||||
|
||||
/* configure ADC resolution */
|
||||
void adc_resolution_config(uint32_t resolution);
|
||||
/* configure ADC oversample mode */
|
||||
void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
|
||||
/* enable ADC oversample mode */
|
||||
void adc_oversample_mode_enable(void);
|
||||
/* disable ADC oversample mode */
|
||||
void adc_oversample_mode_disable(void);
|
||||
|
||||
#endif /* GD32F3X0_ADC_H */
|
||||
@@ -0,0 +1,250 @@
|
||||
/*!
|
||||
\file gd32f3x0_cec.h
|
||||
\brief definitions for the CEC
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifdef GD32F350
|
||||
|
||||
#ifndef GD32F3X0_CEC_H
|
||||
#define GD32F3X0_CEC_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* CEC definitions */
|
||||
#define CEC CEC_BASE /*!< CEC base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CEC_CTL REG32(CEC + 0x00000000U) /*!< CEC control register */
|
||||
#define CEC_CFG REG32(CEC + 0x00000004U) /*!< CEC configuration register */
|
||||
#define CEC_TDATA REG32(CEC + 0x00000008U) /*!< CEC transmit data register */
|
||||
#define CEC_RDATA REG32(CEC + 0x0000000CU) /*!< CEC receive data register */
|
||||
#define CEC_INTF REG32(CEC + 0x00000010U) /*!< CEC interrupt flag Register */
|
||||
#define CEC_INTEN REG32(CEC + 0x00000014U) /*!< CEC interrupt enable register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CEC_CTL */
|
||||
#define CEC_CTL_CECEN BIT(0) /*!< enable or disable HDMI-CEC controller bit */
|
||||
#define CEC_CTL_STAOM BIT(1) /*!< start of sending a message. */
|
||||
#define CEC_CTL_ENDOM BIT(2) /*!< ENDOM bit value in the next frame in Tx mode */
|
||||
|
||||
/* CEC_CFG */
|
||||
#define CEC_CFG_SFT BITS(0,2) /*!< signal free time */
|
||||
#define CEC_CFG_RTOL BIT(3) /*!< reception bit timing tolerance */
|
||||
#define CEC_CFG_BRES BIT(4) /*!< whether stop receive message when detected BRE */
|
||||
#define CEC_CFG_BREG BIT(5) /*!< generate Error-bit when detected BRE in singlecast */
|
||||
#define CEC_CFG_BPLEG BIT(6) /*!< generate Error-bit when detected BPLE in singlecast */
|
||||
#define CEC_CFG_BCNG BIT(7) /*!< do not generate Error-bit in broadcast message */
|
||||
#define CEC_CFG_SFTOPT BIT(8) /*!< the SFT start option bit */
|
||||
#define CEC_CFG_OWN_ADDRESS BITS(16,30) /*!< own address */
|
||||
#define CEC_CFG_LMEN BIT(31) /*!< listen mode enable bit */
|
||||
|
||||
/* CEC_TDATA */
|
||||
#define CEC_TDATA_TDATA BITS(0,7) /*!< Tx data register */
|
||||
|
||||
/* CEC_RDATA */
|
||||
#define CEC_RDATA_RDATA BITS(0,7) /*!< Rx data register */
|
||||
|
||||
/* CEC_INTF */
|
||||
#define CEC_INTF_BR BIT(0) /*!< Rx-byte data received */
|
||||
#define CEC_INTF_REND BIT(1) /*!< end of reception */
|
||||
#define CEC_INTF_RO BIT(2) /*!< Rx overrun */
|
||||
#define CEC_INTF_BRE BIT(3) /*!< bit rising error */
|
||||
#define CEC_INTF_BPSE BIT(4) /*!< short bit period error */
|
||||
#define CEC_INTF_BPLE BIT(5) /*!< long bit period error */
|
||||
#define CEC_INTF_RAE BIT(6) /*!< Rx ACK error */
|
||||
#define CEC_INTF_ARBF BIT(7) /*!< arbitration fail */
|
||||
#define CEC_INTF_TBR BIT(8) /*!< Tx-byte data request */
|
||||
#define CEC_INTF_TEND BIT(9) /*!< transmission successfully end */
|
||||
#define CEC_INTF_TU BIT(10) /*!< Tx data buffer underrun */
|
||||
#define CEC_INTF_TERR BIT(11) /*!< Tx-error */
|
||||
#define CEC_INTF_TAERR BIT(12) /*!< Tx ACK error flag */
|
||||
|
||||
/* CEC_INTEN */
|
||||
#define CEC_INTEN_BRIE BIT(0) /*!< BR interrupt enable */
|
||||
#define CEC_INTEN_RENDIE BIT(1) /*!< REND interrupt enable */
|
||||
#define CEC_INTEN_ROIE BIT(2) /*!< RO interrupt enable */
|
||||
#define CEC_INTEN_BREIE BIT(3) /*!< BRE interrupt enable. */
|
||||
#define CEC_INTEN_BPSEIE BIT(4) /*!< BPSE interrupt enable */
|
||||
#define CEC_INTEN_BPLEIE BIT(5) /*!< BPLE interrupt enable. */
|
||||
#define CEC_INTEN_RAEIE BIT(6) /*!< RAE interrupt enable */
|
||||
#define CEC_INTEN_ARBFIE BIT(7) /*!< ARBF interrupt enable */
|
||||
#define CEC_INTEN_TBRIE BIT(8) /*!< TBR interrupt enable */
|
||||
#define CEC_INTEN_TENDIE BIT(9) /*!< TEND interrupt enable */
|
||||
#define CEC_INTEN_TUIE BIT(10) /*!< TU interrupt enable */
|
||||
#define CEC_INTEN_TERRIE BIT(11) /*!< TE interrupt enable */
|
||||
#define CEC_INTEN_TAERRIE BIT(12) /*!< TAE interrupt enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* signal free time */
|
||||
#define CFG_SFT(regval) (BITS(0, 2) & ((regval) << 0U))
|
||||
#define CEC_SFT_PROTOCOL_PERIOD CFG_SFT(0) /*!< the signal free time will perform as HDMI-CEC protocol description */
|
||||
#define CEC_SFT_1POINT5_PERIOD CFG_SFT(1) /*!< 1.5 nominal data bit periods */
|
||||
#define CEC_SFT_2POINT5_PERIOD CFG_SFT(2) /*!< 2.5 nominal data bit periods */
|
||||
#define CEC_SFT_3POINT5_PERIOD CFG_SFT(3) /*!< 3.5 nominal data bit periods */
|
||||
#define CEC_SFT_4POINT5_PERIOD CFG_SFT(4) /*!< 4.5 nominal data bit periods */
|
||||
#define CEC_SFT_5POINT5_PERIOD CFG_SFT(5) /*!< 5.5 nominal data bit periods */
|
||||
#define CEC_SFT_6POINT5_PERIOD CFG_SFT(6) /*!< 6.5 nominal data bit periods */
|
||||
#define CEC_SFT_7POINT5_PERIOD CFG_SFT(7) /*!< 7.5 nominal data bit periods */
|
||||
|
||||
/* signal free time start option */
|
||||
#define CEC_SFT_START_STAOM ((uint32_t)0x00000000U) /*!< signal free time counter starts counting when STAOM is asserted */
|
||||
#define CEC_SFT_START_LAST CEC_CFG_SFTOPT /*!< signal free time counter starts automatically after transmission/reception end */
|
||||
|
||||
/* own address */
|
||||
#define CEC_OWN_ADDRESS_CLEAR ((uint32_t)0x00000000U) /*!< own address is cleared */
|
||||
#define CEC_OWN_ADDRESS0 BIT(16) /*!< own address is 0 */
|
||||
#define CEC_OWN_ADDRESS1 BIT(17) /*!< own address is 1 */
|
||||
#define CEC_OWN_ADDRESS2 BIT(18) /*!< own address is 2 */
|
||||
#define CEC_OWN_ADDRESS3 BIT(19) /*!< own address is 3 */
|
||||
#define CEC_OWN_ADDRESS4 BIT(20) /*!< own address is 4 */
|
||||
#define CEC_OWN_ADDRESS5 BIT(21) /*!< own address is 5 */
|
||||
#define CEC_OWN_ADDRESS6 BIT(22) /*!< own address is 6 */
|
||||
#define CEC_OWN_ADDRESS7 BIT(23) /*!< own address is 7 */
|
||||
#define CEC_OWN_ADDRESS8 BIT(24) /*!< own address is 8 */
|
||||
#define CEC_OWN_ADDRESS9 BIT(25) /*!< own address is 9 */
|
||||
#define CEC_OWN_ADDRESS10 BIT(26) /*!< own address is 10 */
|
||||
#define CEC_OWN_ADDRESS11 BIT(27) /*!< own address is 11 */
|
||||
#define CEC_OWN_ADDRESS12 BIT(28) /*!< own address is 12 */
|
||||
#define CEC_OWN_ADDRESS13 BIT(29) /*!< own address is 13 */
|
||||
#define CEC_OWN_ADDRESS14 BIT(30) /*!< own address is 14 */
|
||||
|
||||
/* error-bit generate */
|
||||
#define CEC_BROADCAST_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< generate Error-bit in broadcast */
|
||||
#define CEC_BROADCAST_ERROR_BIT_OFF CEC_CFG_BCNG /*!< do not generate Error-bit in broadcast */
|
||||
#define CEC_LONG_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on long bit period error */
|
||||
#define CEC_LONG_PERIOD_ERROR_BIT_ON CEC_CFG_BPLEG /*!< do not generate Error-bit on long bit period error */
|
||||
#define CEC_RISING_PERIOD_ERROR_BIT_OFF ((uint32_t)0x00000000U) /*!< generate Error-bit on bit rising error */
|
||||
#define CEC_RISING_PERIOD_ERROR_BIT_ON CEC_CFG_BREG /*!< do not generate Error-bit on bit rising error */
|
||||
|
||||
/* whether stop receive message when detected bit rising error */
|
||||
#define CEC_STOP_RISING_ERROR_BIT_ON ((uint32_t)0x00000000U) /*!< stop reception when detected bit rising error */
|
||||
#define CEC_STOP_RISING_ERROR_BIT_OFF ((uint32_t)0x00000001U) /*!< do not stop reception when detected bit rising error */
|
||||
|
||||
/* flag bits */
|
||||
#define CEC_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */
|
||||
#define CEC_FLAG_REND CEC_INTF_REND /*!< end of reception */
|
||||
#define CEC_FLAG_RO CEC_INTF_RO /*!< RX overrun */
|
||||
#define CEC_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */
|
||||
#define CEC_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */
|
||||
#define CEC_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */
|
||||
#define CEC_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */
|
||||
#define CEC_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */
|
||||
#define CEC_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */
|
||||
#define CEC_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */
|
||||
#define CEC_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */
|
||||
#define CEC_FLAG_TERR CEC_INTF_TERR /*!< TX-error */
|
||||
#define CEC_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */
|
||||
|
||||
/* interrupt flag bits */
|
||||
#define CEC_INT_FLAG_BR CEC_INTF_BR /*!< RX-byte data received */
|
||||
#define CEC_INT_FLAG_REND CEC_INTF_REND /*!< end of reception */
|
||||
#define CEC_INT_FLAG_RO CEC_INTF_RO /*!< RX overrun */
|
||||
#define CEC_INT_FLAG_BRE CEC_INTF_BRE /*!< bit rising error */
|
||||
#define CEC_INT_FLAG_BPSE CEC_INTF_BPSE /*!< short bit period error */
|
||||
#define CEC_INT_FLAG_BPLE CEC_INTF_BPLE /*!< long bit period error */
|
||||
#define CEC_INT_FLAG_RAE CEC_INTF_RAE /*!< RX ACK error */
|
||||
#define CEC_INT_FLAG_ARBF CEC_INTF_ARBF /*!< arbitration lost */
|
||||
#define CEC_INT_FLAG_TBR CEC_INTF_TBR /*!< TX-byte data request */
|
||||
#define CEC_INT_FLAG_TEND CEC_INTF_TEND /*!< transmission successfully end */
|
||||
#define CEC_INT_FLAG_TU CEC_INTF_TU /*!< TX data buffer underrun */
|
||||
#define CEC_INT_FLAG_TERR CEC_INTF_TERR /*!< TX-error */
|
||||
#define CEC_INT_FLAG_TAERR CEC_INTF_TAERR /*!< TX ACK error flag */
|
||||
|
||||
/* interrupt enable bits */
|
||||
#define CEC_INT_BR CEC_INTEN_BRIE /*!< RBR interrupt enable */
|
||||
#define CEC_INT_REND CEC_INTEN_RENDIE /*!< REND interrupt enable */
|
||||
#define CEC_INT_RO CEC_INTEN_ROIE /*!< RO interrupt enable */
|
||||
#define CEC_INT_BRE CEC_INTEN_BREIE /*!< RBRE interrupt enable. */
|
||||
#define CEC_INT_BPSE CEC_INTEN_BPSEIE /*!< RSBPE interrupt enable */
|
||||
#define CEC_INT_BPLE CEC_INTEN_BPLEIE /*!< RLBPE interrupt enable. */
|
||||
#define CEC_INT_RAE CEC_INTEN_RAEIE /*!< RAE interrupt enable */
|
||||
#define CEC_INT_ARBF CEC_INTEN_ARBFIE /*!< ALRLST interrupt enable */
|
||||
#define CEC_INT_TBR CEC_INTEN_TBRIE /*!< TBR interrupt enable */
|
||||
#define CEC_INT_TEND CEC_INTEN_TENDIE /*!< TEND interrupt enable */
|
||||
#define CEC_INT_TU CEC_INTEN_TUIE /*!< TU interrupt enable */
|
||||
#define CEC_INT_TERR CEC_INTEN_TERRIE /*!< TE interrupt enable */
|
||||
#define CEC_INT_TAERR CEC_INTEN_TAERRIE /*!< TAE interrupt enable */
|
||||
|
||||
/* function declarations */
|
||||
/* reset HDMI-CEC controller */
|
||||
void cec_deinit(void);
|
||||
/* configure signal free time,the signal free time counter start option,own address */
|
||||
void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address);
|
||||
/* configure generate Error-bit, whether stop receive message when detected bit rising error */
|
||||
void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp);
|
||||
/* enable HDMI-CEC controller */
|
||||
void cec_enable(void);
|
||||
/* disable HDMI-CEC controller */
|
||||
void cec_disable(void);
|
||||
|
||||
/* start CEC message transmission */
|
||||
void cec_transmission_start(void);
|
||||
/* end CEC message transmission */
|
||||
void cec_transmission_end(void);
|
||||
/* enable CEC listen mode */
|
||||
void cec_listen_mode_enable(void);
|
||||
/* disable CEC listen mode */
|
||||
void cec_listen_mode_disable(void);
|
||||
/* configure and clear own address */
|
||||
void cec_own_address_config(uint32_t address);
|
||||
/* configure signal free time and the signal free time counter start option */
|
||||
void cec_sft_config(uint32_t sftmopt,uint32_t sft);
|
||||
/* configure generate Error-bit when detected some abnormal situation or not */
|
||||
void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre);
|
||||
/* whether stop receive message when detected bit rising error */
|
||||
void cec_stop_receive_bre_config(uint32_t rxbrestp);
|
||||
/* enable reception bit timing tolerance */
|
||||
void cec_reception_tolerance_enable(void);
|
||||
/* disable reception bit timing tolerance */
|
||||
void cec_reception_tolerance_disable(void);
|
||||
/* send a data by the CEC peripheral */
|
||||
void cec_data_send(uint8_t data);
|
||||
/* receive a data by the CEC peripheral */
|
||||
uint8_t cec_data_receive(void);
|
||||
|
||||
/* enable interrupt */
|
||||
void cec_interrupt_enable(uint32_t flag);
|
||||
/* disable interrupt */
|
||||
void cec_interrupt_disable(uint32_t flag);
|
||||
/* get CEC status */
|
||||
FlagStatus cec_flag_get(uint32_t flag);
|
||||
/* clear CEC status */
|
||||
void cec_flag_clear(uint32_t flag);
|
||||
/* get CEC int flag and status */
|
||||
FlagStatus cec_interrupt_flag_get(uint32_t flag);
|
||||
/* clear CEC int flag and status */
|
||||
void cec_interrupt_flag_clear(uint32_t flag);
|
||||
|
||||
#endif /* GD32F3X0_CEC_H */
|
||||
|
||||
#endif /* GD32F350 */
|
||||
@@ -0,0 +1,219 @@
|
||||
/*!
|
||||
\file gd32f3x0_cmp.h
|
||||
\brief definitions for the CMP
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_CMP_H
|
||||
#define GD32F3X0_CMP_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* CMP definitions */
|
||||
#define CMP CMP_BASE /*!< CMP base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */
|
||||
|
||||
/* CMP_CS bits definitions */
|
||||
#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */
|
||||
#define CMP_CS_CMP0SW BIT(1) /*!< CMP0 switch */
|
||||
#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */
|
||||
#define CMP_CS_CMP0MSEL BITS(4,6) /*!< COMP0_M input selection */
|
||||
#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */
|
||||
#define CMP_CS_CMP0PL BIT(11) /*!< polarity of CMP0 output */
|
||||
#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */
|
||||
#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output */
|
||||
#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */
|
||||
#define CMP_CS_CMP1EN BIT(16) /*!< CMP1 enable */
|
||||
#define CMP_CS_CMP1M BITS(18,19) /*!< CMP1 mode */
|
||||
#define CMP_CS_CMP1MSEL BITS(20,22) /*!< CMP1_M input selection */
|
||||
#define CMP_CS_WNDEN BIT(23) /*!< window mode enable */
|
||||
#define CMP_CS_CMP1OSEL BITS(24,26) /*!< CMP1 output selection */
|
||||
#define CMP_CS_CMP1PL BIT(27) /*!< polarity of CMP1 output */
|
||||
#define CMP_CS_CMP1HST BITS(28,29) /*!< CMP1 hysteresis */
|
||||
#define CMP_CS_CMP1O BIT(30) /*!< CMP1 output */
|
||||
#define CMP_CS_CMP1LK BIT(31) /*!< CMP1 lock */
|
||||
|
||||
/* consts definitions */
|
||||
/* operating mode */
|
||||
typedef enum{
|
||||
CMP_HIGHSPEED = 0, /*!< high speed mode */
|
||||
CMP_MIDDLESPEED, /*!< medium speed mode */
|
||||
CMP_LOWSPEED, /*!< low speed mode */
|
||||
CMP_VERYLOWSPEED /*!< very-low speed mode */
|
||||
}operating_mode_enum;
|
||||
|
||||
/* inverting input */
|
||||
typedef enum{
|
||||
CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */
|
||||
CMP_1_2VREFINT, /*!< VREFINT /2 input */
|
||||
CMP_3_4VREFINT, /*!< VREFINT *3/4 input */
|
||||
CMP_VREFINT, /*!< VREFINT input */
|
||||
CMP_DAC, /*!< PA4 (DAC) input */
|
||||
CMP_PA5, /*!< PA5 input */
|
||||
CMP_PA_0_2 /*!< PA0 or PA2 input */
|
||||
}inverting_input_enum;
|
||||
|
||||
/* hysteresis */
|
||||
typedef enum{
|
||||
CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */
|
||||
CMP_HYSTERESIS_LOW, /*!< output low hysteresis */
|
||||
CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */
|
||||
CMP_HYSTERESIS_HIGH /*!< output high hysteresis */
|
||||
}cmp_hysteresis_enum;
|
||||
|
||||
/* output */
|
||||
typedef enum{
|
||||
CMP_OUTPUT_NONE = 0, /*!< output no selection */
|
||||
CMP_OUTPUT_TIMER0BKIN, /*!< TIMER 0 break input */
|
||||
CMP_OUTPUT_TIMER0IC0, /*!< TIMER 0 channel0 input capture */
|
||||
CMP_OUTPUT_TIMER0OCPRECLR, /*!< TIMER 0 OCPRE_CLR input */
|
||||
CMP_OUTPUT_TIMER1IC3, /*!< TIMER 1 channel3 input capture */
|
||||
CMP_OUTPUT_TIMER1OCPRECLR, /*!< TIMER 1 OCPRE_CLR input */
|
||||
CMP_OUTPUT_TIMER2IC0, /*!< TIMER 2 channel0 input capture */
|
||||
CMP_OUTPUT_TIMER2OCPRECLR /*!< TIMER 2 OCPRE_CLR input */
|
||||
}cmp_output_enum;
|
||||
|
||||
/* CMP0 mode */
|
||||
#define CS_CMP0M(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define CS_CMP0M_HIGHSPEED CS_CMP0M(0) /*!< CMP0 mode high speed */
|
||||
#define CS_CMP0M_MIDDLESPEED CS_CMP0M(1) /*!< CMP0 mode middle speed */
|
||||
#define CS_CMP0M_LOWSPEED CS_CMP0M(2) /*!< CMP0 mode low speed */
|
||||
#define CS_CMP0M_VERYLOWSPEED CS_CMP0M(3) /*!< CMP0 mode very low speed */
|
||||
|
||||
/* comparator 0 inverting input */
|
||||
#define CS_CMP0MSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
||||
#define CS_CMP0MSEL_1_4VREFINT CS_CMP0MSEL(0) /*!< CMP0 inverting input 1/4 Vrefint */
|
||||
#define CS_CMP0MSEL_1_2VREFINT CS_CMP0MSEL(1) /*!< CMP0 inverting input 1/2 Vrefint */
|
||||
#define CS_CMP0MSEL_3_4VREFINT CS_CMP0MSEL(2) /*!< CMP0 inverting input 3/4 Vrefint */
|
||||
#define CS_CMP0MSEL_VREFINT CS_CMP0MSEL(3) /*!< CMP0 inverting input Vrefint */
|
||||
#define CS_CMP0MSEL_DAC CS_CMP0MSEL(4) /*!< CMP0 inverting input DAC*/
|
||||
#define CS_CMP0MSEL_PA5 CS_CMP0MSEL(5) /*!< CMP0 inverting input PA5*/
|
||||
#define CS_CMP0MSEL_PA0 CS_CMP0MSEL(6) /*!< CMP0 inverting input PA0*/
|
||||
|
||||
/* CMP0 output */
|
||||
#define CS_CMP0OSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
|
||||
#define CS_CMP0OSEL_OUTPUT_NONE CS_CMP0OSEL(0) /*!< CMP0 output none */
|
||||
#define CS_CMP0OSEL_OUTPUT_TIMER0BKIN CS_CMP0OSEL(1) /*!< CMP0 output TIMER 0 break input */
|
||||
#define CS_CMP0OSEL_OUTPUT_TIMER0IC0 CS_CMP0OSEL(2) /*!< CMP0 output TIMER 0 channel 0 input capture */
|
||||
#define CS_CMP0OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP0OSEL(3) /*!< CMP0 output TIMER 0 ocpreclear input */
|
||||
#define CS_CMP0OSEL_OUTPUT_TIMER1IC3 CS_CMP0OSEL(4) /*!< CMP0 output TIMER 1 channel 3 input capture */
|
||||
#define CS_CMP0OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP0OSEL(5) /*!< CMP0 output TIMER 1 ocpreclear input */
|
||||
#define CS_CMP0OSEL_OUTPUT_TIMER2IC0 CS_CMP0OSEL(6) /*!< CMP0 output TIMER 2 channle 0 input capture */
|
||||
#define CS_CMP0OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP0OSEL(7) /*!< CMP0 output TIMER 2 ocpreclear input */
|
||||
|
||||
/* CMP0 hysteresis */
|
||||
#define CS_CMP0HST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
|
||||
#define CS_CMP0HST_HYSTERESIS_NO CS_CMP0HST(0) /*!< CMP0 output no hysteresis */
|
||||
#define CS_CMP0HST_HYSTERESIS_LOW CS_CMP0HST(1) /*!< CMP0 output low hysteresis */
|
||||
#define CS_CMP0HST_HYSTERESIS_MIDDLE CS_CMP0HST(2) /*!< CMP0 output middle hysteresis */
|
||||
#define CS_CMP0HST_HYSTERESIS_HIGH CS_CMP0HST(3) /*!< CMP0 output high hysteresis */
|
||||
|
||||
/* CMP1 mode */
|
||||
#define CS_CMP1M(regval) (BITS(18,19) & ((uint32_t)(regval) << 18))
|
||||
#define CS_CMP1M_HIGHSPEED CS_CMP1M(0) /*!< CMP1 mode high speed */
|
||||
#define CS_CMP1M_MIDDLESPEED CS_CMP1M(1) /*!< CMP1 mode middle speed */
|
||||
#define CS_CMP1M_LOWSPEED CS_CMP1M(2) /*!< CMP1 mode low speed */
|
||||
#define CS_CMP1M_VERYLOWSPEED CS_CMP1M(3) /*!< CMP1 mode very low speed */
|
||||
|
||||
/* CMP1 inverting input */
|
||||
#define CS_CMP1MSEL(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
|
||||
#define CS_CMP1MSEL_1_4VREFINT CS_CMP1MSEL(0) /*!< CMP1 inverting input 1/4 Vrefint */
|
||||
#define CS_CMP1MSEL_1_2VREFINT CS_CMP1MSEL(1) /*!< CMP1 inverting input 1/2 Vrefint */
|
||||
#define CS_CMP1MSEL_3_4VREFINT CS_CMP1MSEL(2) /*!< CMP1 inverting input 3/4 Vrefint */
|
||||
#define CS_CMP1MSEL_VREFINT CS_CMP1MSEL(3) /*!< CMP1 inverting input Vrefint */
|
||||
#define CS_CMP1MSEL_DAC CS_CMP1MSEL(4) /*!< CMP1 inverting input DAC */
|
||||
#define CS_CMP1MSEL_PA5 CS_CMP1MSEL(5) /*!< CMP1 inverting input PA5 */
|
||||
#define CS_CMP1MSEL_PA2 CS_CMP1MSEL(6) /*!< CMP1 inverting input PA2 */
|
||||
|
||||
/* CMP1 output */
|
||||
#define CS_CMP1OSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||
#define CS_CMP1OSEL_OUTPUT_NONE CS_CMP1OSEL(0) /*!< CMP1 output none */
|
||||
#define CS_CMP1OSEL_OUTPUT_TIMER0BKIN CS_CMP1OSEL(1) /*!< CMP1 output TIMER 0 break input */
|
||||
#define CS_CMP1OSEL_OUTPUT_TIMER0IC0 CS_CMP1OSEL(2) /*!< CMP1 output TIMER 0 channel 0 input capture */
|
||||
#define CS_CMP1OSEL_OUTPUT_TIMER0OCPRECLR CS_CMP1OSEL(3) /*!< CMP1 output TIMER 0 ocpreclear input */
|
||||
#define CS_CMP1OSEL_OUTPUT_TIMER1IC3 CS_CMP1OSEL(4) /*!< CMP1 output TIMER 1 channel 3 input capture */
|
||||
#define CS_CMP1OSEL_OUTPUT_TIMER1OCPRECLR CS_CMP1OSEL(5) /*!< CMP1 output TIMER 1 ocpreclear input */
|
||||
#define CS_CMP1OSEL_OUTPUT_TIMER2IC0 CS_CMP1OSEL(6) /*!< CMP1 output TIMER 2 channle 0 input capture */
|
||||
#define CS_CMP1OSEL_OUTPUT_TIMER2OCPRECLR CS_CMP1OSEL(7) /*!< CMP1 output TIMER 2 ocpreclear input */
|
||||
|
||||
/* CMP1 hysteresis */
|
||||
#define CS_CMP1HST(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define CS_CMP1HST_HSTHYSTERESIS_NO CS_CMP1HST(0) /*!< CMP1 output no hysteresis */
|
||||
#define CS_CMP1HST_HYSTERESIS_LOW CS_CMP1HST(1) /*!< CMP1 output low hysteresis */
|
||||
#define CS_CMP1HST_HYSTERESIS_MIDDLE CS_CMP1HST(2) /*!< CMP1 output middle hysteresis */
|
||||
#define CS_CMP1HST_HYSTERESIS_HIGH CS_CMP1HST(3) /*!< CMP1 output high hysteresis */
|
||||
|
||||
/* comparator x definitions */
|
||||
#define CMP0 ((uint32_t)0x00000000) /*!< comparator 0 */
|
||||
#define CMP1 ((uint32_t)0x00000010) /*!< comparator 1 */
|
||||
|
||||
/* comparator output level */
|
||||
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */
|
||||
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */
|
||||
|
||||
/* output polarity of comparator */
|
||||
#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */
|
||||
#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */
|
||||
|
||||
/* function declarations */
|
||||
|
||||
/* initialization functions */
|
||||
/* CMP deinit */
|
||||
void cmp_deinit(void);
|
||||
/* CMP mode init */
|
||||
void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis);
|
||||
/* CMP output init */
|
||||
void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity);
|
||||
|
||||
/* enable functions */
|
||||
/* enable CMP */
|
||||
void cmp_enable(uint32_t cmp_periph);
|
||||
/* disable CMP */
|
||||
void cmp_disable(uint32_t cmp_periph);
|
||||
/* enable CMP switch */
|
||||
void cmp_switch_enable(void);
|
||||
/* disable CMP switch */
|
||||
void cmp_switch_disable(void);
|
||||
/* enable the window mode */
|
||||
void cmp_window_enable(void);
|
||||
/* disable the window mode */
|
||||
void cmp_window_disable(void);
|
||||
/* lock the CMP */
|
||||
void cmp_lock_enable(uint32_t cmp_periph);
|
||||
|
||||
/* output functions */
|
||||
/* get output level */
|
||||
uint32_t cmp_output_level_get(uint32_t cmp_periph);
|
||||
|
||||
#endif /* GD32F3X0_CMP_H */
|
||||
@@ -0,0 +1,119 @@
|
||||
/*!
|
||||
\file gd32f3x0_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_CRC_H
|
||||
#define GD32F3X0_CRC_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */
|
||||
#define CRC_IDATA REG32(CRC + 0x00000010U) /*!< CRC initialization data register */
|
||||
#define CRC_POLY REG32(CRC + 0x00000014U) /*!< CRC polynomial register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
|
||||
#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */
|
||||
#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
|
||||
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
|
||||
|
||||
/* CRC_INIT */
|
||||
#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
|
||||
|
||||
/* CRC_POLY */
|
||||
#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* size of polynomial function */
|
||||
#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3))
|
||||
#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */
|
||||
|
||||
/* input data reverse function */
|
||||
#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
|
||||
#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
|
||||
#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
|
||||
#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
|
||||
#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* enable the reverse operation of output data */
|
||||
void crc_reverse_output_data_enable(void);
|
||||
/* disable the reverse operation of output data */
|
||||
void crc_reverse_output_data_disable(void);
|
||||
|
||||
/* reset data register to the value of initializaiton data register */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* write the initial value register */
|
||||
void crc_init_data_register_write(uint32_t init_data);
|
||||
/* configure the CRC input data function */
|
||||
void crc_input_data_reverse_config(uint32_t data_reverse);
|
||||
|
||||
/* configure the CRC size of polynomial function */
|
||||
void crc_polynomial_size_set(uint32_t poly_size);
|
||||
/* configure the CRC polynomial value function */
|
||||
void crc_polynomial_set(uint32_t poly);
|
||||
|
||||
/* CRC calculate a 32-bit data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||
/* CRC calculate a 32-bit data array */
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
||||
|
||||
#endif /* GD32F3X0_CRC_H */
|
||||
@@ -0,0 +1,191 @@
|
||||
/*!
|
||||
\file gd32f3x0_ctc.h
|
||||
\brief definitions for the CTC
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_CTC_H
|
||||
#define GD32F3X0_CTC_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* CTC definitions */
|
||||
#define CTC CTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CTC_CTL0 REG32(CTC + 0x00000000U) /*!< CTC control register 0 */
|
||||
#define CTC_CTL1 REG32(CTC + 0x00000004U) /*!< CTC control register 1 */
|
||||
#define CTC_STAT REG32(CTC + 0x00000008U) /*!< CTC status register */
|
||||
#define CTC_INTC REG32(CTC + 0x0000000CU) /*!< CTC interrupt clear register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CTC_CTL0 */
|
||||
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
|
||||
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
|
||||
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
|
||||
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
|
||||
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
|
||||
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
|
||||
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
|
||||
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
|
||||
|
||||
/* CTC_CTL1 */
|
||||
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
|
||||
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
|
||||
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
|
||||
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
|
||||
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
|
||||
|
||||
/* CTC_STAT */
|
||||
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
|
||||
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
|
||||
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
|
||||
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
|
||||
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
|
||||
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
|
||||
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
|
||||
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
|
||||
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
|
||||
|
||||
/* CTC_INTC */
|
||||
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
|
||||
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
|
||||
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
|
||||
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
|
||||
|
||||
/* constants definitions */
|
||||
#define CTL0_TRIMVALUE(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
|
||||
#define CTL1_CKLIM(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||
#define GET_STAT_REFCAP(regval) GET_BITS((regval),16,31)
|
||||
#define GET_CTL0_TRIMVALUE(regval) GET_BITS((regval),8,13)
|
||||
|
||||
/* hardware automatically trim mode definitions */
|
||||
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
|
||||
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
|
||||
|
||||
/* reference signal source polarity definitions */
|
||||
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
|
||||
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
|
||||
|
||||
/* reference signal source selection definitions */
|
||||
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
|
||||
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
|
||||
#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFSSOF selected */
|
||||
|
||||
/* reference signal source prescaler definitions */
|
||||
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
|
||||
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
|
||||
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
|
||||
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
|
||||
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
|
||||
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
|
||||
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
|
||||
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
|
||||
|
||||
/* CTC interrupt enable definitions */
|
||||
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
|
||||
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
|
||||
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
|
||||
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
|
||||
|
||||
/* CTC interrupt source definitions */
|
||||
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
|
||||
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
|
||||
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
|
||||
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
|
||||
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
|
||||
|
||||
/* CTC flag definitions */
|
||||
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
|
||||
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
|
||||
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
|
||||
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
|
||||
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset ctc clock trim controller */
|
||||
void ctc_deinit(void);
|
||||
/* configure reference signal source polarity */
|
||||
void ctc_refsource_polarity_config(uint32_t polarity);
|
||||
/* select reference signal source */
|
||||
void ctc_refsource_signal_select(uint32_t refs);
|
||||
/* configure reference signal source prescaler */
|
||||
void ctc_refsource_prescaler_config(uint32_t prescaler);
|
||||
/* configure clock trim base limit value */
|
||||
void ctc_clock_limit_value_config(uint8_t limit_value);
|
||||
/* configure CTC counter reload value */
|
||||
void ctc_counter_reload_value_config(uint16_t reload_value);
|
||||
/* enable CTC trim counter */
|
||||
void ctc_counter_enable(void);
|
||||
/* disable CTC trim counter */
|
||||
void ctc_counter_disable(void);
|
||||
|
||||
/* function configuration */
|
||||
/* configure the IRC48M trim value */
|
||||
void ctc_irc48m_trim_value_config(uint8_t trim_value);
|
||||
/* generate software reference source sync pulse */
|
||||
void ctc_software_refsource_pulse_generate(void);
|
||||
/* configure hardware automatically trim mode */
|
||||
void ctc_hardware_trim_mode_config(uint32_t hardmode);
|
||||
|
||||
/* reading functions */
|
||||
/* read CTC counter capture value when reference sync pulse occurred */
|
||||
uint16_t ctc_counter_capture_value_read(void);
|
||||
/* read CTC trim counter direction when reference sync pulse occurred */
|
||||
FlagStatus ctc_counter_direction_read(void);
|
||||
/* read CTC counter reload value */
|
||||
uint16_t ctc_counter_reload_value_read(void);
|
||||
/* read the IRC48M trim value */
|
||||
uint8_t ctc_irc48m_trim_value_read(void);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable the CTC interrupt */
|
||||
void ctc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable the CTC interrupt */
|
||||
void ctc_interrupt_disable(uint32_t interrupt);
|
||||
/* get CTC flag */
|
||||
FlagStatus ctc_flag_get(uint32_t flag);
|
||||
/* clear CTC flag */
|
||||
void ctc_flag_clear(uint32_t flag);
|
||||
/* get CTC interrupt flag */
|
||||
FlagStatus ctc_interrupt_flag_get(uint32_t interrupt);
|
||||
/* clear CTC interrupt flag */
|
||||
void ctc_interrupt_flag_clear(uint32_t interrupt);
|
||||
|
||||
#endif /* GD32F3X0_CTC_H */
|
||||
@@ -0,0 +1,204 @@
|
||||
/*!
|
||||
\file gd32f3x0_dac.h
|
||||
\brief definitions for the DAC
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifdef GD32F350
|
||||
#ifndef GD32F3X0_DAC_H
|
||||
#define GD32F3X0_DAC_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* DAC definitions */
|
||||
#define DAC DAC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DAC_CTL REG32(DAC + (0x00000000U)) /*!< DAC control register */
|
||||
#define DAC_SWT REG32(DAC + (0x00000004U)) /*!< DAC software trigger register */
|
||||
#define DAC_R12DH REG32(DAC + (0x00000008U)) /*!< DAC 12-bit right-aligned data holding register */
|
||||
#define DAC_L12DH REG32(DAC + (0x0000000CU)) /*!< DAC 12-bit left-aligned data holding register */
|
||||
#define DAC_R8DH REG32(DAC + (0x00000010U)) /*!< DAC 8-bit right-aligned data holding register */
|
||||
#define DAC_DO REG32(DAC + (0x0000002CU)) /*!< DAC output data register */
|
||||
#define DAC_STAT REG32(DAC + (0x00000034U)) /*!< DAC status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DAC_CTL */
|
||||
#define DAC_CTL_DEN BIT(0) /*!< DAC enable/disable bit */
|
||||
#define DAC_CTL_DBOFF BIT(1) /*!< DAC output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN BIT(2) /*!< DAC trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL BITS(3,5) /*!< DAC trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM BITS(6,7) /*!< DAC noise wave mode */
|
||||
#define DAC_CTL_DWBW BITS(8,11) /*!< DAC noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN BIT(12) /*!< DAC DMA enable/disable bit */
|
||||
#define DAC_CTL_DDUDRIE BIT(13) /*!< DAC DMA underrun interrupt enable/disable bit */
|
||||
|
||||
/* DAC_SWT */
|
||||
#define DAC_SWT_SWTR BIT(0) /*!< DAC software trigger bit,cleared by hardware */
|
||||
|
||||
/* DAC_R12DH */
|
||||
#define DAC_R12DH_DAC_DH BITS(0,11) /*!< DAC 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC_L12DH */
|
||||
#define DAC_L12DH_DAC_DH BITS(4,15) /*!< DAC 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC_R8DH */
|
||||
#define DAC_R8DH_DAC_DH BITS(0,7) /*!< DAC 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC_DO */
|
||||
#define DAC_DO_DAC_DO BITS(0,11) /*!< DAC 12-bit output data bits */
|
||||
|
||||
/* DAC_STAT */
|
||||
#define DAC_STAT_DDUDR BIT(13) /*!< DAC DMA underrun flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* DAC trigger source */
|
||||
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
|
||||
#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */
|
||||
#define DAC_TRIGGER_T14_TRGO CTL_DTSEL(3) /*!< TIMER14 TRGO */
|
||||
#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
|
||||
#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
|
||||
#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
|
||||
|
||||
/* DAC noise wave mode */
|
||||
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */
|
||||
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
|
||||
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
|
||||
|
||||
/* DAC noise wave bit width */
|
||||
#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
|
||||
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
|
||||
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
|
||||
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
|
||||
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
|
||||
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
|
||||
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
|
||||
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
|
||||
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
|
||||
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
|
||||
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
|
||||
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
|
||||
|
||||
/* unmask LFSR bits in DAC LFSR noise mode */
|
||||
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
|
||||
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
|
||||
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
|
||||
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
|
||||
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
|
||||
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
|
||||
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
|
||||
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
|
||||
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
|
||||
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
|
||||
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
|
||||
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
|
||||
|
||||
/* triangle amplitude in DAC triangle noise mode */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
|
||||
|
||||
/* DAC data alignment */
|
||||
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */
|
||||
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */
|
||||
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize DAC */
|
||||
void dac_deinit(void);
|
||||
|
||||
/* enable DAC */
|
||||
void dac_enable(void);
|
||||
/* disable DAC */
|
||||
void dac_disable(void);
|
||||
/* enable DAC DMA */
|
||||
void dac_dma_enable(void);
|
||||
/* disable DAC DMA */
|
||||
void dac_dma_disable(void);
|
||||
/* enable DAC output buffer */
|
||||
void dac_output_buffer_enable(void);
|
||||
/* disable DAC output buffer */
|
||||
void dac_output_buffer_disable(void);
|
||||
/* enable DAC trigger */
|
||||
void dac_trigger_enable(void);
|
||||
/* disable DAC trigger */
|
||||
void dac_trigger_disable(void);
|
||||
/* enable DAC software trigger */
|
||||
void dac_software_trigger_enable(void);
|
||||
/* disable DAC software trigger */
|
||||
void dac_software_trigger_disable(void);
|
||||
/* enable DAC interrupt(DAC DMA underrun interrupt) */
|
||||
void dac_interrupt_enable(void);
|
||||
/* disable DAC interrupt(DAC DMA underrun interrupt) */
|
||||
void dac_interrupt_disable(void);
|
||||
|
||||
/* configure DAC trigger source */
|
||||
void dac_trigger_source_config(uint32_t triggersource);
|
||||
/* configure DAC wave mode */
|
||||
void dac_wave_mode_config(uint32_t wave_mode);
|
||||
/* configure DAC wave bit width */
|
||||
void dac_wave_bit_width_config(uint32_t bit_width);
|
||||
/* configure DAC LFSR noise mode */
|
||||
void dac_lfsr_noise_config(uint32_t unmask_bits);
|
||||
/* configure DAC triangle noise mode */
|
||||
void dac_triangle_noise_config(uint32_t amplitude);
|
||||
/* get the last data output value */
|
||||
uint16_t dac_output_value_get(void);
|
||||
|
||||
/* get the specified DAC flag(DAC DMA underrun flag) */
|
||||
FlagStatus dac_flag_get(void);
|
||||
/* clear the specified DAC flag(DAC DMA underrun flag) */
|
||||
void dac_flag_clear(void);
|
||||
/* get the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
||||
FlagStatus dac_interrupt_flag_get(void);
|
||||
/* clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag) */
|
||||
void dac_interrupt_flag_clear(void);
|
||||
|
||||
/* set DAC data holding register value */
|
||||
void dac_data_set(uint32_t dac_align, uint16_t data);
|
||||
|
||||
#endif /* GD32F3X0_DAC_H */
|
||||
|
||||
#endif /* GD32F350 */
|
||||
@@ -0,0 +1,128 @@
|
||||
/*!
|
||||
\file gd32f3x0_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_DBG_H
|
||||
#define GD32F3X0_DBG_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00000000U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL0 REG32(DBG + 0x00000004U) /*!< DBG control register 0 */
|
||||
#define DBG_CTL1 REG32(DBG + 0x00000008U) /*!< DBG control register 1 */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL0 */
|
||||
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
|
||||
#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#ifdef GD32F350
|
||||
#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
||||
#endif /* GD32F350 */
|
||||
#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
|
||||
|
||||
/* DBG_CTL1 */
|
||||
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* define the peripheral debug hold bit position and its register index offset */
|
||||
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||
|
||||
/* register index */
|
||||
typedef enum
|
||||
{
|
||||
DBG_IDX_CTL0 = 0x04U, /*!< DBG control register 0 offset */
|
||||
DBG_IDX_CTL1 = 0x08U, /*!< DBG control register 1 offset */
|
||||
}dbg_reg_idx;
|
||||
|
||||
/* peripherals hold bit */
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< hold TIMER0 counter when core is halted */
|
||||
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U), /*!< hold TIMER1 counter when core is halted */
|
||||
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< hold TIMER2 counter when core is halted */
|
||||
#ifdef GD32F350
|
||||
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< hold TIMER5 counter when core is halted */
|
||||
#endif /* GD32F350 */
|
||||
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< hold TIMER13 counter when core is halted */
|
||||
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< hold TIMER14 counter when core is halted */
|
||||
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< hold TIMER15 counter when core is halted */
|
||||
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< hold TIMER16 counter when core is halted */
|
||||
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< hold I2C0 smbus when core is halted */
|
||||
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< hold I2C1 smbus when core is halted */
|
||||
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the DBG */
|
||||
void dbg_deinit(void);
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
#endif /* GD32F3X0_DBG_H */
|
||||
@@ -0,0 +1,273 @@
|
||||
/*!
|
||||
\file gd32f3x0_dma.h
|
||||
\brief definitions for the DMA
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_DMA_H
|
||||
#define GD32F3X0_DMA_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA DMA_BASE /*!< DMA base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF REG32(DMA + 0x00000000U) /*!< DMA interrupt flag register */
|
||||
#define DMA_INTC REG32(DMA + 0x00000004U) /*!< DMA interrupt flag clear register */
|
||||
#define DMA_CH0CTL REG32(DMA + 0x00000008U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT REG32(DMA + 0x0000000CU) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR REG32(DMA + 0x00000010U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0MADDR REG32(DMA + 0x00000014U) /*!< DMA channel 0 memory base address register */
|
||||
#define DMA_CH1CTL REG32(DMA + 0x0000001CU) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT REG32(DMA + 0x00000020U) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR REG32(DMA + 0x00000024U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1MADDR REG32(DMA + 0x00000028U) /*!< DMA channel 1 memory base address register */
|
||||
#define DMA_CH2CTL REG32(DMA + 0x00000030U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT REG32(DMA + 0x00000034U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR REG32(DMA + 0x00000038U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2MADDR REG32(DMA + 0x0000003CU) /*!< DMA channel 2 memory base address register */
|
||||
#define DMA_CH3CTL REG32(DMA + 0x00000044U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT REG32(DMA + 0x00000048U) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR REG32(DMA + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3MADDR REG32(DMA + 0x00000050U) /*!< DMA channel 3 memory base address register */
|
||||
#define DMA_CH4CTL REG32(DMA + 0x00000058U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT REG32(DMA + 0x0000005CU) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR REG32(DMA + 0x00000060U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4MADDR REG32(DMA + 0x00000064U) /*!< DMA channel 4 memory base address register */
|
||||
#define DMA_CH5CTL REG32(DMA + 0x0000006CU) /*!< DMA channel 5 control register */
|
||||
#define DMA_CH5CNT REG32(DMA + 0x00000070U) /*!< DMA channel 5 counter register */
|
||||
#define DMA_CH5PADDR REG32(DMA + 0x00000074U) /*!< DMA channel 5 peripheral base address register */
|
||||
#define DMA_CH5MADDR REG32(DMA + 0x00000078U) /*!< DMA channel 5 memory base address register */
|
||||
#define DMA_CH6CTL REG32(DMA + 0x00000080U) /*!< DMA channel 6 control register */
|
||||
#define DMA_CH6CNT REG32(DMA + 0x00000084U) /*!< DMA channel 6 counter register */
|
||||
#define DMA_CH6PADDR REG32(DMA + 0x00000088U) /*!< DMA channel 6 peripheral base address register */
|
||||
#define DMA_CH6MADDR REG32(DMA + 0x0000008CU) /*!< DMA channel 6 memory base address register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
|
||||
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
|
||||
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
|
||||
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
|
||||
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
|
||||
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
|
||||
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL,x=0..6 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
|
||||
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */
|
||||
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */
|
||||
#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */
|
||||
#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */
|
||||
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */
|
||||
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */
|
||||
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT,x=0..6 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR,x=0..6 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxMADDR,x=0..6 */
|
||||
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA Channel0 */
|
||||
DMA_CH1, /*!< DMA Channel1 */
|
||||
DMA_CH2, /*!< DMA Channel2 */
|
||||
DMA_CH3, /*!< DMA Channel3 */
|
||||
DMA_CH4, /*!< DMA Channel4 */
|
||||
DMA_CH5, /*!< DMA Channel5 */
|
||||
DMA_CH6 /*!< DMA Channel6 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint8_t periph_inc; /*!< peripheral increasing mode */
|
||||
uint32_t memory_addr; /*!< memory base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint8_t memory_inc; /*!< memory increasing mode */
|
||||
uint8_t direction; /*!< channel data transfer direction */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
} dma_parameter_struct;
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
|
||||
DMA_INTF_HTFIF | DMA_INTF_ERRIF)
|
||||
|
||||
#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_CHCTL base address */
|
||||
#define DMA_CHXCTL_BASE (DMA + (uint32_t)0x00000008U) /*!< the base address of DMA channel CHXCTL register */
|
||||
#define DMA_CHXCNT_BASE (DMA + (uint32_t)0x0000000CU) /*!< the base address of DMA channel CHXCNT register */
|
||||
#define DMA_CHXPADDR_BASE (DMA + (uint32_t)0x00000010U) /*!< the base address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHXMADDR_BASE (DMA + (uint32_t)0x00000014U) /*!< the base address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA channel shift bit */
|
||||
#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + (uint32_t)0x0000014U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
|
||||
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL register */
|
||||
/* interrupt enable bits */
|
||||
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
|
||||
|
||||
/* transfer direction */
|
||||
#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */
|
||||
|
||||
/* transfer data size of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */
|
||||
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */
|
||||
|
||||
/* transfer data size of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */
|
||||
|
||||
/* DMA_CHxCNT register */
|
||||
/* transfer counter */
|
||||
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(dma_channel_enum channelx);
|
||||
/* initialize the parameters of DMA struct with the default values */
|
||||
void dma_struct_para_init(dma_parameter_struct* init_struct);
|
||||
/* initialize DMA channel */
|
||||
void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct);
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(dma_channel_enum channelx);
|
||||
/* enable memory to memory mode */
|
||||
void dma_memory_to_memory_enable(dma_channel_enum channelx);
|
||||
/* disable memory to memory mode */
|
||||
void dma_memory_to_memory_disable(dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(dma_channel_enum channelx);
|
||||
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA memory base address */
|
||||
void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(dma_channel_enum channelx);
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
|
||||
/* enable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_enable(dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_disable(dma_channel_enum channelx);
|
||||
/* enable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_enable(dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_disable(dma_channel_enum channelx);
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction);
|
||||
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
|
||||
/* check DMA flag and interrupt enable bit is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
|
||||
|
||||
#endif /* GD32F3X0_DMA_H */
|
||||
@@ -0,0 +1,285 @@
|
||||
/*!
|
||||
\file gd32f3x0_exti.h
|
||||
\brief definitions for the EXTI
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_EXTI_H
|
||||
#define GD32F3X0_EXTI_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* EXTI definitions */
|
||||
#define EXTI EXTI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define EXTI_INTEN REG32(EXTI + 0x00000000U)/*!< interrupt enable register */
|
||||
#define EXTI_EVEN REG32(EXTI + 0x00000004U)/*!< event enable register */
|
||||
#define EXTI_RTEN REG32(EXTI + 0x00000008U)/*!< rising edge trigger enable register */
|
||||
#define EXTI_FTEN REG32(EXTI + 0x0000000CU)/*!< falling trigger enable register */
|
||||
#define EXTI_SWIEV REG32(EXTI + 0x00000010U)/*!< software interrupt event register */
|
||||
#define EXTI_PD REG32(EXTI + 0x00000014U)/*!< pending register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXTI_INTEN */
|
||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
|
||||
#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */
|
||||
#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */
|
||||
#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */
|
||||
#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */
|
||||
#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */
|
||||
#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */
|
||||
#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */
|
||||
#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */
|
||||
|
||||
/* EXTI_EVEN */
|
||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
|
||||
#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */
|
||||
#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */
|
||||
#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */
|
||||
#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */
|
||||
#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */
|
||||
#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */
|
||||
#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */
|
||||
#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */
|
||||
|
||||
/* EXTI_RTEN */
|
||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
|
||||
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
|
||||
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
|
||||
#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */
|
||||
|
||||
/* EXTI_FTEN */
|
||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
|
||||
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
|
||||
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
|
||||
#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */
|
||||
|
||||
/* EXTI_SWIEV */
|
||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
|
||||
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
|
||||
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
|
||||
#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
|
||||
|
||||
/* EXTI_PD */
|
||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
|
||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
|
||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
|
||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
|
||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
|
||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
|
||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
|
||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
|
||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
|
||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
|
||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
|
||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
|
||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
|
||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
|
||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
|
||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
|
||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
|
||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
|
||||
#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */
|
||||
#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */
|
||||
#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */
|
||||
#define EXTI_PD_PD22 BIT(22) /*!< interrupt/event pending status from line 22 */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXTI line number */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||
EXTI_19 = BIT(19), /*!< EXTI line 19 */
|
||||
EXTI_20 = BIT(20), /*!< EXTI line 20 */
|
||||
EXTI_21 = BIT(21), /*!< EXTI line 21 */
|
||||
EXTI_22 = BIT(22), /*!< EXTI line 22 */
|
||||
EXTI_23 = BIT(23), /*!< EXTI line 23 */
|
||||
EXTI_24 = BIT(24), /*!< EXTI line 24 */
|
||||
EXTI_25 = BIT(25), /*!< EXTI line 25 */
|
||||
EXTI_26 = BIT(26), /*!< EXTI line 26 */
|
||||
EXTI_27 = BIT(27), /*!< EXTI line 27 */
|
||||
}exti_line_enum;
|
||||
|
||||
/* external interrupt and event */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||
EXTI_EVENT /*!< EXTI event mode */
|
||||
}exti_mode_enum;
|
||||
|
||||
/* interrupt trigger mode */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||
EXTI_TRIG_BOTH /*!< EXTI rising and falling edge trigger */
|
||||
}exti_trig_type_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the EXTI */
|
||||
void exti_deinit(void);
|
||||
/* initialize the EXTI, enable the configuration of EXTI initialize */
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||
/* enable the interrupts from EXTI line x */
|
||||
void exti_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the interrupts from EXTI line x */
|
||||
void exti_interrupt_disable(exti_line_enum linex);
|
||||
/* enable the events from EXTI line x */
|
||||
void exti_event_enable(exti_line_enum linex);
|
||||
/* disable the events from EXTI line x */
|
||||
void exti_event_disable(exti_line_enum linex);
|
||||
|
||||
/* enable EXTI software interrupt event */
|
||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||
/* disable EXTI software interrupt event */
|
||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||
/* get EXTI line x pending flag */
|
||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x pending flag */
|
||||
void exti_flag_clear(exti_line_enum linex);
|
||||
/* get EXTI line x flag when the interrupt flag is set */
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x pending flag */
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||
|
||||
#endif /* GD32F3X0_EXTI_H */
|
||||
@@ -0,0 +1,258 @@
|
||||
/*!
|
||||
\file gd32f3x0_fmc.h
|
||||
\brief definitions for the FMC
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F3X0_FMC_H
|
||||
#define GD32F3X0_FMC_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* FMC and option byte definition */
|
||||
#define FMC FMC_BASE /*!< FMC register base address */
|
||||
#define OB OB_BASE /*!< option byte base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FMC_WS REG32(FMC + 0x00000000U) /*!< FMC wait state register */
|
||||
#define FMC_KEY REG32(FMC + 0x00000004U) /*!< FMC unlock key register */
|
||||
#define FMC_OBKEY REG32(FMC + 0x00000008U) /*!< FMC option bytes unlock key register */
|
||||
#define FMC_STAT REG32(FMC + 0x0000000CU) /*!< FMC status register */
|
||||
#define FMC_CTL REG32(FMC + 0x00000010U) /*!< FMC control register */
|
||||
#define FMC_ADDR REG32(FMC + 0x00000014U) /*!< FMC address register */
|
||||
#define FMC_OBSTAT REG32(FMC + 0x0000001CU) /*!< FMC option bytes status register */
|
||||
#define FMC_WP REG32(FMC + 0x00000020U) /*!< FMC write protection register */
|
||||
#define FMC_WSEN REG32(FMC + 0x000000FCU) /*!< FMC wait state enable register */
|
||||
#define FMC_PID REG32(FMC + 0x00000100U) /*!< FMC product ID register */
|
||||
|
||||
#define OB_SPC REG16(OB + 0x00000000U) /*!< option byte security protection value */
|
||||
#define OB_USER REG16(OB + 0x00000002U) /*!< option byte user value*/
|
||||
#define OB_DATA0 REG16(OB + 0x00000004U) /*!< option byte data bit[7:0] value*/
|
||||
#define OB_DATA1 REG16(OB + 0x00000006U) /*!< option byte data bit[15:8] value*/
|
||||
#define OB_WP0 REG16(OB + 0x00000008U) /*!< option byte write protection 0 */
|
||||
#define OB_WP1 REG16(OB + 0x0000000AU) /*!< option byte write protection 1 */
|
||||
|
||||
/* bits definitions */
|
||||
/* FMC_WS */
|
||||
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
|
||||
|
||||
/* FMC_KEY */
|
||||
#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */
|
||||
|
||||
/* FMC_OBKEY */
|
||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
|
||||
|
||||
/* FMC_STAT */
|
||||
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */
|
||||
#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL */
|
||||
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
|
||||
#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */
|
||||
#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */
|
||||
#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */
|
||||
#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */
|
||||
#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL_LK BIT(7) /*!< flash lock bit */
|
||||
#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
|
||||
#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */
|
||||
|
||||
/* FMC_ADDR */
|
||||
#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */
|
||||
|
||||
/* FMC_OBSTAT */
|
||||
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */
|
||||
#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */
|
||||
#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */
|
||||
#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */
|
||||
#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */
|
||||
|
||||
/* FMC_WSEN */
|
||||
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
||||
#define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */
|
||||
|
||||
/* FMC_PID */
|
||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* fmc state */
|
||||
typedef enum
|
||||
{
|
||||
FMC_READY, /*!< the operation has been completed */
|
||||
FMC_BUSY, /*!< the operation is in progress */
|
||||
FMC_PGERR, /*!< program error */
|
||||
FMC_WPERR, /*!< erase/program protection error */
|
||||
FMC_TOERR, /*!< timeout error */
|
||||
FMC_OB_HSPC /*!< option byte security protection code high */
|
||||
}fmc_state_enum;
|
||||
|
||||
/* option byte parameter */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t spc; /*!< option byte parameter spc */
|
||||
uint8_t user; /*!< option byte parameter user */
|
||||
uint8_t data0; /*!< option byte parameter data0 */
|
||||
uint8_t data1; /*!< option byte parameter data1 */
|
||||
uint8_t wp0; /*!< option byte parameter wp0 */
|
||||
uint8_t wp1; /*!< option byte parameter wp1 */
|
||||
}ob_parm_struct;
|
||||
|
||||
/* unlock key */
|
||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||
|
||||
/* wait state counter value */
|
||||
#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */
|
||||
#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */
|
||||
#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */
|
||||
|
||||
/* read protect configure */
|
||||
#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
|
||||
#define FMC_LSPC ((uint8_t)0xBBU) /*!< low security protection, any value except 0xA5 or 0xCC */
|
||||
#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */
|
||||
|
||||
/* option byte write protection */
|
||||
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
|
||||
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
|
||||
|
||||
#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */
|
||||
#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */
|
||||
#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */
|
||||
#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */
|
||||
#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */
|
||||
#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */
|
||||
|
||||
/* option byte security protection level in FMC_OBSTAT register */
|
||||
#define OB_OBSTAT_PLEVEL_NO ((uint32_t)0x00000000U) /*!< no security protection */
|
||||
#define OB_OBSTAT_PLEVEL_LOW ((uint32_t)0x00000002U) /*!< low security protection */
|
||||
#define OB_OBSTAT_PLEVEL_HIGH ((uint32_t)0x00000006U) /*!< high security protection */
|
||||
|
||||
#define OB_USER_DEFAULT ((uint8_t)0xDFU) /*!< OB_USER default value */
|
||||
|
||||
/* option byte parameter address */
|
||||
#define OB_SPC_ADDR (uint32_t)(OB + 0x00000000U)/*!< option byte spc address */
|
||||
#define OB_USER_ADDR (uint32_t)(OB + 0x00000002U)/*!< option byte user address */
|
||||
#define OB_DATA_ADDR0 (uint32_t)(OB + 0x00000004U)/*!< option byte data address 0 */
|
||||
#define OB_DATA_ADDR1 (uint32_t)(OB + 0x00000006U)/*!< option byte data address 1 */
|
||||
#define OB_WP_ADDR0 (uint32_t)(OB + 0x00000008U)/*!< option byte wp address 0 */
|
||||
#define OB_WP_ADDR1 (uint32_t)(OB + 0x0000000AU)/*!< option byte wp address 1 */
|
||||
|
||||
/* FMC flags */
|
||||
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
|
||||
#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
|
||||
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
|
||||
#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
|
||||
|
||||
/* FMC interrupt enable */
|
||||
#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */
|
||||
#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */
|
||||
|
||||
/* FMC time out */
|
||||
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */
|
||||
|
||||
/* function declarations */
|
||||
/* FMC main memory programming functions */
|
||||
/* unlock the main FMC operation */
|
||||
void fmc_unlock(void);
|
||||
/* lock the main FMC operation */
|
||||
void fmc_lock(void);
|
||||
/* set the wait state counter value */
|
||||
void fmc_wscnt_set(uint8_t wscnt);
|
||||
/* fmc wait state enable */
|
||||
void fmc_wait_state_enable(void);
|
||||
/* fmc wait state disable */
|
||||
void fmc_wait_state_disable(void);
|
||||
/* FMC erase page */
|
||||
fmc_state_enum fmc_page_erase(uint32_t page_address);
|
||||
/* FMC erase whole chip */
|
||||
fmc_state_enum fmc_mass_erase(void);
|
||||
/* FMC program a word at the corresponding address */
|
||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||
/* FMC program a half word at the corresponding address */
|
||||
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
|
||||
/* FMC program a word at the corresponding address without erasing */
|
||||
fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data);
|
||||
|
||||
/* FMC option bytes programming functions */
|
||||
/* unlock the option byte operation */
|
||||
void ob_unlock(void);
|
||||
/* lock the option byte operation */
|
||||
void ob_lock(void);
|
||||
/* reload the option byte and generate a system reset */
|
||||
void ob_reset(void);
|
||||
/* erase option byte */
|
||||
fmc_state_enum ob_erase(void);
|
||||
/* enable option byte write protection (OB_WP) */
|
||||
fmc_state_enum ob_write_protection_enable(uint16_t ob_wp);
|
||||
/* configure read out protect */
|
||||
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
|
||||
/* write the FMC option byte user */
|
||||
fmc_state_enum ob_user_write(uint8_t ob_user);
|
||||
/* write the FMC option byte data */
|
||||
fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
|
||||
/* get the FMC option byte OB_USER */
|
||||
uint8_t ob_user_get(void);
|
||||
/* get the FMC option byte OB_DATA */
|
||||
uint16_t ob_data_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint16_t ob_write_protection_get(void);
|
||||
/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
|
||||
uint32_t ob_obstat_plevel_get(void);
|
||||
|
||||
/* FMC interrupts and flags management functions */
|
||||
/* enable FMC interrupt */
|
||||
void fmc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable FMC interrupt */
|
||||
void fmc_interrupt_disable(uint32_t interrupt);
|
||||
/* get flag set or reset */
|
||||
FlagStatus fmc_flag_get(uint32_t flag);
|
||||
/* clear the FMC pending flag */
|
||||
void fmc_flag_clear(uint32_t flag);
|
||||
/* get interrupt flag set or reset */
|
||||
FlagStatus fmc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear the FMC interrupt pending flag */
|
||||
void fmc_interrupt_flag_clear(uint32_t flag);
|
||||
/* return the FMC state */
|
||||
fmc_state_enum fmc_state_get(void);
|
||||
/* check FMC ready or not */
|
||||
fmc_state_enum fmc_ready_wait(uint32_t timeout);
|
||||
/* get current option byte value */
|
||||
void ob_parm_get(ob_parm_struct *ob_parm);
|
||||
/* modify the target option byte depending on the original value */
|
||||
void ob_value_modify(uint32_t address, uint16_t value,ob_parm_struct *ob_parm);
|
||||
|
||||
#endif /* GD32F3X0_FMC_H */
|
||||
@@ -0,0 +1,124 @@
|
||||
/*!
|
||||
\file gd32f3x0_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F3X0_FWDGT_H
|
||||
#define GD32F3X0_FWDGT_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32(FWDGT + 0x00000000U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32(FWDGT + 0x00000004U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32(FWDGT + 0x00000008U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32(FWDGT + 0x0000000CU) /*!< FWDGT status register */
|
||||
#define FWDGT_WND REG32(FWDGT + 0x00000010U) /*!< FWDGT window register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
|
||||
|
||||
/* FWDGT_WND */
|
||||
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
|
||||
|
||||
/* constants definitions */
|
||||
/* FWDGT_CTL register value */
|
||||
#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_CTL_CMD bit field */
|
||||
|
||||
/* FWDGT_PSC register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* FWDGT_RLD register value */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_RLD_RLD bit field */
|
||||
|
||||
/* FWDGT_WND register value */
|
||||
#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) /*!< write value to FWDGT_WND_WND bit field */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
|
||||
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* configure the free watchdog timer counter window value */
|
||||
ErrStatus fwdgt_window_value_config(uint16_t window_value);
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32F3X0_FWDGT_H */
|
||||
@@ -0,0 +1,408 @@
|
||||
/*!
|
||||
\file gd32f3x0_gpio.h
|
||||
\brief definitions for the GPIO
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_GPIO_H
|
||||
#define GD32F3X0_GPIO_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* GPIOx(x=A,B,C,D,F) definitions */
|
||||
#define GPIOA (GPIO_BASE + 0x00000000U)
|
||||
#define GPIOB (GPIO_BASE + 0x00000400U)
|
||||
#define GPIOC (GPIO_BASE + 0x00000800U)
|
||||
#define GPIOD (GPIO_BASE + 0x00000C00U)
|
||||
#define GPIOF (GPIO_BASE + 0x00001400U)
|
||||
|
||||
/* registers definitions */
|
||||
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00000000U) /*!< GPIO port control register */
|
||||
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x00000004U) /*!< GPIO port output mode register */
|
||||
#define GPIO_OSPD0(gpiox) REG32((gpiox) + 0x00000008U) /*!< GPIO port output speed register 0 */
|
||||
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0000000CU) /*!< GPIO port pull-up/pull-down register */
|
||||
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x00000010U) /*!< GPIO port input status register */
|
||||
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x00000014U) /*!< GPIO port output control register */
|
||||
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x00000018U) /*!< GPIO port bit operation register */
|
||||
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x0000001CU) /*!< GPIO port configuration lock register */
|
||||
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x00000020U) /*!< GPIO alternate function selected register 0 */
|
||||
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x00000024U) /*!< GPIO alternate function selected register 1 */
|
||||
#define GPIO_BC(gpiox) REG32((gpiox) + 0x00000028U) /*!< GPIO bit clear register */
|
||||
#define GPIO_TG(gpiox) REG32((gpiox) + 0x0000002CU) /*!< GPIO port bit toggle register */
|
||||
#define GPIO_OSPD1(gpiox) REG32((gpiox) + 0x0000003CU) /*!< GPIO port output speed register 1 */
|
||||
|
||||
/* bits definitions */
|
||||
/* GPIO_CTL */
|
||||
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
|
||||
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
|
||||
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
|
||||
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
|
||||
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
|
||||
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
|
||||
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
|
||||
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
|
||||
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
|
||||
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
|
||||
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
|
||||
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
|
||||
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
|
||||
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
|
||||
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
|
||||
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
|
||||
|
||||
/* GPIO_OMODE */
|
||||
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
|
||||
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
|
||||
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
|
||||
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
|
||||
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
|
||||
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
|
||||
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
|
||||
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
|
||||
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
|
||||
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
|
||||
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
|
||||
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
|
||||
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
|
||||
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
|
||||
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
|
||||
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
|
||||
|
||||
/* GPIO_OSPD0 */
|
||||
#define GPIO_OSPD0_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
|
||||
#define GPIO_OSPD0_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
|
||||
|
||||
/* GPIO_PUD */
|
||||
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
|
||||
|
||||
/* GPIO_ISTAT */
|
||||
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
|
||||
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
|
||||
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
|
||||
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
|
||||
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
|
||||
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
|
||||
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
|
||||
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
|
||||
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
|
||||
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
|
||||
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
|
||||
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
|
||||
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
|
||||
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
|
||||
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
|
||||
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
||||
|
||||
/* GPIO_OCTL */
|
||||
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
|
||||
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
|
||||
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
|
||||
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
|
||||
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
|
||||
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
|
||||
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
|
||||
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
|
||||
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
|
||||
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
|
||||
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
|
||||
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
|
||||
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
|
||||
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
|
||||
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
|
||||
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
|
||||
|
||||
/* GPIO_BOP */
|
||||
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
||||
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
|
||||
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
|
||||
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
|
||||
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
|
||||
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
|
||||
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
|
||||
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
|
||||
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
|
||||
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
|
||||
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
|
||||
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
|
||||
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
|
||||
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
|
||||
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
|
||||
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
|
||||
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
|
||||
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
|
||||
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
|
||||
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
|
||||
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
|
||||
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
|
||||
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
|
||||
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
|
||||
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
|
||||
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
|
||||
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
|
||||
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
|
||||
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
|
||||
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
|
||||
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
|
||||
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_LOCK */
|
||||
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
|
||||
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
|
||||
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
|
||||
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
|
||||
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
|
||||
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
|
||||
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
|
||||
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
|
||||
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
|
||||
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
|
||||
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
|
||||
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
|
||||
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
|
||||
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
||||
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
||||
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
||||
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
|
||||
|
||||
/* GPIO_AFSEL0 */
|
||||
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
|
||||
|
||||
/* GPIO_AFSEL1 */
|
||||
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
|
||||
|
||||
/* GPIO_BC */
|
||||
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
|
||||
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
|
||||
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
|
||||
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
|
||||
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
|
||||
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
|
||||
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
|
||||
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
|
||||
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
|
||||
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
|
||||
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
|
||||
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
|
||||
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
|
||||
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
|
||||
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
|
||||
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_TG */
|
||||
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
|
||||
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
|
||||
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
|
||||
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
|
||||
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
|
||||
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
|
||||
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
|
||||
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
|
||||
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
|
||||
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
|
||||
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
|
||||
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
|
||||
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
|
||||
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
|
||||
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
|
||||
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
|
||||
|
||||
/* GPIO_OSPD1 */
|
||||
#define GPIO_OSPD1_SPD0 BIT(0) /*!< set pin 0 very high output speed when OSPD0 is "11" */
|
||||
#define GPIO_OSPD1_SPD1 BIT(1) /*!< set pin 1 very high output speed when OSPD1 is "11" */
|
||||
#define GPIO_OSPD1_SPD2 BIT(2) /*!< set pin 2 very high output speed when OSPD2 is "11" */
|
||||
#define GPIO_OSPD1_SPD3 BIT(3) /*!< set pin 3 very high output speed when OSPD3 is "11" */
|
||||
#define GPIO_OSPD1_SPD4 BIT(4) /*!< set pin 4 very high output speed when OSPD4 is "11" */
|
||||
#define GPIO_OSPD1_SPD5 BIT(5) /*!< set pin 5 very high output speed when OSPD5 is "11" */
|
||||
#define GPIO_OSPD1_SPD6 BIT(6) /*!< set pin 6 very high output speed when OSPD6 is "11" */
|
||||
#define GPIO_OSPD1_SPD7 BIT(7) /*!< set pin 7 very high output speed when OSPD7 is "11" */
|
||||
#define GPIO_OSPD1_SPD8 BIT(8) /*!< set pin 8 very high output speed when OSPD8 is "11" */
|
||||
#define GPIO_OSPD1_SPD9 BIT(9) /*!< set pin 9 very high output speed when OSPD9 is "11" */
|
||||
#define GPIO_OSPD1_SPD10 BIT(10) /*!< set pin 10 very high output speed when OSPD10 is "11" */
|
||||
#define GPIO_OSPD1_SPD11 BIT(11) /*!< set pin 11 very high output speed when OSPD11 is "11" */
|
||||
#define GPIO_OSPD1_SPD12 BIT(12) /*!< set pin 12 very high output speed when OSPD12 is "11" */
|
||||
#define GPIO_OSPD1_SPD13 BIT(13) /*!< set pin 13 very high output speed when OSPD13 is "11" */
|
||||
#define GPIO_OSPD1_SPD14 BIT(14) /*!< set pin 14 very high output speed when OSPD14 is "11" */
|
||||
#define GPIO_OSPD1_SPD15 BIT(15) /*!< set pin 15 very high output speed when OSPD15 is "11" */
|
||||
|
||||
/* constants definitions */
|
||||
typedef FlagStatus bit_status;
|
||||
|
||||
/* output mode definitions */
|
||||
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
|
||||
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
|
||||
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
|
||||
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
|
||||
|
||||
/* pull-up/pull-down definitions */
|
||||
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */
|
||||
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */
|
||||
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */
|
||||
|
||||
/* GPIO pin definitions */
|
||||
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
|
||||
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
|
||||
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
|
||||
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
|
||||
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
|
||||
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
|
||||
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
|
||||
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
|
||||
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
|
||||
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
|
||||
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
|
||||
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
|
||||
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
|
||||
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
|
||||
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
|
||||
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
|
||||
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
|
||||
|
||||
/* GPIO mode configuration values */
|
||||
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
|
||||
#define GPIO_MODE_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n))))
|
||||
|
||||
/* GPIO pull-up/pull-down values */
|
||||
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
|
||||
#define GPIO_PUPD_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n))))
|
||||
|
||||
/* GPIO output speed values */
|
||||
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
|
||||
#define GPIO_OSPEED_MASK(n) ((uint32_t)((uint32_t)0x00000003U << (2U * (n))))
|
||||
|
||||
/* GPIO output type */
|
||||
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
|
||||
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
|
||||
|
||||
/* GPIO output max speed value */
|
||||
#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */
|
||||
#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */
|
||||
#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */
|
||||
#define GPIO_OSPEED_MAX ((uint32_t)0x0000FFFFU) /*!< GPIO very high output speed, max speed more than 50MHz */
|
||||
|
||||
/* GPIO alternate function values */
|
||||
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
|
||||
#define GPIO_AFR_MASK(n) ((uint32_t)((uint32_t)0x0000000FU << (4U * (n))))
|
||||
|
||||
/* GPIO alternate function */
|
||||
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
|
||||
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
|
||||
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */
|
||||
#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */
|
||||
#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */
|
||||
#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */
|
||||
#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */
|
||||
#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */
|
||||
|
||||
/* function declarations */
|
||||
/* reset GPIO port */
|
||||
void gpio_deinit(uint32_t gpio_periph);
|
||||
/* set GPIO mode */
|
||||
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
|
||||
/* set GPIO output type and speed */
|
||||
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
|
||||
|
||||
/* set GPIO pin bit */
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
|
||||
/* reset GPIO pin bit */
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
|
||||
/* write data to the specified GPIO pin */
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
|
||||
/* write data to the specified GPIO port */
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
|
||||
|
||||
/* get GPIO pin input status */
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port input status */
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph);
|
||||
/* get GPIO pin output status */
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port output status */
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph);
|
||||
|
||||
/* set GPIO alternate function */
|
||||
void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin);
|
||||
/* lock GPIO pin bit */
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
|
||||
|
||||
/* toggle GPIO pin status */
|
||||
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
|
||||
/* toggle GPIO port status */
|
||||
void gpio_port_toggle(uint32_t gpio_periph);
|
||||
|
||||
#endif /* GD32F3X0_GPIO_H */
|
||||
@@ -0,0 +1,347 @@
|
||||
/*!
|
||||
\file gd32f3x0_i2c.h
|
||||
\brief definitions for the I2C
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F3X0_I2C_H
|
||||
#define GD32F3X0_I2C_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* I2Cx(x=0,1) definitions */
|
||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||
#define I2C1 (I2C_BASE+0x00000400U) /*!< I2C1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
|
||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
|
||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/
|
||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register */
|
||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
|
||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
|
||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
|
||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
|
||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
|
||||
#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast-mode-plus configure register */
|
||||
|
||||
/* bits definitions */
|
||||
/* I2Cx_CTL0 */
|
||||
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
||||
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
||||
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
||||
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
||||
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
||||
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
||||
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
||||
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
||||
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
||||
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
||||
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
||||
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
||||
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
||||
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
||||
|
||||
/* I2Cx_CTL1 */
|
||||
#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */
|
||||
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt inable */
|
||||
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
||||
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
||||
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
||||
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
||||
|
||||
/* I2Cx_SADDR0 */
|
||||
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
||||
|
||||
/* I2Cx_SADDR1 */
|
||||
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
||||
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
||||
|
||||
/* I2Cx_DATA */
|
||||
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
||||
|
||||
/* I2Cx_STAT0 */
|
||||
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
||||
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
||||
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
||||
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
||||
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
||||
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
||||
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
||||
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
||||
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
||||
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
||||
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
||||
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
||||
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
||||
|
||||
/* I2Cx_STAT1 */
|
||||
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
||||
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
||||
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
||||
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
||||
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
||||
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
||||
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
||||
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
||||
|
||||
/* I2Cx_CKCFG */
|
||||
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */
|
||||
#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */
|
||||
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
||||
|
||||
/* I2Cx_RT */
|
||||
#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */
|
||||
|
||||
/* I2Cx_FMPCFG */
|
||||
#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the I2C bit position and its register index offset */
|
||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
|
||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define I2C_CTL1_REG_OFFSET (0x00000004U) /*!< CTL1 register offset */
|
||||
#define I2C_STAT0_REG_OFFSET (0x00000014U) /*!< STAT0 register offset */
|
||||
#define I2C_STAT1_REG_OFFSET (0x00000018U) /*!< STAT1 register offset */
|
||||
/* I2C flags */
|
||||
typedef enum
|
||||
{
|
||||
/* flags in STAT0 register */
|
||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */
|
||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||
/* flags in STAT1 register */
|
||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U) /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||
}i2c_flag_enum;
|
||||
|
||||
/* I2C interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt flags in CTL1 register */
|
||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving interrupt flag */
|
||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */
|
||||
}i2c_interrupt_flag_enum;
|
||||
|
||||
/* I2C interrupt enable or disable */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt in CTL1 register */
|
||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */
|
||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */
|
||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */
|
||||
}i2c_interrupt_enum;
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
||||
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
||||
|
||||
/* I2C transfer direction */
|
||||
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
||||
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
||||
|
||||
/* whether or not to send an ACK */
|
||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||
#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */
|
||||
|
||||
/* I2C POAP position*/
|
||||
#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||
|
||||
/* whether or not to stretch SCL low */
|
||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is enabled */
|
||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is disabled */
|
||||
|
||||
/* whether or not to response to a general call */
|
||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||
|
||||
/* software reset I2C */
|
||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||
|
||||
/* I2C DMA mode configure */
|
||||
/* DMA mode switch */
|
||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */
|
||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */
|
||||
|
||||
/* flag indicating DMA last transfer */
|
||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||
|
||||
/* I2C PEC configure */
|
||||
/* PEC enable */
|
||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||
|
||||
/* PEC transfer */
|
||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */
|
||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||
|
||||
/* I2C SMBus configure */
|
||||
/* issue or not alert through SMBA pin */
|
||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||
|
||||
/* ARP protocol in SMBus switch */
|
||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */
|
||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */
|
||||
|
||||
/* fast mode plus enable */
|
||||
#define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */
|
||||
#define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */
|
||||
|
||||
/* transmit I2C data */
|
||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* receive I2C data */
|
||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||
|
||||
/* I2C duty cycle in fast mode or fast mode plus */
|
||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */
|
||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */
|
||||
|
||||
/* address mode for the I2C slave */
|
||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */
|
||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */
|
||||
|
||||
/* function declarations */
|
||||
/* reset I2C */
|
||||
void i2c_deinit(uint32_t i2c_periph);
|
||||
/* configure I2C clock */
|
||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||
/* configure I2C address */
|
||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
||||
/* SMBus type selection */
|
||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||
/* whether or not to send an ACK */
|
||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||
/* configure I2C position of ACK and PEC when receiving */
|
||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
||||
/* master sends slave address */
|
||||
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
|
||||
/* enable dual-address mode */
|
||||
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
|
||||
/* disable dual-address mode */
|
||||
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||
/* enable I2C */
|
||||
void i2c_enable(uint32_t i2c_periph);
|
||||
/* disable I2C */
|
||||
void i2c_disable(uint32_t i2c_periph);
|
||||
|
||||
/* generate a START condition on I2C bus */
|
||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||
/* generate a STOP condition on I2C bus */
|
||||
void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||
/* I2C transmit data function */
|
||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||
/* I2C receive data function */
|
||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||
/* enable I2C DMA mode */
|
||||
void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate);
|
||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||
/* whether or not to response to a general call */
|
||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||
/* software reset I2C */
|
||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||
|
||||
/* whether to enable I2C PEC calculation or not */
|
||||
void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate);
|
||||
/* I2C whether to transfer PEC value */
|
||||
void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara);
|
||||
/* packet error checking value */
|
||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||
/* I2C issue alert through SMBA pin */
|
||||
void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara);
|
||||
/* whether ARP is enabled under SMBus */
|
||||
void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate);
|
||||
|
||||
/* check I2C flag is set or not */
|
||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* clear I2C flag */
|
||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* enable I2C interrupt */
|
||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* disable I2C interrupt */
|
||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* check I2C interrupt flag */
|
||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
/* clear I2C interrupt flag */
|
||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
#endif /* GD32F3X0_I2C_H */
|
||||
@@ -0,0 +1,92 @@
|
||||
/*!
|
||||
\file gd32f3x0_misc.h
|
||||
\brief definitions for the MISC
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_MISC_H
|
||||
#define GD32F3X0_MISC_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* set the RAM and FLASH base address */
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
|
||||
|
||||
/* set the NVIC vector table offset mask */
|
||||
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */
|
||||
|
||||
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
|
||||
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */
|
||||
|
||||
/* priority group - define the pre-emption priority and the subpriority */
|
||||
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x00000700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x00000600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x00000500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x00000400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
|
||||
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x00000300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
|
||||
|
||||
/* choose the method to enter or exit the lowpower mode */
|
||||
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
|
||||
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
|
||||
|
||||
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */
|
||||
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */
|
||||
|
||||
/* choose the systick clock source */
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
|
||||
|
||||
/* function declarations */
|
||||
/* set the priority group */
|
||||
void nvic_priority_group_set(uint32_t nvic_prigroup);
|
||||
|
||||
/* enable NVIC request */
|
||||
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
|
||||
/* disable NVIC request */
|
||||
void nvic_irq_disable(uint8_t nvic_irq);
|
||||
|
||||
/* set the NVIC vector table base address */
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
|
||||
|
||||
/* set the state of the low power mode */
|
||||
void system_lowpower_set(uint8_t lowpower_mode);
|
||||
/* reset the state of the low power mode */
|
||||
void system_lowpower_reset(uint8_t lowpower_mode);
|
||||
|
||||
/* set the systick clock source */
|
||||
void systick_clksource_set(uint32_t systick_clksource);
|
||||
|
||||
#endif /* GD32F3X0_MISC_H */
|
||||
@@ -0,0 +1,197 @@
|
||||
/*!
|
||||
\file gd32f3x0_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_PMU_H
|
||||
#define GD32F3X0_PMU_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32(PMU + 0x00000000U) /*!< PMU control register */
|
||||
#define PMU_CS REG32(PMU + 0x00000004U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */
|
||||
#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */
|
||||
#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
|
||||
#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */
|
||||
#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */
|
||||
#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN4 BIT(12) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */
|
||||
#define PMU_CS_LDOVSRF BIT(15) /*!< LDO voltage select ready flag */
|
||||
#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */
|
||||
#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */
|
||||
#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
|
||||
|
||||
/* PMU LDO output voltage select definitions */
|
||||
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
|
||||
#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */
|
||||
#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */
|
||||
#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */
|
||||
|
||||
/* PMU low-driver mode enable in deep-sleep mode */
|
||||
#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
||||
#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */
|
||||
#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */
|
||||
|
||||
/* PMU high-driver mode switch */
|
||||
#define PMU_HIGHDR_SWITCH_NONE ((uint32_t)0x00000000U) /*!< no high-driver mode switch */
|
||||
#define PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS /*!< high-driver mode switch */
|
||||
|
||||
/* PMU low-driver mode when use normal power LDO */
|
||||
#define PMU_NORMALDR_NORMALPWR ((uint32_t)0x00000000U) /*!< normal-driver when use normal power LDO */
|
||||
#define PMU_LOWDR_NORMALPWR PMU_CTL_LDNP /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
|
||||
|
||||
/* PMU low-driver mode when use low power LDO */
|
||||
#define PMU_NORMALDR_LOWPWR ((uint32_t)0x00000000U) /*!< normal-driver when use low power LDO */
|
||||
#define PMU_LOWDR_LOWPWR PMU_CTL_LDLP /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */
|
||||
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU low power mode ready flag definitions */
|
||||
#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
||||
#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal-driver in deep-sleep mode */
|
||||
#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */
|
||||
#define PMU_FLAG_LDOVSR PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */
|
||||
#define PMU_FLAG_HDR PMU_CS_HDRF /*!< high-driver ready flag */
|
||||
#define PMU_FLAG_HDSR PMU_CS_HDSRF /*!< high-driver switch ready flag */
|
||||
#define PMU_FLAG_LDR PMU_CS_LDRF /*!< low-driver mode ready flag */
|
||||
|
||||
/* PMU WKUP pin definitions */
|
||||
#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
|
||||
#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */
|
||||
#define PMU_WAKEUP_PIN4 PMU_CS_WUPEN4 /*!< WKUP Pin 4 (PC5) enable */
|
||||
#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */
|
||||
#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* function configuration */
|
||||
/* reset PMU registers */
|
||||
void pmu_deinit(void);
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* select LDO output voltage */
|
||||
void pmu_ldo_output_select(uint32_t ldo_output);
|
||||
/* disable PMU lvd */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* functions of low-driver mode and high-driver mode in deep-sleep mode */
|
||||
/* enable low-driver mode in deep-sleep mode */
|
||||
void pmu_lowdriver_mode_enable(void);
|
||||
/* disable low-driver mode in deep-sleep mode */
|
||||
void pmu_lowdriver_mode_disable(void);
|
||||
/* enable high-driver mode */
|
||||
void pmu_highdriver_mode_enable(void);
|
||||
/* disable high-driver mode */
|
||||
void pmu_highdriver_mode_disable(void);
|
||||
/* switch high-driver mode */
|
||||
void pmu_highdriver_switch_select(uint32_t highdr_switch);
|
||||
/* in deep-sleep mode, low-driver mode when use low power LDO */
|
||||
void pmu_lowpower_driver_config(uint32_t mode);
|
||||
/* in deep-sleep mode, low-driver mode when use normal power LDO */
|
||||
void pmu_normalpower_driver_config(uint32_t mode);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work in sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work in deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work in standby mode */
|
||||
void pmu_to_standbymode(uint8_t standbymodecmd);
|
||||
/* enable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
|
||||
/* disable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
|
||||
|
||||
/* backup related functions */
|
||||
/* enable backup domain write */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* disable backup domain write */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* clear flag bit */
|
||||
void pmu_flag_clear(uint32_t flag_clear);
|
||||
/* get flag state */
|
||||
FlagStatus pmu_flag_get(uint32_t flag);
|
||||
|
||||
#endif /* GD32F3X0_PMU_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,368 @@
|
||||
/*!
|
||||
\file gd32f3x0_spi.h
|
||||
\brief definitions for the SPI
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_SPI_H
|
||||
#define GD32F3X0_SPI_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* SPIx(x=0,1) definitions */
|
||||
#define SPI0 (SPI_BASE + 0x0000F800U)
|
||||
#define SPI1 SPI_BASE
|
||||
|
||||
/* SPI registers definitions */
|
||||
#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
|
||||
#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
|
||||
#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
|
||||
#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
|
||||
#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
|
||||
#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
|
||||
#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
|
||||
#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
|
||||
#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
|
||||
#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only SPI1) */
|
||||
|
||||
/* bits definitions */
|
||||
/* SPI_CTL0 */
|
||||
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
|
||||
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
|
||||
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
|
||||
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
|
||||
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
|
||||
#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */
|
||||
#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */
|
||||
#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */
|
||||
#define SPI_CTL0_RO BIT(10) /*!< receive only */
|
||||
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
|
||||
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
|
||||
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
|
||||
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
|
||||
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
|
||||
|
||||
/* SPI_CTL1 */
|
||||
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */
|
||||
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */
|
||||
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */
|
||||
#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */
|
||||
#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
|
||||
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
|
||||
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
|
||||
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
|
||||
|
||||
/* SPI_STAT */
|
||||
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
|
||||
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
|
||||
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
|
||||
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
|
||||
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
|
||||
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
|
||||
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
|
||||
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
|
||||
#define SPI_STAT_FERR BIT(8) /*!< format error bit */
|
||||
|
||||
/* SPI_DATA */
|
||||
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
|
||||
|
||||
/* SPI_CRCPOLY */
|
||||
#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */
|
||||
|
||||
/* SPI_RCRC */
|
||||
#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */
|
||||
|
||||
/* SPI_TCRC */
|
||||
#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */
|
||||
|
||||
/* SPI_I2SCTL */
|
||||
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
|
||||
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
|
||||
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
|
||||
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
|
||||
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
|
||||
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
|
||||
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
|
||||
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
|
||||
|
||||
/* SPI_I2SPSC */
|
||||
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
|
||||
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
|
||||
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
|
||||
|
||||
/* SPI_QCTL(only for SPI1) */
|
||||
#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
|
||||
#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
|
||||
#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* SPI and I2S parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t device_mode; /*!< SPI master or slave */
|
||||
uint32_t trans_mode; /*!< SPI transtype */
|
||||
uint32_t frame_size; /*!< SPI frame size */
|
||||
uint32_t nss; /*!< SPI NSS control by handware or software */
|
||||
uint32_t endian; /*!< SPI big endian or little endian */
|
||||
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
|
||||
uint32_t prescale; /*!< SPI prescale factor */
|
||||
}spi_parameter_struct;
|
||||
|
||||
/* SPI mode definitions */
|
||||
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
|
||||
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||
|
||||
/* SPI bidirectional transfer direction */
|
||||
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
|
||||
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
|
||||
|
||||
/* SPI transmit type */
|
||||
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
|
||||
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
|
||||
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
|
||||
|
||||
/* SPI frame size */
|
||||
#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
|
||||
#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
|
||||
|
||||
/* SPI NSS control mode */
|
||||
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */
|
||||
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
|
||||
|
||||
/* SPI transmit way */
|
||||
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||
|
||||
/* SPI clock phase and polarity */
|
||||
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||
|
||||
/* SPI clock prescale factor */
|
||||
#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */
|
||||
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */
|
||||
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */
|
||||
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */
|
||||
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */
|
||||
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */
|
||||
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */
|
||||
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */
|
||||
|
||||
#ifdef GD32F350
|
||||
/* I2S audio sample rate */
|
||||
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||
|
||||
/* I2S frame format */
|
||||
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||
|
||||
/* I2S master clock output */
|
||||
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
|
||||
|
||||
/* I2S operation mode */
|
||||
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||
|
||||
/* I2S standard */
|
||||
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
|
||||
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||
|
||||
/* I2S clock polarity */
|
||||
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||
#endif /* GD32F350 */
|
||||
|
||||
/* SPI DMA constants definitions */
|
||||
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||
|
||||
/* SPI CRC constants definitions */
|
||||
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||
|
||||
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||
#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */
|
||||
#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */
|
||||
#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */
|
||||
|
||||
/* SPI/I2S interrupt flag constants definitions */
|
||||
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
|
||||
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
|
||||
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
|
||||
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
|
||||
|
||||
/* SPI flag definitions */
|
||||
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
|
||||
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
|
||||
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */
|
||||
|
||||
#ifdef GD32F350
|
||||
/* I2S flag definitions */
|
||||
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
|
||||
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */
|
||||
#endif /* GD32F350 */
|
||||
|
||||
/* function declarations */
|
||||
/* SPI/I2S deinitialization and initialization functions */
|
||||
/* reset SPI and I2S */
|
||||
void spi_i2s_deinit(uint32_t spi_periph);
|
||||
/* initialize the parameters of SPI struct with the default values */
|
||||
void spi_struct_para_init(spi_parameter_struct* spi_struct);
|
||||
/* initialize SPI parameter */
|
||||
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
|
||||
/* enable SPI */
|
||||
void spi_enable(uint32_t spi_periph);
|
||||
/* disable SPI */
|
||||
void spi_disable(uint32_t spi_periph);
|
||||
|
||||
#ifdef GD32F350
|
||||
/* initialize I2S parameter */
|
||||
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
|
||||
/* configure I2S prescaler */
|
||||
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
|
||||
/* enable I2S */
|
||||
void i2s_enable(uint32_t spi_periph);
|
||||
/* disable I2S */
|
||||
void i2s_disable(uint32_t spi_periph);
|
||||
#endif /* GD32F350 */
|
||||
|
||||
/* NSS functions */
|
||||
/* enable SPI NSS output */
|
||||
void spi_nss_output_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS output */
|
||||
void spi_nss_output_disable(uint32_t spi_periph);
|
||||
/* SPI NSS pin high level in software mode */
|
||||
void spi_nss_internal_high(uint32_t spi_periph);
|
||||
/* SPI NSS pin low level in software mode */
|
||||
void spi_nss_internal_low(uint32_t spi_periph);
|
||||
|
||||
/* enable SPI DMA */
|
||||
void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
|
||||
/* disable SPI DMA */
|
||||
void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
|
||||
|
||||
/* configure SPI/I2S data frame format */
|
||||
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
|
||||
/* SPI transmit data */
|
||||
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
|
||||
/* SPI receive data */
|
||||
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||
/* configure SPI bidirectional transfer direction */
|
||||
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||
|
||||
/* SPI CRC functions */
|
||||
/* set SPI CRC polynomial */
|
||||
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
|
||||
/* get SPI CRC polynomial */
|
||||
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||
/* turn on SPI CRC function */
|
||||
void spi_crc_on(uint32_t spi_periph);
|
||||
/* turn off SPI CRC function */
|
||||
void spi_crc_off(uint32_t spi_periph);
|
||||
/* SPI next data is CRC value */
|
||||
void spi_crc_next(uint32_t spi_periph);
|
||||
/* get SPI CRC send value or receive value */
|
||||
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
|
||||
|
||||
/* SPI TI mode functions */
|
||||
/* enable SPI TI mode */
|
||||
void spi_ti_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI TI mode */
|
||||
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* SPI NSS pulse mode functions */
|
||||
/* enable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* quad wire SPI functions */
|
||||
/* enable quad wire SPI */
|
||||
void qspi_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI */
|
||||
void qspi_disable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI write */
|
||||
void qspi_write_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI read */
|
||||
void qspi_read_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void qspi_io23_output_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void qspi_io23_output_disable(uint32_t spi_periph);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* enable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* disable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S interrupt status */
|
||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S flag status */
|
||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||
/* clear SPI CRC error flag status */
|
||||
void spi_crc_error_clear(uint32_t spi_periph);
|
||||
|
||||
#endif /* GD32F3X0_SPI_H */
|
||||
@@ -0,0 +1,190 @@
|
||||
/*!
|
||||
\file gd32f3x0_syscfg.h
|
||||
\brief definitions for the SYSCFG
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_SYSCFG_H
|
||||
#define GD32F3X0_SYSCFG_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* SYSCFG definitions */
|
||||
#define SYSCFG SYSCFG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SYSCFG_CFG0 REG32(SYSCFG + 0x00000000U) /*!< system configuration register 0 */
|
||||
#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x00000008U) /*!< EXTI sources selection register 0 */
|
||||
#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0000000CU) /*!< EXTI sources selection register 1 */
|
||||
#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x00000010U) /*!< EXTI sources selection register 2 */
|
||||
#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x00000014U) /*!< EXTI sources selection register 3 */
|
||||
#define SYSCFG_CFG2 REG32(SYSCFG + 0x00000018U) /*!< system configuration register 2 */
|
||||
#define SYSCFG_CPSCTL REG32(SYSCFG + 0x00000020U) /*!< system I/O compensation control register */
|
||||
|
||||
/* SYSCFG_CFG0 bits definitions */
|
||||
#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */
|
||||
#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */
|
||||
#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */
|
||||
#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */
|
||||
#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */
|
||||
#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */
|
||||
#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */
|
||||
|
||||
/* SYSCFG_EXTISS0 bits definitions */
|
||||
#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS1 bits definitions */
|
||||
#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS2 bits definitions */
|
||||
#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS3 bits definitions */
|
||||
#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */
|
||||
|
||||
/* SYSCFG_CFG2 bits definitions */
|
||||
#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M4 with break input of TIMER0/14/15/16 */
|
||||
#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */
|
||||
#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */
|
||||
#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */
|
||||
|
||||
/* SYSCFG_CPSCTL bits definitions */
|
||||
#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */
|
||||
#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA remap definitions */
|
||||
#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */
|
||||
|
||||
/* high current definitions */
|
||||
#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */
|
||||
#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */
|
||||
|
||||
/* EXTI source select definition */
|
||||
#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */
|
||||
#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */
|
||||
#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */
|
||||
#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */
|
||||
|
||||
/* EXTI source select mask bits definition */
|
||||
#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */
|
||||
|
||||
/* EXTI source select jumping step definition */
|
||||
#define EXTI_SS_JSTEP ((uint8_t)0x04U) /*!< EXTI source select jumping step */
|
||||
|
||||
/* EXTI source select moving step definition */
|
||||
#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */
|
||||
|
||||
/* EXTI source port definitions */
|
||||
#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */
|
||||
#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */
|
||||
#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */
|
||||
#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */
|
||||
#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */
|
||||
|
||||
/* EXTI source pin definitions */
|
||||
#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */
|
||||
#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */
|
||||
#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */
|
||||
#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */
|
||||
#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */
|
||||
#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */
|
||||
#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */
|
||||
#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */
|
||||
#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */
|
||||
#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */
|
||||
#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */
|
||||
#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */
|
||||
#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */
|
||||
#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */
|
||||
#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */
|
||||
#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */
|
||||
|
||||
/* lock definitions */
|
||||
#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */
|
||||
#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */
|
||||
#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */
|
||||
|
||||
/* SRAM parity check error flag definitions */
|
||||
#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */
|
||||
|
||||
/* I/O compensation cell enable/disable */
|
||||
#define SYSCFG_COMPENSATION(regval) (BIT(0) & ((uint32_t)(regval) << 0))
|
||||
#define SYSCFG_COMPENSATION_DISABLE SYSCFG_COMPENSATION(0) /*!< I/O compensation cell is power-down */
|
||||
#define SYSCFG_COMPENSATION_ENABLE SYSCFG_COMPENSATION(1) /*!< I/O compensation cell is enabled */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit syscfg module */
|
||||
void syscfg_deinit(void);
|
||||
|
||||
/* enable the DMA channels remapping */
|
||||
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap);
|
||||
/* disable the DMA channels remapping */
|
||||
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap);
|
||||
|
||||
/* enable PB9 high current capability */
|
||||
void syscfg_high_current_enable(void);
|
||||
/* disable PB9 high current capability */
|
||||
void syscfg_high_current_disable(void);
|
||||
|
||||
/* configure the GPIO pin as EXTI Line */
|
||||
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
|
||||
/* connect TIMER0/14/15/16 break input to the selected parameter */
|
||||
void syscfg_lock_config(uint32_t syscfg_lock);
|
||||
|
||||
/* check if the specified flag in SYSCFG_CFG2 is set or not */
|
||||
FlagStatus syscfg_flag_get(uint32_t syscfg_flag);
|
||||
/* clear the flag in SYSCFG_CFG2 by writing 1 */
|
||||
void syscfg_flag_clear(uint32_t syscfg_flag);
|
||||
|
||||
/* configure the I/O compensation cell */
|
||||
void syscfg_compensation_config(uint32_t syscfg_compensation);
|
||||
/* check if the I/O compensation cell ready flag is set or not */
|
||||
FlagStatus syscfg_cps_rdy_flag_get(void);
|
||||
|
||||
#endif /* GD32F3X0_SYSCFG_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,396 @@
|
||||
/*!
|
||||
\file gd32f3x0_tsi.h
|
||||
\brief definitions for the TSI
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_TSI_H
|
||||
#define GD32F3X0_TSI_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* TSI definitions */
|
||||
#define TSI TSI_BASE /*!< TSI base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define TSI_CTL0 REG32(TSI + 0x00000000U)/*!< TSI control register0 */
|
||||
#define TSI_INTEN REG32(TSI + 0x00000004U)/*!< TSI interrupt enable register */
|
||||
#define TSI_INTC REG32(TSI + 0x00000008U)/*!< TSI interrupt flag clear register */
|
||||
#define TSI_INTF REG32(TSI + 0x0000000CU)/*!< TSI interrupt flag register */
|
||||
#define TSI_PHM REG32(TSI + 0x00000010U)/*!< TSI pin hysteresis mode register */
|
||||
#define TSI_ASW REG32(TSI + 0x00000018U)/*!< TSI analog switch register */
|
||||
#define TSI_SAMPCFG REG32(TSI + 0x00000020U)/*!< TSI sample configuration register */
|
||||
#define TSI_CHCFG REG32(TSI + 0x00000028U)/*!< TSI channel configuration register */
|
||||
#define TSI_GCTL REG32(TSI + 0x00000030U)/*!< TSI group control register */
|
||||
#define TSI_G0CYCN REG32(TSI + 0x00000034U)/*!< TSI group 0 cycle number register */
|
||||
#define TSI_G1CYCN REG32(TSI + 0x00000038U)/*!< TSI group 1 cycle number register */
|
||||
#define TSI_G2CYCN REG32(TSI + 0x0000003CU)/*!< TSI group 2 cycle number register */
|
||||
#define TSI_G3CYCN REG32(TSI + 0x00000040U)/*!< TSI group 3 cycle number register */
|
||||
#define TSI_G4CYCN REG32(TSI + 0x00000044U)/*!< TSI group 4 cycle number register */
|
||||
#define TSI_G5CYCN REG32(TSI + 0x00000048U)/*!< TSI group 5 cycle number register */
|
||||
#define TSI_CTL1 REG32(TSI + 0x00000300U)/*!< TSI control registers1 */
|
||||
|
||||
/* bits definitions */
|
||||
/* TSI_CTL0 */
|
||||
#define TSI_CTL0_TSIEN BIT(0) /*!< TSI enable */
|
||||
#define TSI_CTL0_TSIS BIT(1) /*!< TSI start */
|
||||
#define TSI_CTL0_TRGMOD BIT(2) /*!< trigger mode selection */
|
||||
#define TSI_CTL0_EGSEL BIT(3) /*!< edge selection */
|
||||
#define TSI_CTL0_PINMOD BIT(4) /*!< pin mode */
|
||||
#define TSI_CTL0_MCN BITS(5,7) /*!< max cycle number of a sequence */
|
||||
#define TSI_CTL0_CTCDIV BITS(12,14) /*!< CTCLK clock division factor */
|
||||
#define TSI_CTL0_ECDIV BIT(15) /*!< ECCLK clock division factor */
|
||||
#define TSI_CTL0_ECEN BIT(16) /*!< extend charge state enable */
|
||||
#define TSI_CTL0_ECDT BITS(17,23) /*!< extend charge State maximum duration time */
|
||||
#define TSI_CTL0_CTDT BITS(24,27) /*!< charge transfer state duration time */
|
||||
#define TSI_CTL0_CDT BITS(28,31) /*!< charge state duration time */
|
||||
|
||||
/* TSI_INTEN */
|
||||
#define TSI_INTEN_CTCFIE BIT(0) /*!< charge transfer complete flag interrupt enable */
|
||||
#define TSI_INTEN_MNERRIE BIT(1) /*!< max cycle number error interrupt enable */
|
||||
|
||||
/* TSI_INTC */
|
||||
#define TSI_INTC_CCTCF BIT(0) /*!< clear charge transfer complete flag */
|
||||
#define TSI_INTC_CMNERR BIT(1) /*!< clear max cycle number error */
|
||||
|
||||
/* TSI_INTF */
|
||||
#define TSI_INTF_CTCF BIT(0) /*!< charge transfer complete flag */
|
||||
#define TSI_INTF_MNERR BIT(1) /*!< max cycle number error */
|
||||
|
||||
/* TSI_PHM */
|
||||
#define TSI_PHM_G0P0 BIT(0) /*!< pin G0P0 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G0P1 BIT(1) /*!< pin G0P1 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G0P2 BIT(2) /*!< pin G0P2 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G0P3 BIT(3) /*!< pin G0P3 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G1P0 BIT(4) /*!< pin G1P0 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G1P1 BIT(5) /*!< pin G1P1 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G1P2 BIT(6) /*!< pin G1P2 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G1P3 BIT(7) /*!< pin G1P3 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G2P0 BIT(8) /*!< pin G2P0 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G2P1 BIT(9) /*!< pin G2P1 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G2P2 BIT(10) /*!< pin G2P2 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G2P3 BIT(11) /*!< pin G2P3 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G3P0 BIT(12) /*!< pin G3P0 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G3P1 BIT(13) /*!< pin G3P1 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G3P2 BIT(14) /*!< pin G3P2 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G3P3 BIT(15) /*!< pin G3P3 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G4P0 BIT(16) /*!< pin G4P0 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G4P1 BIT(17) /*!< pin G4P1 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G4P2 BIT(18) /*!< pin G4P2 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G4P3 BIT(19) /*!< pin G4P3 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G5P0 BIT(20) /*!< pin G5P0 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G5P1 BIT(21) /*!< pin G5P1 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G5P2 BIT(22) /*!< pin G5P2 Schmitt trigger hysteresis state */
|
||||
#define TSI_PHM_G5P3 BIT(23) /*!< pin G5P3 Schmitt trigger hysteresis state */
|
||||
|
||||
/* TSI_ASW */
|
||||
#define TSI_ASW_G0P0 BIT(0) /*!< pin G0P0 analog switch state */
|
||||
#define TSI_ASW_G0P1 BIT(1) /*!< pin G0P1 analog switch state */
|
||||
#define TSI_ASW_G0P2 BIT(2) /*!< pin G0P2 analog switch state */
|
||||
#define TSI_ASW_G0P3 BIT(3) /*!< pin G0P3 analog switch state */
|
||||
#define TSI_ASW_G1P0 BIT(4) /*!< pin G1P0 analog switch state */
|
||||
#define TSI_ASW_G1P1 BIT(5) /*!< pin G1P1 analog switch state */
|
||||
#define TSI_ASW_G1P2 BIT(6) /*!< pin G1P2 analog switch state */
|
||||
#define TSI_ASW_G1P3 BIT(7) /*!< pin G1P3 analog switch state */
|
||||
#define TSI_ASW_G2P0 BIT(8) /*!< pin G2P0 analog switch state */
|
||||
#define TSI_ASW_G2P1 BIT(9) /*!< pin G2P1 analog switch state */
|
||||
#define TSI_ASW_G2P2 BIT(10) /*!< pin G2P2 analog switch state */
|
||||
#define TSI_ASW_G2P3 BIT(11) /*!< pin G2P3 analog switch state */
|
||||
#define TSI_ASW_G3P0 BIT(12) /*!< pin G3P0 analog switch state */
|
||||
#define TSI_ASW_G3P1 BIT(13) /*!< pin G3P1 analog switch state */
|
||||
#define TSI_ASW_G3P2 BIT(14) /*!< pin G3P2 analog switch state */
|
||||
#define TSI_ASW_G3P3 BIT(15) /*!< pin G3P3 analog switch state */
|
||||
#define TSI_ASW_G4P0 BIT(16) /*!< pin G4P0 analog switch state */
|
||||
#define TSI_ASW_G4P1 BIT(17) /*!< pin G4P1 analog switch state */
|
||||
#define TSI_ASW_G4P2 BIT(18) /*!< pin G4P2 analog switch state */
|
||||
#define TSI_ASW_G4P3 BIT(19) /*!< pin G4P3 analog switch state */
|
||||
#define TSI_ASW_G5P0 BIT(20) /*!< pin G5P0 analog switch state */
|
||||
#define TSI_ASW_G5P1 BIT(21) /*!< pin G5P1 analog switch state */
|
||||
#define TSI_ASW_G5P2 BIT(22) /*!< pin G5P2 analog switch state */
|
||||
#define TSI_ASW_G5P3 BIT(23) /*!< pin G5P3 analog switch state */
|
||||
|
||||
/* TSI_SAMPCFG */
|
||||
#define TSI_SAMPCFG_G0P0 BIT(0) /*!< pin G0P0 sample pin mode */
|
||||
#define TSI_SAMPCFG_G0P1 BIT(1) /*!< pin G0P1 sample pin mode */
|
||||
#define TSI_SAMPCFG_G0P2 BIT(2) /*!< pin G0P2 sample pin mode */
|
||||
#define TSI_SAMPCFG_G0P3 BIT(3) /*!< pin G0P3 sample pin mode */
|
||||
#define TSI_SAMPCFG_G1P0 BIT(4) /*!< pin G1P0 sample pin mode */
|
||||
#define TSI_SAMPCFG_G1P1 BIT(5) /*!< pin G1P1 sample pin mode */
|
||||
#define TSI_SAMPCFG_G1P2 BIT(6) /*!< pin G1P2 sample pin mode */
|
||||
#define TSI_SAMPCFG_G1P3 BIT(7) /*!< pin G1P3 sample pin mode */
|
||||
#define TSI_SAMPCFG_G2P0 BIT(8) /*!< pin G2P0 sample pin mode */
|
||||
#define TSI_SAMPCFG_G2P1 BIT(9) /*!< pin G2P1 sample pin mode */
|
||||
#define TSI_SAMPCFG_G2P2 BIT(10) /*!< pin G2P2 sample pin mode */
|
||||
#define TSI_SAMPCFG_G2P3 BIT(11) /*!< pin G2P3 sample pin mode */
|
||||
#define TSI_SAMPCFG_G3P0 BIT(12) /*!< pin G3P0 sample pin mode */
|
||||
#define TSI_SAMPCFG_G3P1 BIT(13) /*!< pin G3P1 sample pin mode */
|
||||
#define TSI_SAMPCFG_G3P2 BIT(14) /*!< pin G3P2 sample pin mode */
|
||||
#define TSI_SAMPCFG_G3P3 BIT(15) /*!< pin G3P3 sample pin mode */
|
||||
#define TSI_SAMPCFG_G4P0 BIT(16) /*!< pin G4P0 sample pin mode */
|
||||
#define TSI_SAMPCFG_G4P1 BIT(17) /*!< pin G4P1 sample pin mode */
|
||||
#define TSI_SAMPCFG_G4P2 BIT(18) /*!< pin G4P2 sample pin mode */
|
||||
#define TSI_SAMPCFG_G4P3 BIT(19) /*!< pin G4P3 sample pin mode */
|
||||
#define TSI_SAMPCFG_G5P0 BIT(20) /*!< pin G5P0 sample pin mode */
|
||||
#define TSI_SAMPCFG_G5P1 BIT(21) /*!< pin G5P1 sample pin mode */
|
||||
#define TSI_SAMPCFG_G5P2 BIT(22) /*!< pin G5P2 sample pin mode */
|
||||
#define TSI_SAMPCFG_G5P3 BIT(23) /*!< pin G5P3 sample pin mode */
|
||||
|
||||
/* TSI_CHCFG */
|
||||
#define TSI_CHCFG_G0P0 BIT(0) /*!< pin G0P0 channel pin mode */
|
||||
#define TSI_CHCFG_G0P1 BIT(1) /*!< pin G0P1 channel pin mode */
|
||||
#define TSI_CHCFG_G0P2 BIT(2) /*!< pin G0P2 channel pin mode */
|
||||
#define TSI_CHCFG_G0P3 BIT(3) /*!< pin G0P3 channel pin mode */
|
||||
#define TSI_CHCFG_G1P0 BIT(4) /*!< pin G1P0 channel pin mode */
|
||||
#define TSI_CHCFG_G1P1 BIT(5) /*!< pin G1P1 channel pin mode */
|
||||
#define TSI_CHCFG_G1P2 BIT(6) /*!< pin G1P2 channel pin mode */
|
||||
#define TSI_CHCFG_G1P3 BIT(7) /*!< pin G1P3 channel pin mode */
|
||||
#define TSI_CHCFG_G2P0 BIT(8) /*!< pin G2P0 channel pin mode */
|
||||
#define TSI_CHCFG_G2P1 BIT(9) /*!< pin G2P1 channel pin mode */
|
||||
#define TSI_CHCFG_G2P2 BIT(10) /*!< pin G2P2 channel pin mode */
|
||||
#define TSI_CHCFG_G2P3 BIT(11) /*!< pin G2P3 channel pin mode */
|
||||
#define TSI_CHCFG_G3P0 BIT(12) /*!< pin G3P0 channel pin mode */
|
||||
#define TSI_CHCFG_G3P1 BIT(13) /*!< pin G3P1 channel pin mode */
|
||||
#define TSI_CHCFG_G3P2 BIT(14) /*!< pin G3P2 channel pin mode */
|
||||
#define TSI_CHCFG_G3P3 BIT(15) /*!< pin G3P3 channel pin mode */
|
||||
#define TSI_CHCFG_G4P0 BIT(16) /*!< pin G4P0 channel pin mode */
|
||||
#define TSI_CHCFG_G4P1 BIT(17) /*!< pin G4P1 channel pin mode */
|
||||
#define TSI_CHCFG_G4P2 BIT(18) /*!< pin G4P2 channel pin mode */
|
||||
#define TSI_CHCFG_G4P3 BIT(19) /*!< pin G4P3 channel pin mode */
|
||||
#define TSI_CHCFG_G5P0 BIT(20) /*!< pin G5P0 channel pin mode */
|
||||
#define TSI_CHCFG_G5P1 BIT(21) /*!< pin G5P1 channel pin mode */
|
||||
#define TSI_CHCFG_G5P2 BIT(22) /*!< pin G5P2 channel pin mode */
|
||||
#define TSI_CHCFG_G5P3 BIT(23) /*!< pin G5P3 channel pin mode */
|
||||
|
||||
/* TSI_GCTL */
|
||||
#define TSI_GCTL_GE0 BIT(0) /*!< group0 enable */
|
||||
#define TSI_GCTL_GE1 BIT(1) /*!< group1 enable */
|
||||
#define TSI_GCTL_GE2 BIT(2) /*!< group2 enable */
|
||||
#define TSI_GCTL_GE3 BIT(3) /*!< group3 enable */
|
||||
#define TSI_GCTL_GE4 BIT(4) /*!< group4 enable */
|
||||
#define TSI_GCTL_GE5 BIT(5) /*!< group5 enable */
|
||||
#define TSI_GCTL_GC0 BIT(16) /*!< group0 complete */
|
||||
#define TSI_GCTL_GC1 BIT(17) /*!< group1 complete */
|
||||
#define TSI_GCTL_GC2 BIT(18) /*!< group2 complete */
|
||||
#define TSI_GCTL_GC3 BIT(19) /*!< group3 complete */
|
||||
#define TSI_GCTL_GC4 BIT(20) /*!< group4 complete */
|
||||
#define TSI_GCTL_GC5 BIT(21) /*!< group5 complete */
|
||||
|
||||
/* TSI_CTL1 */
|
||||
#define TSI_CTL1_CTCDIV BIT(24) /*!< CTCLK clock division factor */
|
||||
#define TSI_CTL1_ECDIV BITS(28,29) /*!< ECCLK clock division factor */
|
||||
|
||||
/* constants definitions */
|
||||
/* TSI interrupt enable bit */
|
||||
#define TSI_INT_CCTCF TSI_INTEN_CTCFIE /*!< charge transfer complete flag interrupt enable */
|
||||
#define TSI_INT_MNERR TSI_INTEN_MNERRIE /*!< max cycle number error interrupt enable */
|
||||
|
||||
/* I2C interrupt flags */
|
||||
#define TSI_INT_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */
|
||||
#define TSI_INT_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */
|
||||
|
||||
/* I2C interrupt clear flags */
|
||||
#define TSI_INT_FLAG_CTCF_CLR TSI_INTC_CCTCF /*!< clear charge transfer complete flag */
|
||||
#define TSI_INT_FLAG_MNERR_CLR TSI_INTC_CMNERR /*!< clear max cycle number error */
|
||||
|
||||
/* I2C flags */
|
||||
#define TSI_FLAG_CTCF TSI_INTF_CTCF /*!< charge transfer complete flag */
|
||||
#define TSI_FLAG_MNERR TSI_INTF_MNERR /*!< max cycle number error */
|
||||
|
||||
/* I2C clear flags */
|
||||
#define TSI_FLAG_CTCF_CLR TSI_INTC_CCTCF /*!< clear charge transfer complete flag */
|
||||
#define TSI_FLAG_MNERR_CLR TSI_INTC_CMNERR /*!< clear max cycle number error */
|
||||
|
||||
/* CTCLK clock division factor */
|
||||
#define TSI_CTCDIV_DIV1 ((uint32_t)0x00000000U) /*!< fCTCLK = fHCLK */
|
||||
#define TSI_CTCDIV_DIV2 ((uint32_t)0x00000001U) /*!< fCTCLK = fHCLK/2 */
|
||||
#define TSI_CTCDIV_DIV4 ((uint32_t)0x00000002U) /*!< fCTCLK = fHCLK/4 */
|
||||
#define TSI_CTCDIV_DIV8 ((uint32_t)0x00000003U) /*!< fCTCLK = fHCLK/8 */
|
||||
#define TSI_CTCDIV_DIV16 ((uint32_t)0x00000004U) /*!< fCTCLK = fHCLK/16 */
|
||||
#define TSI_CTCDIV_DIV32 ((uint32_t)0x00000005U) /*!< fCTCLK = fHCLK/32 */
|
||||
#define TSI_CTCDIV_DIV64 ((uint32_t)0x00000006U) /*!< fCTCLK = fHCLK/64 */
|
||||
#define TSI_CTCDIV_DIV128 ((uint32_t)0x00000007U) /*!< fCTCLK = fHCLK/128 */
|
||||
#define TSI_CTCDIV_DIV256 ((uint32_t)0x00000008U) /*!< fCTCLK = fHCLK/256 */
|
||||
#define TSI_CTCDIV_DIV512 ((uint32_t)0x00000009U) /*!< fCTCLK = fHCLK/512 */
|
||||
#define TSI_CTCDIV_DIV1024 ((uint32_t)0x0000000AU) /*!< fCTCLK = fHCLK/1024 */
|
||||
#define TSI_CTCDIV_DIV2048 ((uint32_t)0x0000000BU) /*!< fCTCLK = fHCLK/2048 */
|
||||
#define TSI_CTCDIV_DIV4096 ((uint32_t)0x0000000CU) /*!< fCTCLK = fHCLK/4096 */
|
||||
#define TSI_CTCDIV_DIV8192 ((uint32_t)0x0000000DU) /*!< fCTCLK = fHCLK/8192 */
|
||||
#define TSI_CTCDIV_DIV16384 ((uint32_t)0x0000000EU) /*!< fCTCLK = fHCLK/16384 */
|
||||
#define TSI_CTCDIV_DIV32768 ((uint32_t)0x0000000FU) /*!< fCTCLK = fHCLK/32768 */
|
||||
|
||||
/* charge transfer state duration Time */
|
||||
#define CTL_CTDT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U))
|
||||
#define TSI_TRANSFER_1CTCLK CTL_CTDT(0) /*!< the duration time of transfer state is 1 CTCLK */
|
||||
#define TSI_TRANSFER_2CTCLK CTL_CTDT(1) /*!< the duration time of transfer state is 2 CTCLK */
|
||||
#define TSI_TRANSFER_3CTCLK CTL_CTDT(2) /*!< the duration time of transfer state is 3 CTCLK */
|
||||
#define TSI_TRANSFER_4CTCLK CTL_CTDT(3) /*!< the duration time of transfer state is 4 CTCLK */
|
||||
#define TSI_TRANSFER_5CTCLK CTL_CTDT(4) /*!< the duration time of transfer state is 5 CTCLK */
|
||||
#define TSI_TRANSFER_6CTCLK CTL_CTDT(5) /*!< the duration time of transfer state is 6 CTCLK */
|
||||
#define TSI_TRANSFER_7CTCLK CTL_CTDT(6) /*!< the duration time of transfer state is 7 CTCLK */
|
||||
#define TSI_TRANSFER_8CTCLK CTL_CTDT(7) /*!< the duration time of transfer state is 8 CTCLK */
|
||||
#define TSI_TRANSFER_9CTCLK CTL_CTDT(8) /*!< the duration time of transfer state is 9 CTCLK */
|
||||
#define TSI_TRANSFER_10CTCLK CTL_CTDT(9) /*!< the duration time of transfer state is 10 CTCLK */
|
||||
#define TSI_TRANSFER_11CTCLK CTL_CTDT(10) /*!< the duration time of transfer state is 11 CTCLK */
|
||||
#define TSI_TRANSFER_12CTCLK CTL_CTDT(11) /*!< the duration time of transfer state is 12 CTCLK */
|
||||
#define TSI_TRANSFER_13CTCLK CTL_CTDT(12) /*!< the duration time of transfer state is 13 CTCLK */
|
||||
#define TSI_TRANSFER_14CTCLK CTL_CTDT(13) /*!< the duration time of transfer state is 14 CTCLK */
|
||||
#define TSI_TRANSFER_15CTCLK CTL_CTDT(14) /*!< the duration time of transfer state is 15 CTCLK */
|
||||
#define TSI_TRANSFER_16CTCLK CTL_CTDT(15) /*!< the duration time of transfer state is 16 CTCLK */
|
||||
|
||||
/* charge state duration time */
|
||||
#define CTL_CDT(regval) (BITS(28,31) & ((uint32_t)(regval) << 28U))
|
||||
#define TSI_CHARGE_1CTCLK CTL_CDT(0) /*!< the duration time of charge state is 1 CTCLK */
|
||||
#define TSI_CHARGE_2CTCLK CTL_CDT(1) /*!< the duration time of charge state is 2 CTCLK */
|
||||
#define TSI_CHARGE_3CTCLK CTL_CDT(2) /*!< the duration time of charge state is 3 CTCLK */
|
||||
#define TSI_CHARGE_4CTCLK CTL_CDT(3) /*!< the duration time of charge state is 4 CTCLK */
|
||||
#define TSI_CHARGE_5CTCLK CTL_CDT(4) /*!< the duration time of charge state is 5 CTCLK */
|
||||
#define TSI_CHARGE_6CTCLK CTL_CDT(5) /*!< the duration time of charge state is 6 CTCLK */
|
||||
#define TSI_CHARGE_7CTCLK CTL_CDT(6) /*!< the duration time of charge state is 7 CTCLK */
|
||||
#define TSI_CHARGE_8CTCLK CTL_CDT(7) /*!< the duration time of charge state is 8 CTCLK */
|
||||
#define TSI_CHARGE_9CTCLK CTL_CDT(8) /*!< the duration time of charge state is 9 CTCLK */
|
||||
#define TSI_CHARGE_10CTCLK CTL_CDT(9) /*!< the duration time of charge state is 10 CTCLK */
|
||||
#define TSI_CHARGE_11CTCLK CTL_CDT(10) /*!< the duration time of charge state is 11 CTCLK */
|
||||
#define TSI_CHARGE_12CTCLK CTL_CDT(11) /*!< the duration time of charge state is 12 CTCLK */
|
||||
#define TSI_CHARGE_13CTCLK CTL_CDT(12) /*!< the duration time of charge state is 13 CTCLK */
|
||||
#define TSI_CHARGE_14CTCLK CTL_CDT(13) /*!< the duration time of charge state is 14 CTCLK */
|
||||
#define TSI_CHARGE_15CTCLK CTL_CDT(14) /*!< the duration time of charge state is 15 CTCLK */
|
||||
#define TSI_CHARGE_16CTCLK CTL_CDT(15) /*!< the duration time of charge state is 16 CTCLK */
|
||||
|
||||
/* max cycle number of a sequence */
|
||||
#define CTL_MCN(regval) (BITS(5,7) & ((uint32_t)(regval) << 5U))
|
||||
#define TSI_MAXNUM255 CTL_MCN(0) /*!< the max cycle number of a sequence is 255 */
|
||||
#define TSI_MAXNUM511 CTL_MCN(1) /*!< the max cycle number of a sequence is 511 */
|
||||
#define TSI_MAXNUM1023 CTL_MCN(2) /*!< the max cycle number of a sequence is 1023 */
|
||||
#define TSI_MAXNUM2047 CTL_MCN(3) /*!< the max cycle number of a sequence is 2047 */
|
||||
#define TSI_MAXNUM4095 CTL_MCN(4) /*!< the max cycle number of a sequence is 4095 */
|
||||
#define TSI_MAXNUM8191 CTL_MCN(5) /*!< the max cycle number of a sequence is 8191 */
|
||||
#define TSI_MAXNUM16383 CTL_MCN(6) /*!< the max cycle number of a sequence is 16383 */
|
||||
|
||||
/* ECCLK clock division factor */
|
||||
#define TSI_EXTEND_DIV1 ((uint32_t)0x00000000U) /*!< fECCLK = fHCLK */
|
||||
#define TSI_EXTEND_DIV2 ((uint32_t)0x00000001U) /*!< fECCLK = fHCLK/2 */
|
||||
#define TSI_EXTEND_DIV3 ((uint32_t)0x00000002U) /*!< fECCLK = fHCLK/3 */
|
||||
#define TSI_EXTEND_DIV4 ((uint32_t)0x00000003U) /*!< fECCLK = fHCLK/4 */
|
||||
#define TSI_EXTEND_DIV5 ((uint32_t)0x00000004U) /*!< fECCLK = fHCLK/5 */
|
||||
#define TSI_EXTEND_DIV6 ((uint32_t)0x00000005U) /*!< fECCLK = fHCLK/6 */
|
||||
#define TSI_EXTEND_DIV7 ((uint32_t)0x00000006U) /*!< fECCLK = fHCLK/7 */
|
||||
#define TSI_EXTEND_DIV8 ((uint32_t)0x00000007U) /*!< fECCLK = fHCLK/8 */
|
||||
|
||||
/* extend charge state maximum duration time */
|
||||
#define TSI_EXTENDMAX(regval) (BITS(17,23) & ((uint32_t)(regval) << 17U)) /* value range 1..128,extend charge state maximum duration time */
|
||||
|
||||
/* hardware trigger mode */
|
||||
#define TSI_FALLING_TRIGGER 0x00U /*!< falling edge trigger TSI charge transfer sequence */
|
||||
#define TSI_RISING_TRIGGER 0x01U /*!< rising edge trigger TSI charge transfer sequence */
|
||||
|
||||
/* pin mode */
|
||||
#define TSI_OUTPUT_LOW 0x00U /*!< TSI pin will output low when IDLE */
|
||||
#define TSI_INPUT_FLOATING 0x01U /*!< TSI pin will keep input_floating when IDLE */
|
||||
|
||||
/* function declarations */
|
||||
/* reset TSI peripheral */
|
||||
void tsi_deinit(void);
|
||||
/* initialize TSI plus prescaler,charge plus,transfer plus,max cycle number */
|
||||
void tsi_init(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration,uint32_t max_number);
|
||||
/* enable TSI module */
|
||||
void tsi_enable(void);
|
||||
/* disable TSI module */
|
||||
void tsi_disable(void);
|
||||
/* enable sample pin */
|
||||
void tsi_sample_pin_enable(uint32_t sample);
|
||||
/* disable sample pin */
|
||||
void tsi_sample_pin_disable(uint32_t sample);
|
||||
/* enable channel pin */
|
||||
void tsi_channel_pin_enable(uint32_t channel);
|
||||
/* disable channel pin */
|
||||
void tsi_channel_pin_disable(uint32_t channel);
|
||||
|
||||
/* configure TSI triggering by software */
|
||||
void tsi_sofeware_mode_config(void);
|
||||
/* start a charge-transfer sequence when TSI is in software trigger mode */
|
||||
void tsi_software_start(void);
|
||||
/* stop a charge-transfer sequence when TSI is in software trigger mode */
|
||||
void tsi_software_stop(void);
|
||||
/* configure TSI triggering by hardware */
|
||||
void tsi_hardware_mode_config(uint8_t trigger_edge);
|
||||
/* configure TSI pin mode when charge-transfer sequence is IDLE */
|
||||
void tsi_pin_mode_config(uint8_t pin_mode);
|
||||
/* configure extend charge state */
|
||||
void tsi_extend_charge_config(ControlStatus extend,uint8_t prescaler,uint32_t max_duration);
|
||||
|
||||
/* configure charge plus and transfer plus */
|
||||
void tsi_plus_config(uint32_t prescaler,uint32_t charge_duration,uint32_t transfer_duration);
|
||||
/* configure the max cycle number of a charge-transfer sequence */
|
||||
void tsi_max_number_config(uint32_t max_number);
|
||||
/* switch on hysteresis pin */
|
||||
void tsi_hysteresis_on(uint32_t group_pin);
|
||||
/* switch off hysteresis pin */
|
||||
void tsi_hysteresis_off(uint32_t group_pin);
|
||||
/* switch on analog pin */
|
||||
void tsi_analog_on(uint32_t group_pin);
|
||||
/* switch off analog pin */
|
||||
void tsi_analog_off(uint32_t group_pin);
|
||||
|
||||
/* enable TSI interrupt */
|
||||
void tsi_interrupt_enable(uint32_t source);
|
||||
/* disable TSI interrupt */
|
||||
void tsi_interrupt_disable(uint32_t source);
|
||||
/* clear interrupt flag */
|
||||
void tsi_interrupt_flag_clear(uint32_t flag);
|
||||
/* get TSI interrupt flag */
|
||||
FlagStatus tsi_interrupt_flag_get(uint32_t flag);
|
||||
|
||||
/* clear flag */
|
||||
void tsi_flag_clear(uint32_t flag);
|
||||
/* get flag */
|
||||
FlagStatus tsi_flag_get(uint32_t flag);
|
||||
|
||||
/* enbale group */
|
||||
void tsi_group_enable(uint32_t group);
|
||||
/* disbale group */
|
||||
void tsi_group_disable(uint32_t group);
|
||||
/* get group complete status */
|
||||
FlagStatus tsi_group_status_get(uint32_t group);
|
||||
/* get the cycle number for group0 as soon as a charge-transfer sequence completes */
|
||||
uint16_t tsi_group0_cycle_get(void);
|
||||
/* get the cycle number for group1 as soon as a charge-transfer sequence completes */
|
||||
uint16_t tsi_group1_cycle_get(void);
|
||||
/* get the cycle number for group2 as soon as a charge-transfer sequence completes */
|
||||
uint16_t tsi_group2_cycle_get(void);
|
||||
/* get the cycle number for group3 as soon as a charge-transfer sequence completes */
|
||||
uint16_t tsi_group3_cycle_get(void);
|
||||
/* get the cycle number for group4 as soon as a charge-transfer sequence completes */
|
||||
uint16_t tsi_group4_cycle_get(void);
|
||||
/* get the cycle number for group5 as soon as a charge-transfer sequence completes */
|
||||
uint16_t tsi_group5_cycle_get(void);
|
||||
|
||||
#endif /* GD32F3X0_TSI_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,93 @@
|
||||
/*!
|
||||
\file gd32f3x0_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F3X0_WWDGT_H
|
||||
#define GD32F3X0_WWDGT_H
|
||||
|
||||
#include "gd32f3x0.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32(WWDGT + 0x00000000U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32(WWDGT + 0x00000004U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32(WWDGT + 0x00000008U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* WWDGT_CTL register value */
|
||||
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CTL_CNT bit field */
|
||||
|
||||
/* WWDGT_CFG register value */
|
||||
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to WWDGT_CFG_WIN bit field */
|
||||
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||
|
||||
/* function declarations */
|
||||
/* reset the window watchdog timer configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the window watchdog timer counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the window watchdog timer counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
|
||||
#endif /* GD32F3X0_WWDGT_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,499 @@
|
||||
/*!
|
||||
\file gd32f3x0_cec.c
|
||||
\brief CEC driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifdef GD32F350
|
||||
|
||||
#include "gd32f3x0_cec.h"
|
||||
|
||||
/*!
|
||||
\brief reset HDMI-CEC controller
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_deinit(void)
|
||||
{
|
||||
rcu_periph_reset_enable(RCU_CECRST);
|
||||
rcu_periph_reset_disable(RCU_CECRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure signal free time,the signal free time counter start option,own address
|
||||
\param[in] sftmopt: signal free time counter start option
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted
|
||||
\arg CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end
|
||||
\param[in] sft: signal free time
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_SFT_PROTOCOL_PERIOD: the signal free time will perform as HDMI-CEC protocol description
|
||||
\arg CEC_SFT_1POINT5_PERIOD: 1.5 nominal data bit periods
|
||||
\arg CEC_SFT_2POINT5_PERIOD: 2.5 nominal data bit periods
|
||||
\arg CEC_SFT_3POINT5_PERIOD: 3.5 nominal data bit periods
|
||||
\arg CEC_SFT_4POINT5_PERIOD: 4.5 nominal data bit periods
|
||||
\arg CEC_SFT_5POINT5_PERIOD: 5.5 nominal data bit periods
|
||||
\arg CEC_SFT_6POINT5_PERIOD: 6.5 nominal data bit periods
|
||||
\arg CEC_SFT_7POINT5_PERIOD: 7.5 nominal data bit periods
|
||||
\param[in] address: own address
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_OWN_ADDRESS_CLEAR: own address is cleared
|
||||
\arg CEC_OWN_ADDRESSx(x=0..14): own address is x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_init(uint32_t sftmopt, uint32_t sft, uint32_t address)
|
||||
{
|
||||
uint32_t cfg;
|
||||
cfg = CEC_CFG;
|
||||
/* clear SFTMOPT bit,SFT[2:0] */
|
||||
cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT);
|
||||
/* assign SFTMOPT bit,SFT[2:0] */
|
||||
cfg |= (sftmopt | sft);
|
||||
CEC_CFG = cfg;
|
||||
if(CEC_OWN_ADDRESS_CLEAR == address){
|
||||
CEC_CFG &= ~CEC_CFG_OWN_ADDRESS;
|
||||
}else{
|
||||
CEC_CFG |= address;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure generate Error-bit when detected some abnormal situation or not,
|
||||
whether stop receive message when detected bit rising error
|
||||
\param[in] broadcast:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_BROADCAST_ERROR_BIT_ON:generate Error-bit in broadcast
|
||||
\arg CEC_BROADCAST_ERROR_BIT_OFF:do not generate Error-bit in broadcast
|
||||
\param[in] singlecast_lbpe:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error
|
||||
\arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error
|
||||
\param[in] singlecast_bre:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error
|
||||
\arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error
|
||||
\param[in] rxbrestp:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_STOP_RISING_ERROR_BIT_ON: stop reception when detected bit rising error
|
||||
\arg CEC_STOP_RISING_ERROR_BIT_OFF: do not stop reception when detected bit rising error
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_error_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre, uint32_t rxbrestp)
|
||||
{
|
||||
uint32_t cfg;
|
||||
cfg = CEC_CFG;
|
||||
/* clear BCNG bit, BPLEG bit, BREG bit */
|
||||
cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG);
|
||||
/* assign BCNG bit, BPLEG bit, BREG bit */
|
||||
cfg |= (broadcast | singlecast_lbpe | singlecast_bre);
|
||||
CEC_CFG = cfg;
|
||||
if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){
|
||||
CEC_CFG |= CEC_CFG_BRES;
|
||||
}else{
|
||||
CEC_CFG &= ~CEC_CFG_BRES;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable HDMI-CEC controller
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_enable(void)
|
||||
{
|
||||
CEC_CTL |= CEC_CTL_CECEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable HDMI-CEC controller
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_disable(void)
|
||||
{
|
||||
CEC_CTL &= ~CEC_CTL_CECEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start CEC message transmission
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_transmission_start(void)
|
||||
{
|
||||
CEC_CTL |= CEC_CTL_STAOM;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief end CEC message transmission
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_transmission_end(void)
|
||||
{
|
||||
CEC_CTL |= CEC_CTL_ENDOM;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable CEC listen mode.
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_listen_mode_enable(void)
|
||||
{
|
||||
CEC_CFG |= CEC_CFG_LMEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable CEC listen mode.
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_listen_mode_disable(void)
|
||||
{
|
||||
CEC_CFG &= ~CEC_CFG_LMEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure and clear own address.the controller can be configured to multiple own address
|
||||
\param[in] address: own address
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CEC_OWN_ADDRESS_CLEAR: own address is cleared
|
||||
\arg CEC_OWN_ADDRESSx(x=0..14): own address is x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_own_address_config(uint32_t address)
|
||||
{
|
||||
if(CEC_OWN_ADDRESS_CLEAR == address){
|
||||
CEC_CFG &= ~CEC_CFG_OWN_ADDRESS;
|
||||
} else {
|
||||
CEC_CFG |= address;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure signal free time and the signal free time counter start option
|
||||
\param[in] sftmopt: signal free time counter start option
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_SFT_START_STAOM: signal free time counter starts counting when STAOM is asserted
|
||||
\arg CEC_SFT_START_LAST: signal free time counter starts automatically after transmission/reception end
|
||||
\param[in] sft: signal free time
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_SFT_PROTOCOL_PERIOD: the signal free time will perform as HDMI-CEC protocol description
|
||||
\arg CEC_SFT_1POINT5_PERIOD: 1.5 nominal data bit periods
|
||||
\arg CEC_SFT_2POINT5_PERIOD: 2.5 nominal data bit periods
|
||||
\arg CEC_SFT_3POINT5_PERIOD: 3.5 nominal data bit periods
|
||||
\arg CEC_SFT_4POINT5_PERIOD: 4.5 nominal data bit periods
|
||||
\arg CEC_SFT_5POINT5_PERIOD: 5.5 nominal data bit periods
|
||||
\arg CEC_SFT_6POINT5_PERIOD: 6.5 nominal data bit periods
|
||||
\arg CEC_SFT_7POINT5_PERIOD: 7.5 nominal data bit periods
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_sft_config(uint32_t sftmopt, uint32_t sft)
|
||||
{
|
||||
uint32_t cfg;
|
||||
cfg = CEC_CFG;
|
||||
/* clear SFTMOPT bit,SFT[2:0] */
|
||||
cfg &= ~(CEC_CFG_SFTOPT | CEC_CFG_SFT);
|
||||
/* assign SFTMOPT bit,SFT[2:0] */
|
||||
cfg |= (sftmopt | sft);
|
||||
CEC_CFG = cfg;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure generate Error-bit when detected some abnormal situation or not
|
||||
\param[in] broadcast:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_BROADCAST_ERROR_BIT_ON:generate Error-bit in broadcast
|
||||
\arg CEC_BROADCAST_ERROR_BIT_OFF:do not generate Error-bit in broadcast
|
||||
\param[in] singlecast_lbpe:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_LONG_PERIOD_ERROR_BIT_ON:generate Error-bit on long bit period error
|
||||
\arg CEC_LONG_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on long bit period error
|
||||
\param[in] singlecast_bre:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_RISING_PERIOD_ERROR_BIT_ON:generate Error-bit on bit rising error
|
||||
\arg CEC_RISING_PERIOD_ERROR_BIT_OFF:do not generate Error-bit on bit rising error
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_generate_errorbit_config(uint32_t broadcast, uint32_t singlecast_lbpe, uint32_t singlecast_bre)
|
||||
{
|
||||
uint32_t cfg;
|
||||
cfg = CEC_CFG;
|
||||
/* clear BCNG bit, RLBPEGEN bit, RBREGEN bit */
|
||||
cfg &= ~(CEC_CFG_BCNG | CEC_CFG_BPLEG | CEC_CFG_BREG);
|
||||
/* assign BCNG bit, RLBPEGEN bit, RBREGEN bit */
|
||||
cfg |= (broadcast | singlecast_lbpe | singlecast_bre);
|
||||
CEC_CFG = cfg;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief whether stop receive message when detected bit rising error
|
||||
\param[in] rxbrestp:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CEC_STOP_RISING_ERROR_BIT_ON: stop reception when detected bit rising error
|
||||
\arg CEC_STOP_RISING_ERROR_BIT_OFF: do not stop reception when detected bit rising error
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_stop_receive_bre_config(uint32_t rxbrestp)
|
||||
{
|
||||
if(CEC_STOP_RISING_ERROR_BIT_ON == rxbrestp){
|
||||
CEC_CFG |= CEC_CFG_BRES;
|
||||
} else {
|
||||
CEC_CFG &= ~CEC_CFG_BRES;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable reception bit timing tolerance
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_reception_tolerance_enable(void)
|
||||
{
|
||||
CEC_CFG |= CEC_CFG_RTOL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable reception bit timing tolerance
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_reception_tolerance_disable(void)
|
||||
{
|
||||
CEC_CFG &= ~CEC_CFG_RTOL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief send a data by the CEC peripheral
|
||||
\param[in] data: the data to transmit
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_data_send(uint8_t data)
|
||||
{
|
||||
CEC_TDATA = (uint32_t)data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief receive a data by the CEC peripheral
|
||||
\param[in] data: the data to receive
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
uint8_t cec_data_receive(void)
|
||||
{
|
||||
return (uint8_t)CEC_RDATA;
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief enable interrupt
|
||||
\param[in] flag: specify which flag
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CEC_INT_BR: enable Rx-byte data received interrupt
|
||||
\arg CEC_INT_REND: enable end of reception interrupt
|
||||
\arg CEC_INT_RO: enable RX overrun interrupt
|
||||
\arg CEC_INT_BRE: enable bit rising error interrupt
|
||||
\arg CEC_INT_BPSE: enable short bit period error interrupt
|
||||
\arg CEC_INT_BPLE: enable long bit period error interrupt
|
||||
\arg CEC_INT_RAE: enable Rx ACK error interrupt
|
||||
\arg CEC_INT_ARBF: enable arbitration lost interrupt
|
||||
\arg CEC_INT_TBR: enable Tx-byte data request interrupt
|
||||
\arg CEC_INT_TEND: enable transmission successfully end interrupt
|
||||
\arg CEC_INT_TU: enable Tx data buffer underrun interrupt
|
||||
\arg CEC_INT_TERR: enable Tx-error interrupt
|
||||
\arg CEC_INT_TAERR: enable Tx ACK error interrupt
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_interrupt_enable(uint32_t flag)
|
||||
{
|
||||
CEC_INTEN |= flag;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable interrupt
|
||||
\param[in] flag: specify which flag
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CEC_INT_BR: disable Rx-byte data received interrupt
|
||||
\arg CEC_INT_REND: disable end of reception interrupt
|
||||
\arg CEC_INT_RO: disable RX overrun interrupt
|
||||
\arg CEC_INT_BRE: disable bit rising error interrupt
|
||||
\arg CEC_INT_BPSE: disable short bit period error interrupt
|
||||
\arg CEC_INT_BPLE: disable long bit period error interrupt
|
||||
\arg CEC_INT_RAE: disable Rx ACK error interrupt
|
||||
\arg CEC_INT_ARBF: disable arbitration lost interrupt
|
||||
\arg CEC_INT_TBR: disable Tx-byte data request interrupt
|
||||
\arg CEC_INT_TEND: disable transmission successfully end interrupt
|
||||
\arg CEC_INT_TU: disable Tx data buffer underrun interrupt
|
||||
\arg CEC_INT_TERR: disable Tx-error interrupt
|
||||
\arg CEC_INT_TAERR: disable Tx ACK error interrupt
|
||||
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_interrupt_disable(uint32_t flag)
|
||||
{
|
||||
CEC_INTEN &= ~flag;
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief get CEC status
|
||||
\param[in] flag: specify which flag
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CEC_FLAG_BR: Rx-byte data received
|
||||
\arg CEC_FLAG_REND: end of reception
|
||||
\arg CEC_FLAG_RO: RX overrun
|
||||
\arg CEC_FLAG_BRE: bit rising error
|
||||
\arg CEC_FLAG_BPSE: short bit period error
|
||||
\arg CEC_FLAG_BPLE: long bit period error
|
||||
\arg CEC_FLAG_RAE: Rx ACK error
|
||||
\arg CEC_FLAG_ARBF: arbitration lost
|
||||
\arg CEC_FLAG_TBR: Tx-byte data request
|
||||
\arg CEC_FLAG_TEND: transmission successfully end
|
||||
\arg CEC_FLAG_TU: Tx data buffer underrun
|
||||
\arg CEC_FLAG_TERR: Tx-error
|
||||
\arg CEC_FLAG_TAERR Tx ACK error flag
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus cec_flag_get(uint32_t flag)
|
||||
{
|
||||
if(CEC_INTF & flag){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear CEC status
|
||||
\param[in] flag: specify which flag
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CEC_FLAG_BR: Rx-byte data received
|
||||
\arg CEC_FLAG_REND: end of reception
|
||||
\arg CEC_FLAG_RO: RX overrun
|
||||
\arg CEC_FLAG_BRE: bit rising error
|
||||
\arg CEC_FLAG_BPSE: short bit period error
|
||||
\arg CEC_FLAG_BPLE: long bit period error
|
||||
\arg CEC_FLAG_RAE: Rx ACK error
|
||||
\arg CEC_FLAG_ARBF: arbitration lost
|
||||
\arg CEC_FLAG_TBR: Tx-byte data request
|
||||
\arg CEC_FLAG_TEND: transmission successfully end
|
||||
\arg CEC_FLAG_TU: Tx data buffer underrun
|
||||
\arg CEC_FLAG_TERR: Tx-error
|
||||
\arg CEC_FLAG_TAERR: Tx ACK error flag
|
||||
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
void cec_flag_clear(uint32_t flag)
|
||||
{
|
||||
CEC_INTF |= flag;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get CEC int flag and status
|
||||
\param[in] flag: specify which flag
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CEC_INT_FLAG_BR: Rx-byte data received
|
||||
\arg CEC_INT_FLAG_REND: end of reception
|
||||
\arg CEC_INT_FLAG_RO: RX overrun
|
||||
\arg CEC_INT_FLAG_BRE: bit rising error
|
||||
\arg CEC_INT_FLAG_BPSE: short bit period error
|
||||
\arg CEC_INT_FLAG_BPLE: long bit period error
|
||||
\arg CEC_INT_FLAG_RAE: Rx ACK error
|
||||
\arg CEC_INT_FLAG_ARBF: arbitration lost
|
||||
\arg CEC_INT_FLAG_TBR: Tx-byte data request
|
||||
\arg CEC_INT_FLAG_TEND: transmission successfully end
|
||||
\arg CEC_INT_FLAG_TU: Tx data buffer underrun
|
||||
\arg CEC_INT_FLAG_TERR: Tx-error
|
||||
\arg CEC_INT_FLAG_TAERR: Tx ACK error flag
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus cec_interrupt_flag_get(uint32_t flag)
|
||||
{
|
||||
uint32_t interrupt_enable = 0U,interrupt_flag = 0U;
|
||||
interrupt_flag = (CEC_INTF & flag);
|
||||
interrupt_enable = (CEC_INTEN & flag);
|
||||
if(interrupt_flag && interrupt_enable){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear CEC int flag and status
|
||||
\param[in] flag: specify which flag
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CEC_INT_FLAG_BR: Rx-byte data received
|
||||
\arg CEC_INT_FLAG_REND: end of reception
|
||||
\arg CEC_INT_FLAG_RO: RX overrun
|
||||
\arg CEC_INT_FLAG_BRE: bit rising error
|
||||
\arg CEC_INT_FLAG_BPSE: short bit period error
|
||||
\arg CEC_INT_FLAG_BPLE: long bit period error
|
||||
\arg CEC_INT_FLAG_RAE: Rx ACK error
|
||||
\arg CEC_INT_FLAG_ARBF: arbitration lost
|
||||
\arg CEC_INT_FLAG_TBR: Tx-byte data request
|
||||
\arg CEC_INT_FLAG_TEND: transmission successfully end
|
||||
\arg CEC_INT_FLAG_TU: Tx data buffer underrun
|
||||
\arg CEC_INT_FLAG_TERR: Tx-error
|
||||
\arg CEC_INT_FLAG_TAERR: Tx ACK error flag
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cec_interrupt_flag_clear(uint32_t flag)
|
||||
{
|
||||
CEC_INTF = flag;
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,255 @@
|
||||
/*!
|
||||
\file gd32f3x0_cmp.c
|
||||
\brief CMP driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_cmp.h"
|
||||
|
||||
/*!
|
||||
\brief deinitialize comparator
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_deinit(void)
|
||||
{
|
||||
CMP_CS = ((uint32_t)0x00000000U);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize comparator mode
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\arg CMP1: comparator 1
|
||||
\param[in] operating_mode
|
||||
\arg CMP_HIGHSPEED: high speed mode
|
||||
\arg CMP_MIDDLESPEED: medium speed mode
|
||||
\arg CMP_LOWSPEED: low speed mode
|
||||
\arg CMP_VERYLOWSPEED: very-low speed mode
|
||||
\param[in] inverting_input
|
||||
\arg CMP_1_4VREFINT: VREFINT *1/4 input
|
||||
\arg CMP_1_2VREFINT: VREFINT *1/2 input
|
||||
\arg CMP_3_4VREFINT: VREFINT *3/4 input
|
||||
\arg CMP_VREFINT: VREFINT input
|
||||
\arg CMP_DAC: PA4 (DAC) input
|
||||
\arg CMP_PA5: PA5 input
|
||||
\arg CMP_PA_0_2: PA0 or PA2 input
|
||||
\param[in] hysteresis
|
||||
\arg CMP_HYSTERESIS_NO: output no hysteresis
|
||||
\arg CMP_HYSTERESIS_LOW: output low hysteresis
|
||||
\arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis
|
||||
\arg CMP_HYSTERESIS_HIGH: output high hysteresis
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_mode_init(uint32_t cmp_periph, operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis)
|
||||
{
|
||||
if(CMP0 == cmp_periph){
|
||||
/* initialize comparator 0 mode */
|
||||
CMP_CS &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST );
|
||||
CMP_CS |= CS_CMP0M(operating_mode) | CS_CMP0MSEL(inverting_input) | CS_CMP0HST(output_hysteresis);
|
||||
}else{
|
||||
/* initialize comparator 1 mode */
|
||||
CMP_CS &= ~(uint32_t)(CMP_CS_CMP1M | CMP_CS_CMP1MSEL | CMP_CS_CMP1HST );
|
||||
CMP_CS |= CS_CMP1M(operating_mode) | CS_CMP1MSEL(inverting_input) | CS_CMP1HST(output_hysteresis);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize comparator output
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\arg CMP1: comparator 1
|
||||
\param[in] output_slection
|
||||
\arg CMP_OUTPUT_NONE: output no selection
|
||||
\arg CMP_OUTPUT_TIMER0BKIN: TIMER 0 break input
|
||||
\arg CMP_OUTPUT_TIMER0IC0: TIMER 0 channel0 input capture
|
||||
\arg CMP_OUTPUT_TIMER0OCPRECLR: TIMER 0 OCPRE_CLR input
|
||||
\arg CMP_OUTPUT_TIMER1IC3: TIMER 1 channel3 input capture
|
||||
\arg CMP_OUTPUT_TIMER1OCPRECLR: TIMER 1 OCPRE_CLR input
|
||||
\arg CMP_OUTPUT_TIMER2IC0: TIMER 2 channel0 input capture
|
||||
\arg CMP_OUTPUT_TIMER2OCPRECLR: TIMER 2 OCPRE_CLR input
|
||||
\param[in] output_polarity
|
||||
\arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted
|
||||
\arg CMP_OUTPUT_POLARITY_NOINVERTED: output is not inverted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_output_init(uint32_t cmp_periph, cmp_output_enum output_slection, uint32_t output_polarity)
|
||||
{
|
||||
/* initialize comparator 0 output */
|
||||
if(CMP0 == cmp_periph){
|
||||
CMP_CS &= ~(uint32_t)CMP_CS_CMP0OSEL;
|
||||
CMP_CS |= CS_CMP0OSEL(output_slection);
|
||||
/* output polarity */
|
||||
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
|
||||
CMP_CS |= CMP_CS_CMP0PL;
|
||||
}else{
|
||||
CMP_CS &= ~CMP_CS_CMP0PL;
|
||||
}
|
||||
}else{
|
||||
/* initialize comparator 1 output */
|
||||
CMP_CS &= ~(uint32_t)CMP_CS_CMP1OSEL;
|
||||
CMP_CS |= CS_CMP1OSEL(output_slection);
|
||||
/* output polarity */
|
||||
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity){
|
||||
CMP_CS |= CMP_CS_CMP1PL;
|
||||
}else{
|
||||
CMP_CS &= ~CMP_CS_CMP1PL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable comparator
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\arg CMP1: comparator 1
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_enable(uint32_t cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph){
|
||||
CMP_CS |= CMP_CS_CMP0EN;
|
||||
}else{
|
||||
CMP_CS |= CMP_CS_CMP1EN;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable comparator
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\arg CMP1: comparator 1
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_disable(uint32_t cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph){
|
||||
CMP_CS &= ~CMP_CS_CMP0EN;
|
||||
}else{
|
||||
CMP_CS &= ~CMP_CS_CMP1EN;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable comparator switch
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_switch_enable(void)
|
||||
{
|
||||
CMP_CS |= CMP_CS_CMP0SW;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable comparator switch
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_switch_disable(void)
|
||||
{
|
||||
CMP_CS &= ~CMP_CS_CMP0SW;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the window mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_window_enable(void)
|
||||
{
|
||||
CMP_CS |= CMP_CS_WNDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the window mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_window_disable(void)
|
||||
{
|
||||
CMP_CS &= ~CMP_CS_WNDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief lock the comparator
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\arg CMP1: comparator 1
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_lock_enable(uint32_t cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph){
|
||||
/* lock CMP0 */
|
||||
CMP_CS |= CMP_CS_CMP0LK;
|
||||
}else{
|
||||
/* lock CMP1 */
|
||||
CMP_CS |= CMP_CS_CMP1LK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get output level
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\arg CMP1: comparator 1
|
||||
\param[out] none
|
||||
\retval the output level
|
||||
*/
|
||||
uint32_t cmp_output_level_get(uint32_t cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph){
|
||||
/* get output level of CMP0 */
|
||||
if(CMP_CS & CMP_CS_CMP0O){
|
||||
return CMP_OUTPUTLEVEL_HIGH;
|
||||
}else{
|
||||
return CMP_OUTPUTLEVEL_LOW;
|
||||
}
|
||||
}else{
|
||||
/* get output level of CMP1 */
|
||||
if(CMP_CS & CMP_CS_CMP1O){
|
||||
return CMP_OUTPUTLEVEL_HIGH;
|
||||
}else{
|
||||
return CMP_OUTPUTLEVEL_LOW;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,207 @@
|
||||
/*!
|
||||
\file gd32f3x0_crc.c
|
||||
\brief CRC driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_crc.h"
|
||||
|
||||
/*!
|
||||
\brief deinit CRC calculation unit
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_deinit(void)
|
||||
{
|
||||
CRC_IDATA = (uint32_t)0xFFFFFFFFU;
|
||||
CRC_DATA = (uint32_t)0xFFFFFFFFU;
|
||||
CRC_FDATA = (uint32_t)0x00000000U;
|
||||
CRC_POLY = (uint32_t)0x04C11DB7U;
|
||||
CRC_CTL = CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the reverse operation of output data
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_reverse_output_data_enable(void)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_REV_O;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the reverse operation of output data
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_reverse_output_data_disable(void)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset data register to the value of initializaiton data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_data_register_reset(void)
|
||||
{
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 32-bit value of the data register
|
||||
*/
|
||||
uint32_t crc_data_register_read(void)
|
||||
{
|
||||
uint32_t data;
|
||||
data = CRC_DATA;
|
||||
return (data);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the free data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 8-bit value of the free data register
|
||||
*/
|
||||
uint8_t crc_free_data_register_read(void)
|
||||
{
|
||||
uint8_t fdata;
|
||||
fdata = (uint8_t)CRC_FDATA;
|
||||
return (fdata);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write the free data register
|
||||
\param[in] free_data: specify 8-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_free_data_register_write(uint8_t free_data)
|
||||
{
|
||||
CRC_FDATA = (uint32_t)free_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write the initializaiton data register
|
||||
\param[in] init_data:specify 32-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_init_data_register_write(uint32_t init_data)
|
||||
{
|
||||
CRC_IDATA = (uint32_t)init_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC input data function
|
||||
\param[in] data_reverse: specify input data reverse function
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CRC_INPUT_DATA_NOT: input data is not reversed
|
||||
\arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
|
||||
\arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
|
||||
\arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_input_data_reverse_config(uint32_t data_reverse)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I);
|
||||
CRC_CTL |= (uint32_t)data_reverse;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC size of polynomial function
|
||||
\param[in] poly_size: size of polynomial
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_polynomial_size_set(uint32_t poly_size)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
|
||||
CRC_CTL |= (uint32_t)poly_size;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC polynomial value function
|
||||
\param[in] poly: configurable polynomial value
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_polynomial_set(uint32_t poly)
|
||||
{
|
||||
CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
|
||||
CRC_POLY = poly;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CRC calculate a 32-bit data
|
||||
\param[in] sdata: specify 32-bit data
|
||||
\param[out] none
|
||||
\retval 32-bit CRC calculate value
|
||||
*/
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata)
|
||||
{
|
||||
CRC_DATA = sdata;
|
||||
return(CRC_DATA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CRC calculate a 32-bit data array
|
||||
\param[in] array: pointer to an array of 32 bit data words
|
||||
\param[in] size: size of the array
|
||||
\param[out] none
|
||||
\retval 32-bit CRC calculate value
|
||||
*/
|
||||
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
|
||||
{
|
||||
uint32_t index;
|
||||
for(index = 0U; index < size; index++){
|
||||
CRC_DATA = array[index];
|
||||
}
|
||||
return (CRC_DATA);
|
||||
}
|
||||
@@ -0,0 +1,382 @@
|
||||
/*!
|
||||
\file gd32f3x0_ctc.c
|
||||
\brief CTC driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_ctc.h"
|
||||
|
||||
#define CTC_FLAG_MASK ((uint32_t)0x00000700U)
|
||||
|
||||
/*!
|
||||
\brief reset CTC clock trim controller
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_deinit(void)
|
||||
{
|
||||
/* reset CTC */
|
||||
rcu_periph_reset_enable(RCU_CTCRST);
|
||||
rcu_periph_reset_disable(RCU_CTCRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure reference signal source polarity
|
||||
\param[in] polarity:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge
|
||||
\arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_refsource_polarity_config(uint32_t polarity)
|
||||
{
|
||||
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL);
|
||||
CTC_CTL1 |= (uint32_t)polarity;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief select reference signal source
|
||||
\param[in] refs:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CTC_REFSOURCE_GPIO: GPIO is selected
|
||||
\arg CTC_REFSOURCE_LXTAL: LXTAL is clock selected
|
||||
\arg CTC_REFSOURCE_USBSOF: USBSOF is selected
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_refsource_signal_select(uint32_t refs)
|
||||
{
|
||||
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL);
|
||||
CTC_CTL1 |= (uint32_t)refs;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure reference signal source prescaler
|
||||
\param[in] prescaler:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CTC_REFSOURCE_PSC_OFF: reference signal not divided
|
||||
\arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2
|
||||
\arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4
|
||||
\arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8
|
||||
\arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16
|
||||
\arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32
|
||||
\arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64
|
||||
\arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_refsource_prescaler_config(uint32_t prescaler)
|
||||
{
|
||||
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC);
|
||||
CTC_CTL1 |= (uint32_t)prescaler;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure clock trim base limit value
|
||||
\param[in] limit_value: 8-bit clock trim base limit value
|
||||
\arg 0x00-0xFF
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_clock_limit_value_config(uint8_t limit_value)
|
||||
{
|
||||
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM);
|
||||
CTC_CTL1 |= CTL1_CKLIM(limit_value);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure CTC counter reload value
|
||||
\param[in] reload_value: 16-bit CTC counter reload value
|
||||
\arg 0x0000-0xFFFF
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_counter_reload_value_config(uint16_t reload_value)
|
||||
{
|
||||
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE);
|
||||
CTC_CTL1 |= (uint32_t)reload_value;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable CTC trim counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_counter_enable(void)
|
||||
{
|
||||
CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable CTC trim counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_counter_disable(void)
|
||||
{
|
||||
CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the IRC48M trim value
|
||||
\param[in] trim_value: 8-bit IRC48M trim value
|
||||
\arg 0x00-0x3F
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_irc48m_trim_value_config(uint8_t trim_value)
|
||||
{
|
||||
/* clear TRIMVALUE bits */
|
||||
CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE);
|
||||
/* set TRIMVALUE bits */
|
||||
CTC_CTL0 |= CTL0_TRIMVALUE(trim_value);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief generate software reference source sync pulse
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_software_refsource_pulse_generate(void)
|
||||
{
|
||||
CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure hardware automatically trim mode
|
||||
\param[in] hardmode:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable
|
||||
\arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_hardware_trim_mode_config(uint32_t hardmode)
|
||||
{
|
||||
CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM);
|
||||
CTC_CTL0 |= (uint32_t)hardmode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read CTC counter capture value when reference sync pulse occurred
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval the 16-bit CTC counter capture value
|
||||
*/
|
||||
uint16_t ctc_counter_capture_value_read(void)
|
||||
{
|
||||
uint16_t capture_value = 0U;
|
||||
capture_value = (uint16_t)GET_STAT_REFCAP(CTC_STAT);
|
||||
return (capture_value);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read CTC trim counter direction when reference sync pulse occurred
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
\arg SET: CTC trim counter direction is down-counting
|
||||
\arg RESET: CTC trim counter direction is up-counting
|
||||
*/
|
||||
FlagStatus ctc_counter_direction_read(void)
|
||||
{
|
||||
FlagStatus ret_status = RESET;
|
||||
if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){
|
||||
ret_status = SET;
|
||||
}
|
||||
return ret_status;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read CTC counter reload value
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval the 16-bit CTC counter reload value
|
||||
*/
|
||||
uint16_t ctc_counter_reload_value_read(void)
|
||||
{
|
||||
uint16_t reload_value = 0U;
|
||||
reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE);
|
||||
return (reload_value);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the IRC48M trim value
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval the 8-bit IRC48M trim value
|
||||
*/
|
||||
uint8_t ctc_irc48m_trim_value_read(void)
|
||||
{
|
||||
uint8_t trim_value = 0U;
|
||||
trim_value = (uint8_t)GET_CTL0_TRIMVALUE(CTC_CTL0);
|
||||
return (trim_value);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the CTC interrupt
|
||||
\param[in] interrupt: CTC interrupt enable
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CTC_INT_CKOK: clock trim OK interrupt enable
|
||||
\arg CTC_INT_CKWARN: clock trim warning interrupt enable
|
||||
\arg CTC_INT_ERR: error interrupt enable
|
||||
\arg CTC_INT_EREF: expect reference interrupt enable
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_interrupt_enable(uint32_t interrupt)
|
||||
{
|
||||
CTC_CTL0 |= (uint32_t)interrupt;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the CTC interrupt
|
||||
\param[in] interrupt: CTC interrupt enable source
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg CTC_INT_CKOK: clock trim OK interrupt enable
|
||||
\arg CTC_INT_CKWARN: clock trim warning interrupt enable
|
||||
\arg CTC_INT_ERR: error interrupt enable
|
||||
\arg CTC_INT_EREF: expect reference interrupt enable
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_interrupt_disable(uint32_t interrupt)
|
||||
{
|
||||
CTC_CTL0 &= (uint32_t)(~(interrupt));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get CTC flag
|
||||
\param[in] flag: the CTC flag
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CTC_FLAG_CKOK: clock trim OK flag
|
||||
\arg CTC_FLAG_CKWARN: clock trim warning flag
|
||||
\arg CTC_FLAG_ERR: error flag
|
||||
\arg CTC_FLAG_EREF: expect reference flag
|
||||
\arg CTC_FLAG_CKERR: clock trim error bit
|
||||
\arg CTC_FLAG_REFMISS: reference sync pulse miss
|
||||
\arg CTC_FLAG_TRIMERR: trim value error bit
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus ctc_flag_get(uint32_t flag)
|
||||
{
|
||||
FlagStatus ret_status = RESET;
|
||||
|
||||
if(RESET != (CTC_STAT & flag)){
|
||||
ret_status = SET;
|
||||
}
|
||||
return ret_status;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear CTC flag
|
||||
\param[in] flag: the CTC flag
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CTC_FLAG_CKOK: clock trim OK flag
|
||||
\arg CTC_FLAG_CKWARN: clock trim warning flag
|
||||
\arg CTC_FLAG_ERR: error flag
|
||||
\arg CTC_FLAG_EREF: expect reference flag
|
||||
\arg CTC_FLAG_CKERR: clock trim error bit
|
||||
\arg CTC_FLAG_REFMISS: reference sync pulse miss
|
||||
\arg CTC_FLAG_TRIMERR: trim value error bit
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_flag_clear(uint32_t flag)
|
||||
{
|
||||
if(flag & CTC_FLAG_MASK){
|
||||
CTC_INTC |= CTC_INTC_ERRIC;
|
||||
}else{
|
||||
CTC_INTC |= flag;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get CTC interrupt flag
|
||||
\param[in] interrupt: the CTC interrupt flag
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt
|
||||
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt
|
||||
\arg CTC_INT_FLAG_ERR: error interrupt
|
||||
\arg CTC_INT_FLAG_EREF: expect reference interrupt
|
||||
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt
|
||||
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
|
||||
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus ctc_interrupt_flag_get(uint32_t interrupt)
|
||||
{
|
||||
uint32_t ctc_int = 0U, intenable = 0U;
|
||||
FlagStatus ret_status = RESET;
|
||||
|
||||
if(interrupt & CTC_FLAG_MASK){
|
||||
intenable = CTC_CTL0 & CTC_INT_ERR;
|
||||
}else{
|
||||
intenable = CTC_CTL0 & interrupt;
|
||||
}
|
||||
ctc_int = CTC_STAT & interrupt;
|
||||
|
||||
if(ctc_int && intenable){
|
||||
ret_status = SET;
|
||||
}
|
||||
return ret_status;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear CTC interrupt flag
|
||||
\param[in] interrupt: the CTC interrupt flag
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt
|
||||
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt
|
||||
\arg CTC_INT_FLAG_ERR: error interrupt
|
||||
\arg CTC_INT_FLAG_EREF: expect reference interrupt
|
||||
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt
|
||||
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
|
||||
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void ctc_interrupt_flag_clear(uint32_t interrupt)
|
||||
{
|
||||
if(interrupt & CTC_FLAG_MASK){
|
||||
CTC_INTC |= CTC_INTC_ERRIC;
|
||||
}else{
|
||||
CTC_INTC |= interrupt;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,387 @@
|
||||
/*!
|
||||
\file gd32f3x0_dac.c
|
||||
\brief DAC driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifdef GD32F350
|
||||
#include "gd32f3x0_dac.h"
|
||||
|
||||
/*!
|
||||
\brief deinitialize DAC
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_deinit(void)
|
||||
{
|
||||
rcu_periph_reset_enable(RCU_DACRST);
|
||||
rcu_periph_reset_disable(RCU_DACRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable DAC
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_enable(void)
|
||||
{
|
||||
DAC_CTL |= DAC_CTL_DEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable DAC
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_disable(void)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable DAC DMA
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_dma_enable(void)
|
||||
{
|
||||
DAC_CTL |= DAC_CTL_DDMAEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable DAC DMA
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_dma_disable(void)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DDMAEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable DAC output buffer
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_output_buffer_enable(void)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DBOFF;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable DAC output buffer
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_output_buffer_disable(void)
|
||||
{
|
||||
DAC_CTL |= DAC_CTL_DBOFF;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable DAC trigger
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_trigger_enable(void)
|
||||
{
|
||||
DAC_CTL |= DAC_CTL_DTEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable DAC trigger
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_trigger_disable(void)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DTEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable DAC software trigger
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_software_trigger_enable(void)
|
||||
{
|
||||
DAC_SWT |= DAC_SWT_SWTR;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable DAC software trigger
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_software_trigger_disable(void)
|
||||
{
|
||||
DAC_SWT &= ~DAC_SWT_SWTR;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable DAC interrupt(DAC DMA underrun interrupt)
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_interrupt_enable(void)
|
||||
{
|
||||
DAC_CTL |= DAC_CTL_DDUDRIE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable DAC interrupt(DAC DMA underrun interrupt)
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_interrupt_disable(void)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DDUDRIE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set DAC tgigger source
|
||||
\param[in] triggersource: external triggers of DAC
|
||||
\arg DAC_TRIGGER_T1_TRGO: trigger source is TIMER1 TRGO
|
||||
\arg DAC_TRIGGER_T2_TRGO: trigger source is TIMER2 TRGO
|
||||
\arg DAC_TRIGGER_T5_TRGO: trigger source is TIMER5 TRGO
|
||||
\arg DAC_TRIGGER_T14_TRGO: trigger source is TIMER14 TRGO
|
||||
\arg DAC_TRIGGER_EXTI_9: trigger source is EXTI interrupt line9 event
|
||||
\arg DAC_TRIGGER_SOFTWARE: software trigger
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_trigger_source_config(uint32_t triggersource)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DTSEL;
|
||||
DAC_CTL |= triggersource;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure DAC wave mode
|
||||
\param[in] wave_mode
|
||||
\arg DAC_WAVE_DISABLE: wave disable
|
||||
\arg DAC_WAVE_MODE_LFSR: LFSR noise mode
|
||||
\arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_wave_mode_config(uint32_t wave_mode)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DWM;
|
||||
DAC_CTL |= wave_mode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure DAC wave bit width
|
||||
\param[in] bit_width
|
||||
\arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
|
||||
\arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
|
||||
\arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
|
||||
\arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
|
||||
\arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
|
||||
\arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
|
||||
\arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
|
||||
\arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
|
||||
\arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
|
||||
\arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
|
||||
\arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
|
||||
\arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_wave_bit_width_config(uint32_t bit_width)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DWBW;
|
||||
DAC_CTL |= bit_width;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure DAC LFSR noise mode
|
||||
\param[in] unmask_bits
|
||||
\arg DAC_LFSR_BIT0: unmask the LFSR bit0
|
||||
\arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
|
||||
\arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
|
||||
\arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
|
||||
\arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
|
||||
\arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
|
||||
\arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
|
||||
\arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
|
||||
\arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
|
||||
\arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
|
||||
\arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
|
||||
\arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_lfsr_noise_config(uint32_t unmask_bits)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DWBW;
|
||||
DAC_CTL |= unmask_bits;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure DAC triangle noise mode
|
||||
\param[in] amplitude
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
|
||||
\arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_triangle_noise_config(uint32_t amplitude)
|
||||
{
|
||||
DAC_CTL &= ~DAC_CTL_DWBW;
|
||||
DAC_CTL |= amplitude;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get DAC output value
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval DAC output data
|
||||
*/
|
||||
uint16_t dac_output_value_get(void)
|
||||
{
|
||||
uint16_t data = 0U;
|
||||
data = (uint16_t)DAC_DO;
|
||||
return data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get the specified DAC flag(DAC DMA underrun flag)
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval the state of dac bit(SET or RESET)
|
||||
*/
|
||||
FlagStatus dac_flag_get(void)
|
||||
{
|
||||
/* check the DMA underrun flag */
|
||||
if((uint8_t)RESET != (DAC_STAT & DAC_STAT_DDUDR)){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear the specified DAC flag(DAC DMA underrun flag)
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_flag_clear(void)
|
||||
{
|
||||
DAC_STAT |= DAC_STAT_DDUDR;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval the state of DAC interrupt flag(SET or RESET)
|
||||
*/
|
||||
FlagStatus dac_interrupt_flag_get(void)
|
||||
{
|
||||
FlagStatus temp_flag = RESET;
|
||||
uint32_t ddudr_flag = 0U, ddudrie_flag = 0U;
|
||||
/* check the DMA underrun flag and DAC DMA underrun interrupt enable flag */
|
||||
ddudr_flag = DAC_STAT & DAC_STAT_DDUDR;
|
||||
ddudrie_flag = DAC_CTL & DAC_CTL_DDUDRIE;
|
||||
if((RESET != ddudr_flag) && (RESET != ddudrie_flag)){
|
||||
temp_flag = SET;
|
||||
}
|
||||
return temp_flag;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear the specified DAC interrupt flag(DAC DMA underrun interrupt flag)
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_interrupt_flag_clear(void)
|
||||
{
|
||||
DAC_STAT |= DAC_STAT_DDUDR;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set DAC data holding register value
|
||||
\param[in] dac_align
|
||||
\arg DAC_ALIGN_8B_R: data right 8b alignment
|
||||
\arg DAC_ALIGN_12B_R: data right 12b alignment
|
||||
\arg DAC_ALIGN_12B_L: data left 12b alignment
|
||||
\param[in] data: data to be loaded
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dac_data_set(uint32_t dac_align, uint16_t data)
|
||||
{
|
||||
switch(dac_align){
|
||||
/* data right 12b alignment */
|
||||
case DAC_ALIGN_12B_R:
|
||||
DAC_R12DH = data;
|
||||
break;
|
||||
/* data left 12b alignment */
|
||||
case DAC_ALIGN_12B_L:
|
||||
DAC_L12DH = data;
|
||||
break;
|
||||
/* data right 8b alignment */
|
||||
case DAC_ALIGN_8B_R:
|
||||
DAC_R8DH = data;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* GD32F350 */
|
||||
@@ -0,0 +1,131 @@
|
||||
/*!
|
||||
\file gd32f3x0_dbg.c
|
||||
\brief DBG driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_dbg.h"
|
||||
|
||||
#define DBG_RESET_VAL ((uint32_t)0x00000000U) /*!< DBG reset value */
|
||||
|
||||
/*!
|
||||
\brief deinitialize the DBG
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_deinit(void)
|
||||
{
|
||||
DBG_CTL0 = DBG_RESET_VAL;
|
||||
DBG_CTL1 = DBG_RESET_VAL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read DBG_ID code register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval DBG_ID code
|
||||
*/
|
||||
uint32_t dbg_id_get(void)
|
||||
{
|
||||
return DBG_ID;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL0 |= dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL0 &= ~dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode
|
||||
\arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
|
||||
\arg DBG_STANDBY_HOLD: keep debugger connection during standby mode
|
||||
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
|
||||
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: refer to dbg_periph_enum
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg DBG_SLEEP_HOLD: keep debugger connection during sleep mode
|
||||
\arg DBG_DEEPSLEEP_HOLD: keep debugger connection during deepsleep mode
|
||||
\arg DBG_STANDBY_HOLD: keep debugger connection during standby mode
|
||||
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||
\arg DBG_TIMERx_HOLD (x=0,1,2,5,13,14,15,16,TIMER5 is only available in GD32F350): hold TIMERx counter when core is halted
|
||||
\arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
|
||||
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,253 @@
|
||||
/*!
|
||||
\file gd32f3x0_exti.c
|
||||
\brief EXTI driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_exti.h"
|
||||
|
||||
/*!
|
||||
\brief deinitialize the EXTI
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_deinit(void)
|
||||
{
|
||||
/* reset the value of all the EXTI registers */
|
||||
EXTI_INTEN = (uint32_t)0x0F940000U;
|
||||
EXTI_EVEN = (uint32_t)0x00000000U;
|
||||
EXTI_RTEN = (uint32_t)0x00000000U;
|
||||
EXTI_FTEN = (uint32_t)0x00000000U;
|
||||
EXTI_SWIEV = (uint32_t)0x00000000U;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize the EXTI, enable the configuration of EXTI initialize
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..19,21,22): EXTI line x
|
||||
\param[in] mode: interrupt or event mode, refer to exti_mode_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_INTERRUPT: interrupt mode
|
||||
\arg EXTI_EVENT: event mode
|
||||
\param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_TRIG_RISING: rising edge trigger
|
||||
\arg EXTI_TRIG_FALLING: falling trigger
|
||||
\arg EXTI_TRIG_BOTH: rising and falling trigger
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_init(exti_line_enum linex, \
|
||||
exti_mode_enum mode, \
|
||||
exti_trig_type_enum trig_type)
|
||||
{
|
||||
/* reset the EXTI line x */
|
||||
EXTI_INTEN &= ~(uint32_t)linex;
|
||||
EXTI_EVEN &= ~(uint32_t)linex;
|
||||
EXTI_RTEN &= ~(uint32_t)linex;
|
||||
EXTI_FTEN &= ~(uint32_t)linex;
|
||||
|
||||
/* set the EXTI mode and enable the interrupts or events from EXTI line x */
|
||||
switch(mode){
|
||||
case EXTI_INTERRUPT:
|
||||
EXTI_INTEN |= (uint32_t)linex;
|
||||
break;
|
||||
case EXTI_EVENT:
|
||||
EXTI_EVEN |= (uint32_t)linex;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* set the EXTI trigger type */
|
||||
switch(trig_type){
|
||||
case EXTI_TRIG_RISING:
|
||||
EXTI_RTEN |= (uint32_t)linex;
|
||||
EXTI_FTEN &= ~(uint32_t)linex;
|
||||
break;
|
||||
case EXTI_TRIG_FALLING:
|
||||
EXTI_RTEN &= ~(uint32_t)linex;
|
||||
EXTI_FTEN |= (uint32_t)linex;
|
||||
break;
|
||||
case EXTI_TRIG_BOTH:
|
||||
EXTI_RTEN |= (uint32_t)linex;
|
||||
EXTI_FTEN |= (uint32_t)linex;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the interrupts from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_INTEN |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the interrupt from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_INTEN &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the events from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_event_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_EVEN |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the events from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_event_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_EVEN &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable EXTI software interrupt event
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..19,21,22): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_software_interrupt_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_SWIEV |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable EXTI software interrupt event
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..19,21,22): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_software_interrupt_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_SWIEV &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get EXTI line x pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..19,21,22): EXTI line x
|
||||
\param[out] none
|
||||
\retval FlagStatus: status of flag (RESET or SET)
|
||||
*/
|
||||
FlagStatus exti_flag_get(exti_line_enum linex)
|
||||
{
|
||||
if(RESET != (EXTI_PD & (uint32_t)linex)){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear EXTI line x pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..19,21,22): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_flag_clear(exti_line_enum linex)
|
||||
{
|
||||
EXTI_PD = (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get EXTI line x flag when the interrupt flag is set
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..19,21,22): EXTI line x
|
||||
\param[out] none
|
||||
\retval FlagStatus: status of flag (RESET or SET)
|
||||
*/
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
|
||||
{
|
||||
uint32_t flag_left, flag_right;
|
||||
|
||||
flag_left = EXTI_PD & (uint32_t)linex;
|
||||
flag_right = EXTI_INTEN & (uint32_t)linex;
|
||||
|
||||
if((RESET != flag_left) && (RESET != flag_right)){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear EXTI line x pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..19,21,22): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex)
|
||||
{
|
||||
EXTI_PD = (uint32_t)linex;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f3x0_fwdgt.c
|
||||
\brief FWDGT driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_fwdgt.h"
|
||||
|
||||
/*!
|
||||
\brief enable write access to FWDGT_PSC and FWDGT_RLD
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_disable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the free watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the free watchdog timer counter window value
|
||||
\param[in] window_value: specify window value(0x0000 - 0x0FFF)
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_window_value_config(uint16_t window_value)
|
||||
{
|
||||
uint32_t time_index = FWDGT_WND_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_WND */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the WUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
|
||||
}while((--time_index > 0U) && (RESET != flag_status));
|
||||
|
||||
if (RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
FWDGT_WND = WND_WND(window_value);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reload the counter of FWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_counter_reload(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
}
|
||||
|
||||
|
||||
/*!
|
||||
\brief configure counter reload value, and prescaler divider value
|
||||
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[in] prescaler_div: FWDGT prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
|
||||
{
|
||||
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the PUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
}while((--timeout > 0U) && (RESET != flag_status));
|
||||
|
||||
if (RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* configure FWDGT */
|
||||
FWDGT_PSC = (uint32_t)prescaler_div;
|
||||
|
||||
timeout = FWDGT_RLD_TIMEOUT;
|
||||
/* wait until the RUD flag to be reset */
|
||||
do{
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
}while((--timeout > 0U) && (RESET != flag_status));
|
||||
|
||||
if (RESET != flag_status){
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
FWDGT_RLD = RLD_RLD(reload_value);
|
||||
|
||||
/* reload the counter */
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state of FWDGT
|
||||
\param[in] flag: flag to get
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
|
||||
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
|
||||
\arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag)
|
||||
{
|
||||
if(FWDGT_STAT & flag){
|
||||
return SET;
|
||||
}
|
||||
return RESET;
|
||||
}
|
||||
@@ -0,0 +1,424 @@
|
||||
/*!
|
||||
\file gd32f3x0_gpio.c
|
||||
\brief GPIO driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_gpio.h"
|
||||
|
||||
/*!
|
||||
\brief reset GPIO port
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_deinit(uint32_t gpio_periph)
|
||||
{
|
||||
switch(gpio_periph){
|
||||
case GPIOA:
|
||||
/* reset GPIOA */
|
||||
rcu_periph_reset_enable(RCU_GPIOARST);
|
||||
rcu_periph_reset_disable(RCU_GPIOARST);
|
||||
break;
|
||||
case GPIOB:
|
||||
/* reset GPIOB */
|
||||
rcu_periph_reset_enable(RCU_GPIOBRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOBRST);
|
||||
break;
|
||||
case GPIOC:
|
||||
/* reset GPIOC */
|
||||
rcu_periph_reset_enable(RCU_GPIOCRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOCRST);
|
||||
break;
|
||||
case GPIOD:
|
||||
/* reset GPIOD */
|
||||
rcu_periph_reset_enable(RCU_GPIODRST);
|
||||
rcu_periph_reset_disable(RCU_GPIODRST);
|
||||
break;
|
||||
case GPIOF:
|
||||
/* reset GPIOF */
|
||||
rcu_periph_reset_enable(RCU_GPIOFRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOFRST);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO mode
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] mode: gpio pin mode
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIO_MODE_INPUT: input mode
|
||||
\arg GPIO_MODE_OUTPUT: output mode
|
||||
\arg GPIO_MODE_AF: alternate function mode
|
||||
\arg GPIO_MODE_ANALOG: analog mode
|
||||
\param[in] pull_up_down: gpio pin with pull-up or pull-down resistor
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors
|
||||
\arg GPIO_PUPD_PULLUP: with pull-up resistor
|
||||
\arg GPIO_PUPD_PULLDOWN:with pull-down resistor
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t ctl, pupd;
|
||||
|
||||
ctl = GPIO_CTL(gpio_periph);
|
||||
pupd = GPIO_PUD(gpio_periph);
|
||||
|
||||
for(i = 0U;i < 16U;i++){
|
||||
if((1U << i) & pin){
|
||||
/* clear the specified pin mode bits */
|
||||
ctl &= ~GPIO_MODE_MASK(i);
|
||||
/* set the specified pin mode bits */
|
||||
ctl |= GPIO_MODE_SET(i, mode);
|
||||
|
||||
/* clear the specified pin pupd bits */
|
||||
pupd &= ~GPIO_PUPD_MASK(i);
|
||||
/* set the specified pin pupd bits */
|
||||
pupd |= GPIO_PUPD_SET(i, pull_up_down);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_CTL(gpio_periph) = ctl;
|
||||
GPIO_PUD(gpio_periph) = pupd;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO output type and speed
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] otype: gpio pin output mode
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIO_OTYPE_PP: push pull mode
|
||||
\arg GPIO_OTYPE_OD: open drain mode
|
||||
\param[in] speed: gpio pin output max speed
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIO_OSPEED_2MHZ: output max speed 2MHz
|
||||
\arg GPIO_OSPEED_10MHZ: output max speed 10MHz
|
||||
\arg GPIO_OSPEED_50MHZ: output max speed 50MHz
|
||||
\arg GPIO_OSPEED_MAX: GPIO very high output speed, max speed more than 50MHz
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t ospeed0,ospeed1;
|
||||
|
||||
if(GPIO_OTYPE_OD == otype){
|
||||
GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
|
||||
}else{
|
||||
GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
|
||||
}
|
||||
|
||||
/* get the specified pin output speed bits value */
|
||||
ospeed0 = GPIO_OSPD0(gpio_periph);
|
||||
|
||||
if(GPIO_OSPEED_MAX == speed){
|
||||
ospeed1 = GPIO_OSPD1(gpio_periph);
|
||||
|
||||
for(i = 0U;i < 16U;i++){
|
||||
if((1U << i) & pin){
|
||||
/* enable very high output speed function of the pin when the corresponding OSPDy(y=0..15)
|
||||
is "11" (output max speed 50MHz) */
|
||||
ospeed0 |= GPIO_OSPEED_SET(i,0x03);
|
||||
ospeed1 |= (1U << i);
|
||||
}
|
||||
}
|
||||
GPIO_OSPD0(gpio_periph) = ospeed0;
|
||||
GPIO_OSPD1(gpio_periph) = ospeed1;
|
||||
}else{
|
||||
for(i = 0U;i < 16U;i++){
|
||||
if((1U << i) & pin){
|
||||
/* clear the specified pin output speed bits */
|
||||
ospeed0 &= ~GPIO_OSPEED_MASK(i);
|
||||
/* set the specified pin output speed bits */
|
||||
ospeed0 |= GPIO_OSPEED_SET(i,speed);
|
||||
}
|
||||
}
|
||||
GPIO_OSPD0(gpio_periph) = ospeed0;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_BOP(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_BC(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the specified GPIO pin
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[in] bit_value: SET or RESET
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg RESET: clear the port pin
|
||||
\arg SET: set the port pin
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
|
||||
{
|
||||
if(RESET != bit_value){
|
||||
GPIO_BOP(gpio_periph) = (uint32_t)pin;
|
||||
}else{
|
||||
GPIO_BC(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the specified GPIO port
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] data: specify the value to be written to the port output control register
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data)
|
||||
{
|
||||
GPIO_OCTL(gpio_periph) = (uint32_t)data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO pin input status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval SET or RESET
|
||||
*/
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO all pins input status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[out] none
|
||||
\retval state of GPIO all pins
|
||||
*/
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph)
|
||||
{
|
||||
return (uint16_t)GPIO_ISTAT(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO pin output status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval SET or RESET
|
||||
*/
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
if((uint32_t)RESET != (GPIO_OCTL(gpio_periph)&(pin))){
|
||||
return SET;
|
||||
}else{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO all pins output status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[out] none
|
||||
\retval state of GPIO all pins
|
||||
*/
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph)
|
||||
{
|
||||
return (uint16_t)GPIO_OCTL(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO alternate function
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C)
|
||||
\param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIO_AF_0: TIMER2, TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, CEC,
|
||||
IFRP, TSI, CTC, I2C0, I2C1, SWDIO, SWCLK
|
||||
\arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1, IFRP, CEC
|
||||
\arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0
|
||||
\arg GPIO_AF_3: TSI, I2C0, TIMER14
|
||||
\arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13
|
||||
\arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, USBFS, I2S0
|
||||
\arg GPIO_AF_6(port A,B only): CTC, SPI1
|
||||
\arg GPIO_AF_7(port A,B only): CMP0, CMP1
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t afrl, afrh;
|
||||
|
||||
afrl = GPIO_AFSEL0(gpio_periph);
|
||||
afrh = GPIO_AFSEL1(gpio_periph);
|
||||
|
||||
for(i = 0U;i < 8U;i++){
|
||||
if((1U << i) & pin){
|
||||
/* clear the specified pin alternate function bits */
|
||||
afrl &= ~GPIO_AFR_MASK(i);
|
||||
afrl |= GPIO_AFR_SET(i,alt_func_num);
|
||||
}
|
||||
}
|
||||
|
||||
for(i = 8U;i < 16U;i++){
|
||||
if((1U << i) & pin){
|
||||
/* clear the specified pin alternate function bits */
|
||||
afrh &= ~GPIO_AFR_MASK(i - 8U);
|
||||
afrh |= GPIO_AFR_SET(i - 8U,alt_func_num);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_AFSEL0(gpio_periph) = afrl;
|
||||
GPIO_AFSEL1(gpio_periph) = afrh;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief lock GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
uint32_t lock = 0x00010000U;
|
||||
lock |= pin;
|
||||
|
||||
/* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)pin;
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
|
||||
lock = GPIO_LOCK(gpio_periph);
|
||||
lock = GPIO_LOCK(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief toggle GPIO pin status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,D,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_TG(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief toggle GPIO port status
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,D,F)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_port_toggle(uint32_t gpio_periph)
|
||||
{
|
||||
GPIO_TG(gpio_periph) = 0x0000FFFFU;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,189 @@
|
||||
/*!
|
||||
\file gd32f3x0_misc.c
|
||||
\brief MISC driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_misc.h"
|
||||
|
||||
/*!
|
||||
\brief set the priority group
|
||||
\param[in] nvic_prigroup: the NVIC priority group
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
|
||||
\arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
|
||||
\arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
|
||||
\arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
|
||||
\arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_priority_group_set(uint32_t nvic_prigroup)
|
||||
{
|
||||
/* set the priority group value */
|
||||
SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable NVIC request
|
||||
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
|
||||
\param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
|
||||
\param[in] nvic_irq_sub_priority: the subpriority needed to set
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_irq_enable(uint8_t nvic_irq,
|
||||
uint8_t nvic_irq_pre_priority,
|
||||
uint8_t nvic_irq_sub_priority)
|
||||
{
|
||||
uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
|
||||
|
||||
/* use the priority group value to get the temp_pre and the temp_sub */
|
||||
switch ((SCB->AIRCR) & (uint32_t)0x700U) {
|
||||
case NVIC_PRIGROUP_PRE0_SUB4:
|
||||
temp_pre = 0U;
|
||||
temp_sub = 0x4U;
|
||||
break;
|
||||
case NVIC_PRIGROUP_PRE1_SUB3:
|
||||
temp_pre = 1U;
|
||||
temp_sub = 0x3U;
|
||||
break;
|
||||
case NVIC_PRIGROUP_PRE2_SUB2:
|
||||
temp_pre = 2U;
|
||||
temp_sub = 0x2U;
|
||||
break;
|
||||
case NVIC_PRIGROUP_PRE3_SUB1:
|
||||
temp_pre = 3U;
|
||||
temp_sub = 0x1U;
|
||||
break;
|
||||
case NVIC_PRIGROUP_PRE4_SUB0:
|
||||
temp_pre = 4U;
|
||||
temp_sub = 0x0U;
|
||||
break;
|
||||
default:
|
||||
nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
|
||||
temp_pre = 2U;
|
||||
temp_sub = 0x2U;
|
||||
break;
|
||||
}
|
||||
|
||||
/* get the temp_priority to fill the NVIC->IP register */
|
||||
temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
|
||||
temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
|
||||
temp_priority = temp_priority << 0x04U;
|
||||
NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
|
||||
|
||||
/* enable the selected IRQ */
|
||||
NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable NVIC request
|
||||
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_irq_disable(uint8_t nvic_irq)
|
||||
{
|
||||
/* disable the selected IRQ.*/
|
||||
NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the NVIC vector table base address
|
||||
\param[in] nvic_vict_tab: the RAM or FLASH base address
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg NVIC_VECTTAB_RAM: RAM base address
|
||||
\are NVIC_VECTTAB_FLASH: Flash base address
|
||||
\param[in] offset: Vector Table offset
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
|
||||
{
|
||||
SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the state of the low power mode
|
||||
\param[in] lowpower_mode: the low power mode state
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
|
||||
mode by exiting from ISR
|
||||
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
|
||||
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
|
||||
by all the enable and disable interrupts
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void system_lowpower_set(uint8_t lowpower_mode)
|
||||
{
|
||||
SCB->SCR |= (uint32_t)lowpower_mode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset the state of the low power mode
|
||||
\param[in] lowpower_mode: the low power mode state
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
|
||||
mode by exiting from ISR
|
||||
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
|
||||
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
|
||||
woke up by the enable interrupts
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void system_lowpower_reset(uint8_t lowpower_mode)
|
||||
{
|
||||
SCB->SCR &= (~(uint32_t)lowpower_mode);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the systick clock source
|
||||
\param[in] systick_clksource: the systick clock source needed to choose
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
|
||||
\arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
|
||||
void systick_clksource_set(uint32_t systick_clksource)
|
||||
{
|
||||
if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
|
||||
/* set the systick clock source from HCLK */
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}else{
|
||||
/* set the systick clock source from HCLK/8 */
|
||||
SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,407 @@
|
||||
/*!
|
||||
\file gd32f3x0_pmu.c
|
||||
\brief PMU driver
|
||||
|
||||
\version 2017-06-06, V1.0.0, firmware for GD32F3x0
|
||||
\version 2019-06-01, V2.0.0, firmware for GD32F3x0
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32f3x0_pmu.h"
|
||||
|
||||
|
||||
/*!
|
||||
\brief reset PMU register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_deinit(void)
|
||||
{
|
||||
/* reset PMU */
|
||||
rcu_periph_reset_enable(RCU_PMURST);
|
||||
rcu_periph_reset_disable(RCU_PMURST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief select low voltage detector threshold
|
||||
\param[in] lvdt_n:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LVDT_0: voltage threshold is 2.1V
|
||||
\arg PMU_LVDT_1: voltage threshold is 2.3V
|
||||
\arg PMU_LVDT_2: voltage threshold is 2.4V
|
||||
\arg PMU_LVDT_3: voltage threshold is 2.6V
|
||||
\arg PMU_LVDT_4: voltage threshold is 2.7V
|
||||
\arg PMU_LVDT_5: voltage threshold is 2.9V
|
||||
\arg PMU_LVDT_6: voltage threshold is 3.0V
|
||||
\arg PMU_LVDT_7: voltage threshold is 3.1V
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lvd_select(uint32_t lvdt_n)
|
||||
{
|
||||
/* disable LVD */
|
||||
PMU_CTL &= ~PMU_CTL_LVDEN;
|
||||
/* clear LVDT bits */
|
||||
PMU_CTL &= ~PMU_CTL_LVDT;
|
||||
/* set LVDT bits according to lvdt_n */
|
||||
PMU_CTL |= lvdt_n;
|
||||
/* enable LVD */
|
||||
PMU_CTL |= PMU_CTL_LVDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief select LDO output voltage
|
||||
these bits set by software when the main PLL closed
|
||||
\param[in] ldo_output:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LDOVS_LOW: LDO output voltage low mode
|
||||
\arg PMU_LDOVS_MID: LDO output voltage mid mode
|
||||
\arg PMU_LDOVS_HIGH: LDO output voltage high mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_ldo_output_select(uint32_t ldo_output)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_LDOVS;
|
||||
PMU_CTL |= ldo_output;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable PMU lvd
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lvd_disable(void)
|
||||
{
|
||||
/* disable LVD */
|
||||
PMU_CTL &= ~PMU_CTL_LVDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable low-driver mode in deep-sleep mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lowdriver_mode_enable(void)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_LDEN;
|
||||
PMU_CTL |= PMU_LOWDRIVER_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable low-driver mode in deep-sleep mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lowdriver_mode_disable(void)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_LDEN;
|
||||
PMU_CTL |= PMU_LOWDRIVER_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable high-driver mode
|
||||
this bit set by software only when IRC8M or HXTAL used as system clock
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_highdriver_mode_enable(void)
|
||||
{
|
||||
PMU_CTL |= PMU_CTL_HDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable high-driver mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_highdriver_mode_disable(void)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_HDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief switch high-driver mode
|
||||
this bit set by software only when IRC8M or HXTAL used as system clock
|
||||
\param[in] highdr_switch:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch
|
||||
\arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_highdriver_switch_select(uint32_t highdr_switch)
|
||||
{
|
||||
/* wait for HDRF flag to be set */
|
||||
while(SET != pmu_flag_get(PMU_FLAG_HDR)){
|
||||
}
|
||||
PMU_CTL &= ~PMU_CTL_HDS;
|
||||
PMU_CTL |= highdr_switch;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief low-driver mode when use low power LDO
|
||||
\param[in] mode:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_NORMALDR_LOWPWR: normal-driver when use low power LDO
|
||||
\arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lowpower_driver_config(uint32_t mode)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_LDLP;
|
||||
PMU_CTL |= mode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief low-driver mode when use normal power LDO
|
||||
\param[in] mode:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_NORMALDR_NORMALPWR: normal-driver when use low power LDO
|
||||
\arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_normalpower_driver_config(uint32_t mode)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_LDNP;
|
||||
PMU_CTL |= mode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief PMU work at sleep mode
|
||||
\param[in] sleepmodecmd:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WFI_CMD: use WFI command
|
||||
\arg WFE_CMD: use WFE command
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd)
|
||||
{
|
||||
/* clear sleepdeep bit of Cortex-M4 system control register */
|
||||
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* select WFI or WFE command to enter sleep mode */
|
||||
if(WFI_CMD == sleepmodecmd){
|
||||
__WFI();
|
||||
}else{
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief PMU work at deepsleep mode
|
||||
\param[in] ldo:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode
|
||||
\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
|
||||
\param[in] deepsleepmodecmd:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WFI_CMD: use WFI command
|
||||
\arg WFE_CMD: use WFE command
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_deepsleepmode(uint32_t ldo,uint8_t deepsleepmodecmd)
|
||||
{
|
||||
static uint32_t reg_snap[ 4 ];
|
||||
/* clear stbmod and ldolp bits */
|
||||
PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
|
||||
|
||||
/* set ldolp bit according to pmu_ldo */
|
||||
PMU_CTL |= ldo;
|
||||
|
||||
/* set sleepdeep bit of Cortex-M4 system control register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
reg_snap[ 0 ] = REG32( 0xE000E010U );
|
||||
reg_snap[ 1 ] = REG32( 0xE000E100U );
|
||||
reg_snap[ 2 ] = REG32( 0xE000E104U );
|
||||
reg_snap[ 3 ] = REG32( 0xE000E108U );
|
||||
|
||||
REG32( 0xE000E010U ) &= 0x00010004U;
|
||||
REG32( 0xE000E180U ) = 0XB7FFEF19U;
|
||||
REG32( 0xE000E184U ) = 0XFFFFFBFFU;
|
||||
REG32( 0xE000E188U ) = 0xFFFFFFFFU;
|
||||
|
||||
/* select WFI or WFE command to enter deepsleep mode */
|
||||
if(WFI_CMD == deepsleepmodecmd){
|
||||
__WFI();
|
||||
}else{
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
REG32( 0xE000E010U ) = reg_snap[ 0 ] ;
|
||||
REG32( 0xE000E100U ) = reg_snap[ 1 ] ;
|
||||
REG32( 0xE000E104U ) = reg_snap[ 2 ] ;
|
||||
REG32( 0xE000E108U ) = reg_snap[ 3 ] ;
|
||||
|
||||
/* reset sleepdeep bit of Cortex-M4 system control register */
|
||||
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief pmu work at standby mode
|
||||
\param[in] standbymodecmd:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WFI_CMD: use WFI command
|
||||
\arg WFE_CMD: use WFE command
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_standbymode(uint8_t standbymodecmd)
|
||||
{
|
||||
/* set sleepdeep bit of Cortex-M4 system control register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* set stbmod bit */
|
||||
PMU_CTL |= PMU_CTL_STBMOD;
|
||||
|
||||
/* reset wakeup flag */
|
||||
PMU_CTL |= PMU_CTL_WURST;
|
||||
|
||||
/* select WFI or WFE command to enter standby mode */
|
||||
if(WFI_CMD == standbymodecmd){
|
||||
__WFI();
|
||||
}else{
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable wakeup pin
|
||||
\param[in] wakeup_pin:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
|
||||
\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
|
||||
\arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
|
||||
\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
|
||||
\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
|
||||
{
|
||||
PMU_CS |= wakeup_pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable wakeup pin
|
||||
\param[in] wakeup_pin:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
|
||||
\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
|
||||
\arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
|
||||
\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
|
||||
\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
|
||||
{
|
||||
PMU_CS &= ~(wakeup_pin);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable backup domain write
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_backup_write_enable(void)
|
||||
{
|
||||
PMU_CTL |= PMU_CTL_BKPWEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable backup domain write
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_backup_write_disable(void)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_BKPWEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear flag bit
|
||||
\param[in] flag_clear:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
|
||||
\arg PMU_FLAG_RESET_STANDBY: reset standby flag
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_flag_clear(uint32_t flag_clear)
|
||||
{
|
||||
if(RESET != (flag_clear & PMU_FLAG_RESET_WAKEUP)){
|
||||
/* reset wakeup flag */
|
||||
PMU_CTL |= PMU_CTL_WURST;
|
||||
}
|
||||
if(RESET != (flag_clear & PMU_FLAG_RESET_STANDBY)){
|
||||
/* reset standby flag */
|
||||
PMU_CTL |= PMU_CTL_STBRST;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state
|
||||
\param[in] flag:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_FLAG_WAKEUP: wakeup flag
|
||||
\arg PMU_FLAG_STANDBY: standby flag
|
||||
\arg PMU_FLAG_LVD: lvd flag
|
||||
\arg PMU_FLAG_LDOVSR: LDO voltage select ready flag
|
||||
\arg PMU_FLAG_HDR: high-driver ready flag
|
||||
\arg PMU_FLAG_HDSR: high-driver switch ready flag
|
||||
\arg PMU_FLAG_LDR: low-driver mode ready flag
|
||||
\param[out] none
|
||||
\retval FlagStatus SET or RESET
|
||||
*/
|
||||
FlagStatus pmu_flag_get(uint32_t flag)
|
||||
{
|
||||
FlagStatus ret_status = RESET;
|
||||
|
||||
if(PMU_CS & flag){
|
||||
ret_status = SET;
|
||||
}
|
||||
|
||||
return ret_status;
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user