mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-05-23 20:15:44 +08:00
Merge pull request #5043 from liuhy-2020/master
delete bsp ：es8p508x、es32f0271、es32f0334. update driver and Library.
This commit is contained in:
Bernard Xiong
GitHub
@@ -1,439 +0,0 @@
|
||||
#
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||||
# Automatically generated file; DO NOT EDIT.
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# RT-Thread Configuration
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#
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#
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# RT-Thread Kernel
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#
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||||
CONFIG_RT_NAME_MAX=8
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# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
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# CONFIG_RT_USING_SMP is not set
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CONFIG_RT_ALIGN_SIZE=4
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# CONFIG_RT_THREAD_PRIORITY_8 is not set
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CONFIG_RT_THREAD_PRIORITY_32=y
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# CONFIG_RT_THREAD_PRIORITY_256 is not set
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CONFIG_RT_THREAD_PRIORITY_MAX=32
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CONFIG_RT_TICK_PER_SECOND=100
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CONFIG_RT_USING_OVERFLOW_CHECK=y
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CONFIG_RT_USING_HOOK=y
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CONFIG_RT_USING_IDLE_HOOK=y
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CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
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CONFIG_IDLE_THREAD_STACK_SIZE=256
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# CONFIG_RT_USING_TIMER_SOFT is not set
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CONFIG_RT_DEBUG=y
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CONFIG_RT_DEBUG_COLOR=y
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# CONFIG_RT_DEBUG_INIT_CONFIG is not set
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# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
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||||
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
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# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
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# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
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# CONFIG_RT_DEBUG_MEM_CONFIG is not set
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# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
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# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
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# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
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#
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# Inter-Thread communication
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#
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CONFIG_RT_USING_SEMAPHORE=y
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CONFIG_RT_USING_MUTEX=y
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CONFIG_RT_USING_EVENT=y
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CONFIG_RT_USING_MAILBOX=y
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CONFIG_RT_USING_MESSAGEQUEUE=y
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# CONFIG_RT_USING_SIGNALS is not set
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#
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# Memory Management
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#
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CONFIG_RT_USING_MEMPOOL=y
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# CONFIG_RT_USING_MEMHEAP is not set
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# CONFIG_RT_USING_NOHEAP is not set
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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CONFIG_RT_USING_HEAP=y
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#
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# Kernel Device Object
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#
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CONFIG_RT_USING_DEVICE=y
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# CONFIG_RT_USING_DEVICE_OPS is not set
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# CONFIG_RT_USING_INTERRUPT_INFO is not set
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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CONFIG_RT_VER_NUM=0x40002
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# CONFIG_RT_USING_CPU_FFS is not set
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# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
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#
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# RT-Thread Components
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#
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CONFIG_RT_USING_COMPONENTS_INIT=y
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CONFIG_RT_USING_USER_MAIN=y
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CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024
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CONFIG_RT_MAIN_THREAD_PRIORITY=10
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#
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# C++ features
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#
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# CONFIG_RT_USING_CPLUSPLUS is not set
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#
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# Command shell
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#
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CONFIG_RT_USING_FINSH=y
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CONFIG_FINSH_THREAD_NAME="tshell"
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CONFIG_FINSH_USING_HISTORY=y
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CONFIG_FINSH_HISTORY_LINES=5
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CONFIG_FINSH_USING_SYMTAB=y
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CONFIG_FINSH_USING_DESCRIPTION=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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CONFIG_FINSH_THREAD_PRIORITY=20
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CONFIG_FINSH_THREAD_STACK_SIZE=2048
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CONFIG_FINSH_CMD_SIZE=80
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_USING_MSH=y
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CONFIG_FINSH_USING_MSH_DEFAULT=y
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CONFIG_FINSH_USING_MSH_ONLY=y
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CONFIG_FINSH_ARG_MAX=10
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#
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# Device virtual file system
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#
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# CONFIG_RT_USING_DFS is not set
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#
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# Device Drivers
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#
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||||
CONFIG_RT_USING_DEVICE_IPC=y
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CONFIG_RT_PIPE_BUFSZ=512
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# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
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CONFIG_RT_USING_SERIAL=y
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# CONFIG_RT_SERIAL_USING_DMA is not set
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CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_CAN is not set
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_PWM is not set
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# CONFIG_RT_USING_MTD_NOR is not set
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# CONFIG_RT_USING_MTD_NAND is not set
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# CONFIG_RT_USING_PM is not set
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# CONFIG_RT_USING_RTC is not set
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# CONFIG_RT_USING_SDIO is not set
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# CONFIG_RT_USING_SPI is not set
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# CONFIG_RT_USING_WDT is not set
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# CONFIG_RT_USING_AUDIO is not set
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# CONFIG_RT_USING_SENSOR is not set
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# CONFIG_RT_USING_TOUCH is not set
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# CONFIG_RT_USING_HWCRYPTO is not set
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# CONFIG_RT_USING_PULSE_ENCODER is not set
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# CONFIG_RT_USING_INPUT_CAPTURE is not set
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# CONFIG_RT_USING_WIFI is not set
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#
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# Using USB
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#
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# CONFIG_RT_USING_USB_HOST is not set
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# CONFIG_RT_USING_USB_DEVICE is not set
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#
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# POSIX layer and C standard library
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#
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# CONFIG_RT_USING_LIBC is not set
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# CONFIG_RT_USING_PTHREADS is not set
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# CONFIG_RT_LIBC_USING_TIME is not set
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#
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# Network
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#
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#
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# Socket abstraction layer
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#
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# CONFIG_RT_USING_SAL is not set
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#
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# Network interface device
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#
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# CONFIG_RT_USING_NETDEV is not set
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#
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# light weight TCP/IP stack
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#
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# CONFIG_RT_USING_LWIP is not set
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#
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# AT commands
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#
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# CONFIG_RT_USING_AT is not set
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||||
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#
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# VBUS(Virtual Software BUS)
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#
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# CONFIG_RT_USING_VBUS is not set
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#
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# Utilities
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#
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# CONFIG_RT_USING_RYM is not set
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# CONFIG_RT_USING_ULOG is not set
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# CONFIG_RT_USING_UTEST is not set
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#
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# RT-Thread online packages
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#
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#
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# IoT - internet of things
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#
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||||
# CONFIG_PKG_USING_PAHOMQTT is not set
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# CONFIG_PKG_USING_WEBCLIENT is not set
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# CONFIG_PKG_USING_WEBNET is not set
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# CONFIG_PKG_USING_MONGOOSE is not set
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# CONFIG_PKG_USING_MYMQTT is not set
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# CONFIG_PKG_USING_WEBTERMINAL is not set
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# CONFIG_PKG_USING_CJSON is not set
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# CONFIG_PKG_USING_JSMN is not set
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# CONFIG_PKG_USING_LIBMODBUS is not set
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# CONFIG_PKG_USING_FREEMODBUS is not set
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# CONFIG_PKG_USING_LJSON is not set
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# CONFIG_PKG_USING_EZXML is not set
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# CONFIG_PKG_USING_NANOPB is not set
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#
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# Wi-Fi
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#
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||||
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#
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# Marvell WiFi
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#
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# CONFIG_PKG_USING_WLANMARVELL is not set
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#
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# Wiced WiFi
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#
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||||
# CONFIG_PKG_USING_WLAN_WICED is not set
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# CONFIG_PKG_USING_RW007 is not set
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# CONFIG_PKG_USING_COAP is not set
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# CONFIG_PKG_USING_NOPOLL is not set
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# CONFIG_PKG_USING_NETUTILS is not set
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# CONFIG_PKG_USING_PPP_DEVICE is not set
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||||
# CONFIG_PKG_USING_AT_DEVICE is not set
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||||
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
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# CONFIG_PKG_USING_WIZNET is not set
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#
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# IoT Cloud
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||||
#
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||||
# CONFIG_PKG_USING_ONENET is not set
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||||
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
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# CONFIG_PKG_USING_ALI_IOTKIT is not set
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||||
# CONFIG_PKG_USING_AZURE is not set
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# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
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||||
# CONFIG_PKG_USING_JIOT-C-SDK is not set
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||||
# CONFIG_PKG_USING_NIMBLE is not set
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# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
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||||
# CONFIG_PKG_USING_IPMSG is not set
|
||||
# CONFIG_PKG_USING_LSSDP is not set
|
||||
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
|
||||
# CONFIG_PKG_USING_LIBRWS is not set
|
||||
# CONFIG_PKG_USING_TCPSERVER is not set
|
||||
# CONFIG_PKG_USING_PROTOBUF_C is not set
|
||||
# CONFIG_PKG_USING_ONNX_PARSER is not set
|
||||
# CONFIG_PKG_USING_ONNX_BACKEND is not set
|
||||
# CONFIG_PKG_USING_DLT645 is not set
|
||||
# CONFIG_PKG_USING_QXWZ is not set
|
||||
# CONFIG_PKG_USING_SMTP_CLIENT is not set
|
||||
# CONFIG_PKG_USING_ABUP_FOTA is not set
|
||||
|
||||
#
|
||||
# security packages
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||||
#
|
||||
# CONFIG_PKG_USING_MBEDTLS is not set
|
||||
# CONFIG_PKG_USING_libsodium is not set
|
||||
# CONFIG_PKG_USING_TINYCRYPT is not set
|
||||
|
||||
#
|
||||
# language packages
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||||
#
|
||||
# CONFIG_PKG_USING_LUA is not set
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||||
# CONFIG_PKG_USING_JERRYSCRIPT is not set
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||||
# CONFIG_PKG_USING_MICROPYTHON is not set
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||||
|
||||
#
|
||||
# multimedia packages
|
||||
#
|
||||
# CONFIG_PKG_USING_OPENMV is not set
|
||||
# CONFIG_PKG_USING_MUPDF is not set
|
||||
# CONFIG_PKG_USING_STEMWIN is not set
|
||||
# CONFIG_PKG_USING_WAVPLAYER is not set
|
||||
# CONFIG_PKG_USING_TJPGD is not set
|
||||
|
||||
#
|
||||
# tools packages
|
||||
#
|
||||
# CONFIG_PKG_USING_CMBACKTRACE is not set
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||||
# CONFIG_PKG_USING_EASYFLASH is not set
|
||||
# CONFIG_PKG_USING_EASYLOGGER is not set
|
||||
# CONFIG_PKG_USING_SYSTEMVIEW is not set
|
||||
# CONFIG_PKG_USING_RDB is not set
|
||||
# CONFIG_PKG_USING_QRCODE is not set
|
||||
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
|
||||
# CONFIG_PKG_USING_ADBD is not set
|
||||
# CONFIG_PKG_USING_COREMARK is not set
|
||||
# CONFIG_PKG_USING_DHRYSTONE is not set
|
||||
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
|
||||
|
||||
#
|
||||
# system packages
|
||||
#
|
||||
# CONFIG_PKG_USING_GUIENGINE is not set
|
||||
# CONFIG_PKG_USING_CAIRO is not set
|
||||
# CONFIG_PKG_USING_PIXMAN is not set
|
||||
# CONFIG_PKG_USING_LWEXT4 is not set
|
||||
# CONFIG_PKG_USING_PARTITION is not set
|
||||
# CONFIG_PKG_USING_FAL is not set
|
||||
# CONFIG_PKG_USING_SQLITE is not set
|
||||
# CONFIG_PKG_USING_RTI is not set
|
||||
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
|
||||
# CONFIG_PKG_USING_CMSIS is not set
|
||||
# CONFIG_PKG_USING_DFS_YAFFS is not set
|
||||
# CONFIG_PKG_USING_LITTLEFS is not set
|
||||
# CONFIG_PKG_USING_THREAD_POOL is not set
|
||||
# CONFIG_PKG_USING_ROBOTS is not set
|
||||
|
||||
#
|
||||
# peripheral libraries and drivers
|
||||
#
|
||||
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
|
||||
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
|
||||
# CONFIG_PKG_USING_SHT2X is not set
|
||||
# CONFIG_PKG_USING_SHT3X is not set
|
||||
# CONFIG_PKG_USING_STM32_SDIO is not set
|
||||
# CONFIG_PKG_USING_ICM20608 is not set
|
||||
# CONFIG_PKG_USING_U8G2 is not set
|
||||
# CONFIG_PKG_USING_BUTTON is not set
|
||||
# CONFIG_PKG_USING_PCF8574 is not set
|
||||
# CONFIG_PKG_USING_SX12XX is not set
|
||||
# CONFIG_PKG_USING_SIGNAL_LED is not set
|
||||
# CONFIG_PKG_USING_LEDBLINK is not set
|
||||
# CONFIG_PKG_USING_WM_LIBRARIES is not set
|
||||
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
|
||||
# CONFIG_PKG_USING_INFRARED is not set
|
||||
# CONFIG_PKG_USING_ROSSERIAL is not set
|
||||
# CONFIG_PKG_USING_AGILE_BUTTON is not set
|
||||
# CONFIG_PKG_USING_AGILE_LED is not set
|
||||
# CONFIG_PKG_USING_AT24CXX is not set
|
||||
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
|
||||
# CONFIG_PKG_USING_AD7746 is not set
|
||||
# CONFIG_PKG_USING_PCA9685 is not set
|
||||
# CONFIG_PKG_USING_I2C_TOOLS is not set
|
||||
# CONFIG_PKG_USING_NRF24L01 is not set
|
||||
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
|
||||
# CONFIG_PKG_USING_LCD_DRIVERS is not set
|
||||
# CONFIG_PKG_USING_MAX17048 is not set
|
||||
# CONFIG_PKG_USING_RPLIDAR is not set
|
||||
|
||||
#
|
||||
# miscellaneous packages
|
||||
#
|
||||
# CONFIG_PKG_USING_LIBCSV is not set
|
||||
# CONFIG_PKG_USING_OPTPARSE is not set
|
||||
# CONFIG_PKG_USING_FASTLZ is not set
|
||||
# CONFIG_PKG_USING_MINILZO is not set
|
||||
# CONFIG_PKG_USING_QUICKLZ is not set
|
||||
# CONFIG_PKG_USING_MULTIBUTTON is not set
|
||||
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
|
||||
# CONFIG_PKG_USING_CANFESTIVAL is not set
|
||||
# CONFIG_PKG_USING_ZLIB is not set
|
||||
# CONFIG_PKG_USING_DSTR is not set
|
||||
# CONFIG_PKG_USING_TINYFRAME is not set
|
||||
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
|
||||
# CONFIG_PKG_USING_DIGITALCTRL is not set
|
||||
# CONFIG_PKG_USING_UPACKER is not set
|
||||
# CONFIG_PKG_USING_UPARAM is not set
|
||||
|
||||
#
|
||||
# samples: kernel and components samples
|
||||
#
|
||||
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
|
||||
# CONFIG_PKG_USING_HELLO is not set
|
||||
# CONFIG_PKG_USING_VI is not set
|
||||
# CONFIG_PKG_USING_NNOM is not set
|
||||
# CONFIG_PKG_USING_LIBANN is not set
|
||||
# CONFIG_PKG_USING_ELAPACK is not set
|
||||
# CONFIG_PKG_USING_ARMv7M_DWT is not set
|
||||
# CONFIG_PKG_USING_VT100 is not set
|
||||
# CONFIG_PKG_USING_ULAPACK is not set
|
||||
# CONFIG_PKG_USING_UKAL is not set
|
||||
CONFIG_SOC_ES32F0271LT=y
|
||||
|
||||
#
|
||||
# Hardware Drivers Config
|
||||
#
|
||||
|
||||
#
|
||||
# On-chip Peripheral Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# PIN Drivers
|
||||
#
|
||||
CONFIG_BSP_USING_GPIO=y
|
||||
|
||||
#
|
||||
# UART Drivers
|
||||
#
|
||||
CONFIG_BSP_USING_UART1=y
|
||||
# CONFIG_BSP_USING_UART2 is not set
|
||||
# CONFIG_BSP_USING_UART3 is not set
|
||||
|
||||
#
|
||||
# SPI Drivers
|
||||
#
|
||||
# CONFIG_BSP_USING_SPI1 is not set
|
||||
# CONFIG_BSP_USING_SPI2 is not set
|
||||
|
||||
#
|
||||
# I2C Drivers
|
||||
#
|
||||
# CONFIG_BSP_USING_I2C1 is not set
|
||||
# CONFIG_BSP_USING_I2C2 is not set
|
||||
|
||||
#
|
||||
# HWtimer Drivers
|
||||
#
|
||||
# CONFIG_BSP_USING_HWTIMER1 is not set
|
||||
|
||||
#
|
||||
# PWM Drivers
|
||||
#
|
||||
# CONFIG_BSP_USING_PWM_GP16C2T1 is not set
|
||||
# CONFIG_BSP_USING_PWM_GP16C2T4 is not set
|
||||
|
||||
#
|
||||
# RTC Drivers
|
||||
#
|
||||
# CONFIG_BSP_USING_RTC is not set
|
||||
|
||||
#
|
||||
# ADC Drivers
|
||||
#
|
||||
# CONFIG_BSP_USING_ADC is not set
|
||||
|
||||
#
|
||||
# Onboard Peripheral Drivers
|
||||
#
|
||||
|
||||
#
|
||||
# Offboard Peripheral Drivers
|
||||
#
|
||||
@@ -1,27 +0,0 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "../../.."
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
|
||||
config SOC_ES32F0271LT
|
||||
bool
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
source "drivers/Kconfig"
|
||||
@@ -1,95 +0,0 @@
|
||||
# ES-PDS-ES32F0271 开发板 BSP 说明
|
||||
标签： EastSoft、国产MCU、Cortex-M0、ES32F0271LT
|
||||
|
||||
## 1. 简介
|
||||
|
||||
本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0271 开发板提供的 BSP (板级支持包) 说明。
|
||||
通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
|
||||
|
||||
### 1.1 开发板介绍
|
||||
|
||||
主要内容如下：
|
||||
ES-PDS-ES32F0271 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。
|
||||
|
||||
ES-PDS-ES32F0271-V1.1
|
||||
|
||||
该开发板常用 **板载资源** 如下：
|
||||
|
||||
- MCU：ES32F0271LT，主频 48MHz，8KB SRAM，64KB FLASH
|
||||
- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B)
|
||||
- 常用外设
|
||||
- 可调电阻：1个，(PC03)
|
||||
- LED：2个，(PD03/PB08)
|
||||
- 五轴按键：
|
||||
- 常用接口：GPIO、UART、SPI、I2C
|
||||
- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载
|
||||
|
||||
外设支持:
|
||||
|
||||
本 BSP 目前对外设的支持情况如下：
|
||||
|
||||
| **板载外设** | **支持情况** | **备注** |
|
||||
| :---------------- | :----------: | :------------------------------------|
|
||||
| **片上外设** | **支持情况** | **备注** |
|
||||
| GPIO | 支持 | GPIOs |
|
||||
| UART | 支持 | UART1/2/3 |
|
||||
| SPI | 支持 | SPI1/2 |
|
||||
| I2C | 支持 | I2C1/2 |
|
||||
| PWM | 支持 | PWM1/2 |
|
||||
| TIMER | 支持 | TIMER1 |
|
||||
| RTC | 支持 | RTC |
|
||||
| ADC | 支持 | ADC |
|
||||
|
||||
### 1.2 注意事项
|
||||
|
||||
- 本BSP中，SPI2和PWM2不能同时使用
|
||||
|
||||
更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
|
||||
|
||||
## 2. 快速上手
|
||||
|
||||
本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
||||
|
||||
### 硬件连接
|
||||
|
||||
使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC端，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PB06)、UART1_RX(PB07)、GND 接到串口工具上。
|
||||
|
||||
ESLinkⅡ(mini) + ES-PDS-ES32F0271-V1.1
|
||||
|
||||
### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。
|
||||
|
||||
### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
|
||||
|
||||
```bash
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 4.0.2 build Oct 31 2019
|
||||
2006 - 2019 Copyright by rt-thread team
|
||||
msh >
|
||||
```
|
||||
## 3. 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
|
||||
|
||||
## 4. 联系人信息
|
||||
|
||||
- [yuzr](https://github.com/essemi-yuzr)
|
||||
|
||||
## 5. 参考
|
||||
|
||||
- [ EastSoft 官网](http://www.essemi.com)
|
||||
|
||||
@@ -1,14 +0,0 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
|
||||
objs = []
|
||||
cwd = str(Dir('#'))
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -1,39 +0,0 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
@@ -1,11 +0,0 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = os.path.join(str(Dir('#')), 'applications')
|
||||
src = Glob('*.c')
|
||||
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define LED_PIN 61
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* LED pin configuration */
|
||||
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(1000);
|
||||
rt_pin_write(LED_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(1000);
|
||||
}
|
||||
}
|
||||
@@ -1,102 +0,0 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
menu "PIN Drivers"
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
endmenu
|
||||
|
||||
menu "UART Drivers"
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1 PB06/PB07(T/R)"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "Enable UART2 PA02/PA03(T/R)"
|
||||
select RT_USING_SERIAL
|
||||
default n
|
||||
|
||||
config BSP_USING_UART3
|
||||
bool "Enable UART3 PC06/PC07(T/R)"
|
||||
select RT_USING_SERIAL
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "SPI Drivers"
|
||||
config BSP_USING_SPI1
|
||||
bool "Enable SPI1 BUS PB03/PB04/PB05(CLK/MISO/MOSI)"
|
||||
select RT_USING_SPI
|
||||
select RT_USING_PIN
|
||||
default n
|
||||
|
||||
config BSP_USING_SPI2
|
||||
bool "Enable SPI2 BUS PB13/PB14/PB15(CLK/MISO/MOSI)"
|
||||
select RT_USING_SPI
|
||||
select RT_USING_PIN
|
||||
default n
|
||||
depends on !BSP_USING_PWM_GP16C2T4
|
||||
endmenu
|
||||
|
||||
menu "I2C Drivers"
|
||||
config BSP_USING_I2C1
|
||||
bool "Enable I2C1 BUS PC12/PD02(SCL/SDA)"
|
||||
select RT_USING_I2C
|
||||
default n
|
||||
|
||||
config BSP_USING_I2C2
|
||||
bool "Enable I2C2 BUS PB10/PB11(SCL/SDA)"
|
||||
select RT_USING_I2C
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "HWtimer Drivers"
|
||||
|
||||
config BSP_USING_HWTIMER1
|
||||
bool "Using timer1"
|
||||
select RT_USING_HWTIMER
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "PWM Drivers"
|
||||
|
||||
config BSP_USING_PWM_GP16C2T1
|
||||
bool "Using PWM_1(GP16C2T1) PB01/PB02"
|
||||
select RT_USING_PWM
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM_GP16C2T4
|
||||
bool "Using PWM2(GP16C2T4) PB12/PB14"
|
||||
select RT_USING_PWM
|
||||
default n
|
||||
depends on !BSP_USING_SPI2
|
||||
|
||||
endmenu
|
||||
|
||||
menu "RTC Drivers"
|
||||
config BSP_USING_RTC
|
||||
bool "Using RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "ADC Drivers"
|
||||
config BSP_USING_ADC
|
||||
bool "Using ADC"
|
||||
select RT_USING_ADC
|
||||
default n
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Offboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -1,45 +0,0 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split('''
|
||||
board.c
|
||||
''')
|
||||
|
||||
# add gpio code
|
||||
if GetDepend('RT_USING_PIN'):
|
||||
src += ['drv_gpio.c']
|
||||
|
||||
# add serial driver code
|
||||
if GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'):
|
||||
src += ['drv_uart.c']
|
||||
|
||||
# add spi driver code
|
||||
if GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'):
|
||||
src += ['drv_spi.c']
|
||||
|
||||
# add i2c driver code
|
||||
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'):
|
||||
src += ['drv_i2c.c']
|
||||
|
||||
# add pwm driver code
|
||||
if GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3') or GetDepend('BSP_USING_PWM4') or GetDepend('BSP_USING_PWM_GP16C2T1') or GetDepend('BSP_USING_PWM_GP16C2T4'):
|
||||
src += ['drv_pwm.c']
|
||||
|
||||
# add hwtimer driver code
|
||||
if GetDepend('BSP_USING_HWTIMER1'):
|
||||
src += ['drv_hwtimer.c']
|
||||
|
||||
# add rtc driver code
|
||||
if GetDepend(['BSP_USING_RTC']):
|
||||
src += ['drv_rtc.c']
|
||||
|
||||
# add adc driver code
|
||||
if GetDepend(['BSP_USING_ADC']):
|
||||
src += ['drv_adc.c']
|
||||
|
||||
CPPPATH = [cwd]
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -1,136 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
#include "drv_gpio.h"
|
||||
#include "md_gpio.h"
|
||||
|
||||
/**
|
||||
* @addtogroup es32f0
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_Configuration
|
||||
* Description : Configures Vector Table base location.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SystemClock_Configuration
|
||||
* Description : Configures the System Clock.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
/*-------------------------Clock Config-------------------------/
|
||||
* Config system clock to 48MHz of which the clock source
|
||||
* is PLL0.
|
||||
*/
|
||||
|
||||
//
|
||||
// Open PLL0/HRC then wait it ready.
|
||||
//
|
||||
SET_BIT(RCU->CON, RCU_CON_PLL0ON_MSK);
|
||||
SET_BIT(RCU->CON, RCU_CON_HRCON_MSK);
|
||||
|
||||
/* Wait HRC clock steady. */
|
||||
while (!READ_BIT(RCU->CON, RCU_CON_HRCRDY_MSK));
|
||||
|
||||
//
|
||||
// Change system clock source,PLL0,48MHz.
|
||||
//
|
||||
/* Chose PLL0 as system clock. */
|
||||
MODIFY_REG(RCU->CFG, RCU_CFG_SW_MSK, (0x4 << RCU_CFG_SW_POSS));
|
||||
/* Config mul of PLL0. */
|
||||
MODIFY_REG(RCU->CFG, RCU_CFG_PLLMUL_MSK, (11 << RCU_CFG_PLLMUL_POSS));
|
||||
|
||||
//
|
||||
// Start to change system clock and wait it ready.
|
||||
//
|
||||
/* Config flash read wait time. */
|
||||
MODIFY_REG(FC->CON, FC_CON_WAIT_MSK, (0X2 << FC_CON_WAIT_POSS));
|
||||
/* Start to change. */
|
||||
SET_BIT(RCU->CFG, RCU_CFG_CKCFG_MSK);
|
||||
|
||||
/* Wait system clock ready. */
|
||||
while (!READ_BIT(RCU->CON, RCU_CON_SWRDY_MSK));
|
||||
|
||||
//
|
||||
// Remember the system clock.
|
||||
//
|
||||
SystemCoreClock = 48000000;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SysTick_Configuration
|
||||
* Description : Configures the SysTick for OS tick.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SysTick_Configuration(void)
|
||||
{
|
||||
/* ticks = sysclk / RT_TICK_PER_SECOND */
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
/**
|
||||
* This function will initial ES32F0 board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
/* NVIC Configuration */
|
||||
NVIC_Configuration();
|
||||
|
||||
/*System Clock Configuration */
|
||||
SystemClock_Config();
|
||||
|
||||
/* Configure the SysTick */
|
||||
SysTick_Configuration();
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "es32f0271.h"
|
||||
|
||||
#define ES32F0_SRAM_SIZE 0x2000
|
||||
#define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE)
|
||||
|
||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN ((void *)&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END ES32F0_SRAM_END
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,148 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "board.h"
|
||||
#include "drv_adc.h"
|
||||
#include "md_gpio.h"
|
||||
#include "md_adc.h"
|
||||
#include "md_rcu.h"
|
||||
#include "md_syscfg.h"
|
||||
|
||||
#ifdef RT_USING_ADC
|
||||
|
||||
#define BSP_ADC_CHANNEL_NUM 8
|
||||
|
||||
/* define adc instance */
|
||||
static struct rt_adc_device _device_adc0;
|
||||
|
||||
/* enable or disable adc */
|
||||
static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
|
||||
{
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
if (enabled)
|
||||
{
|
||||
md_adc_enable_ssen_ss0en(ADC);
|
||||
}
|
||||
else
|
||||
{
|
||||
md_adc_disable_ssen_ss0en(ADC);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static void _adc_channel_config(rt_uint32_t channel)
|
||||
{
|
||||
/* select gpio pin as adc function */
|
||||
switch (channel)
|
||||
{
|
||||
case 0:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_0, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 1:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_1, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 2:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 3:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 4:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_4, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 5:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_5, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 6:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_6, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 7:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_7, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
|
||||
{
|
||||
rt_uint32_t chn_data[BSP_ADC_CHANNEL_NUM];
|
||||
rt_uint32_t i;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(value != RT_NULL);
|
||||
|
||||
/* config adc channel */
|
||||
_adc_channel_config(channel);
|
||||
|
||||
md_adc_set_swtri_ss0(ADC);
|
||||
|
||||
while ((ADC->RIF & ADC_RIF_SS0RIF_MSK) == 0);
|
||||
|
||||
for (i=0; i<BSP_ADC_CHANNEL_NUM; i++)
|
||||
chn_data[i] = md_adc_get_ss0_data(ADC);
|
||||
|
||||
*value = chn_data[channel];
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_adc_ops es32f0_adc_ops =
|
||||
{
|
||||
es32f0_adc_enabled,
|
||||
es32f0_get_adc_value,
|
||||
};
|
||||
|
||||
int rt_hw_adc_init(void)
|
||||
{
|
||||
int result = RT_EOK;
|
||||
|
||||
md_rcu_enable_apb2en_adcen(RCU);
|
||||
|
||||
md_syscfg_enable_cfg_currgen(SYSCFG);
|
||||
md_syscfg_enable_cfg_vrefen(SYSCFG);
|
||||
md_syscfg_set_cfg_vlrs(SYSCFG, 7);
|
||||
|
||||
md_adc_set_ss0_con_sel(ADC, MD_ADC_SS_CON_SEL_SW);
|
||||
md_adc_set_ss0_con_type(ADC, MD_ADC_SS_CON_TYPE_EDGE);
|
||||
md_adc_set_frf_ffrst(ADC);
|
||||
md_adc_set_ss0_mux0_mux7(ADC, MD_ADC_SS_MUX_ADIN7);
|
||||
md_adc_set_ss0_mux0_mux6(ADC, MD_ADC_SS_MUX_ADIN6);
|
||||
md_adc_set_ss0_mux0_mux5(ADC, MD_ADC_SS_MUX_ADIN5);
|
||||
md_adc_set_ss0_mux0_mux4(ADC, MD_ADC_SS_MUX_ADIN4);
|
||||
md_adc_set_ss0_mux0_mux3(ADC, MD_ADC_SS_MUX_ADIN3);
|
||||
md_adc_set_ss0_mux0_mux2(ADC, MD_ADC_SS_MUX_ADIN2);
|
||||
md_adc_set_ss0_mux0_mux1(ADC, MD_ADC_SS_MUX_ADIN1);
|
||||
md_adc_set_ss0_mux0_mux0(ADC, MD_ADC_SS_MUX_ADIN0);
|
||||
md_adc_enable_ier_ss0ie(ADC);
|
||||
md_adc_set_ss0_end_end(ADC, 7);
|
||||
md_adc_enable_ss0_end_ie7(ADC);
|
||||
md_adc_set_gainl_ch7pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch6pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch5pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch4pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch3pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch2pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch1pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch0pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_srate(ADC, MD_ADC_SRATE_CLKDIV1 | ADC_SRATE_CKEN_MSK);
|
||||
|
||||
rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, ADC);
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_adc_init);
|
||||
|
||||
#endif
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_ADC_H__
|
||||
#define DRV_ADC_H__
|
||||
|
||||
int rt_hw_adc_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_GPIO_H__
|
||||
#define DRV_GPIO_H__
|
||||
|
||||
int rt_hw_pin_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,174 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <drv_hwtimer.h>
|
||||
#include <board.h>
|
||||
#include "md_ad16c4t.h"
|
||||
#include "md_rcu.h"
|
||||
|
||||
#ifdef RT_USING_HWTIMER
|
||||
|
||||
/* Defien the hardware timer control struct */
|
||||
struct es32f0_hwtimer_dev
|
||||
{
|
||||
rt_hwtimer_t parent;
|
||||
AD16C4T_TypeDef *hwtimer_periph;
|
||||
IRQn_Type IRQn;
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_HWTIMER1
|
||||
static struct es32f0_hwtimer_dev hwtimer1;
|
||||
|
||||
void BS16T1_IRQHandler(void)
|
||||
{
|
||||
/* if BS16T1 IT */
|
||||
if (BS16T1->IFM & AD16C4T_RIF_UI_MSK)
|
||||
{
|
||||
SET_BIT(BS16T1->ICR, AD16C4T_ICR_UI_MSK);
|
||||
rt_device_hwtimer_isr(&hwtimer1.parent);
|
||||
|
||||
if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
|
||||
{
|
||||
CLEAR_BIT(BS16T1->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct rt_hwtimer_info es32f0_hwtimer_info =
|
||||
{
|
||||
48000000, /* maximum count frequency */
|
||||
1, /* minimum count frequency */
|
||||
65535, /* counter maximum value */
|
||||
HWTIMER_CNTMODE_UP
|
||||
};
|
||||
|
||||
static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
|
||||
{
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
if (1 == state)
|
||||
{
|
||||
/* Set frequency */
|
||||
WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/hwtimer->parent.freq - 1));
|
||||
/* Enable timer IT */
|
||||
SET_BIT(hwtimer->hwtimer_periph->IER, AD16C4T_IER_UI_MSK);
|
||||
NVIC_EnableIRQ(hwtimer->IRQn);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Dsiable timer IT */
|
||||
SET_BIT(hwtimer->hwtimer_periph->IDR, AD16C4T_IER_UI_MSK);
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
|
||||
rt_uint32_t cnt,
|
||||
rt_hwtimer_mode_t mode)
|
||||
{
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
WRITE_REG(hwtimer->hwtimer_periph->AR, cnt);
|
||||
SET_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static void es32f0_hwtimer_stop(rt_hwtimer_t *timer)
|
||||
{
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
}
|
||||
|
||||
static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer)
|
||||
{
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
uint32_t hwtimer_count = 0;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
hwtimer_count = READ_REG(hwtimer->hwtimer_periph->COUNT);
|
||||
|
||||
return hwtimer_count;
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
|
||||
rt_uint32_t cmd,
|
||||
void *args)
|
||||
{
|
||||
rt_err_t ret = RT_EOK;
|
||||
rt_uint32_t freq = 0;
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case HWTIMER_CTRL_FREQ_SET:
|
||||
freq = *(rt_uint32_t *)args;
|
||||
if ((freq < hwtimer->parent.info->minfreq) || (freq > hwtimer->parent.info->maxfreq))
|
||||
{
|
||||
ret = RT_EINVAL;
|
||||
}
|
||||
/* Set frequency */
|
||||
WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/freq - 1));
|
||||
break;
|
||||
|
||||
case HWTIMER_CTRL_STOP:
|
||||
CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = RT_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct rt_hwtimer_ops es32f0_hwtimer_ops =
|
||||
{
|
||||
es32f0_hwtimer_init,
|
||||
es32f0_hwtimer_start,
|
||||
es32f0_hwtimer_stop,
|
||||
es32f0_hwtimer_count_get,
|
||||
es32f0_hwtimer_control
|
||||
};
|
||||
|
||||
int rt_hw_hwtimer_init(void)
|
||||
{
|
||||
rt_err_t ret = RT_EOK;
|
||||
|
||||
#ifdef BSP_USING_HWTIMER1
|
||||
/*Open clock*/
|
||||
SET_BIT(RCU->APB1EN, RCU_APB1EN_BS16T1EN_MSK);
|
||||
|
||||
hwtimer1.hwtimer_periph = BS16T1;
|
||||
hwtimer1.IRQn = BS16T1_IRQn;
|
||||
hwtimer1.parent.info = &es32f0_hwtimer_info;
|
||||
hwtimer1.parent.ops = &es32f0_hwtimer_ops;
|
||||
ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
|
||||
|
||||
#endif
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_HWTIMER_H__
|
||||
#define DRV_HWTIMER_H__
|
||||
|
||||
int rt_hw_hwtimer_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,275 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rtdbg.h>
|
||||
#include "board.h"
|
||||
#include "drv_i2c.h"
|
||||
#include "md_i2c.h"
|
||||
#include "md_gpio.h"
|
||||
|
||||
#ifdef RT_USING_I2C
|
||||
|
||||
#define TIMEOUT 0xF
|
||||
/* Define I2C hardware SCL timeout */
|
||||
#define I2C_TIMING_48MHZ_CLK100KHZ ((0xBU<<28)|(4<<20)|(2<<16)|(0xF<<8)|(0x13))
|
||||
|
||||
/**
|
||||
* @brief: I2C receive.
|
||||
* @param: i2cx, pointer to the I2Cx
|
||||
* @param: addr, address
|
||||
* @param: buf, send data buffer
|
||||
* @param: len, the length of buf
|
||||
* @param: timout, timeout
|
||||
* @retval: rt_err_t
|
||||
*/
|
||||
static rt_err_t __i2c_master_recv(I2C_TypeDef *i2cx, rt_uint16_t addr,
|
||||
rt_uint8_t *buf, rt_uint16_t len, rt_uint32_t timout)
|
||||
{
|
||||
rt_uint32_t rt_timout;
|
||||
|
||||
//
|
||||
// Config I2C transfer mode
|
||||
//
|
||||
md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT);
|
||||
/* Config slaver address */
|
||||
md_i2c_set_con2_sadd(i2cx, addr);
|
||||
/* Config data size */
|
||||
md_i2c_set_con2_nbytes(i2cx, len);
|
||||
/* Reset TX FIFO */
|
||||
md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET);
|
||||
/* Config mode */
|
||||
md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_READ);
|
||||
/* Config auto-reload */
|
||||
md_i2c_set_con2_reload(i2cx, MD_I2C_NORELOAD_MODE);
|
||||
/* When NBYTES is matched, the communication will be automatically stop */
|
||||
md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE);
|
||||
/* Start the I2C communication */
|
||||
md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION);
|
||||
|
||||
while (len > 0)
|
||||
{
|
||||
/* Wait Rx FIFO non-empty */
|
||||
rt_timout = timout;
|
||||
while (md_i2c_is_active_stat_rxe(i2cx) && (--rt_timout));
|
||||
if (rt_timout == 0)
|
||||
return RT_ETIMEOUT;
|
||||
|
||||
*buf++ = md_i2c_recv(i2cx);
|
||||
len--;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief: I2C send.
|
||||
* @param: i2cx, pointer to the I2Cx
|
||||
* @param: addr, address
|
||||
* @param: buf, send data buffer
|
||||
* @param: len, the length of buf
|
||||
* @param: timout, timeout
|
||||
* @retval: rt_err_t
|
||||
*/
|
||||
static rt_err_t __i2c_master_send(I2C_TypeDef *i2cx, rt_uint16_t addr,
|
||||
rt_uint8_t *buf, rt_uint16_t len, rt_uint32_t timout)
|
||||
{
|
||||
rt_uint32_t rt_timout;
|
||||
rt_uint8_t index;
|
||||
|
||||
//
|
||||
// Config I2C transfer mode
|
||||
//
|
||||
md_i2c_set_con2_add10(i2cx, MD_I2C_ADDRESSINGMODE_7BIT);
|
||||
/* Config slaver address */
|
||||
md_i2c_set_con2_sadd(i2cx, addr);
|
||||
/* Config data size */
|
||||
md_i2c_set_con2_nbytes(i2cx, len);
|
||||
/* Reset TX FIFO */
|
||||
md_i2c_set_fcon_txfrst(i2cx, MD_I2C_TXFIFO_RESET);
|
||||
/* Config mode */
|
||||
md_i2c_set_con2_rd_wrn(i2cx, MD_I2C_MASTER_WRITE);
|
||||
/* Enable auto-end */
|
||||
md_i2c_set_con2_autoend(i2cx, MD_I2C_AUTOEND_MODE);
|
||||
|
||||
//
|
||||
// Check if the bus is busy
|
||||
//
|
||||
/* Wait bus to be ready */
|
||||
rt_timout = timout;
|
||||
while ((READ_BIT(i2cx->STAT, I2C_STAT_BUSY_MSK) == I2C_STAT_BUSY_MSK) && (--rt_timout));
|
||||
if (rt_timout == 0)
|
||||
return RT_EBUSY;
|
||||
|
||||
//
|
||||
// Start to send
|
||||
//
|
||||
if (len <= 8)
|
||||
{
|
||||
for (index = 0; index < len; index++)
|
||||
md_i2c_send(i2cx, *buf++);
|
||||
|
||||
len = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
for (index = 0; index < 8; index++)
|
||||
md_i2c_send(i2cx, *buf++);
|
||||
|
||||
len -= 8;
|
||||
}
|
||||
|
||||
/* Start the I2C communication */
|
||||
md_i2c_set_con2_start(i2cx, MD_I2C_START_GENERATION);
|
||||
|
||||
while (len > 0)
|
||||
{
|
||||
rt_timout = timout;
|
||||
while (md_i2c_is_active_stat_txf(i2cx) && (--rt_timout));
|
||||
if (rt_timout == 0)
|
||||
return RT_ETIMEOUT;
|
||||
|
||||
md_i2c_send(i2cx, *buf++);
|
||||
len--;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t es32f0_master_xfer(struct rt_i2c_bus_device *bus,
|
||||
struct rt_i2c_msg msgs[],
|
||||
rt_uint32_t num)
|
||||
{
|
||||
struct rt_i2c_msg *msg;
|
||||
rt_uint32_t i;
|
||||
rt_err_t ret = RT_ERROR;
|
||||
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
msg = &msgs[i];
|
||||
if (msg->flags & RT_I2C_RD)
|
||||
{
|
||||
if (__i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
|
||||
{
|
||||
LOG_E("i2c bus write failed,i2c bus stop!\n");
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (__i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
|
||||
{
|
||||
LOG_E("i2c bus write failed,i2c bus stop!\n");
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ret = i;
|
||||
|
||||
out:
|
||||
LOG_E("send stop condition\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
const struct rt_i2c_bus_device_ops es32f0_i2c_ops =
|
||||
{
|
||||
es32f0_master_xfer,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
};
|
||||
|
||||
static void _i2c_init(void)
|
||||
{
|
||||
md_i2c_inittypedef I2C_Init =
|
||||
{
|
||||
.Timing = CLK100kHz48M,
|
||||
.Address1 = 0x55 << 1,
|
||||
.AddrSize = MD_I2C_ADDRESSINGMODE_7BIT,
|
||||
.DualAddressMode = MD_I2C_DUALADDRESS_DISABLE,
|
||||
.Address2 = 0xAA,
|
||||
.Address2Masks = MD_I2C_ADDR2_NOMASK
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_I2C1
|
||||
/* Open I2C clock */
|
||||
SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C1EN_MSK);
|
||||
|
||||
/* GPIO configuration */
|
||||
md_gpio_set_pull (GPIOC, MD_GPIO_PIN_12, MD_GPIO_PULL_UP);
|
||||
md_gpio_set_pull (GPIOD, MD_GPIO_PIN_2, MD_GPIO_PULL_UP);
|
||||
md_gpio_set_output_type (GPIOC, MD_GPIO_PIN_12, MD_GPIO_OUTPUT_OPENDRAIN);
|
||||
md_gpio_set_output_type (GPIOD, MD_GPIO_PIN_2, MD_GPIO_OUTPUT_OPENDRAIN);
|
||||
md_gpio_set_mode (GPIOC, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOD, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function8_15(GPIOC, MD_GPIO_PIN_12, MD_GPIO_AF1);
|
||||
md_gpio_set_function0_7 (GPIOD, MD_GPIO_PIN_2, MD_GPIO_AF1);
|
||||
|
||||
//
|
||||
// Config I2C
|
||||
//
|
||||
md_i2c_init(I2C1, &I2C_Init);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C2
|
||||
/* Open I2C clock */
|
||||
SET_BIT(RCU->APB1EN, RCU_APB1EN_I2C2EN_MSK);
|
||||
|
||||
/* GPIO configuration */
|
||||
md_gpio_set_pull (GPIOB, MD_GPIO_PIN_10, MD_GPIO_PULL_UP);
|
||||
md_gpio_set_pull (GPIOB, MD_GPIO_PIN_11, MD_GPIO_PULL_UP);
|
||||
md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_10, MD_GPIO_OUTPUT_OPENDRAIN);
|
||||
md_gpio_set_output_type (GPIOB, MD_GPIO_PIN_11, MD_GPIO_OUTPUT_OPENDRAIN);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_10, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_11, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_10, MD_GPIO_AF1);
|
||||
md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_11, MD_GPIO_AF1);
|
||||
|
||||
//
|
||||
// Config I2C
|
||||
//
|
||||
md_i2c_init(I2C2, &I2C_Init);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_I2C2
|
||||
static struct rt_i2c_bus_device i2c_device2;
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C1
|
||||
static struct rt_i2c_bus_device i2c_device1;
|
||||
#endif
|
||||
int rt_hw_i2c_init(void)
|
||||
{
|
||||
_i2c_init();
|
||||
|
||||
#ifdef BSP_USING_I2C2
|
||||
/* define i2c Instance */
|
||||
rt_memset((void *)&i2c_device2, 0, sizeof(struct rt_i2c_bus_device));
|
||||
i2c_device2.ops = &es32f0_i2c_ops;
|
||||
i2c_device2.priv = I2C2;
|
||||
rt_i2c_bus_device_register(&i2c_device2, "i2c2");
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C1
|
||||
/* define i2c Instance */
|
||||
rt_memset((void *)&i2c_device1, 0, sizeof(struct rt_i2c_bus_device));
|
||||
i2c_device1.ops = &es32f0_i2c_ops;
|
||||
i2c_device1.priv = I2C1;
|
||||
rt_i2c_bus_device_register(&i2c_device1, "i2c1");
|
||||
#endif
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_i2c_init);
|
||||
|
||||
#endif
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_I2C_H__
|
||||
#define DRV_I2C_H__
|
||||
|
||||
int rt_hw_i2c_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,208 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
#include "md_gpio.h"
|
||||
|
||||
/* PWM device control struct */
|
||||
struct pwm_dev_ctrl {
|
||||
AD16C4T_TypeDef *timx;
|
||||
rt_uint8_t chnm; /* Cannel number */
|
||||
struct rt_pwm_configuration *cfg;
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_PWM_GP16C2T1
|
||||
|
||||
/* Remember channel configuration */
|
||||
static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t1[2] = {
|
||||
[0] = {
|
||||
.channel = 1,
|
||||
.period = 0,
|
||||
.pulse = 0
|
||||
},
|
||||
[1] = {
|
||||
.channel = 2,
|
||||
.period = 0,
|
||||
.pulse = 0
|
||||
}
|
||||
};
|
||||
|
||||
/* Define static device */
|
||||
static struct rt_device_pwm pwm_dev_gp16c2t1;
|
||||
static struct pwm_dev_ctrl pwm_dev_gp16c2t1_ctrl;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_GP16C2T4
|
||||
|
||||
/* Remember channel configuration */
|
||||
static struct rt_pwm_configuration pwm_ch_cfg_gp16c2t4[2] = {
|
||||
[0] = {
|
||||
.channel = 1,
|
||||
.period = 0,
|
||||
.pulse = 0
|
||||
},
|
||||
[1] = {
|
||||
.channel = 2,
|
||||
.period = 0,
|
||||
.pulse = 0
|
||||
}
|
||||
};
|
||||
|
||||
/* Define static device */
|
||||
static struct rt_device_pwm pwm_dev_gp16c2t4;
|
||||
static struct pwm_dev_ctrl pwm_dev_gp16c2t4_ctrl;
|
||||
#endif
|
||||
|
||||
static void pwm_auto_config_freq(AD16C4T_TypeDef *timerx, uint32_t ns)
|
||||
{
|
||||
uint32_t temp_ar;
|
||||
uint32_t temp_pres = timerx->PRES & 0xFFFF;
|
||||
uint32_t err_cnt = 0;
|
||||
|
||||
/* Automatic setting frequency division ratio */
|
||||
while (err_cnt++ < 65536)
|
||||
{
|
||||
temp_ar = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1);
|
||||
if (temp_ar <= 0xFFFF)
|
||||
break;
|
||||
temp_pres++;
|
||||
}
|
||||
|
||||
/* Write back to PRES */
|
||||
timerx->PRES = (uint16_t)(temp_pres & 0xFFFF);
|
||||
timerx->AR = temp_ar;
|
||||
}
|
||||
|
||||
static void pwm_set_duty(AD16C4T_TypeDef *timerx, uint8_t ch, uint32_t ns)
|
||||
{
|
||||
uint32_t temp_pres = timerx->PRES & 0xFFFF;
|
||||
uint64_t tmp = (uint64_t)SystemCoreClock * ns / 1000000000 / (temp_pres + 1);
|
||||
|
||||
if (ch == 1)
|
||||
WRITE_REG(timerx->CCVAL1, (uint32_t)tmp);
|
||||
else if (ch == 2)
|
||||
WRITE_REG(timerx->CCVAL2, (uint32_t)tmp);
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
|
||||
{
|
||||
rt_err_t ret = RT_EOK;
|
||||
struct pwm_dev_ctrl *dev_ctrl
|
||||
= (struct pwm_dev_ctrl *)device->parent.user_data;
|
||||
struct rt_pwm_configuration *cfg = (struct rt_pwm_configuration *)arg;
|
||||
AD16C4T_TypeDef *timerx = (AD16C4T_TypeDef *)dev_ctrl->timx;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case PWM_CMD_ENABLE:
|
||||
{
|
||||
if (cfg->channel == 1)
|
||||
SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK);
|
||||
else if (cfg->channel == 2)
|
||||
SET_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK);
|
||||
break;
|
||||
}
|
||||
case PWM_CMD_DISABLE:
|
||||
{
|
||||
if (cfg->channel == 1)
|
||||
CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC1EN_MSK);
|
||||
else if (cfg->channel == 2)
|
||||
CLEAR_BIT(timerx->CCEP, AD16C4T_CCEP_CC2EN_MSK);
|
||||
break;
|
||||
}
|
||||
case PWM_CMD_SET:
|
||||
{
|
||||
/* count registers max 0xFFFF, auto adjust prescaler */
|
||||
pwm_auto_config_freq(timerx, cfg->period);
|
||||
pwm_set_duty(timerx, cfg->channel, cfg->pulse);
|
||||
/* Remember configuration */
|
||||
dev_ctrl->cfg[cfg->channel-1].period = cfg->period;
|
||||
dev_ctrl->cfg[cfg->channel-1].pulse = cfg->pulse;
|
||||
break;
|
||||
}
|
||||
case PWM_CMD_GET:
|
||||
{
|
||||
cfg->period = dev_ctrl->cfg[cfg->channel-1].period;
|
||||
cfg->pulse = dev_ctrl->cfg[cfg->channel-1].pulse;
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
const static struct rt_pwm_ops es32f0_pwm_ops =
|
||||
{
|
||||
es32f0_pwm_control
|
||||
};
|
||||
|
||||
int rt_hw_pwm_init(void)
|
||||
{
|
||||
rt_err_t ret = RT_EOK;
|
||||
|
||||
#ifdef BSP_USING_PWM_GP16C2T1 /* 2 channels */
|
||||
/* Open clock */
|
||||
SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T1EN_MSK);
|
||||
|
||||
/* GPIO configuration */
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_1, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_1, MD_GPIO_AF5);
|
||||
md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_2, MD_GPIO_AF5);
|
||||
|
||||
/* Timer configuration */
|
||||
MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK,
|
||||
(6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS));
|
||||
MODIFY_REG(GP16C2T1->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK,
|
||||
(6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS));
|
||||
SET_BIT(GP16C2T1->BDCFG, AD16C4T_BDCFG_GOEN_MSK);
|
||||
SET_BIT(GP16C2T1->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
|
||||
pwm_dev_gp16c2t1_ctrl.chnm = 2;
|
||||
pwm_dev_gp16c2t1_ctrl.timx = GP16C2T1;
|
||||
pwm_dev_gp16c2t1_ctrl.cfg = pwm_ch_cfg_gp16c2t1;
|
||||
/* Register PWM device */
|
||||
ret = rt_device_pwm_register(&pwm_dev_gp16c2t1,
|
||||
"pwm1", &es32f0_pwm_ops, &pwm_dev_gp16c2t1_ctrl);
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM_GP16C2T4 /* 2 channels */
|
||||
/* Open clock */
|
||||
SET_BIT(RCU->APB2EN, RCU_APB2EN_GP16C2T4EN_MSK);
|
||||
|
||||
/* GPIO configuration */
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_12, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_12, MD_GPIO_AF5);
|
||||
md_gpio_set_function8_15(GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF5);
|
||||
|
||||
/* Timer configuration */
|
||||
MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH1MOD_MSK,
|
||||
(6 << AD16C4T_CHMR1_OUTPUT_CH1MOD_POSS));
|
||||
MODIFY_REG(GP16C2T4->CHMR1, AD16C4T_CHMR1_OUTPUT_CH2MOD_MSK,
|
||||
(6 << AD16C4T_CHMR1_OUTPUT_CH2MOD_POSS));
|
||||
SET_BIT(GP16C2T4->BDCFG, AD16C4T_BDCFG_GOEN_MSK);
|
||||
SET_BIT(GP16C2T4->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
|
||||
pwm_dev_gp16c2t4_ctrl.chnm = 2;
|
||||
pwm_dev_gp16c2t4_ctrl.timx = GP16C2T4;
|
||||
pwm_dev_gp16c2t4_ctrl.cfg = pwm_ch_cfg_gp16c2t4;
|
||||
/* Register PWM device */
|
||||
ret = rt_device_pwm_register(&pwm_dev_gp16c2t4,
|
||||
"pwm2", &es32f0_pwm_ops, &pwm_dev_gp16c2t4_ctrl);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_pwm_init);
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_PWM_H__
|
||||
#define DRV_PWM_H__
|
||||
|
||||
int rt_hw_pwm_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,253 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <string.h>
|
||||
#include <sys/time.h>
|
||||
#include "board.h"
|
||||
#include "drv_rtc.h"
|
||||
|
||||
#ifdef RT_USING_RTC
|
||||
|
||||
/**
|
||||
* @brief Time structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t hour; /**< Hours */
|
||||
uint8_t minute; /**< Minutes */
|
||||
uint8_t second; /**< Seconds */
|
||||
uint16_t sub_sec; /**< Sub-seconds */
|
||||
} rtc_time_t;
|
||||
|
||||
/**
|
||||
* @brief Date structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t week; /**< Weeks */
|
||||
uint8_t day; /**< days */
|
||||
uint8_t month; /**< months */
|
||||
uint8_t year; /**< years */
|
||||
} rtc_date_t;
|
||||
|
||||
static rt_uint32_t bcd_to_dec(rt_uint32_t bcd)
|
||||
{
|
||||
return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10);
|
||||
}
|
||||
|
||||
static void rtc_get_time(rtc_time_t *time)
|
||||
{
|
||||
rt_uint32_t tmp = RTC->TIME;
|
||||
|
||||
time->second = bcd_to_dec(tmp & 0x7F);
|
||||
time->minute = bcd_to_dec((tmp >> 8) & 0x7F);
|
||||
time->hour = bcd_to_dec((tmp >> 16) & 0x7F);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void rtc_get_date(rtc_date_t *date)
|
||||
{
|
||||
uint32_t tmp = RTC->CAL;
|
||||
|
||||
date->day = bcd_to_dec(tmp & 0x3F);
|
||||
date->month = bcd_to_dec((tmp >> 8) & 0x1F);
|
||||
date->year = bcd_to_dec((tmp >> 16) & 0xFF);
|
||||
date->week = bcd_to_dec((RTC->TIME >> 24) & 0x7);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_rtc_control(rt_device_t dev, int cmd, void *args)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
struct tm time_temp;
|
||||
struct tm *pNow;
|
||||
rt_uint16_t timout = 0xFFF;
|
||||
rtc_time_t *time = rt_malloc(sizeof(rtc_time_t));
|
||||
rtc_date_t *date = rt_malloc(sizeof(rtc_date_t));
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_RTC_GET_TIME:
|
||||
{
|
||||
/* Wait RTC data ready then read */
|
||||
while ((--timout)&&((RTC->STAT & RTC_STAT_SYNDONE_MSK) != RTC_STAT_SYNDONE_MSK));
|
||||
if (timout == 0)
|
||||
result = RT_ERROR;
|
||||
/* Read */
|
||||
rtc_get_time(time);
|
||||
rtc_get_date(date);
|
||||
|
||||
time_temp.tm_sec = time->second;
|
||||
time_temp.tm_min = time->minute;
|
||||
time_temp.tm_hour = time->hour;
|
||||
time_temp.tm_wday = date->week - 1;
|
||||
time_temp.tm_mday = date->day;
|
||||
time_temp.tm_mon = date->month - 1;
|
||||
time_temp.tm_year = date->year - 1900 + 2000;
|
||||
*((time_t *)args) = timegm(&time_temp);
|
||||
break;
|
||||
}
|
||||
case RT_DEVICE_CTRL_RTC_SET_TIME:
|
||||
{
|
||||
rt_enter_critical();
|
||||
/* converts calendar time time into local time. */
|
||||
pNow = gmtime((const time_t *)args);
|
||||
/* copy the statically located variable */
|
||||
memcpy(&time_temp, pNow, sizeof(struct tm));
|
||||
/* unlock scheduler. */
|
||||
rt_exit_critical();
|
||||
|
||||
time->hour = time_temp.tm_hour;
|
||||
time->minute = time_temp.tm_min;
|
||||
time->second = time_temp.tm_sec;
|
||||
date->year = time_temp.tm_year + 1900 - 2000;
|
||||
date->month = time_temp.tm_mon + 1;
|
||||
date->day = time_temp.tm_mday;
|
||||
/* Stop RTC */
|
||||
CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK);
|
||||
WRITE_REG(RTC->TIME, ((time->hour/10)<<RTC_TIME_HOUR_T_POSS) /* hour */
|
||||
|((time->hour%10)<<RTC_TIME_HOUR_U_POSS)
|
||||
|((time->minute/10)<<RTC_TIME_MIN_T_POSS) /* minute */
|
||||
|((time->minute%10)<<RTC_TIME_MIN_U_POSS)
|
||||
|((time->second/10)<<RTC_TIME_SEC_T_POSS) /* second */
|
||||
|((time->second%10)<<RTC_TIME_SEC_U_POSS));
|
||||
WRITE_REG(RTC->CAL, ((date->year/10)<<RTC_CAL_YEAR_T_POSS) /* year */
|
||||
|((date->year%10)<<RTC_CAL_YEAR_U_POSS)
|
||||
|((date->month/10)<<RTC_CAL_MON_T_POS) /* month */
|
||||
|((date->month%10)<<RTC_CAL_MON_U_POSS)
|
||||
|((date->day/10)<<RTC_CAL_DATE_T_POSS) /* date */
|
||||
|((date->day%10)<<RTC_CAL_DATE_U_POSS));
|
||||
/* start RTC */
|
||||
SET_BIT(RTC->CON, RTC_CON_RTCEN_MSK);
|
||||
break;
|
||||
}
|
||||
case RT_DEVICE_CTRL_RTC_GET_ALARM:
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_RTC_SET_ALARM:
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
rt_free(time);
|
||||
rt_free(date);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
const static struct rt_device_ops es32f0_rtc_ops =
|
||||
{
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
es32f0_rtc_control
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct rt_device rtc_dev;
|
||||
#define RTC_SOURCE_LOSC 0x1
|
||||
#define RTC_SOURCE_LRC 0x2
|
||||
int rt_hw_rtc_init(void)
|
||||
{
|
||||
rt_err_t ret = RT_EOK;
|
||||
rt_uint16_t timout = 0xFFFF;
|
||||
rt_uint32_t rtc_clk = 32768-1;
|
||||
rt_uint8_t rtc_src = RTC_SOURCE_LOSC;
|
||||
|
||||
/*
|
||||
* Config RTC clock
|
||||
* We config the external 32.768K crystal as RTC clock source for the first
|
||||
* choice. If external 32.768K crystal is not ready, we will choose LRC.
|
||||
*/
|
||||
/* Enable LOSC then wait it ready */
|
||||
if ((RCU->CON & RCU_CON_LOSCON_MSK) != RCU_CON_LOSCON_MSK)
|
||||
SET_BIT(RCU->CON, RCU_CON_LOSCON_MSK);
|
||||
|
||||
/* Wait external 32.768K crystal ready */
|
||||
while (((RCU->CON & RCU_CON_LOSCRDY_MSK) != RCU_CON_LOSCRDY_MSK)&&(--timout));
|
||||
if (timout == 0)
|
||||
{
|
||||
/* We use LRC if external 32.768K crystal is not ready */
|
||||
if ((RCU->CON & RCU_CON_LRCON_MSK) != RCU_CON_LRCON_MSK)
|
||||
SET_BIT(RCU->CON, RCU_CON_LRCON_MSK);
|
||||
/* Wait LRC ready */
|
||||
timout = 0xFF;
|
||||
while (((RCU->CON & RCU_CON_LRCRDY_MSK) != RCU_CON_LRCRDY_MSK)&&(--timout));
|
||||
rtc_clk = 32000-1;
|
||||
rtc_src = RTC_SOURCE_LRC;
|
||||
}
|
||||
|
||||
/* Open RTC clock */
|
||||
SET_BIT(RCU->AHBEN, RCU_AHBEN_RTCEN_MSK);
|
||||
|
||||
/* Reset RTC */
|
||||
SET_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK);
|
||||
CLEAR_BIT(RCU->AHBRST, RCU_AHBRST_RTCEN_MSK);
|
||||
CLEAR_BIT(RTC->CON, RTC_CON_RTCEN_MSK);
|
||||
|
||||
/* Config RTC clock source */
|
||||
MODIFY_REG(RTC->CON, RTC_CON_CKSEL_MSK, rtc_src<<RTC_CON_CKSEL_POSS);
|
||||
MODIFY_REG(RTC->CON, RTC_CON_PSCALE_MSK|RTC_CON_SCALE_MSK,
|
||||
((rtc_clk&0x7F)<<RTC_CON_PSCALE_POSS)|
|
||||
(((rtc_clk>>7)&0xFF)<<RTC_CON_SCALE_POSS));
|
||||
|
||||
/* Set default time - Wed Oct 30 08:00:00 2019 */
|
||||
WRITE_REG(RTC->TIME, (0x3<<RTC_TIME_WEEK_POSS) /* week */
|
||||
|(0x0<<RTC_TIME_HOUR_T_POSS) /* hour */
|
||||
|(0x8<<RTC_TIME_HOUR_U_POSS)
|
||||
|(0x0<<RTC_TIME_MIN_T_POSS) /* minute */
|
||||
|(0x0<<RTC_TIME_MIN_U_POSS)
|
||||
|(0x0<<RTC_TIME_SEC_T_POSS) /* second */
|
||||
|(0x0<<RTC_TIME_SEC_U_POSS));
|
||||
WRITE_REG(RTC->CAL, (0x1<<RTC_CAL_YEAR_T_POSS) /* year */
|
||||
|(0x9<<RTC_CAL_YEAR_U_POSS)
|
||||
|(0x1<<RTC_CAL_MON_T_POS) /* month */
|
||||
|(0x0<<RTC_CAL_MON_U_POSS)
|
||||
|(0x3<<RTC_CAL_DATE_T_POSS) /* date */
|
||||
|(0x0<<RTC_CAL_DATE_U_POSS));
|
||||
|
||||
/* RTC start */
|
||||
SET_BIT(RTC->CON, RTC_CON_RTCEN_MSK);
|
||||
|
||||
rtc_dev.type = RT_Device_Class_RTC;
|
||||
rtc_dev.rx_indicate = RT_NULL;
|
||||
rtc_dev.tx_complete = RT_NULL;
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
rtc_dev.ops = &es32f0_rtc_ops;
|
||||
#else
|
||||
rtc_dev.init = RT_NULL;
|
||||
rtc_dev.open = RT_NULL;
|
||||
rtc_dev.close = RT_NULL;
|
||||
rtc_dev.read = RT_NULL;
|
||||
rtc_dev.write = RT_NULL;
|
||||
rtc_dev.control = es32f0_rtc_control;
|
||||
#endif
|
||||
|
||||
rtc_dev.user_data = RTC;
|
||||
|
||||
ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR);
|
||||
|
||||
return ret;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
|
||||
|
||||
#endif
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_RTC_H__
|
||||
#define DRV_RTC_H__
|
||||
|
||||
int rt_hw_rtc_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,439 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <string.h>
|
||||
#include <rthw.h>
|
||||
#include "board.h"
|
||||
#include "drv_spi.h"
|
||||
#include "md_spi.h"
|
||||
#include "md_gpio.h"
|
||||
|
||||
#ifdef RT_USING_SPI
|
||||
|
||||
#define SPITIMEOUT 0x0FFF
|
||||
|
||||
static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf,
|
||||
rt_int32_t len, rt_uint32_t tmout);
|
||||
static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf,
|
||||
rt_int32_t len, rt_uint32_t tmout);
|
||||
static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf,
|
||||
rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout);
|
||||
|
||||
/**
|
||||
* @brief: SPI single line send.
|
||||
* @param: device, pointer to the SPI device
|
||||
* @param: buf, send data buffer
|
||||
* @param: len, the length of buf
|
||||
* @param: tmout, timeout
|
||||
* @retval: rt_err_t
|
||||
*/
|
||||
static rt_err_t __spi_send(struct rt_spi_device *device, rt_uint8_t *buf,
|
||||
rt_int32_t len, rt_uint32_t tmout)
|
||||
{
|
||||
SPI_TypeDef *hspi;
|
||||
rt_uint32_t rt_timout;
|
||||
rt_uint8_t temp_data;
|
||||
|
||||
/* Get the SPI port */
|
||||
hspi = (SPI_TypeDef *)device->bus->parent.user_data;
|
||||
|
||||
/* Open SPI if it is disabled */
|
||||
if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK)
|
||||
SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK);
|
||||
|
||||
while (len > 0)
|
||||
{
|
||||
/* Confirm that no data is being transmitted */
|
||||
rt_timout = tmout;
|
||||
while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout));
|
||||
if (rt_timout == 0)
|
||||
return RT_ETIMEOUT;
|
||||
|
||||
/* Send data */
|
||||
if (device->config.data_width == 8)
|
||||
{
|
||||
hspi->DATA = *(rt_uint8_t *)buf;
|
||||
buf++;
|
||||
len--;
|
||||
}
|
||||
else if (device->config.data_width == 16)
|
||||
{
|
||||
hspi->DATA = *(rt_uint16_t *)buf;
|
||||
buf += 2;
|
||||
len -= 2;
|
||||
}
|
||||
else
|
||||
return RT_EINVAL;
|
||||
}
|
||||
|
||||
/* At here, we have transmitted all the data.
|
||||
* The next step is to clear the IT flag.
|
||||
*/
|
||||
for (rt_uint8_t i = 0; i < md_spi_get_stat_rxflv(hspi); i++)
|
||||
temp_data = hspi->DATA;
|
||||
UNUSED(temp_data);
|
||||
hspi->ICR = hspi->RIF;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief: SPI single line receive.
|
||||
* @param: device, pointer to the SPI device
|
||||
* @param: buf, receive data buffer
|
||||
* @param: len, the length of buf
|
||||
* @param: tmout, timeout
|
||||
* @retval: rt_err_t
|
||||
*/
|
||||
static rt_err_t __spi_recv(struct rt_spi_device *device, rt_uint8_t *buf,
|
||||
rt_int32_t len, rt_uint32_t tmout)
|
||||
{
|
||||
SPI_TypeDef *hspi;
|
||||
rt_uint32_t rt_timout;
|
||||
|
||||
/* Get the SPI port */
|
||||
hspi = (SPI_TypeDef *)device->bus->parent.user_data;
|
||||
|
||||
/* Open SPI if it is disabled */
|
||||
if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK)
|
||||
SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK);
|
||||
|
||||
/* Handle data in __spi_send_recv() function */
|
||||
if (((device->config.mode & RT_SPI_SLAVE) == 0)
|
||||
&& ((device->config.mode & RT_SPI_3WIRE) == 0))
|
||||
__spi_send_recv(device, buf, buf, len, tmout);
|
||||
|
||||
while (len > 0)
|
||||
{
|
||||
/* Waiting for data */
|
||||
rt_timout = tmout;
|
||||
while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout));
|
||||
if (rt_timout == 0)
|
||||
return RT_ETIMEOUT;
|
||||
|
||||
/* Send data */
|
||||
if (device->config.data_width == 8)
|
||||
{
|
||||
*(rt_uint8_t *)buf = hspi->DATA;
|
||||
buf++;
|
||||
len--;
|
||||
}
|
||||
else if (device->config.data_width == 16)
|
||||
{
|
||||
*(rt_uint16_t *)buf = hspi->DATA;
|
||||
buf += 2;
|
||||
len -= 2;
|
||||
}
|
||||
else
|
||||
return RT_EINVAL;
|
||||
}
|
||||
|
||||
/* At here, we have transmitted all the data.
|
||||
* The next step is to clear the IT flag.
|
||||
*/
|
||||
hspi->ICR = hspi->RIF;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief: SPI two line transmission.
|
||||
* @param: device, pointer to the SPI device
|
||||
* @param: tbuf, send data buffer
|
||||
* @param: rbuf, receive data buffer
|
||||
* @param: len, the length of buf
|
||||
* @param: tmout, timeout
|
||||
* @retval: rt_err_t
|
||||
*/
|
||||
static rt_err_t __spi_send_recv(struct rt_spi_device *device, rt_uint8_t *tbuf,
|
||||
rt_uint8_t *rbuf, rt_int32_t len, rt_uint32_t tmout)
|
||||
{
|
||||
SPI_TypeDef *hspi;
|
||||
rt_uint32_t rt_timout;
|
||||
|
||||
/* Get the SPI port */
|
||||
hspi = (SPI_TypeDef *)device->bus->parent.user_data;
|
||||
|
||||
/* Open SPI if it is disabled */
|
||||
if (READ_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK) != SPI_CON1_SPIEN_MSK)
|
||||
SET_BIT(hspi->CON1, SPI_CON1_SPIEN_MSK);
|
||||
|
||||
/* return error if SPI is in 1-line mode */
|
||||
if ((device->config.mode & RT_SPI_3WIRE) == RT_SPI_3WIRE)
|
||||
return RT_ERROR;
|
||||
|
||||
while (len > 0)
|
||||
{
|
||||
/* Confirm that no data is being transmitted */
|
||||
rt_timout = tmout;
|
||||
while (((hspi->STAT & SPI_STAT_TXE_MSK) == 0) && (--rt_timout));
|
||||
if (rt_timout == 0)
|
||||
return RT_ETIMEOUT;
|
||||
|
||||
/* Send data */
|
||||
if (device->config.data_width == 8)
|
||||
{
|
||||
hspi->DATA = *(rt_uint8_t *)tbuf;
|
||||
tbuf++;
|
||||
len--;
|
||||
}
|
||||
else if (device->config.data_width == 16)
|
||||
{
|
||||
hspi->DATA = *(rt_uint16_t *)tbuf;
|
||||
tbuf += 2;
|
||||
len -= 2;
|
||||
}
|
||||
else
|
||||
return RT_EINVAL;
|
||||
|
||||
/* Waiting for data */
|
||||
rt_timout = tmout;
|
||||
while (((hspi->STAT & SPI_STAT_RXTH_MSK) == 0) && (--rt_timout));
|
||||
if (rt_timout == 0)
|
||||
return RT_ETIMEOUT;
|
||||
|
||||
/* Send data */
|
||||
if (device->config.data_width == 8)
|
||||
{
|
||||
*(rt_uint8_t *)rbuf = hspi->DATA;
|
||||
rbuf++;
|
||||
}
|
||||
else if (device->config.data_width == 16)
|
||||
{
|
||||
*(rt_uint16_t *)rbuf = hspi->DATA;
|
||||
rbuf += 2;
|
||||
}
|
||||
}
|
||||
|
||||
/* At here, we have transmitted all the data.
|
||||
* The next step is to clear the IT flag.
|
||||
*/
|
||||
hspi->ICR = hspi->RIF;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_err_t spi_configure(struct rt_spi_device *device,
|
||||
struct rt_spi_configuration *cfg)
|
||||
{
|
||||
SPI_TypeDef *hspi;
|
||||
hspi = (SPI_TypeDef *)device->bus->parent.user_data;
|
||||
|
||||
/* Close SPI temporarily */
|
||||
md_spi_disable_con1_spien(hspi);
|
||||
|
||||
/* config spi mode */
|
||||
if (cfg->mode & RT_SPI_SLAVE)
|
||||
md_spi_set_con1_mstren(hspi, MD_SPI_MODE_SLAVE);
|
||||
else
|
||||
md_spi_set_con1_mstren(hspi, MD_SPI_MODE_MASTER);
|
||||
|
||||
/* Config data mode */
|
||||
if (cfg->mode & RT_SPI_3WIRE)
|
||||
md_spi_set_con1_bidimode(hspi, MD_SPI_HALF_DUPLEX);
|
||||
else
|
||||
md_spi_set_con1_bidimode(hspi, MD_SPI_FULL_DUPLEX);
|
||||
|
||||
/* Config data width */
|
||||
if (cfg->data_width == 8)
|
||||
md_spi_set_con1_flen(hspi, MD_SPI_FRAME_FORMAT_8BIT);
|
||||
else if (cfg->data_width == 16)
|
||||
md_spi_set_con1_flen(hspi, SPI_CON1_FLEN_MSK);
|
||||
|
||||
/* Config phase */
|
||||
if (cfg->mode & RT_SPI_CPHA)
|
||||
md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_2EDGE);
|
||||
else
|
||||
md_spi_set_con1_cpha(hspi, MD_SPI_PHASE_1EDGE);
|
||||
|
||||
/* Config polarity */
|
||||
if (cfg->mode & RT_SPI_CPOL)
|
||||
md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_HIGH);
|
||||
else
|
||||
md_spi_set_con1_cpol(hspi, MD_SPI_POLARITY_LOW);
|
||||
|
||||
/* Config if NSS pin is managed by software */
|
||||
md_spi_disable_con1_ssen(hspi);
|
||||
|
||||
/* config spi clock */
|
||||
if (cfg->max_hz >= SystemCoreClock / 2)
|
||||
{
|
||||
/* pclk1 max speed 48MHz, spi master max speed 10MHz */
|
||||
if (SystemCoreClock / 2 <= 10000000)
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV2);
|
||||
else if (SystemCoreClock / 4 <= 10000000)
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4);
|
||||
else
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8);
|
||||
}
|
||||
else if (cfg->max_hz >= SystemCoreClock / 4)
|
||||
{
|
||||
/* pclk1 max speed 48MHz, spi master max speed 10MHz */
|
||||
if (SystemCoreClock / 4 <= 10000000)
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV4);
|
||||
else
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8);
|
||||
}
|
||||
else if (cfg->max_hz >= SystemCoreClock / 8)
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV8);
|
||||
else if (cfg->max_hz >= SystemCoreClock / 16)
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV16);
|
||||
else if (cfg->max_hz >= SystemCoreClock / 32)
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV32);
|
||||
else if (cfg->max_hz >= SystemCoreClock / 64)
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV64);
|
||||
else if (cfg->max_hz >= SystemCoreClock / 128)
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV128);
|
||||
else
|
||||
md_spi_set_con1_baud(hspi, MD_SPI_BAUDRATEPRESCALER_DIV256);
|
||||
|
||||
/* Enable SPI */
|
||||
md_spi_enable_con1_spien(hspi);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||||
{
|
||||
rt_err_t res;
|
||||
rt_uint32_t *cs;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(device->bus != RT_NULL);
|
||||
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
|
||||
RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
|
||||
|
||||
cs = (rt_uint32_t *)device->parent.user_data;
|
||||
|
||||
/* only send data */
|
||||
if (message->recv_buf == RT_NULL)
|
||||
{
|
||||
if (message->cs_take)
|
||||
{
|
||||
rt_pin_write(*cs, 0);
|
||||
}
|
||||
res = __spi_send(device, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
|
||||
if (message->cs_release)
|
||||
{
|
||||
rt_pin_write(*cs, 1);
|
||||
}
|
||||
if (res != RT_EOK)
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
/* only receive data */
|
||||
if (message->send_buf == RT_NULL)
|
||||
{
|
||||
if (message->cs_take)
|
||||
{
|
||||
rt_pin_write(*cs, 0);
|
||||
}
|
||||
res = __spi_recv(device, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
|
||||
if (message->cs_release)
|
||||
{
|
||||
rt_pin_write(*cs, 1);
|
||||
}
|
||||
if (res != RT_EOK)
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
/* send & receive */
|
||||
else
|
||||
{
|
||||
if (message->cs_take)
|
||||
{
|
||||
rt_pin_write(*cs, 0);
|
||||
}
|
||||
res = __spi_send_recv(device, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
|
||||
(rt_int32_t)message->length, SPITIMEOUT);
|
||||
if (message->cs_release)
|
||||
{
|
||||
rt_pin_write(*cs, 1);
|
||||
}
|
||||
if (res != RT_EOK)
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
return message->length;
|
||||
}
|
||||
|
||||
const struct rt_spi_ops es32f0_spi_ops =
|
||||
{
|
||||
spi_configure,
|
||||
spixfer,
|
||||
};
|
||||
|
||||
static struct rt_spi_bus _spi_bus1, _spi_bus2;
|
||||
int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
|
||||
{
|
||||
struct rt_spi_bus *spi_bus;
|
||||
|
||||
if (SPIx == SPI2)
|
||||
{
|
||||
/* Open GPIO and SPI clock */
|
||||
SET_BIT(RCU->APB1EN, RCU_APB1EN_SPI2EN_MSK);
|
||||
SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK);
|
||||
|
||||
/* Config SPI2 GPIO */
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_13, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_14, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_15, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_13, MD_GPIO_AF0);
|
||||
md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_14, MD_GPIO_AF0);
|
||||
md_gpio_set_function8_15 (GPIOB, MD_GPIO_PIN_15, MD_GPIO_AF0);
|
||||
|
||||
/* Remember SPI bus2 */
|
||||
spi_bus = &_spi_bus2;
|
||||
}
|
||||
else if (SPIx == SPI1)
|
||||
{
|
||||
/* Open GPIO and SPI clock */
|
||||
SET_BIT(RCU->APB2EN, RCU_APB2EN_SPI1EN_MSK);
|
||||
SET_BIT(RCU->AHBEN, RCU_AHBEN_GPBEN_MSK);
|
||||
|
||||
/* Config SPI1 GPIO */
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_3, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_4, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_5, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_3, MD_GPIO_AF0);
|
||||
md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_4, MD_GPIO_AF0);
|
||||
md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_5, MD_GPIO_AF0);
|
||||
|
||||
/* Remember SPI bus1 */
|
||||
spi_bus = &_spi_bus1;
|
||||
}
|
||||
else
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
spi_bus->parent.user_data = SPIx;
|
||||
|
||||
return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops);
|
||||
}
|
||||
|
||||
int rt_hw_spi_init(void)
|
||||
{
|
||||
int result = 0;
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
result = es32f0_spi_register_bus(SPI2, "spi2");
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
result = es32f0_spi_register_bus(SPI1, "spi1");
|
||||
#endif
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_spi_init);
|
||||
|
||||
#endif
|
||||
@@ -1,22 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_SPI_H__
|
||||
#define DRV_SPI_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
///* cannot be used before completion init */
|
||||
//rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name);
|
||||
int rt_hw_spi_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,296 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
#include "md_gpio.h"
|
||||
#include "md_uart.h"
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
|
||||
/* es32 uart driver */
|
||||
struct es32_uart
|
||||
{
|
||||
UART_TypeDef *huart;
|
||||
IRQn_Type irq;
|
||||
};
|
||||
|
||||
static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct es32_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
uart = (struct es32_uart *)serial->parent.user_data;
|
||||
|
||||
/* Close TX/RX temporarily */
|
||||
md_uart_disable_lcon_txen(uart->huart);
|
||||
md_uart_disable_lcon_rxen(uart->huart);
|
||||
|
||||
#ifdef BSP_USING_UART1
|
||||
/* Open UART1 clock */
|
||||
SET_BIT(RCU->APB2EN, RCU_APB2EN_UART1EN_MSK);
|
||||
|
||||
/* Config UART1 GPIO pin */
|
||||
md_gpio_set_pull (GPIOB, MD_GPIO_PIN_7, MD_GPIO_PULL_UP);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_6, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOB, MD_GPIO_PIN_7, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_6, MD_GPIO_AF2);
|
||||
md_gpio_set_function0_7 (GPIOB, MD_GPIO_PIN_7, MD_GPIO_AF2);
|
||||
#endif /* uart2 gpio init */
|
||||
|
||||
#ifdef BSP_USING_UART2
|
||||
/* Open UART2 clock */
|
||||
SET_BIT(RCU->APB1EN, RCU_APB1EN_UART2EN_MSK);
|
||||
|
||||
/* Config UART2 GPIO pin */
|
||||
md_gpio_set_pull (GPIOA, MD_GPIO_PIN_3, MD_GPIO_PULL_UP);
|
||||
md_gpio_set_mode (GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_2, MD_GPIO_AF2);
|
||||
md_gpio_set_function0_7 (GPIOA, MD_GPIO_PIN_3, MD_GPIO_AF2);
|
||||
#endif /* uart1 gpio init */
|
||||
|
||||
#ifdef BSP_USING_UART3
|
||||
/* Open UART3 clock */
|
||||
SET_BIT(RCU->APB1EN, RCU_APB1EN_UART3EN_MSK);
|
||||
|
||||
/* Config UART3 GPIO pin */
|
||||
md_gpio_set_pull (GPIOC, MD_GPIO_PIN_7, MD_GPIO_PULL_UP);
|
||||
md_gpio_set_mode (GPIOC, MD_GPIO_PIN_6, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_mode (GPIOC, MD_GPIO_PIN_7, MD_GPIO_MODE_FUNCTION);
|
||||
md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_6, MD_GPIO_AF2);
|
||||
md_gpio_set_function0_7 (GPIOC, MD_GPIO_PIN_7, MD_GPIO_AF2);
|
||||
#endif /* uart3 gpio init */
|
||||
|
||||
if (cfg->bit_order == BIT_ORDER_MSB)
|
||||
{
|
||||
md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_MSB_FIRST);
|
||||
}
|
||||
else
|
||||
{
|
||||
md_uart_set_lcon_msb(uart->huart, MD_UART_LCON_LSB_FIRST);
|
||||
}
|
||||
|
||||
if (cfg->invert == NRZ_INVERTED)
|
||||
{
|
||||
md_uart_enable_lcon_datainv(uart->huart);
|
||||
}
|
||||
else
|
||||
{
|
||||
md_uart_disable_lcon_datainv(uart->huart);
|
||||
}
|
||||
|
||||
/* Config buadrate */
|
||||
md_uart_set_brr(uart->huart, SystemCoreClock/cfg->baud_rate);
|
||||
/* Config data width */
|
||||
md_uart_set_lcon_dls(uart->huart, 8-cfg->data_bits);
|
||||
/* Config stop bits */
|
||||
md_uart_set_lcon_stop(uart->huart, cfg->stop_bits);
|
||||
/* Config parity */
|
||||
if (cfg->parity > PARITY_NONE)
|
||||
{
|
||||
md_uart_set_lcon_ps(uart->huart, cfg->parity-1);
|
||||
md_uart_enable_lcon_pe(uart->huart);
|
||||
}
|
||||
else
|
||||
md_uart_disable_lcon_pe(uart->huart);
|
||||
|
||||
/* enable rx int */
|
||||
md_uart_set_fcon_rxth(uart->huart, MD_UART_FCON_RXTH_1);
|
||||
md_uart_enable_ier_rfth(uart->huart);
|
||||
md_uart_enable_lcon_txen(uart->huart);
|
||||
md_uart_enable_lcon_rxen(uart->huart);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct es32_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
uart = (struct es32_uart *)serial->parent.user_data;
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
NVIC_DisableIRQ(uart->irq);
|
||||
/* disable interrupt */
|
||||
md_uart_disable_idr_rfth(uart->huart);
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
NVIC_EnableIRQ(uart->irq);
|
||||
/* enable interrupt */
|
||||
md_uart_enable_ier_rfth(uart->huart);
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int es32f0x_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct es32_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct es32_uart *)serial->parent.user_data;
|
||||
|
||||
while (uart->huart->STAT & UART_STAT_TSBUSY_MSK);
|
||||
WRITE_REG(uart->huart->TXBUF, c);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int es32f0x_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
int ch = -1;
|
||||
struct es32_uart *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct es32_uart *)serial->parent.user_data;
|
||||
|
||||
if (uart->huart->STAT & UART_STAT_RFTH_MSK)
|
||||
{
|
||||
ch = (uint8_t)(uart->huart->RXBUF & 0xFF);
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops es32f0x_uart_ops =
|
||||
{
|
||||
es32f0x_configure,
|
||||
es32f0x_control,
|
||||
es32f0x_putc,
|
||||
es32f0x_getc,
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_UART1
|
||||
/* UART1 device driver structure */
|
||||
struct es32_uart uart1 =
|
||||
{
|
||||
UART1,
|
||||
UART1_IRQn
|
||||
};
|
||||
|
||||
struct rt_serial_device serial1;
|
||||
|
||||
void UART1_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
if (md_uart_is_active_flag_rif_rfth(UART1) == 1)
|
||||
{
|
||||
rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
|
||||
md_uart_clear_flag_rfth(UART1);
|
||||
}
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#ifdef BSP_USING_UART2
|
||||
/* UART2 device driver structure */
|
||||
struct es32_uart uart2 =
|
||||
{
|
||||
UART2,
|
||||
UART2_IRQn
|
||||
};
|
||||
|
||||
struct rt_serial_device serial2;
|
||||
|
||||
void UART2_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
if (md_uart_is_active_flag_rif_rfth(UART2) == 1)
|
||||
{
|
||||
rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
|
||||
md_uart_clear_flag_rfth(UART2);
|
||||
}
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#ifdef BSP_USING_UART3
|
||||
/* UART3 device driver structure */
|
||||
struct es32_uart uart3 =
|
||||
{
|
||||
UART3,
|
||||
UART3_IRQn
|
||||
};
|
||||
|
||||
struct rt_serial_device serial3;
|
||||
|
||||
void UART3_AES_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
if (md_uart_is_active_flag_rif_rfth(UART3) == 1)
|
||||
{
|
||||
rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
|
||||
md_uart_clear_flag_rfth(UART3);
|
||||
}
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct es32_uart *uart;
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
#ifdef BSP_USING_UART1
|
||||
uart = &uart1;
|
||||
serial1.ops = &es32f0x_uart_ops;
|
||||
serial1.config = config;
|
||||
|
||||
/* register UART1 device */
|
||||
rt_hw_serial_register(&serial1, "uart1",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
||||
uart);
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#ifdef BSP_USING_UART2
|
||||
uart = &uart2;
|
||||
serial2.ops = &es32f0x_uart_ops;
|
||||
serial2.config = config;
|
||||
|
||||
/* register UART2 device */
|
||||
rt_hw_serial_register(&serial2, "uart2",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
||||
uart);
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#ifdef BSP_USING_UART3
|
||||
uart = &uart3;
|
||||
serial3.ops = &es32f0x_uart_ops;
|
||||
serial3.config = config;
|
||||
|
||||
/* register UART3 device */
|
||||
rt_hw_serial_register(&serial3, "uart3",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
||||
uart);
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_uart_init);
|
||||
|
||||
#endif
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_UART_H__
|
||||
#define DRV_UART_H__
|
||||
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,14 +0,0 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x10000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x10000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x2000{ ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
-683
File diff suppressed because it is too large
Load Diff
-795
File diff suppressed because it is too large
Load Diff
-193
@@ -1,193 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_AES.h
|
||||
* @brief AES Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 11/16/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __AES_H__
|
||||
#define __AES_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for AES_CON register ************************/
|
||||
|
||||
#define AES_CON_READY_POS 22U
|
||||
#define AES_CON_READY_MSK BIT(AES_CON_READY_POS)
|
||||
|
||||
#define AES_CON_OT_DMA_ST_POS 21U
|
||||
#define AES_CON_OT_DMA_ST_MSK BIT(AES_CON_OT_DMA_ST_POS)
|
||||
|
||||
#define AES_CON_IT_DMA_ST_POS 20U
|
||||
#define AES_CON_IT_DMA_ST_MSK BIT(AES_CON_IT_DMA_ST_POS)
|
||||
|
||||
#define AES_CON_OT_DEPTH_POSS 18U
|
||||
#define AES_CON_OT_DEPTH_POSE 19U
|
||||
#define AES_CON_OT_DEPTH_MSK BITS(AES_CON_OT_DEPTH_POSS,AES_CON_OT_DEPTH_POSE)
|
||||
|
||||
#define AES_CON_IT_DEPTH_POSS 16U
|
||||
#define AES_CON_IT_DEPTH_POSE 17U
|
||||
#define AES_CON_IT_DEPTH_MSK BITS(AES_CON_IT_DEPTH_POSS,AES_CON_IT_DEPTH_POSE)
|
||||
|
||||
#define AES_CON_RE_INIT_POS 8U
|
||||
#define AES_CON_RE_INIT_MSK BIT(AES_CON_RE_INIT_POS)
|
||||
|
||||
#define AES_CON_DMA_EN_POSS 6U
|
||||
#define AES_CON_DMA_EN_POSE 7U
|
||||
#define AES_CON_DMA_EN_MSK BITS(AES_CON_DMA_EN_POSS,AES_CON_DMA_EN_POSE)
|
||||
|
||||
#define AES_CON_BL_POSS 3U
|
||||
#define AES_CON_BL_POSE 5U
|
||||
#define AES_CON_BL_MSK BITS(AES_CON_BL_POSS,AES_CON_BL_POSE)
|
||||
|
||||
#define AES_CON_REV_POS 2U
|
||||
#define AES_CON_REV_MSK BIT(AES_CON_REV_POS)
|
||||
|
||||
#define AES_CON_MODE_POS 1U
|
||||
#define AES_CON_MODE_MSK BIT(AES_CON_MODE_POS)
|
||||
|
||||
#define AES_CON_START_POS 0U
|
||||
#define AES_CON_START_MSK BIT(AES_CON_START_POS)
|
||||
|
||||
/****************** Bit definition for AES_IER register ************************/
|
||||
|
||||
#define AES_IER_DECIE_POS 1U
|
||||
#define AES_IER_DECIE_MSK BIT(AES_IER_DECIE_POS)
|
||||
|
||||
#define AES_IER_ENCIE_POS 0U
|
||||
#define AES_IER_ENCIE_MSK BIT(AES_IER_ENCIE_POS)
|
||||
|
||||
/****************** Bit definition for AES_IDR register ************************/
|
||||
|
||||
#define AES_IDR_DECID_POS 1U
|
||||
#define AES_IDR_DECID_MSK BIT(AES_IDR_DECID_POS)
|
||||
|
||||
#define AES_IDR_ENCID_POS 0U
|
||||
#define AES_IDR_ENCID_MSK BIT(AES_IDR_ENCID_POS)
|
||||
|
||||
/****************** Bit definition for AES_IVS register ************************/
|
||||
|
||||
#define AES_IVS_DECIVS_POS 1U
|
||||
#define AES_IVS_DECIVS_MSK BIT(AES_IVS_DECIVS_POS)
|
||||
|
||||
#define AES_IVS_ENCIVS_POS 0U
|
||||
#define AES_IVS_ENCIVS_MSK BIT(AES_IVS_ENCIVS_POS)
|
||||
|
||||
/****************** Bit definition for AES_RIF register ************************/
|
||||
|
||||
#define AES_RIF_DECRIF_POS 1U
|
||||
#define AES_RIF_DECRIF_MSK BIT(AES_RIF_DECRIF_POS)
|
||||
|
||||
#define AES_RIF_ENCRIF_POS 0U
|
||||
#define AES_RIF_ENCRIF_MSK BIT(AES_RIF_ENCRIF_POS)
|
||||
|
||||
/****************** Bit definition for AES_IFM register ************************/
|
||||
|
||||
#define AES_IFM_DECIFM_POS 1U
|
||||
#define AES_IFM_DECIFM_MSK BIT(AES_IFM_DECIFM_POS)
|
||||
|
||||
#define AES_IFM_ENCIFM_POS 0U
|
||||
#define AES_IFM_ENCIFM_MSK BIT(AES_IFM_ENCIFM_POS)
|
||||
|
||||
/****************** Bit definition for AES_ICR register ************************/
|
||||
|
||||
#define AES_ICR_DECICR_POS 1U
|
||||
#define AES_ICR_DECICR_MSK BIT(AES_ICR_DECICR_POS)
|
||||
|
||||
#define AES_ICR_ENCICR_POS 0U
|
||||
#define AES_ICR_ENCICR_MSK BIT(AES_ICR_ENCICR_POS)
|
||||
|
||||
/****************** Bit definition for AES_DIO register ************************/
|
||||
|
||||
#define AES_DIO_DIO_POSS 0U
|
||||
#define AES_DIO_DIO_POSE 31U
|
||||
#define AES_DIO_DIO_MSK BITS(AES_DIO_DIO_POSS,AES_DIO_DIO_POSE)
|
||||
|
||||
/****************** Bit definition for AES_KEY0 register ************************/
|
||||
|
||||
#define AES_KEY0_KEY0_POSS 0U
|
||||
#define AES_KEY0_KEY0_POSE 31U
|
||||
#define AES_KEY0_KEY0_MSK BITS(AES_KEY0_KEY0_POSS,AES_KEY0_KEY0_POSE)
|
||||
|
||||
/****************** Bit definition for AES_KEY1 register ************************/
|
||||
|
||||
#define AES_KEY1_KEY1_POSS 0U
|
||||
#define AES_KEY1_KEY1_POSE 31U
|
||||
#define AES_KEY1_KEY1_MSK BITS(AES_KEY1_KEY1_POSS,AES_KEY1_KEY1_POSE)
|
||||
|
||||
/****************** Bit definition for AES_KEY2 register ************************/
|
||||
|
||||
#define AES_KEY2_KEY2_POSS 0U
|
||||
#define AES_KEY2_KEY2_POSE 31U
|
||||
#define AES_KEY2_KEY2_MSK BITS(AES_KEY2_KEY2_POSS,AES_KEY2_KEY2_POSE)
|
||||
|
||||
/****************** Bit definition for AES_KEY3 register ************************/
|
||||
|
||||
#define AES_KEY3_KEY3_POSS 0U
|
||||
#define AES_KEY3_KEY3_POSE 31U
|
||||
#define AES_KEY3_KEY3_MSK BITS(AES_KEY3_KEY3_POSS,AES_KEY3_KEY3_POSE)
|
||||
|
||||
/****************** Bit definition for AES_IV0 register ************************/
|
||||
|
||||
#define AES_IV0_IV0_POSS 0U
|
||||
#define AES_IV0_IV0_POSE 31U
|
||||
#define AES_IV0_IV0_MSK BITS(AES_IV0_IV0_POSS,AES_IV0_IV0_POSE)
|
||||
|
||||
/****************** Bit definition for AES_IV1 register ************************/
|
||||
|
||||
#define AES_IV1_IV1_POSS 0U
|
||||
#define AES_IV1_IV1_POSE 31U
|
||||
#define AES_IV1_IV1_MSK BITS(AES_IV1_IV1_POSS,AES_IV1_IV1_POSE)
|
||||
|
||||
/****************** Bit definition for AES_IV2 register ************************/
|
||||
|
||||
#define AES_IV2_IV2_POSS 0U
|
||||
#define AES_IV2_IV2_POSE 31U
|
||||
#define AES_IV2_IV2_MSK BITS(AES_IV2_IV2_POSS,AES_IV2_IV2_POSE)
|
||||
|
||||
/****************** Bit definition for AES_IV3 register ************************/
|
||||
|
||||
#define AES_IV3_IV3_POSS 0U
|
||||
#define AES_IV3_IV3_POSE 31U
|
||||
#define AES_IV3_IV3_MSK BITS(AES_IV3_IV3_POSS,AES_IV3_IV3_POSE)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CON; /* 0x000 AES_CON AES Control Register */
|
||||
__O uint32_t IER; /* 0x004 AES_IER AES Interrupt Enable Register */
|
||||
__O uint32_t IDR; /* 0x008 AES_IDR AES Interrupt Disable Register */
|
||||
__I uint32_t IVS; /* 0x00C AES_IVS AES Interrupt Valid Status Register */
|
||||
__I uint32_t RIF; /* 0x010 AES_RIF AES Raw Interrupt Flag Status Register */
|
||||
__I uint32_t IFM; /* 0x014 AES_IFM AES Interrupt Flag Masked Register */
|
||||
__O uint32_t ICR; /* 0x018 AES_ICR AES Interrupt Clear Register */
|
||||
__IO uint32_t DIO; /* 0x01C AES_DIO AES 128-bit Input/Output Data Register */
|
||||
__IO uint32_t KEY0; /* 0x020 AES_KEY0 AES 256-bit Keyword Register 0 */
|
||||
__IO uint32_t KEY1; /* 0x024 AES_KEY1 AES 256-bit Keyword Register 1 */
|
||||
__IO uint32_t KEY2; /* 0x028 AES_KEY2 AES 256-bit Keyword Register 2 */
|
||||
__IO uint32_t KEY3; /* 0x02C AES_KEY3 AES 256-bit Keyword Register 3 */
|
||||
uint32_t RESERVED0[4] ;
|
||||
__IO uint32_t IV0; /* 0x040 AES_IV0 AES 128-bit Initial Vector Register 0 */
|
||||
__IO uint32_t IV1; /* 0x044 AES_IV1 AES 128-bit Initial Vector Register 1 */
|
||||
__IO uint32_t IV2; /* 0x048 AES_IV2 AES 128-bit Initial Vector Register 2 */
|
||||
__IO uint32_t IV3; /* 0x04C AES_IV3 AES 128-bit Initial Vector Register 3 */
|
||||
} AES_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-95
@@ -1,95 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_CMP.h
|
||||
* @brief CMP Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 12/3/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __CMP_H__
|
||||
#define __CMP_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for CMP_CON register ************************/
|
||||
|
||||
#define CMP_CON_REFON_POS 4U
|
||||
#define CMP_CON_REFON_MSK BIT(CMP_CON_REFON_POS)
|
||||
|
||||
#define CMP_CON_CMPON2_POS 1U
|
||||
#define CMP_CON_CMPON2_MSK BIT(CMP_CON_CMPON2_POS)
|
||||
|
||||
#define CMP_CON_CMPON1_POS 0U
|
||||
#define CMP_CON_CMPON1_MSK BIT(CMP_CON_CMPON1_POS)
|
||||
|
||||
/****************** Bit definition for CMP_CFG1 register ************************/
|
||||
|
||||
#define CMP_CFG1_RS_POSS 4U
|
||||
#define CMP_CFG1_RS_POSE 5U
|
||||
#define CMP_CFG1_RS_MSK BITS(CMP_CFG1_RS_POSS,CMP_CFG1_RS_POSE)
|
||||
|
||||
#define CMP_CFG1_FEN_POS 3U
|
||||
#define CMP_CFG1_FEN_MSK BIT(CMP_CFG1_FEN_POS)
|
||||
|
||||
#define CMP_CFG1_PSEN_POS 2U
|
||||
#define CMP_CFG1_PSEN_MSK BIT(CMP_CFG1_PSEN_POS)
|
||||
|
||||
#define CMP_CFG1_INSEL_POS 1U
|
||||
#define CMP_CFG1_INSEL_MSK BIT(CMP_CFG1_INSEL_POS)
|
||||
|
||||
#define CMP_CFG1_IPSEL_POS 0U
|
||||
#define CMP_CFG1_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS)
|
||||
|
||||
/****************** Bit definition for CMP_CFG2 register ************************/
|
||||
|
||||
#define CMP_CFG2_RS_POSS 4U
|
||||
#define CMP_CFG2_RS_POSE 5U
|
||||
#define CMP_CFG2_RS_MSK BITS(CMP_CFG2_RS_POSS,CMP_CFG2_RS_POSE)
|
||||
|
||||
#define CMP_CFG2_FEN_POS 3U
|
||||
#define CMP_CFG2_FEN_MSK BIT(CMP_CFG1_FEN_POS)
|
||||
|
||||
#define CMP_CFG2_PSEN_POS 2U
|
||||
#define CMP_CFG2_PSEN_MSK BIT(CMP_CFG1_PSEN_POS)
|
||||
|
||||
#define CMP_CFG2_INSEL_POS 1U
|
||||
#define CMP_CFG2_INSEL_MSK BIT(CMP_CFG1_INSEL_POS)
|
||||
|
||||
#define CMP_CFG2_IPSEL_POS 0U
|
||||
#define CMP_CFG2_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS)
|
||||
|
||||
/****************** Bit definition for CMP_RULT register ************************/
|
||||
|
||||
#define CMP_RULT_CMPO2_POS 1U
|
||||
#define CMP_RULT_CMPO2_MSK BIT(CMP_RULT_CMPO2_POS)
|
||||
|
||||
#define CMP_RULT_CMPO1_POS 0U
|
||||
#define CMP_RULT_CMPO1_MSK BIT(CMP_RULT_CMPO1_POS)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CON;
|
||||
__IO uint32_t CFG1;
|
||||
__IO uint32_t CFG2;
|
||||
uint32_t RESERVED0[2] ;
|
||||
__I uint32_t RULT;
|
||||
} CMP_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-125
@@ -1,125 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_CRC.h
|
||||
* @brief CRC Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 11/16/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __CRC_H__
|
||||
#define __CRC_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for CRC_INIT register ************************/
|
||||
|
||||
#define CRC_INIT_INIT_POSS 0U
|
||||
#define CRC_INIT_INIT_POSE 31U
|
||||
#define CRC_INIT_INIT_MSK BITS(CRC_INIT_INIT_POSS,CRC_INIT_INIT_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_POLY register ************************/
|
||||
|
||||
#define CRC_POLY_POLY_POSS 0U
|
||||
#define CRC_POLY_POLY_POSE 31U
|
||||
#define CRC_POLY_POLY_MSK BITS(CRC_POLY_POLY_POSS,CRC_POLY_POLY_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_DATA register ************************/
|
||||
|
||||
#define CRC_DATA_DATA_POSS 0U
|
||||
#define CRC_DATA_DATA_POSE 31U
|
||||
#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_COMP register ************************/
|
||||
|
||||
#define CRC_COMP_COMP_POSS 0U
|
||||
#define CRC_COMP_COMP_POSE 31U
|
||||
#define CRC_COMP_COMP_MSK BITS(CRC_COMP_COMP_POSS,CRC_COMP_COMP_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_REMA register ************************/
|
||||
|
||||
#define CRC_REMA_REMA_POSS 0U
|
||||
#define CRC_REMA_REMA_POSE 31U
|
||||
#define CRC_REMA_REMA_MSK BITS(CRC_REMA_REMA_POSS,CRC_REMA_REMA_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_CON register ************************/
|
||||
|
||||
#define CRC_CON_DMA_POS 16U
|
||||
#define CRC_CON_DMA_MSK BIT(CRC_CON_DMA_POS)
|
||||
|
||||
#define CRC_CON_MSB_POS 12U
|
||||
#define CRC_CON_MSB_MSK BIT(CRC_CON_MSB_POS)
|
||||
|
||||
#define CRC_CON_REOUT_POS 10U
|
||||
#define CRC_CON_REOUT_MSK BIT(CRC_CON_REOUT_POS)
|
||||
|
||||
#define CRC_CON_REIN_POS 8U
|
||||
#define CRC_CON_REIN_MSK BIT(CRC_CON_REIN_POS)
|
||||
|
||||
#define CRC_CON_SIZE_POSS 4U
|
||||
#define CRC_CON_SIZE_POSE 5U
|
||||
#define CRC_CON_SIZE_MSK BITS(CRC_CON_SIZE_POSS,CRC_CON_SIZE_POSE)
|
||||
|
||||
#define CRC_CON_MODE_POSS 2U
|
||||
#define CRC_CON_MODE_POSE 3U
|
||||
#define CRC_CON_MODE_MSK BITS(CRC_CON_MODE_POSS,CRC_CON_MODE_POSE)
|
||||
|
||||
#define CRC_CON_RESET_POS 0U
|
||||
#define CRC_CON_RESET_MSK BIT(CRC_CON_RESET_POS)
|
||||
|
||||
/****************** Bit definition for CRC_DOUT register ************************/
|
||||
|
||||
#define CRC_DOUT_DOUT_POSS 0U
|
||||
#define CRC_DOUT_DOUT_POSE 31U
|
||||
#define CRC_DOUT_DOUT_MSK BITS(CRC_DOUT_DOUT_POSS,CRC_DOUT_DOUT_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_DOUT_XOR register ************************/
|
||||
|
||||
#define CRC_DOUT_XOR_DOUT_XOR_POSS 0U
|
||||
#define CRC_DOUT_XOR_DOUT_XOR_POSE 31U
|
||||
#define CRC_DOUT_XOR_DOUT_XOR_MSK BITS(CRC_DOUT_XOR_DOUT_XOR_POSS,CRC_DOUT_XOR_DOUT_XOR_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_STAT register ************************/
|
||||
|
||||
#define CRC_STAT_FAIL_POS 8U
|
||||
#define CRC_STAT_FAIL_MSK BIT(CRC_STAT_FAIL_POS)
|
||||
|
||||
#define CRC_STAT_EMPTY_POS 2U
|
||||
#define CRC_STAT_EMPTY_MSK BIT(CRC_STAT_EMPTY_POS)
|
||||
|
||||
#define CRC_STAT_BUSY_POS 1U
|
||||
#define CRC_STAT_BUSY_MSK BIT(CRC_STAT_BUSY_POS)
|
||||
|
||||
#define CRC_STAT_DONE_POS 0U
|
||||
#define CRC_STAT_DONE_MSK BIT(CRC_STAT_DONE_POS)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t INIT; /* 0x000 CRC_INIT CRC Iintial Value Register */
|
||||
__IO uint32_t POLY; /* 0x004 CRC_POLY CRC Polynomial Register */
|
||||
__IO uint32_t DATA; /* 0x008 CRC_DATA CRC Input Data Register */
|
||||
__IO uint32_t COMP; /* 0x00C CRC_COMP CRC Compare Data Register */
|
||||
__IO uint32_t REMA; /* 0x010 CRC_REMA CRC Remainder Register */
|
||||
__IO uint32_t CON; /* 0x014 CRC_CTRL CRC Control Register */
|
||||
__I uint32_t DOUT; /* 0x018 CRC_DOUT CRC Output Data Register */
|
||||
__I uint32_t DOUT_XOR; /* 0x01C CRC_DOUT_XOR CRC Output Data Register */
|
||||
__I uint32_t STAT; /* 0x020 CRC_STA CRC Status Register */
|
||||
} CRC_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-97
@@ -1,97 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_DAC.h
|
||||
* @brief DAC Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 1/14/2019
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __DAC_H__
|
||||
#define __DAC_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for DAC_CON register ************************/
|
||||
|
||||
#define DAC_CON_T_SEL_POSS 9U
|
||||
#define DAC_CON_T_SEL_POSE 13U
|
||||
#define DAC_CON_T_SEL_MSK BITS(DAC_CON_T_SEL_POSS,DAC_CON_T_SEL_POSE)
|
||||
|
||||
#define DAC_CON_TRIEN_POS 8U
|
||||
#define DAC_CON_TRIEN_MSK BIT(DAC_CON_TRIEN_POS)
|
||||
|
||||
#define DAC_CON_MAMP_POSS 3U
|
||||
#define DAC_CON_MAMP_POSE 6U
|
||||
#define DAC_CON_MAMP_MSK BITS(DAC_CON_MAMP_POSS,DAC_CON_MAMP_POSE)
|
||||
|
||||
#define DAC_CON_WAVE_POSS 1U
|
||||
#define DAC_CON_WAVE_POSE 2U
|
||||
#define DAC_CON_WAVE_MSK BITS(DAC_CON_WAVE_POSS,DAC_CON_WAVE_POSE)
|
||||
|
||||
#define DAC_CON_INVREN_POS 0U
|
||||
#define DAC_CON_INVREN_MSK BIT(DAC_CON_INVREN_POS)
|
||||
|
||||
/****************** Bit definition for DAC_DIV register ************************/
|
||||
|
||||
#define DAC_DIV_DIV_VALUE_POSS 0U
|
||||
#define DAC_DIV_DIV_VALUE_POSE 15U
|
||||
#define DAC_DIV_DIV_VALUE_MSK BITS(DAC_DIV_DIV_VALUE_POSS,DAC_DIV_DIV_VALUE_POSE)
|
||||
|
||||
/****************** Bit definition for DAC_STAT register ************************/
|
||||
|
||||
#define DAC_STAT_TX_FULL_POS 1U
|
||||
#define DAC_STAT_TX_FULL_MSK BIT(DAC_STAT_TX_FULL_POS)
|
||||
|
||||
#define DAC_STAT_BUSY_POS 0U
|
||||
#define DAC_STAT_BUSY_MSK BIT(DAC_STAT_BUSY_POS)
|
||||
|
||||
/****************** Bit definition for DAC_EN register ************************/
|
||||
|
||||
#define DAC_EN_DAC_EN_POS 0U
|
||||
#define DAC_EN_DAC_EN_MSK BIT(DAC_EN_DAC_EN_POS)
|
||||
|
||||
/****************** Bit definition for DAC_DMAC register ************************/
|
||||
|
||||
#define DAC_DMAC_TXDMAEN_POS 0U
|
||||
#define DAC_DMAC_TXDMAEN_MSK BIT(DAC_DMAC_TXDMAEN_POS)
|
||||
|
||||
/****************** Bit definition for DAC_TRIG register ************************/
|
||||
|
||||
#define DAC_TRIG_S_TRIG_POS 0U
|
||||
#define DAC_TRIG_S_TRIG_MSK BIT(DAC_TRIG_S_TRIG_POS)
|
||||
|
||||
/****************** Bit definition for DAC_DATA register ************************/
|
||||
|
||||
#define DAC_DATA_TXDATA_POSS 0U
|
||||
#define DAC_DATA_TXDATA_POSE 11U
|
||||
#define DAC_DATA_TXDATA_MSK BITS(DAC_DATA_TXDATA_POSS,DAC_DATA_TXDATA_POSE)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CON;
|
||||
__IO uint32_t DIV;
|
||||
__I uint32_t STAT;
|
||||
__IO uint32_t EN;
|
||||
__IO uint32_t DMAC;
|
||||
__O uint32_t TRIG;
|
||||
__IO uint32_t DATA;
|
||||
} DAC_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-825
File diff suppressed because it is too large
Load Diff
-809
File diff suppressed because it is too large
Load Diff
-181
@@ -1,181 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_FC.h
|
||||
* @brief FC Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 12/3/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __fc_H__
|
||||
#define __fc_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for FC_CMD register ************************/
|
||||
|
||||
#define FC_CMD_FC_CMD_POSS 0U
|
||||
#define FC_CMD_FC_CMD_POSE 7U
|
||||
#define FC_CMD_FC_CMD_MSK BITS(FC_CMD_FC_CMD_POSS,FC_CMD_FC_CMD_POSE)
|
||||
|
||||
/****************** Bit definition for FC_PA register ************************/
|
||||
|
||||
#define FC_PA_PCNT_POSS 25U
|
||||
#define FC_PA_PCNT_POSE 31U
|
||||
#define FC_PA_PCNT_MSK BITS(FC_PA_PCNT_POSS,FC_PA_PCNT_POSE)
|
||||
|
||||
#define FC_PA_IFREN_POS 24U
|
||||
#define FC_PA_IFREN_MSK BIT(FC_PA_IFREN_POS)
|
||||
|
||||
#define FC_PA_PROG_ADDR_POSS 0U
|
||||
#define FC_PA_PROG_ADDR_POSE 23U
|
||||
#define FC_PA_PROG_ADDR_MSK BITS(FC_PA_PROG_ADDR_POSS,FC_PA_PROG_ADDR_POSE)
|
||||
|
||||
/****************** Bit definition for FC_PLD register ************************/
|
||||
|
||||
#define FC_PLD_PROG_DATA_L_POSS 0U
|
||||
#define FC_PLD_PROG_DATA_L_POSE 31U
|
||||
#define FC_PLD_PROG_DATA_L_MSK BITS(FC_PLD_PROG_DATA_L_POSS,FC_PLD_PROG_DATA_L_POSE)
|
||||
|
||||
/****************** Bit definition for FC_PHD register ************************/
|
||||
|
||||
#define FC_PHD_PROG_DATA_H_POSS 0U
|
||||
#define FC_PHD_PROG_DATA_H_POSE 31U
|
||||
#define FC_PHD_PROG_DATA_H_MSK BITS(FC_PHD_PROG_DATA_H_POSS,FC_PHD_PROG_DATA_H_POSE)
|
||||
|
||||
/****************** Bit definition for FC_CON register ************************/
|
||||
|
||||
#define FC_CON_SLEEP_POS 9U
|
||||
#define FC_CON_SLEEP_MSK BIT(FC_CON_SLEEP_POS)
|
||||
|
||||
#define FC_CON_PFEN_POS 8U
|
||||
#define FC_CON_PFEN_MSK BIT(FC_CON_PFEN_POS)
|
||||
|
||||
#define FC_CON_WAIT_POSS 0U
|
||||
#define FC_CON_WAIT_POSE 1U
|
||||
#define FC_CON_WAIT_MSK BITS(FC_CON_WAIT_POSS,FC_CON_WAIT_POSE)
|
||||
|
||||
/****************** Bit definition for FC_STAT register ************************/
|
||||
|
||||
#define FC_STAT_OPVD_POS 2U
|
||||
#define FC_STAT_OPVD_MSK BIT(FC_STAT_OPVD_POS)
|
||||
|
||||
#define FC_STAT_MUNP2_POS 1U
|
||||
#define FC_STAT_MUNP2_MSK BIT(FC_STAT_MUNP2_POS)
|
||||
|
||||
#define FC_STAT_MUNP1_POS 0U
|
||||
#define FC_STAT_MUNP1_MSK BIT(FC_STAT_MUNP1_POS)
|
||||
|
||||
/****************** Bit definition for FC_UPL register ************************/
|
||||
|
||||
#define FC_UPL_UPL_POSS 0U
|
||||
#define FC_UPL_UPL_POSE 31U
|
||||
#define FC_UPL_UPL_MSK BITS(FC_UPL_UPL_POSS,FC_UPL_UPL_POSE)
|
||||
|
||||
/****************** Bit definition for FC_UPH register ************************/
|
||||
|
||||
#define FC_UPH_UPH_POSS 0U
|
||||
#define FC_UPH_UPH_POSE 31U
|
||||
#define FC_UPH_UPH_MSK BITS(FC_UPH_UPH_POSS,FC_UPH_UPH_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_TRIM register ************************/
|
||||
|
||||
#define FC_OP_TRIM_BGTRIMVD_POSS 24U
|
||||
#define FC_OP_TRIM_BGTRIMVD_POSE 31U
|
||||
#define FC_OP_TRIM_BGTRIMVD_MSK BITS(FC_OP_TRIM_BGTRIMVD_POSS,FC_OP_TRIM_BGTRIMVD_POSE)
|
||||
|
||||
#define FC_OP_TRIM_BGTRIM_POSS 16U
|
||||
#define FC_OP_TRIM_BGTRIM_POSE 23U
|
||||
#define FC_OP_TRIM_BGTRIM_MSK BITS(FC_OP_TRIM_BGTRIM_POSS,FC_OP_TRIM_BGTRIM_POSE)
|
||||
|
||||
#define FC_OP_TRIM_HRCTRIMVD_POSS 8U
|
||||
#define FC_OP_TRIM_HRCTRIMVD_POSE 15U
|
||||
#define FC_OP_TRIM_HRCTRIMVD_MSK BITS(FC_OP_TRIM_HRCTRIMVD_POSS,FC_OP_TRIM_HRCTRIMVD_POSE)
|
||||
|
||||
#define FC_OP_TRIM_HRCTRIM_POSS 0U
|
||||
#define FC_OP_TRIM_HRCTRIM_POSE 7U
|
||||
#define FC_OP_TRIM_HRCTRIM_MSK BITS(FC_OP_TRIM_HRCTRIM_POSS,FC_OP_TRIM_HRCTRIM_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_PRT2L register ************************/
|
||||
|
||||
#define FC_OP_PRT2L_PRTLV2L_POSS 0U
|
||||
#define FC_OP_PRT2L_PRTLV2L_POSE 31U
|
||||
#define FC_OP_PRT2L_PRTLV2L_MSK BITS(FC_OP_PRT2L_PRTLV2L_POSS,FC_OP_PRT2L_PRTLV2L_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_PRT2H register ************************/
|
||||
|
||||
#define FC_OP_PRT2H_PRTLV2H_POSS 0U
|
||||
#define FC_OP_PRT2H_PRTLV2H_POSE 31U
|
||||
#define FC_OP_PRT2H_PRTLV2H_MSK BITS(FC_OP_PRT2H_PRTLV2H_POSS,FC_OP_PRT2H_PRTLV2H_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_PRT1L register ************************/
|
||||
|
||||
#define FC_OP_PRT1L_PRTLV1L_POSS 0U
|
||||
#define FC_OP_PRT1L_PRTLV1L_POSE 31U
|
||||
#define FC_OP_PRT1L_PRTLV1L_MSK BITS(FC_OP_PRT1L_PRTLV1L_POSS,FC_OP_PRT1L_PRTLV1L_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_PRT1H register ************************/
|
||||
|
||||
#define FC_OP_PRT1H_PRTLV1H_POSS 0U
|
||||
#define FC_OP_PRT1H_PRTLV1H_POSE 31U
|
||||
#define FC_OP_PRT1H_PRTLV1H_MSK BITS(FC_OP_PRT1H_PRTLV1H_POSS,FC_OP_PRT1H_PRTLV1H_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_REMAP register ************************/
|
||||
|
||||
#define FC_OP_REMAP_HREMAP_POSS 8U
|
||||
#define FC_OP_REMAP_HREMAP_POSE 15U
|
||||
#define FC_OP_REMAP_HREMAP_MSK BITS(FC_OP_REMAP_HREMAP_POSS,FC_OP_REMAP_HREMAP_POSE)
|
||||
|
||||
#define FC_OP_REMAP_SREMAP_POSS 4U
|
||||
#define FC_OP_REMAP_SREMAP_POSE 5U
|
||||
#define FC_OP_REMAP_SREMAP_MSK BITS(FC_OP_REMAP_SREMAP_POSS,FC_OP_REMAP_SREMAP_POSE)
|
||||
|
||||
#define FC_OP_REMAP_SEFBASE_POSS 0U
|
||||
#define FC_OP_REMAP_SEFBASE_POSE 3U
|
||||
#define FC_OP_REMAP_SEFBASE_MSK BITS(FC_OP_REMAP_SEFBASE_POSS,FC_OP_REMAP_SEFBASE_POSE)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CMD;
|
||||
__IO uint32_t PA;
|
||||
__IO uint32_t PLD;
|
||||
__IO uint32_t PHD;
|
||||
__IO uint32_t CON;
|
||||
__I uint32_t STAT;
|
||||
uint32_t RESERVED0[2] ;
|
||||
__IO uint32_t UPL;
|
||||
__IO uint32_t UPH;
|
||||
uint32_t RESERVED1[2] ;
|
||||
__I uint32_t OP_TRIM;
|
||||
uint32_t RESERVED2[4] ;
|
||||
// uint32_t ADCTRIM_1V;
|
||||
// uint32_t ADCTRIM_2V;
|
||||
// uint32_t RESERVED3;
|
||||
|
||||
uint32_t ADCTRIM_VDD5V_VREF5V;
|
||||
uint32_t ADCTRIM_VDD3V3_VREF3V3;
|
||||
uint32_t ADCTRIM_VDD5V_VREF2V5;
|
||||
__I uint32_t OP_PRT2L;
|
||||
__I uint32_t OP_PRT2H;
|
||||
__I uint32_t OP_PRT1L;
|
||||
__I uint32_t OP_PRT1H;
|
||||
__I uint32_t OP_REMAP;
|
||||
} FC_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-710
File diff suppressed because it is too large
Load Diff
-75
@@ -1,75 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_HDIV.h
|
||||
* @brief HDIV Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 12/3/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __hdiv_H__
|
||||
#define __hdiv_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for HDIV_DIVDR register ************************/
|
||||
|
||||
#define HDIV_DIVDR_DIVS_POSS 0U
|
||||
#define HDIV_DIVDR_DIVS_POSE 31U
|
||||
#define HDIV_DIVDR_DIVD_MSK BITS(HDIV_DIVDR_DIVD_POSS,HDIV_DIVDR_DIVD_POSE)
|
||||
|
||||
/****************** Bit definition for HDIV_DIVSR register ************************/
|
||||
|
||||
#define HDIV_DIVSR_DIVS_POSS 0U
|
||||
#define HDIV_DIVSR_DIVS_POSE 31U
|
||||
#define HDIV_DIVSR_DIVS_MSK BITS(HDIV_DIVSR_DIVS_POSS,HDIV_DIVSR_DIVS_POSE)
|
||||
|
||||
/****************** Bit definition for HDIV_DIVQR register ************************/
|
||||
|
||||
#define HDIV_DIVQR_DIVQ_POSS 0U
|
||||
#define HDIV_DIVQR_DIVQ_POSE 31U
|
||||
#define HDIV_DIVQR_DIVQ_MSK BITS(HDIV_DIVQR_DIVQ_POSS,HDIV_DIVQR_DIVQ_POSE)
|
||||
|
||||
/****************** Bit definition for HDIV_DIVRR register ************************/
|
||||
|
||||
#define HDIV_DIVRR_DIVR_POSS 0U
|
||||
#define HDIV_DIVRR_DIVR_POSE 31U
|
||||
#define HDIV_DIVRR_DIVR_MSK BITS(HDIV_DIVRR_DIVR_POSS,HDIV_DIVRR_DIVR_POSE)
|
||||
|
||||
/****************** Bit definition for HDIV_DIVSTAT register ************************/
|
||||
|
||||
#define HDIV_DIVSTAT_SIGN_POS 2U
|
||||
#define HDIV_DIVSTAT_SIGN_MSK BIT(HDIV_DIVSTAT_SIGN_POS)
|
||||
|
||||
#define HDIV_DIVSTAT_DIV0_POS 1U
|
||||
#define HDIV_DIVSTAT_DIV0_MSK BIT(HDIV_DIVSTAT_DIV0_POS)
|
||||
|
||||
#define HDIV_DIVSTAT_BUSY_POS 0U
|
||||
#define HDIV_DIVSTAT_BUSY_MSK BIT(HDIV_DIVSTAT_BUSY_POS)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t DIVDR;
|
||||
__IO uint32_t DIVSR;
|
||||
__I uint32_t DIVQR;
|
||||
__I uint32_t DIVRR;
|
||||
__I uint32_t DIVSTAT;
|
||||
} HDIV_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-623
File diff suppressed because it is too large
Load Diff
-73
@@ -1,73 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file reg_IWDG.h
|
||||
* @brief IWDG Head File
|
||||
*
|
||||
* @version V1.00.01
|
||||
* @data 19/10/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __IWDG_H__
|
||||
#define __IWDG_H__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t KR ; /* 0x00 IWDG_KR - Key register */
|
||||
__IO uint32_t PR ; /* 0x04 IWDG_PR - Prescaler register */
|
||||
__IO uint32_t RLR ; /* 0x08 IWDG_RLR - Reload register */
|
||||
__I uint32_t FR ; /* 0x0C IWDG_SR - Status register */
|
||||
__IO uint32_t WINR; /* 0x10 IWDG_WINR - Window register */
|
||||
} IWDG_TypeDef;
|
||||
|
||||
/******************************************************************************/
|
||||
/* ¼È¦s¾¹¤º³¡¦ì¤¸©w¸q */
|
||||
/******************************************************************************/
|
||||
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for IWDG_KR register ************************/
|
||||
|
||||
#define IWDG_KR_KEY_POSS 0U
|
||||
#define IWDG_KR_KEY_POSE 15U
|
||||
#define IWDG_KR_KEY_MSK BITS(IWDG_KR_KEY_POSS,IWDG_KR_KEY_POSE)
|
||||
|
||||
/****************** Bit definition for IWDG_PR register ************************/
|
||||
|
||||
#define IWDG_PR_PR_POSS 0U
|
||||
#define IWDG_PR_PR_POSE 2U
|
||||
#define IWDG_PR_PR_MSK BITS(IWDG_PR_PR_POSS,IWDG_PR_PR_POSE)
|
||||
|
||||
/****************** Bit definition for IWDG_RLR register ************************/
|
||||
|
||||
#define IWDG_RLR_RL_POSS 0U
|
||||
#define IWDG_RLR_RL_POSE 12U
|
||||
#define IWDG_RLR_RL_MSK BITS(IWDG_RLR_RL_POSS,IWDG_RLR_RL_POSE)
|
||||
|
||||
/****************** Bit definition for IWDG_FR register ************************/
|
||||
|
||||
#define IWDG_FR_BUSY_POS 15U
|
||||
#define IWDG_FR_BUSY_MSK BIT(IWDG_FR_BUSY_POS)
|
||||
|
||||
#define IWDG_FR_STR_POS 12U
|
||||
#define IWDG_FR_STR_MSK BIT(IWDG_FR_STR_POS)
|
||||
|
||||
#define IWDG_FR_CNT_POSS 0U
|
||||
#define IWDG_FR_CNT_POSE 11U
|
||||
#define IWDG_FR_CNT_MSK BITS(IWDG_FR_CNT_POSS,IWDG_FR_CNT_POSE)
|
||||
|
||||
/****************** Bit definition for IWDG_WINR register ************************/
|
||||
|
||||
#define IWDG_WINR_WIN_POSS 0U
|
||||
#define IWDG_WINR_WIN_POSE 31U
|
||||
#define IWDG_WINR_WIN_MSK BITS(IWDG_WINR_WIN_POSS,IWDG_WINR_WIN_POSE)
|
||||
|
||||
|
||||
#else
|
||||
/* */
|
||||
#endif
|
||||
-211
@@ -1,211 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file reg_MCM.h
|
||||
* @brief MCM Head File
|
||||
*
|
||||
* @version V1.00.01
|
||||
* @data 19/10/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __MCM_H__
|
||||
#define __MCM_H__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t RAMP_INI; // 0x00 MCM Ramp Generator Initialization Register
|
||||
__IO uint32_t RAMP_IDATA; // 0x04 MCM Ramp Generator Initial Data Register
|
||||
__IO uint32_t RAMP_DIV; // 0x08 MCM Ramp Clock Divider Register
|
||||
__IO uint32_t RAMP_SCALE; // 0x0C MCM Ramp Generator Output Scale Register
|
||||
__IO uint32_t RAMP_STEP; // 0x10 MCM Step Increment of the Ramp Output Register
|
||||
__IO uint32_t RAMP_SET; // 0x14 MCM Ramp Generator Reference Data Register
|
||||
__IO uint32_t RAMP_EN; // 0x18 MCM Ramp Generator Enable Register
|
||||
__I uint32_t RAMP_DO; // 0x1C MCM Ramp Generator Output Register
|
||||
__IO uint32_t RMAP_CON; // 0x20 MCM Connect Ramp Generator to PI control Register
|
||||
__IO uint32_t IX_UPD; // 0x24 MCM Inverse Transform Update Register
|
||||
__IO uint32_t IX_VQ; // 0x28 MCM Inverse Park Transform Vq Input Register
|
||||
__IO uint32_t IX_VD; // 0x2C MCM Inverse Park Transform Vd Input Register
|
||||
__I uint32_t IX_VA; // 0x30 MCM Inverse Clarke Transform Va Output Register
|
||||
__I uint32_t IX_VB; // 0x34 MCM Inverse Clarke Transform Vb Output Register
|
||||
__I uint32_t IX_VC; // 0x38 MCM Inverse Clarke Transform Vc Output Register
|
||||
__I uint32_t IX_VALPHA; // 0x3C MCM Inverse Clarke Transform Valpha Output Register
|
||||
__I uint32_t IX_VBETA; // 0x40 MCM Inverse Clarke Transform Vbeta Output Register
|
||||
__I uint32_t IX_SVMVA; // 0x44 MCM Inverse Clarke Transform SVPWM Va Output Register
|
||||
__I uint32_t IX_SVMVB; // 0x48 MCM Inverse Clarke Transform SVPWM Vb Output Register
|
||||
__I uint32_t IX_SVMVC; // 0x4C MCM Inverse Clarke Transform SVPWM Vc Output Register
|
||||
__I uint32_t IX_DONE; // 0x50 MCM Inverse Transform Processing Status Register
|
||||
__I uint32_t IX_SDONE; // 0x54 MCM Inverse SVPWM Process Status Register
|
||||
__IO uint32_t IX_CON; // 0x58 MCM Connect PI Control To The Inverse Transform Register
|
||||
__IO uint32_t IX_NORMAL; // 0x5C MCM Normal Clarke Inverse Transform Register
|
||||
__IO uint32_t X_UPD; // 0x60 MCM Transform Function Update Register
|
||||
__IO uint32_t X_IA; // 0x64 MCM Clarke Transform Ia Input Register
|
||||
__IO uint32_t X_IB; // 0x68 MCM Clarke Transform Ib Input Register
|
||||
__IO uint32_t X_IC; // 0x6C MCM Clarke Transform Ic Input Register
|
||||
__I uint32_t X_IALPHA; // 0x70 MCM Clarke Transform Ialpha Output Register
|
||||
__I uint32_t X_IBETA; // 0x74 MCM Clarke Transform Ibeta Output Register
|
||||
__I uint32_t X_ID; // 0x78 MCM Park Transform Id Output Register
|
||||
__I uint32_t X_IQ; // 0x7C MCM Park Transform Iq Output Register
|
||||
__I uint32_t X_DONE; // 0x80 MCM Transform Process Status Register
|
||||
__IO uint32_t X_CON; // 0x84 MCM Forward Transform Input Source Selection Register
|
||||
uint32_t REV88; // 0x88 RESERVED
|
||||
__IO uint32_t PI0_UPD; // 0x8C MCM PI Control 0 Update Register
|
||||
__IO uint32_t PI0_INI; // 0x90 MCM Initialize PI Control 0 Register
|
||||
__IO uint32_t PI0_IDATA; // 0x94 MCM PI Control 0 Initial Data Register
|
||||
__IO uint32_t PI0_ELIMIT; // 0x98 MCM PI Control 0 Error Limit Register
|
||||
__IO uint32_t PI0_KP; // 0x9C MCM PI Control 0 Kp Coefficient Register
|
||||
__IO uint32_t PI0_KI; // 0xA0 MCM PI Control 0 Ki Coefficient Register
|
||||
__IO uint32_t PI0_REF; // 0xA4 MCM PI Control 0 Reference Value Register
|
||||
__IO uint32_t PI0_ACTUAL; // 0xA8 MCM PI Control 0 Actual Value Register
|
||||
__IO uint32_t PI0_MIN; // 0xAC MCM PI Control 0 Minimum Output Register
|
||||
__IO uint32_t PI0_MAX; // 0xB0 MCM PI Control 0 Maximum Output Register
|
||||
__I uint32_t PI0_DO; // 0xB4 MCM PI Control 0 Data Out Register
|
||||
__IO uint32_t PI0_OSCALE; // 0xB8 MCM PI Control 0 Data Output Scale Register
|
||||
__I uint32_t PI_DONE; // 0xBC MCM PI Control Processing Status Register
|
||||
__IO uint32_t PI1_UPD; // 0xC0 MCM PI Control 1 Update Register
|
||||
__IO uint32_t PI1_INI; // 0xC4 MCM Initialize PI Control 1 Register
|
||||
__IO uint32_t PI1_IDATA; // 0xC8 MCM PI Control 1 Initial Data Register
|
||||
__IO uint32_t PI1_ELIMIT; // 0xCC MCM PI Control 1 Error Limit Register
|
||||
__IO uint32_t PI1_KP; // 0xD0 MCM PI Control 1 Kp Coefficient Register
|
||||
__IO uint32_t PI1_KI; // 0xD4 MCM PI Control 1 Ki Coefficient Register
|
||||
__IO uint32_t PI1_REF; // 0xD8 MCM PI Control 1 Reference Value Register
|
||||
__IO uint32_t PI1_ACTUAL; // 0xDC MCM PI Control 1 Actual Value Register
|
||||
__IO uint32_t PI1_MIN; // 0xE0 MCM PI Control 1 Minimum Output Register
|
||||
__IO uint32_t PI1_MAX; // 0xE4 MCM PI Control 1 Maximum Output Register
|
||||
__I uint32_t PI1_DO; // 0xE8 MCM PI Control 1 Data Out Register
|
||||
__IO uint32_t PI1_OSCALE; // 0xEC MCM PI Control 1 Data Output Scale Register
|
||||
__IO uint32_t PI2_UPD; // 0xF0 MCM PI Control 2 Update Register
|
||||
__IO uint32_t PI2_INI; // 0xF4 MCM Initialize PI Control 2 Register
|
||||
__IO uint32_t PI2_IDATA; // 0xF8 MCM PI Control 2 Initial Data Register
|
||||
__IO uint32_t PI2_ELIMIT; // 0xFC MCM PI Control 2 Error Limit Register
|
||||
__IO uint32_t PI2_KP; // 0x100 MCM PI Control 2 Kp Coefficient Register
|
||||
__IO uint32_t PI2_KI; // 0x104 MCM PI Control 2 Ki Coefficient Register
|
||||
__IO uint32_t PI2_REF; // 0x108 MCM PI Control 2 Reference Value Register
|
||||
__IO uint32_t PI2_ACTUAL; // 0x10C MCM PI Control 2 Actual Value Register
|
||||
__IO uint32_t PI2_MIN; // 0x110 MCM PI Control 2 Minimum Output Register
|
||||
__IO uint32_t PI2_MAX; // 0x114 MCM PI Control 2 Maximum Output Register
|
||||
__I uint32_t PI2_DO; // 0x118 MCM PI Control 2 Data Out Register
|
||||
__IO uint32_t PI2_OSCALE; // 0x11C MCM PI Control 2 Data Output Scale Register
|
||||
__IO uint32_t COR_START; // 0x120 MCM Start CORDIC Calculation Register
|
||||
__IO uint32_t COR_X; // 0x124 MCM CORDIC X Input Register
|
||||
__IO uint32_t COR_Y; // 0x128 MCM CORDIC Y Input Register
|
||||
__I uint32_t COR_RES; // 0x12C MCM CORDIC Result Register
|
||||
__I uint32_t COR_DONE; // 0x130 MCM CORDIC Processing Status Register
|
||||
__IO uint32_t COR_CON; // 0x134 MCM CORDIC Input Selection Register
|
||||
uint32_t REV138; // 0x138 RESERVED
|
||||
uint32_t REV13C; // 0x13C RESERVED
|
||||
__IO uint32_t LPFA_INI; // 0x140 MCM LPF A Channel Initialize Register
|
||||
__IO uint32_t LPFA_UPD; // 0x144 MCM LPF A Channel Update Register
|
||||
__IO uint32_t LPFA_DIN; // 0x148 MCM LPF A Input Register
|
||||
__IO uint32_t LPFA_A0; // 0x14C MCM LPF A a0 Coefficient Register
|
||||
__IO uint32_t LPFA_B0; // 0x150 MCM LPF A b0 Coefficient Register
|
||||
__IO uint32_t LPFA_B1; // 0x154 MCM LPF A b1 Coefficient Register
|
||||
|
||||
__IO uint32_t LPFA_A0SCALE; // 0x158 MCM LPF A a0 Coefficient Scale Register
|
||||
__IO uint32_t LPFA_B0SCALE; // 0x15C MCM LPF A b0 Coefficient Scale Register
|
||||
__IO uint32_t LPFA_B1SCALE; // 0x160 MCM LPF A b1 Coefficient Scale Register
|
||||
|
||||
__I uint32_t LPFA_DO; // 0x164 MCM LPF A Data Output Register
|
||||
__I uint32_t LPFA_DONE; // 0x168 MCM LPF A Process Status Register
|
||||
__IO uint32_t LPFB_INI; // 0x16C MCM LPF B Channel Initialize Register
|
||||
__IO uint32_t LPFB_UPD; // 0x170 MCM LPF B Channel Update Register
|
||||
__IO uint32_t LPFB_DIN; // 0x174 MCM LPF B Input Register
|
||||
__IO uint32_t LPFB_A0; // 0x178 MCM LPF B a0 Coefficient Register
|
||||
__IO uint32_t LPFB_B0; // 0x17C MCM LPF B b0 Coefficient Register
|
||||
__IO uint32_t LPFB_B1; // 0x180 MCM LPF B b1 Coefficient Register
|
||||
|
||||
__IO uint32_t LPFB_A0SCALE; // 0x184 MCM LPF B a0 Coefficient Scale Register
|
||||
__IO uint32_t LPFB_B0SCALE; // 0x188 MCM LPF B b0 Coefficient Scale Register
|
||||
__IO uint32_t LPFB_B1SCALE; // 0x18C MCM LPF B b1 Coefficient Scale Register
|
||||
|
||||
__I uint32_t LPFB_DO; // 0x190 MCM LPF B Data Output Register
|
||||
__I uint32_t LPFB_DONE; // 0x194 MCM LPF B Process Status Register
|
||||
__IO uint32_t LPFC_INI; // 0x198 MCM LPF C Channel Initialize Register
|
||||
__IO uint32_t LPFC_UPD; // 0x19C MCM LPF C Channel Update Register
|
||||
__IO uint32_t LPFC_DIN; // 0x1A0 MCM LPF C Input Register
|
||||
__IO uint32_t LPFC_A0; // 0x1A4 MCM LPF C a0 Coefficient Register
|
||||
__IO uint32_t LPFC_B0; // 0x1A8 MCM LPF C b0 Coefficient Register
|
||||
__IO uint32_t LPFC_B1; // 0x1AC MCM LPF C b1 Coefficient Register
|
||||
|
||||
__IO uint32_t LPFC_A0SCALE; // 0x1B0 MCM LPF C a0 Coefficient Scale Register
|
||||
__IO uint32_t LPFC_B0SCALE; // 0x1B4 MCM LPF C b0 Coefficient Scale Register
|
||||
__IO uint32_t LPFC_B1SCALE; // 0x1B8 MCM LPF C b1 Coefficient Scale Register
|
||||
|
||||
__I uint32_t LPFC_DO; // 0x1BC MCM LPF C Data Output Register
|
||||
__I uint32_t LPFC_DONE; // 0x1C0 MCM LPF C Process Status Register
|
||||
__IO uint32_t GL_UPD; // 0x1C4 MCM Global Update Register
|
||||
__IO uint32_t GL_STAT; // 0x1C8 MCM Global Status Register
|
||||
__IO uint32_t THETA_SIN; // 0x1CC MCM Sine Angle Register
|
||||
__IO uint32_t THETA_COS; // 0x1D0 MCM Cosine Angle Register
|
||||
__IO uint32_t PI_TYPE; // 0x1D4 MCM PI Control Type Register
|
||||
__IO uint32_t MOTOR_DIR; // 0x1D8 MCM Motor Direction Register
|
||||
__I uint32_t MCM_VER; // 0x1DC MCM Version Register
|
||||
__IO uint32_t SMC_UPD; // 0x1E0 MCM Slide Mode Controller Update Register
|
||||
__IO uint32_t SMC_INI; // 0x1E4 MCM Slide Mode Controller Initialization Register
|
||||
__IO uint32_t SMC_ALPHAINI; // 0x1E8 MCM Slide Mode Controller Alpha Initial Data Register
|
||||
__IO uint32_t SMC_BETAINI; // 0x1EC MCM Slide Mode Controller Beta Initial Data Register
|
||||
__IO uint32_t SMC_A0; // 0x1F0 MCM Slide Mode Controller Dynamic LPF coefficient Register
|
||||
__IO uint32_t SMC_ELIMIT; // 0x1F4 MCM Slide Mode Controller Error Limit Register
|
||||
__IO uint32_t SMC_KSLIDE; // 0x1F8 MCM Slide Mode Controller Z Factor Error Amplification Register
|
||||
__I uint32_t SMC_DONE; // 0x1FC MCM Slide Mode Controller Process Status Register
|
||||
__IO uint32_t SMC_IEALPHA; // 0x200 MCM SMC Estimated Current Alpha Register
|
||||
__IO uint32_t SMC_IEBETA; // 0x204 MCM SMC Estimated Current Beta Register
|
||||
__IO uint32_t SMC_IALPHA; // 0x208 MCM SMC Measured Current Alpha Register
|
||||
__IO uint32_t SMC_IBETA; // 0x20C MCM SMC Measured Current Beta Register
|
||||
__IO uint32_t SMC_DISI; // 0x210 MCM SMC Estimated Current Input Selection Register
|
||||
__I uint32_t SMC_ZALPHA; // 0x214 MCM SMC Z Factor Alpha Register
|
||||
__I uint32_t SMC_ZBETA; // 0x218 MCM SMC Z Factor Beta Register
|
||||
__I uint32_t SMC_BEMF1A; // 0x21C MCM SMC Estimated BEMF Alpha Register
|
||||
__I uint32_t SMC_BEMF1B; // 0x220 MCM SMC Estimated BEMF Beta Register
|
||||
__I uint32_t SMC_BEMF2A; // 0x224 MCM SMC BEMF Filtered Alpha Register
|
||||
__I uint32_t SMC_BEMF2B; // 0x228 MCM SMC BEMF Filtered Beta Register
|
||||
__IO uint32_t SMC_LPFSCALE; // 0x22C MCM SMC LPF Coefficient Scale Factor Register
|
||||
uint32_t REV230; // 0x230 RESERVED
|
||||
__IO uint32_t VM_UPD; // 0x234 MCM Virtual Motor Update Register
|
||||
__IO uint32_t VM_INI; // 0x238 MCM Virtual Motor Initialization Register
|
||||
__IO uint32_t VM_ALPHAINI; // 0x23C MCM Virtual Motor Initial Data Alpha Register
|
||||
__IO uint32_t VM_BETAINI; // 0x240 MCM Virtual Motor Initial Data Beta Register
|
||||
__IO uint32_t VM_KF; // 0x244 MCM Virtual Motor F Constant Register
|
||||
__IO uint32_t VM_KG; // 0x248 MCM Virtual Motor G Constant Register
|
||||
__IO uint32_t VM_VALPHA; // 0x24C MCM Virtual Motor Voltage Vector Alpha Register
|
||||
__IO uint32_t VM_VBETA; // 0x250 MCM Virtual Motor Voltage Vector BETA Register
|
||||
__IO uint32_t VM_BEMFA; // 0x254 MCM Virtual Motor BEMF Vector Alpha Register
|
||||
__IO uint32_t VM_BEMFB; // 0x258 MCM Virtual Motor BEMF Vector BETA Register
|
||||
__IO uint32_t VM_ZALPHA; // 0x25C MCM Virtual Motor Z Vector Alpha Register
|
||||
__IO uint32_t VM_ZBETA; // 0x260 MCM Virtual Motor Z Vector BETA Register
|
||||
__IO uint32_t VM_DISZ; // 0x264 MCM Virtual Motor Z Factor Input Selection Register
|
||||
__I uint32_t VM_DONE; // 0x268 MCM Virtual Motor Process Status Register
|
||||
__I uint32_t VM_IEALPHA; // 0x26C MCM Virtual Motor Estimated IS Result Alpha Register
|
||||
__I uint32_t VM_IEBETA; // 0x270 MCM Virtual Motor Estimated IS Result BETA Register
|
||||
__IO uint32_t VM_CON; // 0x274 MCM Virtual Motor Connect Register
|
||||
|
||||
__IO uint32_t VM_KFSCALE; // 0x278 MCM Virtual Motor F Constant Scale Register
|
||||
__IO uint32_t VM_KGSCALE; // 0x27C MCM Virtual Motor G Constant Scale Register
|
||||
__IO uint32_t VM_CONVS; // 0x280 MCM Virtual Motor Voltage Connect Register
|
||||
|
||||
uint32_t REV284; // 0x284 RESERVED
|
||||
__IO uint32_t SVM_UPD; // 0x288 MCM SVM Update Register
|
||||
__IO uint32_t SVM_CON; // 0x28C MCM SVM Source Input Select Register
|
||||
__IO uint32_t SVM_DINA; // 0x290 MCM SVM Phase A Register
|
||||
__IO uint32_t SVM_DINB; // 0x294 MCM SVM Phase B Register
|
||||
__IO uint32_t SVM_DINC; // 0x298 MCM SVM Phase C Register
|
||||
} MCM_TypeDef;
|
||||
|
||||
/******************************************************************************/
|
||||
/* ¼È¦s¾¹¤º³¡¦ì¤¸©w¸q */
|
||||
/******************************************************************************/
|
||||
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for WWDG_CR register ************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#else
|
||||
/* */
|
||||
#endif
|
||||
-58
@@ -1,58 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file reg_MSWD.h
|
||||
* @brief WWDG Head File
|
||||
*
|
||||
* @version V1.00.01
|
||||
* @data 19/10/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __MSWD_H__
|
||||
#define __MSWD_H__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFG; // 0x00 SW_CFG Serial Wire Configure Register
|
||||
__IO uint32_t JTAG2SWD; // 0x04 SW_JTAG2SW Serial Wire JTAG2SWD Register
|
||||
__IO uint32_t LINERESET; // 0x08 SW_LINERESET Serial Wire LINERESET Resister
|
||||
__O uint32_t STS; // 0x0C SW_STS Serial Wire STATUS Register
|
||||
__IO uint32_t DP_IDR_ABORT; // 0x10 SW_DP_IDR_ABORT Serial Wire DP R-IDR W-ABORT Register
|
||||
__IO uint32_t DP_CSR_WCR; // 0x14 SW_DP_CSR_WCR Serial Wire DP R-CSR W-WCR Register
|
||||
__IO uint32_t DP_RESEND_SELECT; // 0x18 SW_DP_RESEND_SELECT Serial Wire DP R-RESEND W-SELECT Register
|
||||
__IO uint32_t DP_RDBUF_ROUTESEL; // 0x1C SW_DP_RDBUF_ROUTESEL Serial Wire DP R-RDBUF W-ROUTESEL Register
|
||||
__IO uint32_t AP_CSW; // 0x20 SW_AP_CSW Serial Wire AP CSW Register
|
||||
__IO uint32_t AP_TAR; // 0x24 SW_AP_TAR Serial Wire AP TAR Register
|
||||
__IO uint32_t AP_DRW; // 0x28 SW_AP_DRW Serial Wire AP DRW Register
|
||||
__IO uint32_t AP_BD0; // 0x2C SW_AP_BD0 Serial Wire AP BD0 Register
|
||||
__IO uint32_t AP_BD1; // 0x30 SW_AP_BD1 Serial Wire AP BD1 Register
|
||||
__IO uint32_t AP_BD2; // 0x34 SW_AP_BD2 Serial Wire AP BD2 Register
|
||||
__IO uint32_t AP_BD3; // 0x38 SW_AP_BD3 Serial Wire AP BD3 Register
|
||||
__IO uint32_t AP_CFG; // 0x3C SW_AP_CFG Serial Wire AP CFG Register
|
||||
__IO uint32_t AP_BASE; // 0x40 SW_AP_BASE Serial Wire AP BASE Register
|
||||
__IO uint32_t AP_IDR; // 0x44 SW_AP_IDR Serial Wire AP IDR Register
|
||||
uint32_t RES0; // 0x48
|
||||
uint32_t RES1; // 0x4C
|
||||
__IO uint32_t ISP_CMD; // 0x50 SW_ISP_CMD Serial Wire ISP Command Register
|
||||
__IO uint32_t ISP_DAT; // 0x54 SW_ISP_DAT Serial Wire ISP Data Register
|
||||
} MSWD_TypeDef;
|
||||
|
||||
/******************************************************************************/
|
||||
/* ¼È¦s¾¹¤º³¡¦ì¤¸©w¸q */
|
||||
/******************************************************************************/
|
||||
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for WWDG_CR register ************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#else
|
||||
/* */
|
||||
#endif
|
||||
-585
File diff suppressed because it is too large
Load Diff
-613
File diff suppressed because it is too large
Load Diff
-444
@@ -1,444 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_SPI.h
|
||||
* @brief SPI Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 12/3/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __SPI_H__
|
||||
#define __SPI_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for SPI_CON1 register ************************/
|
||||
|
||||
#define SPI_CON1_BIDEN_POS 15U
|
||||
#define SPI_CON1_BIDEN_MSK BIT(SPI_CON1_BIDEN_POS)
|
||||
|
||||
#define SPI_CON1_BIDOEN_POS 14U
|
||||
#define SPI_CON1_BIDOEN_MSK BIT(SPI_CON1_BIDOEN_POS)
|
||||
|
||||
#define SPI_CON1_CRCEN_POS 13U
|
||||
#define SPI_CON1_CRCEN_MSK BIT(SPI_CON1_CRCEN_POS)
|
||||
|
||||
#define SPI_CON1_NXTCRC_POS 12U
|
||||
#define SPI_CON1_NXTCRC_MSK BIT(SPI_CON1_NXTCRC_POS)
|
||||
|
||||
#define SPI_CON1_FLEN_POS 11U
|
||||
#define SPI_CON1_FLEN_MSK BIT(SPI_CON1_FLEN_POS)
|
||||
|
||||
#define SPI_CON1_RXO_POS 10U
|
||||
#define SPI_CON1_RXO_MSK BIT(SPI_CON1_RXO_POS)
|
||||
|
||||
#define SPI_CON1_SSEN_POS 9U
|
||||
#define SPI_CON1_SSEN_MSK BIT(SPI_CON1_SSEN_POS)
|
||||
|
||||
#define SPI_CON1_SSOUT_POS 8U
|
||||
#define SPI_CON1_SSOUT_MSK BIT(SPI_CON1_SSOUT_POS)
|
||||
|
||||
#define SPI_CON1_LSBFST_POS 7U
|
||||
#define SPI_CON1_LSBFST_MSK BIT(SPI_CON1_LSBFST_POS)
|
||||
|
||||
#define SPI_CON1_SPIEN_POS 6U
|
||||
#define SPI_CON1_SPIEN_MSK BIT(SPI_CON1_SPIEN_POS)
|
||||
|
||||
#define SPI_CON1_BAUD_POSS 3U
|
||||
#define SPI_CON1_BAUD_POSE 5U
|
||||
#define SPI_CON1_BAUD_MSK BITS(SPI_CON1_BAUD_POSS,SPI_CON1_BAUD_POSE)
|
||||
|
||||
#define SPI_CON1_MSTREN_POS 2U
|
||||
#define SPI_CON1_MSTREN_MSK BIT(SPI_CON1_MSTREN_POS)
|
||||
|
||||
#define SPI_CON1_CPOL_POS 1U
|
||||
#define SPI_CON1_CPOL_MSK BIT(SPI_CON1_CPOL_POS)
|
||||
|
||||
#define SPI_CON1_CPHA_POS 0U
|
||||
#define SPI_CON1_CPHA_MSK BIT(SPI_CON1_CPHA_POS)
|
||||
|
||||
/****************** Bit definition for SPI_CON2 register ************************/
|
||||
|
||||
#define SPI_CON2_RXFTH_POSS 14U
|
||||
#define SPI_CON2_RXFTH_POSE 15U
|
||||
#define SPI_CON2_RXFTH_MSK BITS(SPI_CON2_RXFTH_POSS,SPI_CON2_RXFTH_POSE)
|
||||
|
||||
#define SPI_CON2_TXFTH_POSS 12U
|
||||
#define SPI_CON2_TXFTH_POSE 13U
|
||||
#define SPI_CON2_TXFTH_MSK BITS(SPI_CON2_TXFTH_POSS,SPI_CON2_TXFTH_POSE)
|
||||
|
||||
#define SPI_CON2_FRF_POS 4U
|
||||
#define SPI_CON2_FRF_MSK BIT(SPI_CON2_FRF_POS)
|
||||
|
||||
#define SPI_CON2_NSSP_POS 3U
|
||||
#define SPI_CON2_NSSP_MSK BIT(SPI_CON2_NSSP_POS)
|
||||
|
||||
#define SPI_CON2_NSSOE_POS 2U
|
||||
#define SPI_CON2_NSSOE_MSK BIT(SPI_CON2_NSSOE_POS)
|
||||
|
||||
#define SPI_CON2_TXDMA_POS 1U
|
||||
#define SPI_CON2_TXDMA_MSK BIT(SPI_CON2_TXDMA_POS)
|
||||
|
||||
#define SPI_CON2_RXDMA_POS 0U
|
||||
#define SPI_CON2_RXDMA_MSK BIT(SPI_CON2_RXDMA_POS)
|
||||
|
||||
/****************** Bit definition for SPI_STAT register ************************/
|
||||
|
||||
#define SPI_STAT_RXFLV_POSS 24U
|
||||
#define SPI_STAT_RXFLV_POSE 28U
|
||||
#define SPI_STAT_RXFLV_MSK BITS(SPI_STAT_RXFLV_POSS,SPI_STAT_RXFLV_POSE)
|
||||
|
||||
#define SPI_STAT_TXFLV_POSS 16U
|
||||
#define SPI_STAT_TXFLV_POSE 20U
|
||||
#define SPI_STAT_TXFLV_MSK BITS(SPI_STAT_TXFLV_POSS,SPI_STAT_TXFLV_POSE)
|
||||
|
||||
#define SPI_STAT_BUSY_POS 15U
|
||||
#define SPI_STAT_BUSY_MSK BIT(SPI_STAT_BUSY_POS)
|
||||
|
||||
#define SPI_STAT_CHSIDE_POS 14U
|
||||
#define SPI_STAT_CHSIDE_MSK BIT(SPI_STAT_CHSIDE_POS)
|
||||
|
||||
#define SPI_STAT_RXTH_POS 12U
|
||||
#define SPI_STAT_RXTH_MSK BIT(SPI_STAT_RXTH_POS)
|
||||
|
||||
#define SPI_STAT_RXUD_POS 11U
|
||||
#define SPI_STAT_RXUD_MSK BIT(SPI_STAT_RXUD_POS)
|
||||
|
||||
#define SPI_STAT_RXOV_POS 10U
|
||||
#define SPI_STAT_RXOV_MSK BIT(SPI_STAT_RXOV_POS)
|
||||
|
||||
#define SPI_STAT_RXF_POS 9U
|
||||
#define SPI_STAT_RXF_MSK BIT(SPI_STAT_RXF_POS)
|
||||
|
||||
#define SPI_STAT_RXE_POS 8U
|
||||
#define SPI_STAT_RXE_MSK BIT(SPI_STAT_RXE_POS)
|
||||
|
||||
#define SPI_STAT_TXTH_POS 4U
|
||||
#define SPI_STAT_TXTH_MSK BIT(SPI_STAT_TXTH_POS)
|
||||
|
||||
#define SPI_STAT_TXUD_POS 3U
|
||||
#define SPI_STAT_TXUD_MSK BIT(SPI_STAT_TXUD_POS)
|
||||
|
||||
#define SPI_STAT_TXOV_POS 2U
|
||||
#define SPI_STAT_TXOV_MSK BIT(SPI_STAT_TXOV_POS)
|
||||
|
||||
#define SPI_STAT_TXF_POS 1U
|
||||
#define SPI_STAT_TXF_MSK BIT(SPI_STAT_TXF_POS)
|
||||
|
||||
#define SPI_STAT_TXE_POS 0U
|
||||
#define SPI_STAT_TXE_MSK BIT(SPI_STAT_TXE_POS)
|
||||
|
||||
/****************** Bit definition for SPI_DATA register ************************/
|
||||
|
||||
#define SPI_DATA_DATA_POSS 0U
|
||||
#define SPI_DATA_DATA_POSE 15U
|
||||
#define SPI_DATA_DATA_MSK BITS(SPI_DATA_DATA_POSS,SPI_DATA_DATA_POSE)
|
||||
|
||||
/****************** Bit definition for SPI_CRCPOLY register ************************/
|
||||
|
||||
#define SPI_CRCPOLY_CRCPOLY_POSS 0U
|
||||
#define SPI_CRCPOLY_CRCPOLY_POSE 15U
|
||||
#define SPI_CRCPOLY_CRCPOLY_MSK BITS(SPI_CRCPOLY_CRCPOLY_POSS,SPI_CRCPOLY_CRCPOLY_POSE)
|
||||
|
||||
/****************** Bit definition for SPI_RXCRC register ************************/
|
||||
|
||||
#define SPI_RXCRC_RXCRC_POSS 0U
|
||||
#define SPI_RXCRC_RXCRC_POSE 15U
|
||||
#define SPI_RXCRC_RXCRC_MSK BITS(SPI_RXCRC_RXCRC_POSS,SPI_RXCRC_RXCRC_POSE)
|
||||
|
||||
/****************** Bit definition for SPI_TXCRC register ************************/
|
||||
|
||||
#define SPI_TXCRC_TXCRC_POSS 0U
|
||||
#define SPI_TXCRC_TXCRC_POSE 15U
|
||||
#define SPI_TXCRC_TXCRC_MSK BITS(SPI_TXCRC_TXCRC_POSS,SPI_TXCRC_TXCRC_POSE)
|
||||
|
||||
/****************** Bit definition for SPI_I2SCFG register ************************/
|
||||
|
||||
#define SPI_I2SCFG_I2SMOD_POS 11U
|
||||
#define SPI_I2SCFG_I2SMOD_MSK BIT(SPI_I2SCFG_I2SMOD_POS)
|
||||
|
||||
#define SPI_I2SCFG_I2SE_POS 10U
|
||||
#define SPI_I2SCFG_I2SE_MSK BIT(SPI_I2SCFG_I2SE_POS)
|
||||
|
||||
#define SPI_I2SCFG_I2SCFG_POSS 8U
|
||||
#define SPI_I2SCFG_I2SCFG_POSE 9U
|
||||
#define SPI_I2SCFG_I2SCFG_MSK BITS(SPI_I2SCFG_I2SCFG_POSS,SPI_I2SCFG_I2SCFG_POSE)
|
||||
|
||||
#define SPI_I2SCFG_PCMSYNC_POS 7U
|
||||
#define SPI_I2SCFG_PCMSYNC_MSK BIT(SPI_I2SCFG_PCMSYNC_POS)
|
||||
|
||||
#define SPI_I2SCFG_I2SSTD_POSS 4U
|
||||
#define SPI_I2SCFG_I2SSTD_POSE 5U
|
||||
#define SPI_I2SCFG_I2SSTD_MSK BITS(SPI_I2SCFG_I2SSTD_POSS,SPI_I2SCFG_I2SSTD_POSE)
|
||||
|
||||
#define SPI_I2SCFG_CKPOL_POS 3U
|
||||
#define SPI_I2SCFG_CKPOL_MSK BIT(SPI_I2SCFG_CKPOL_POS)
|
||||
|
||||
#define SPI_I2SCFG_DATLEN_POSS 1U
|
||||
#define SPI_I2SCFG_DATLEN_POSE 2U
|
||||
#define SPI_I2SCFG_DATLEN_MSK BITS(SPI_I2SCFG_DATLEN_POSS,SPI_I2SCFG_DATLEN_POSE)
|
||||
|
||||
#define SPI_I2SCFG_CHLEN_POS 0U
|
||||
#define SPI_I2SCFG_CHLEN_MSK BIT(SPI_I2SCFG_CHLEN_POS)
|
||||
|
||||
/****************** Bit definition for SPI_I2SPR register ************************/
|
||||
|
||||
#define SPI_I2SPR_EXTCKEN_POS 10U
|
||||
#define SPI_I2SPR_EXTCKEN_MSK BIT(SPI_I2SPR_EXTCKEN_POS)
|
||||
|
||||
#define SPI_I2SPR_MCKOE_POS 9U
|
||||
#define SPI_I2SPR_MCKOE_MSK BIT(SPI_I2SPR_MCKOE_POS)
|
||||
|
||||
#define SPI_I2SPR_ODD_POS 8U
|
||||
#define SPI_I2SPR_ODD_MSK BIT(SPI_I2SPR_ODD_POS)
|
||||
|
||||
#define SPI_I2SPR_I2SDIV_POSS 0U
|
||||
#define SPI_I2SPR_I2SDIV_POSE 7U
|
||||
#define SPI_I2SPR_I2SDIV_MSK BITS(SPI_I2SPR_I2SDIV_POSS,SPI_I2SPR_I2SDIV_POSE)
|
||||
|
||||
/****************** Bit definition for SPI_IER register ************************/
|
||||
|
||||
#define SPI_IER_FREIE_POS 18U
|
||||
#define SPI_IER_FREIE_MSK BIT(SPI_IER_FREIE_POS)
|
||||
|
||||
#define SPI_IER_MODFIE_POS 17U
|
||||
#define SPI_IER_MODFIE_MSK BIT(SPI_IER_MODFIE_POS)
|
||||
|
||||
#define SPI_IER_CRCERRIE_POS 16U
|
||||
#define SPI_IER_CRCERRIE_MSK BIT(SPI_IER_CRCERRIE_POS)
|
||||
|
||||
#define SPI_IER_RXTHIE_POS 12U
|
||||
#define SPI_IER_RXTHIE_MSK BIT(SPI_IER_RXTHIE_POS)
|
||||
|
||||
#define SPI_IER_RXUDIE_POS 11U
|
||||
#define SPI_IER_RXUDIE_MSK BIT(SPI_IER_RXUDIE_POS)
|
||||
|
||||
#define SPI_IER_RXOVIE_POS 10U
|
||||
#define SPI_IER_RXOVIE_MSK BIT(SPI_IER_RXOVIE_POS)
|
||||
|
||||
#define SPI_IER_RXFIE_POS 9U
|
||||
#define SPI_IER_RXFIE_MSK BIT(SPI_IER_RXFIE_POS)
|
||||
|
||||
#define SPI_IER_TXTHIE_POS 4U
|
||||
#define SPI_IER_TXTHIE_MSK BIT(SPI_IER_TXTHIE_POS)
|
||||
|
||||
#define SPI_IER_TXUDIE_POS 3U
|
||||
#define SPI_IER_TXUDIE_MSK BIT(SPI_IER_TXUDIE_POS)
|
||||
|
||||
#define SPI_IER_TXOVIE_POS 2U
|
||||
#define SPI_IER_TXOVIE_MSK BIT(SPI_IER_TXOVIE_POS)
|
||||
|
||||
#define SPI_IER_TXEIE_POS 0U
|
||||
#define SPI_IER_TXEIE_MSK BIT(SPI_IER_TXEIE_POS)
|
||||
|
||||
/****************** Bit definition for SPI_IDR register ************************/
|
||||
|
||||
#define SPI_IDR_FREID_POS 18U
|
||||
#define SPI_IDR_FREID_MSK BIT(SPI_IDR_FREID_POS)
|
||||
|
||||
#define SPI_IDR_MODFID_POS 17U
|
||||
#define SPI_IDR_MODFID_MSK BIT(SPI_IDR_MODFID_POS)
|
||||
|
||||
#define SPI_IDR_CRCERRID_POS 16U
|
||||
#define SPI_IDR_CRCERRID_MSK BIT(SPI_IDR_CRCERRID_POS)
|
||||
|
||||
#define SPI_IDR_RXTHID_POS 12U
|
||||
#define SPI_IDR_RXTHID_MSK BIT(SPI_IDR_RXTHID_POS)
|
||||
|
||||
#define SPI_IDR_RXUDID_POS 11U
|
||||
#define SPI_IDR_RXUDID_MSK BIT(SPI_IDR_RXUDID_POS)
|
||||
|
||||
#define SPI_IDR_RXOVID_POS 10U
|
||||
#define SPI_IDR_RXOVID_MSK BIT(SPI_IDR_RXOVID_POS)
|
||||
|
||||
#define SPI_IDR_RXFID_POS 9U
|
||||
#define SPI_IDR_RXFID_MSK BIT(SPI_IDR_RXFID_POS)
|
||||
|
||||
#define SPI_IDR_TXTHID_POS 4U
|
||||
#define SPI_IDR_TXTHID_MSK BIT(SPI_IDR_TXTHID_POS)
|
||||
|
||||
#define SPI_IDR_TXUDID_POS 3U
|
||||
#define SPI_IDR_TXUDID_MSK BIT(SPI_IDR_TXUDID_POS)
|
||||
|
||||
#define SPI_IDR_TXOVID_POS 2U
|
||||
#define SPI_IDR_TXOVID_MSK BIT(SPI_IDR_TXOVID_POS)
|
||||
|
||||
#define SPI_IDR_TXEID_POS 0U
|
||||
#define SPI_IDR_TXEID_MSK BIT(SPI_IDR_TXEID_POS)
|
||||
|
||||
/****************** Bit definition for SPI_IVS register ************************/
|
||||
|
||||
#define SPI_IVS_FREIV_POS 18U
|
||||
#define SPI_IVS_FREIV_MSK BIT(SPI_IVS_FREIV_POS)
|
||||
|
||||
#define SPI_IVS_MODFIV_POS 17U
|
||||
#define SPI_IVS_MODFIV_MSK BIT(SPI_IVS_MODFIV_POS)
|
||||
|
||||
#define SPI_IVS_CRCERRIV_POS 16U
|
||||
#define SPI_IVS_CRCERRIV_MSK BIT(SPI_IVS_CRCERRIV_POS)
|
||||
|
||||
#define SPI_IVS_RXTHIV_POS 12U
|
||||
#define SPI_IVS_RXTHIV_MSK BIT(SPI_IVS_RXTHIV_POS)
|
||||
|
||||
#define SPI_IVS_RXUDIV_POS 11U
|
||||
#define SPI_IVS_RXUDIV_MSK BIT(SPI_IVS_RXUDIV_POS)
|
||||
|
||||
#define SPI_IVS_RXOVIV_POS 10U
|
||||
#define SPI_IVS_RXOVIV_MSK BIT(SPI_IVS_RXOVIV_POS)
|
||||
|
||||
#define SPI_IVS_RXFIV_POS 9U
|
||||
#define SPI_IVS_RXFIV_MSK BIT(SPI_IVS_RXFIV_POS)
|
||||
|
||||
#define SPI_IVS_TXTHIV_POS 4U
|
||||
#define SPI_IVS_TXTHIV_MSK BIT(SPI_IVS_TXTHIV_POS)
|
||||
|
||||
#define SPI_IVS_TXUDIV_POS 3U
|
||||
#define SPI_IVS_TXUDIV_MSK BIT(SPI_IVS_TXUDIV_POS)
|
||||
|
||||
#define SPI_IVS_TXOVIV_POS 2U
|
||||
#define SPI_IVS_TXOVIV_MSK BIT(SPI_IVS_TXOVIV_POS)
|
||||
|
||||
#define SPI_IVS_TXEIV_POS 0U
|
||||
#define SPI_IVS_TXEIV_MSK BIT(SPI_IVS_TXEIV_POS)
|
||||
|
||||
/****************** Bit definition for SPI_RIF register ************************/
|
||||
|
||||
#define SPI_RIF_FRERI_POS 18U
|
||||
#define SPI_RIF_FRERI_MSK BIT(SPI_RIF_FRERI_POS)
|
||||
|
||||
#define SPI_RIF_MODFRI_POS 17U
|
||||
#define SPI_RIF_MODFRI_MSK BIT(SPI_RIF_MODFRI_POS)
|
||||
|
||||
#define SPI_RIF_CRCERRRI_POS 16U
|
||||
#define SPI_RIF_CRCERRRI_MSK BIT(SPI_RIF_CRCERRRI_POS)
|
||||
|
||||
#define SPI_RIF_RXTHRI_POS 12U
|
||||
#define SPI_RIF_RXTHRI_MSK BIT(SPI_RIF_RXTHRI_POS)
|
||||
|
||||
#define SPI_RIF_RXUDRI_POS 11U
|
||||
#define SPI_RIF_RXUDRI_MSK BIT(SPI_RIF_RXUDRI_POS)
|
||||
|
||||
#define SPI_RIF_RXOVRI_POS 10U
|
||||
#define SPI_RIF_RXOVRI_MSK BIT(SPI_RIF_RXOVRI_POS)
|
||||
|
||||
#define SPI_RIF_RXFRI_POS 9U
|
||||
#define SPI_RIF_RXFRI_MSK BIT(SPI_RIF_RXFRI_POS)
|
||||
|
||||
#define SPI_RIF_TXTHRI_POS 4U
|
||||
#define SPI_RIF_TXTHRI_MSK BIT(SPI_RIF_TXTHRI_POS)
|
||||
|
||||
#define SPI_RIF_TXUDRI_POS 3U
|
||||
#define SPI_RIF_TXUDRI_MSK BIT(SPI_RIF_TXUDRI_POS)
|
||||
|
||||
#define SPI_RIF_TXOVRI_POS 2U
|
||||
#define SPI_RIF_TXOVRI_MSK BIT(SPI_RIF_TXOVRI_POS)
|
||||
|
||||
#define SPI_RIF_TXERI_POS 0U
|
||||
#define SPI_RIF_TXERI_MSK BIT(SPI_RIF_TXERI_POS)
|
||||
|
||||
/****************** Bit definition for SPI_IFM register ************************/
|
||||
|
||||
#define SPI_IFM_FREFM_POS 18U
|
||||
#define SPI_IFM_FREFM_MSK BIT(SPI_IFM_FREFM_POS)
|
||||
|
||||
#define SPI_IFM_MODFFM_POS 17U
|
||||
#define SPI_IFM_MODFFM_MSK BIT(SPI_IFM_MODFFM_POS)
|
||||
|
||||
#define SPI_IFM_CRCERRFM_POS 16U
|
||||
#define SPI_IFM_CRCERRFM_MSK BIT(SPI_IFM_CRCERRFM_POS)
|
||||
|
||||
#define SPI_IFM_RXTHFM_POS 12U
|
||||
#define SPI_IFM_RXTHFM_MSK BIT(SPI_IFM_RXTHFM_POS)
|
||||
|
||||
#define SPI_IFM_RXUDFM_POS 11U
|
||||
#define SPI_IFM_RXUDFM_MSK BIT(SPI_IFM_RXUDFM_POS)
|
||||
|
||||
#define SPI_IFM_RXOVFM_POS 10U
|
||||
#define SPI_IFM_RXOVFM_MSK BIT(SPI_IFM_RXOVFM_POS)
|
||||
|
||||
#define SPI_IFM_RXFFM_POS 9U
|
||||
#define SPI_IFM_RXFFM_MSK BIT(SPI_IFM_RXFFM_POS)
|
||||
|
||||
#define SPI_IFM_TXTHFM_POS 4U
|
||||
#define SPI_IFM_TXTHFM_MSK BIT(SPI_IFM_TXTHFM_POS)
|
||||
|
||||
#define SPI_IFM_TXUDFM_POS 3U
|
||||
#define SPI_IFM_TXUDFM_MSK BIT(SPI_IFM_TXUDFM_POS)
|
||||
|
||||
#define SPI_IFM_TXOVFM_POS 2U
|
||||
#define SPI_IFM_TXOVFM_MSK BIT(SPI_IFM_TXOVFM_POS)
|
||||
|
||||
#define SPI_IFM_TXEFM_POS 0U
|
||||
#define SPI_IFM_TXEFM_MSK BIT(SPI_IFM_TXEFM_POS)
|
||||
|
||||
/****************** Bit definition for SPI_ICR register ************************/
|
||||
|
||||
#define SPI_ICR_FREIC_POS 18U
|
||||
#define SPI_ICR_FREIC_MSK BIT(SPI_ICR_FREIC_POS)
|
||||
|
||||
#define SPI_ICR_MODFIC_POS 17U
|
||||
#define SPI_ICR_MODFIC_MSK BIT(SPI_ICR_MODFIC_POS)
|
||||
|
||||
#define SPI_ICR_CRCERRIC_POS 16U
|
||||
#define SPI_ICR_CRCERRIC_MSK BIT(SPI_ICR_CRCERRIC_POS)
|
||||
|
||||
#define SPI_ICR_RXTHIC_POS 12U
|
||||
#define SPI_ICR_RXTHIC_MSK BIT(SPI_ICR_RXTHIC_POS)
|
||||
|
||||
#define SPI_ICR_RXUDIC_POS 11U
|
||||
#define SPI_ICR_RXUDIC_MSK BIT(SPI_ICR_RXUDIC_POS)
|
||||
|
||||
#define SPI_ICR_RXOVIC_POS 10U
|
||||
#define SPI_ICR_RXOVIC_MSK BIT(SPI_ICR_RXOVIC_POS)
|
||||
|
||||
#define SPI_ICR_RXFIC_POS 9U
|
||||
#define SPI_ICR_RXFIC_MSK BIT(SPI_ICR_RXFIC_POS)
|
||||
|
||||
#define SPI_ICR_TXTHIC_POS 4U
|
||||
#define SPI_ICR_TXTHIC_MSK BIT(SPI_ICR_TXTHIC_POS)
|
||||
|
||||
#define SPI_ICR_TXUDIC_POS 3U
|
||||
#define SPI_ICR_TXUDIC_MSK BIT(SPI_ICR_TXUDIC_POS)
|
||||
|
||||
#define SPI_ICR_TXOVIC_POS 2U
|
||||
#define SPI_ICR_TXOVIC_MSK BIT(SPI_ICR_TXOVIC_POS)
|
||||
|
||||
#define SPI_ICR_TXEIC_POS 0U
|
||||
#define SPI_ICR_TXEIC_MSK BIT(SPI_ICR_TXEIC_POS)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CON1;
|
||||
__IO uint32_t CON2;
|
||||
__I uint32_t STAT;
|
||||
__IO uint32_t DATA;
|
||||
__IO uint32_t CRCPOLY;
|
||||
__I uint32_t RXCRC;
|
||||
__I uint32_t TXCRC;
|
||||
__IO uint32_t I2SCFG;
|
||||
__IO uint32_t I2SPR;
|
||||
__O uint32_t IER;
|
||||
__O uint32_t IDR;
|
||||
__I uint32_t IVS;
|
||||
__I uint32_t RIF;
|
||||
__I uint32_t IFM;
|
||||
__O uint32_t ICR;
|
||||
} SPI_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-215
@@ -1,215 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_SYSCFG.h
|
||||
* @brief SYSCFG Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @date 12/5/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __SYSCFG_H__
|
||||
#define __SYSCFG_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for SYSCFG_REMAP register ************************/
|
||||
|
||||
#define SYSCFG_REMAP_REALMOD_POSS 10U
|
||||
#define SYSCFG_REMAP_REALMOD_POSE 11U
|
||||
#define SYSCFG_REMAP_REALMOD_MSK BITS(SYSCFG_REMAP_REALMOD_POSS,SYSCFG_REMAP_REALMOD_POSE)
|
||||
|
||||
#define SYSCFG_REMAP_EFBASE_POSS 4U
|
||||
#define SYSCFG_REMAP_EFBASE_POSE 7U
|
||||
#define SYSCFG_REMAP_EFBASE_MSK BITS(SYSCFG_REMAP_EFBASE_POSS,SYSCFG_REMAP_EFBASE_POSE)
|
||||
|
||||
#define SYSCFG_REMAP_MEMMOD_POSS 2U
|
||||
#define SYSCFG_REMAP_MEMMOD_POSE 3U
|
||||
#define SYSCFG_REMAP_MEMMOD_MSK BITS(SYSCFG_REMAP_MEMMOD_POSS,SYSCFG_REMAP_MEMMOD_POSE)
|
||||
|
||||
#define SYSCFG_REMAP_REMAP_POS 0U
|
||||
#define SYSCFG_REMAP_REMAP_MSK BIT(SYSCFG_REMAP_REMAP_POS)
|
||||
|
||||
/****************** Bit definition for SYSCFG_TRIM register ************************/
|
||||
|
||||
#define SYSCFG_TRIM_CNT_POSS 20U
|
||||
#define SYSCFG_TRIM_CNT_POSE 31U
|
||||
#define SYSCFG_TRIM_CNT_MSK BITS(SYSCFG_TRIM_CNT_POSS,SYSCFG_TRIM_CNT_POSE)
|
||||
|
||||
#define SYSCFG_TRIM_FAIL_POS 18U
|
||||
#define SYSCFG_TRIM_FAIL_MSK BIT(SYSCFG_TRIM_FAIL_POS)
|
||||
|
||||
#define SYSCFG_TRIM_NOEQU_POS 17U
|
||||
#define SYSCFG_TRIM_NOEQU_MSK BIT(SYSCFG_TRIM_NOEQU_POS)
|
||||
|
||||
#define SYSCFG_TRIM_BUSY_POS 16U
|
||||
#define SYSCFG_TRIM_BUSY_MSK BIT(SYSCFG_TRIM_BUSY_POS)
|
||||
|
||||
#define SYSCFG_TRIM_HRCTRIM_POSS 8U
|
||||
#define SYSCFG_TRIM_HRCTRIM_POSE 15U
|
||||
#define SYSCFG_TRIM_HRCTRIM_MSK BITS(SYSCFG_TRIM_HRCTRIM_POSS,SYSCFG_TRIM_HRCTRIM_POSE)
|
||||
|
||||
#define SYSCFG_TRIM_TSRC_POS 1U
|
||||
#define SYSCFG_TRIM_TSRC_MSK BIT(SYSCFG_TRIM_TSRC_POS)
|
||||
|
||||
#define SYSCFG_TRIM_TRIM_POS 0U
|
||||
#define SYSCFG_TRIM_TRIM_MSK BIT(SYSCFG_TRIM_TRIM_POS)
|
||||
|
||||
/****************** Bit definition for SYSCFG_IRSEL register ************************/
|
||||
|
||||
#define SYSCFG_IRSEL_PLR_POS 8U
|
||||
#define SYSCFG_IRSEL_PLR_MSK BIT(SYSCFG_IRSEL_PLR_POS)
|
||||
|
||||
#define SYSCFG_IRSEL_SEL2_POSS 4U
|
||||
#define SYSCFG_IRSEL_SEL2_POSE 7U
|
||||
#define SYSCFG_IRSEL_SEL2_MSK BITS(SYSCFG_IRSEL_SEL2_POSS,SYSCFG_IRSEL_SEL2_POSE)
|
||||
|
||||
#define SYSCFG_IRSEL_SEL1_POSS 0U
|
||||
#define SYSCFG_IRSEL_SEL1_POSE 3U
|
||||
#define SYSCFG_IRSEL_SEL1_MSK BITS(SYSCFG_IRSEL_SEL1_POSS,SYSCFG_IRSEL_SEL1_POSE)
|
||||
|
||||
/****************** Bit definition for SYSCFG_CFG register ************************/
|
||||
|
||||
#define SYSCFG_CFG_DBGH_EN_POSS 16U
|
||||
#define SYSCFG_CFG_DBGH_EN_POSE 31U
|
||||
#define SYSCFG_CFG_DBGH_EN_MSK BITS(SYSCFG_CFG_DBGH_EN_POSS,SYSCFG_CFG_DBGH_EN_POSE)
|
||||
|
||||
#define SYSCFG_CFG_PVD_LCK_POS 14U
|
||||
#define SYSCFG_CFG_PVD_LCK_MSK BIT(SYSCFG_CFG_PVD_LCK_POS)
|
||||
|
||||
#define SYSCFG_CFG_CSS_LCK_POS 13U
|
||||
#define SYSCFG_CFG_CSS_LCK_MSK BIT(SYSCFG_CFG_CSS_LCK_POS)
|
||||
|
||||
#define SYSCFG_CFG_CPU_LCK_POS 12U
|
||||
#define SYSCFG_CFG_CPU_LCK_MSK BIT(SYSCFG_CFG_CPU_LCK_POS)
|
||||
|
||||
#define SYSCFG_CFG_VTST_POSS 8U
|
||||
#define SYSCFG_CFG_VTST_POSE 9U
|
||||
#define SYSCFG_CFG_VTST_MSK BITS(SYSCFG_CFG_VTST_POSS,SYSCFG_CFG_VTST_POSE)
|
||||
|
||||
#define SYSCFG_CFG_NRSTREQ_POS 7U
|
||||
#define SYSCFG_CFG_NRSTREQ_MSK BIT(SYSCFG_CFG_NRSTREQ_POS)
|
||||
|
||||
#define SYSCFG_CFG_CURRGEN_POS 5U
|
||||
#define SYSCFG_CFG_CURRGEN_MSK BIT(SYSCFG_CFG_CURRGEN_POS)
|
||||
|
||||
#define SYSCFG_CFG_TEMPEN_POS 4U
|
||||
#define SYSCFG_CFG_TEMPEN_MSK BIT(SYSCFG_CFG_TEMPEN_POS)
|
||||
|
||||
#define SYSCFG_CFG_VREFEN_POS 3U
|
||||
#define SYSCFG_CFG_VREFEN_MSK BIT(SYSCFG_CFG_VREFEN_POS)
|
||||
|
||||
#define SYSCFG_CFG_VRLS_POSS 0U
|
||||
#define SYSCFG_CFG_VRLS_POSE 2U
|
||||
#define SYSCFG_CFG_VRLS_MSK BITS(SYSCFG_CFG_VRLS_POSS,SYSCFG_CFG_VRLS_POSE)
|
||||
|
||||
/****************** Bit definition for SYSCFG_PWCON register ************************/
|
||||
|
||||
#define SYSCFG_PWCON_IOLOCK_POS 23U
|
||||
#define SYSCFG_PWCON_IOLOCK_MSK BIT(SYSCFG_PWCON_IOLOCK_POS)
|
||||
|
||||
#define SYSCFG_PWCON_BGTRIM_POSS 17U
|
||||
#define SYSCFG_PWCON_BGTRIM_POSE 20U
|
||||
#define SYSCFG_PWCON_BGTRIM_MSK BITS(SYSCFG_PWCON_BGTRIM_POSS,SYSCFG_PWCON_BGTRIM_POSE)
|
||||
|
||||
#define SYSCFG_PWCON_HRCLOCK_POS 16U
|
||||
#define SYSCFG_PWCON_HRCLOCK_MSK BIT(SYSCFG_PWCON_HRCLOCK_POS)
|
||||
|
||||
#define SYSCFG_PWCON_HRCTRIM_POSS 8U
|
||||
#define SYSCFG_PWCON_HRCTRIM_POSE 15U
|
||||
#define SYSCFG_PWCON_HRCTRIM_MSK BITS(SYSCFG_PWCON_HRCTRIM_POSS,SYSCFG_PWCON_HRCTRIM_POSE)
|
||||
|
||||
#define SYSCFG_PWCON_LOSCDRV_POSS 5U
|
||||
#define SYSCFG_PWCON_LOSCDRV_POSE 7U
|
||||
#define SYSCFG_PWCON_LOSCDRV_MSK BITS(SYSCFG_PWCON_LOSCDRV_POSS,SYSCFG_PWCON_LOSCDRV_POSE)
|
||||
|
||||
#define SYSCFG_PWCON_PVDEN_POS 4U
|
||||
#define SYSCFG_PWCON_PVDEN_MSK BIT(SYSCFG_PWCON_PVDEN_POS)
|
||||
|
||||
#define SYSCFG_PWCON_PVLS_POSS 0U
|
||||
#define SYSCFG_PWCON_PVLS_POSE 3U
|
||||
#define SYSCFG_PWCON_PVLS_MSK BITS(SYSCFG_PWCON_PVLS_POSS,SYSCFG_PWCON_PVLS_POSE)
|
||||
|
||||
/****************** Bit definition for SYSCFG_WKCON register ************************/
|
||||
|
||||
#define SYSCFG_WKCON_WKCLR_POS 31U
|
||||
#define SYSCFG_WKCON_WKCLR_MSK BIT(SYSCFG_WKCON_WKCLR_POS)
|
||||
|
||||
#define SYSCFG_WKCON_LPLS_POSS 28U
|
||||
#define SYSCFG_WKCON_LPLS_POSE 30U
|
||||
#define SYSCFG_WKCON_LPLS_MSK BITS(SYSCFG_WKCON_LPLS_POSS,SYSCFG_WKCON_LPLS_POSE)
|
||||
|
||||
#define SYSCFG_WKCON_WKEG_POSS 16U
|
||||
#define SYSCFG_WKCON_WKEG_POSE 27U
|
||||
#define SYSCFG_WKCON_WKEG_MSK BITS(SYSCFG_WKCON_WKEG_POSS,SYSCFG_WKCON_WKEG_POSE)
|
||||
|
||||
#define SYSCFG_WKCON_WKEN_POSS 0U
|
||||
#define SYSCFG_WKCON_WKEN_POSE 11U
|
||||
#define SYSCFG_WKCON_WKEN_MSK BITS(SYSCFG_WKCON_WKEN_POSS,SYSCFG_WKCON_WKEN_POSE)
|
||||
|
||||
/****************** Bit definition for SYSCFG_WKSTAT register ************************/
|
||||
|
||||
#define SYSCFG_WKSTAT_FLAG_POS 16U
|
||||
#define SYSCFG_WKSTAT_FLAG_MSK BIT(SYSCFG_WKSTAT_FLAG_POS)
|
||||
|
||||
#define SYSCFG_WKSTAT_FG_POSS 0U
|
||||
#define SYSCFG_WKSTAT_FG_POSE 11U
|
||||
#define SYSCFG_WKSTAT_FG_MSK BITS(SYSCFG_WKSTAT_FG_POSS,SYSCFG_WKSTAT_FG_POSE)
|
||||
|
||||
/****************** Bit definition for SYSCFG_BKREG0 register ************************/
|
||||
|
||||
#define SYSCFG_BKREG0_BKREG0_POSS 0U
|
||||
#define SYSCFG_BKREG0_BKREG0_POSE 31U
|
||||
#define SYSCFG_BKREG0_BKREG0_MSK BITS(SYSCFG_BKREG0_BKREG0_POSS,SYSCFG_BKREG0_BKREG0_POSE)
|
||||
|
||||
/****************** Bit definition for SYSCFG_BKREG1 register ************************/
|
||||
|
||||
#define SYSCFG_BKREG1_BKREG1_POSS 0U
|
||||
#define SYSCFG_BKREG1_BKREG1_POSE 31U
|
||||
#define SYSCFG_BKREG1_BKREG1_MSK BITS(SYSCFG_BKREG1_BKREG1_POSS,SYSCFG_BKREG1_BKREG1_POSE)
|
||||
|
||||
/****************** Bit definition for SYSCFG_BKREG2 register ************************/
|
||||
|
||||
#define SYSCFG_BKREG2_BKREG2_POSS 0U
|
||||
#define SYSCFG_BKREG2_BKREG2_POSE 31U
|
||||
#define SYSCFG_BKREG2_BKREG2_MSK BITS(SYSCFG_BKREG2_BKREG2_POSS,SYSCFG_BKREG2_BKREG2_POSE)
|
||||
|
||||
/****************** Bit definition for SYSCFG_BKREG3 register ************************/
|
||||
|
||||
#define SYSCFG_BKREG3_BKREG3_POSS 0U
|
||||
#define SYSCFG_BKREG3_BKREG3_POSE 29U
|
||||
#define SYSCFG_BKREG3_BKREG3_MSK BITS(SYSCFG_BKREG3_BKREG3_POSS,SYSCFG_BKREG3_BKREG3_POSE)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t REMAP;
|
||||
__O uint32_t TRIM;
|
||||
__IO uint32_t IRSEL;
|
||||
uint32_t RESERVED0[12] ;
|
||||
__IO uint32_t CFG;
|
||||
__IO uint32_t PWCON;
|
||||
uint32_t RESERVED1 ;
|
||||
__IO uint32_t WKCON;
|
||||
__I uint32_t WKSTAT;
|
||||
__IO uint32_t BKREG0;
|
||||
__IO uint32_t BKREG1;
|
||||
__IO uint32_t BKREG2;
|
||||
__IO uint32_t BKREG3;
|
||||
} SYSCFG_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-113
@@ -1,113 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file reg_TICK.h
|
||||
* @brief TICK Head File
|
||||
*
|
||||
* @version V1.00.01
|
||||
* @date 19/10/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __TICK_H__
|
||||
#define __TICK_H__
|
||||
|
||||
/******************************************************************************/
|
||||
/* ¼È¦s¾¹¤º³¡¦ì¤¸©w¸q */
|
||||
/******************************************************************************/
|
||||
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for TICK_CSR register ************************/
|
||||
|
||||
#define TICK_CSR_ENABLE_POS 0U
|
||||
#define TICK_CSR_ENABLE_MSK BIT(TICK_CSR_ENABLE_POS)
|
||||
|
||||
#define TICK_CSR_TICKINT_POS 1U
|
||||
#define TICK_CSR_TICKINT_MSK BIT(TICK_CSR_TICKINT_POS)
|
||||
|
||||
#define TICK_CSR_CLKSOURCE_POS 2U
|
||||
#define TICK_CSR_CLKSOURCE_MSK BIT(TICK_CSR_CLKSOURCE_POS)
|
||||
|
||||
#define TICK_CSR_COUNTFLAG_POS 16U
|
||||
#define TICK_CSR_COUNTFLAG_MSK BIT(TICK_CSR_COUNTFLAG_POS)
|
||||
|
||||
/****************** Bit definition for TICK_RVR register ************************/
|
||||
|
||||
#define TICK_RVR_RELOAD_POSS 0U
|
||||
#define TICK_RVR_RELOAD_POSE 23U
|
||||
#define TICK_RVR_RELOAD_MSK BITS(TICK_RVR_RELOAD_POSS,TICK_RVR_RELOAD_POSE)
|
||||
|
||||
/****************** Bit definition for TICK_CVR register ************************/
|
||||
|
||||
#define TICK_CVR_CURRENT_POSS 0U
|
||||
#define TICK_CVR_CURRENT_POSE 23U
|
||||
#define TICK_CVR_CURRENT_MSK BITS(TICK_CVR_CURRENT_POSS,TICK_CVR_CURRENT_POSE)
|
||||
|
||||
|
||||
/****************** Bit definition for TICK_CALIB register ************************/
|
||||
|
||||
#define TICK_CALIB_TENMS_POSS 0U
|
||||
#define TICK_CALIB_TENMS_POSE 23U
|
||||
#define TICK_CALIB_TENMS_MSK BITS(TICK_CALIB_TENMS_POSS,TICK_CALIB_TENMS_POSE)
|
||||
|
||||
#define TICK_CALIB_SKEW_POS 30U
|
||||
#define TICK_CALIB_SKEW_MSK BIT(TICK_CALIB_SKEW_POS)
|
||||
|
||||
#define TICK_CALIB_NOREF_POS 31U
|
||||
#define TICK_CALIB_NOREF_MSK BIT(TICK_CALIB_NOREF_POS)
|
||||
|
||||
|
||||
/* TICK Register */
|
||||
#define pTICK TICK
|
||||
|
||||
/* TICK CSR Register(TICK_CSR) */
|
||||
#define CSR_COUNTFLAG(x) (x<<16) /* Indicates whether the counter has counted to 0 since the last read of this register
|
||||
0 timer has not counted to 0
|
||||
1 timer has counted to 0 */
|
||||
#define CSR_CLKSOURCE(x) (x<<2) /* Indicates the SysTick clock source:
|
||||
0 SysTick uses the optional external reference clock
|
||||
1 SysTick uses the processor clock */
|
||||
#define CSR_TICKINT(x) (x<<1) /* Indicates whether counting to 0 causes the status of the SysTick exception to change to pending:
|
||||
0 count to 0 does not affect the SysTick exception status
|
||||
1 count to 0 changes the SysTick exception status to pending */
|
||||
#define CSR_ENABLE(x) (x<<0) /* /Indicates the enabled status of the SysTick counter:
|
||||
0 counter is disabled
|
||||
1 counter is operating */
|
||||
|
||||
|
||||
/* TICK RVR Register(TICK_RVR) */
|
||||
#define RVR_RELOAD(x) (x<<0) /* The value to load into the SYST_CVR register when the counter reaches 0 */
|
||||
|
||||
|
||||
/* TICK CVR Register(TICK_CVR) */
|
||||
#define CVR_CURRENT(x) (x<<0) /* Current counter value
|
||||
This is the value of the counter at the time it is sampled */
|
||||
|
||||
|
||||
/* TICK CALIB Register(TICK_CALIB) */
|
||||
#define CALIB_NOREF(x) (x<<31) /* Indicates whether the IMPLEMENTATION DEFINED reference clock is provided:
|
||||
0 the reference clock is implemented
|
||||
1 the reference clock is not implemented
|
||||
When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot be cleared to 0 */
|
||||
#define CALIB_SKEW(x) (x<<30) /* Indicates whether the 10ms calibration value is exact:
|
||||
0 10ms calibration value is exact
|
||||
1 10ms calibration value is inexact, because of the clock frequency */
|
||||
#define CALIB_TENMS(x) (x<<0) /* Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors.
|
||||
If this field is zero, the calibration value is not known */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CSR; /* 0x0, Control and Status */
|
||||
__IO uint32_t RVR; /* 0x4, Reload Value */
|
||||
__IO uint32_t CVR; /* 0x8, Current Value */
|
||||
__I uint32_t CALIB; /* 0xC, Calibration */
|
||||
} TICK_TypeDef;
|
||||
|
||||
|
||||
#else
|
||||
/* */
|
||||
#endif
|
||||
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Reference in New Issue
Block a user