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https://github.com/RT-Thread/rt-thread.git
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Merge pull request #5043 from liuhy-2020/master
delete bsp ：es8p508x、es32f0271、es32f0334. update driver and Library.
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@@ -1,27 +0,0 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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config SOC_ES32F0271LT
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bool
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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source "drivers/Kconfig"
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@@ -1,95 +0,0 @@
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# ES-PDS-ES32F0271 开发板 BSP 说明
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标签： EastSoft、国产MCU、Cortex-M0、ES32F0271LT
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## 1. 简介
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本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0271 开发板提供的 BSP (板级支持包) 说明。
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通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
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### 1.1 开发板介绍
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主要内容如下：
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ES-PDS-ES32F0271 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。
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ES-PDS-ES32F0271-V1.1
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该开发板常用 **板载资源** 如下：
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- MCU：ES32F0271LT，主频 48MHz，8KB SRAM，64KB FLASH
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- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B)
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- 常用外设
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- 可调电阻：1个，(PC03)
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- LED：2个，(PD03/PB08)
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- 五轴按键：
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- 常用接口：GPIO、UART、SPI、I2C
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- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载
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外设支持:
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本 BSP 目前对外设的支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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| :---------------- | :----------: | :------------------------------------|
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | GPIOs |
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| UART | 支持 | UART1/2/3 |
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| SPI | 支持 | SPI1/2 |
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| I2C | 支持 | I2C1/2 |
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| PWM | 支持 | PWM1/2 |
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| TIMER | 支持 | TIMER1 |
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| RTC | 支持 | RTC |
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| ADC | 支持 | ADC |
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### 1.2 注意事项
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- 本BSP中，SPI2和PWM2不能同时使用
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更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
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## 2. 快速上手
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本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
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### 硬件连接
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使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC端，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PB06)、UART1_RX(PB07)、GND 接到串口工具上。
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ESLinkⅡ(mini) + ES-PDS-ES32F0271-V1.1
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### 编译下载
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双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。
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### 运行结果
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下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
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```bash
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\ | /
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- RT - Thread Operating System
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/ | \ 4.0.2 build Oct 31 2019
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2006 - 2019 Copyright by rt-thread team
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msh >
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```
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## 3. 进阶使用
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此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
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1. 在 bsp 下打开 env 工具。
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2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
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3. 输入`pkgs --update`命令更新软件包。
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4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
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更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
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## 4. 联系人信息
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- [yuzr](https://github.com/essemi-yuzr)
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## 5. 参考
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- [ EastSoft 官网](http://www.essemi.com)
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@@ -1,14 +0,0 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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objs = []
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cwd = str(Dir('#'))
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -1,39 +0,0 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM == 'iar':
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env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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# make a building
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DoBuilding(TARGET, objs)
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@@ -1,11 +0,0 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = os.path.join(str(Dir('#')), 'applications')
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src = Glob('*.c')
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CPPPATH = [cwd, str(Dir('#'))]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -1,28 +0,0 @@
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/*
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* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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||||
* Date Author Notes
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* 2019-10-23 yuzrain the first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#define LED_PIN 61
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int main(void)
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{
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/* LED pin configuration */
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rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
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while (1)
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{
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rt_pin_write(LED_PIN, PIN_HIGH);
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rt_thread_mdelay(1000);
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rt_pin_write(LED_PIN, PIN_LOW);
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rt_thread_mdelay(1000);
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}
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}
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@@ -1,102 +0,0 @@
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menu "Hardware Drivers Config"
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menu "On-chip Peripheral Drivers"
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menu "PIN Drivers"
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config BSP_USING_GPIO
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bool "Enable GPIO"
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select RT_USING_PIN
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default y
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endmenu
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menu "UART Drivers"
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config BSP_USING_UART1
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bool "Enable UART1 PB06/PB07(T/R)"
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select RT_USING_SERIAL
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default y
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config BSP_USING_UART2
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bool "Enable UART2 PA02/PA03(T/R)"
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select RT_USING_SERIAL
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default n
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config BSP_USING_UART3
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bool "Enable UART3 PC06/PC07(T/R)"
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select RT_USING_SERIAL
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default n
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endmenu
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menu "SPI Drivers"
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config BSP_USING_SPI1
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bool "Enable SPI1 BUS PB03/PB04/PB05(CLK/MISO/MOSI)"
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select RT_USING_SPI
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select RT_USING_PIN
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default n
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config BSP_USING_SPI2
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bool "Enable SPI2 BUS PB13/PB14/PB15(CLK/MISO/MOSI)"
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select RT_USING_SPI
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select RT_USING_PIN
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default n
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depends on !BSP_USING_PWM_GP16C2T4
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endmenu
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||||
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menu "I2C Drivers"
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config BSP_USING_I2C1
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bool "Enable I2C1 BUS PC12/PD02(SCL/SDA)"
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select RT_USING_I2C
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default n
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||||
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||||
config BSP_USING_I2C2
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bool "Enable I2C2 BUS PB10/PB11(SCL/SDA)"
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||||
select RT_USING_I2C
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||||
default n
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||||
endmenu
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||||
|
||||
menu "HWtimer Drivers"
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||||
|
||||
config BSP_USING_HWTIMER1
|
||||
bool "Using timer1"
|
||||
select RT_USING_HWTIMER
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "PWM Drivers"
|
||||
|
||||
config BSP_USING_PWM_GP16C2T1
|
||||
bool "Using PWM_1(GP16C2T1) PB01/PB02"
|
||||
select RT_USING_PWM
|
||||
default n
|
||||
|
||||
config BSP_USING_PWM_GP16C2T4
|
||||
bool "Using PWM2(GP16C2T4) PB12/PB14"
|
||||
select RT_USING_PWM
|
||||
default n
|
||||
depends on !BSP_USING_SPI2
|
||||
|
||||
endmenu
|
||||
|
||||
menu "RTC Drivers"
|
||||
config BSP_USING_RTC
|
||||
bool "Using RTC"
|
||||
select RT_USING_RTC
|
||||
default n
|
||||
endmenu
|
||||
|
||||
menu "ADC Drivers"
|
||||
config BSP_USING_ADC
|
||||
bool "Using ADC"
|
||||
select RT_USING_ADC
|
||||
default n
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Offboard Peripheral Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -1,45 +0,0 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split('''
|
||||
board.c
|
||||
''')
|
||||
|
||||
# add gpio code
|
||||
if GetDepend('RT_USING_PIN'):
|
||||
src += ['drv_gpio.c']
|
||||
|
||||
# add serial driver code
|
||||
if GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'):
|
||||
src += ['drv_uart.c']
|
||||
|
||||
# add spi driver code
|
||||
if GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'):
|
||||
src += ['drv_spi.c']
|
||||
|
||||
# add i2c driver code
|
||||
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2'):
|
||||
src += ['drv_i2c.c']
|
||||
|
||||
# add pwm driver code
|
||||
if GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3') or GetDepend('BSP_USING_PWM4') or GetDepend('BSP_USING_PWM_GP16C2T1') or GetDepend('BSP_USING_PWM_GP16C2T4'):
|
||||
src += ['drv_pwm.c']
|
||||
|
||||
# add hwtimer driver code
|
||||
if GetDepend('BSP_USING_HWTIMER1'):
|
||||
src += ['drv_hwtimer.c']
|
||||
|
||||
# add rtc driver code
|
||||
if GetDepend(['BSP_USING_RTC']):
|
||||
src += ['drv_rtc.c']
|
||||
|
||||
# add adc driver code
|
||||
if GetDepend(['BSP_USING_ADC']):
|
||||
src += ['drv_adc.c']
|
||||
|
||||
CPPPATH = [cwd]
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -1,136 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
#include "drv_gpio.h"
|
||||
#include "md_gpio.h"
|
||||
|
||||
/**
|
||||
* @addtogroup es32f0
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : NVIC_Configuration
|
||||
* Description : Configures Vector Table base location.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void NVIC_Configuration(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SystemClock_Configuration
|
||||
* Description : Configures the System Clock.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
/*-------------------------Clock Config-------------------------/
|
||||
* Config system clock to 48MHz of which the clock source
|
||||
* is PLL0.
|
||||
*/
|
||||
|
||||
//
|
||||
// Open PLL0/HRC then wait it ready.
|
||||
//
|
||||
SET_BIT(RCU->CON, RCU_CON_PLL0ON_MSK);
|
||||
SET_BIT(RCU->CON, RCU_CON_HRCON_MSK);
|
||||
|
||||
/* Wait HRC clock steady. */
|
||||
while (!READ_BIT(RCU->CON, RCU_CON_HRCRDY_MSK));
|
||||
|
||||
//
|
||||
// Change system clock source,PLL0,48MHz.
|
||||
//
|
||||
/* Chose PLL0 as system clock. */
|
||||
MODIFY_REG(RCU->CFG, RCU_CFG_SW_MSK, (0x4 << RCU_CFG_SW_POSS));
|
||||
/* Config mul of PLL0. */
|
||||
MODIFY_REG(RCU->CFG, RCU_CFG_PLLMUL_MSK, (11 << RCU_CFG_PLLMUL_POSS));
|
||||
|
||||
//
|
||||
// Start to change system clock and wait it ready.
|
||||
//
|
||||
/* Config flash read wait time. */
|
||||
MODIFY_REG(FC->CON, FC_CON_WAIT_MSK, (0X2 << FC_CON_WAIT_POSS));
|
||||
/* Start to change. */
|
||||
SET_BIT(RCU->CFG, RCU_CFG_CKCFG_MSK);
|
||||
|
||||
/* Wait system clock ready. */
|
||||
while (!READ_BIT(RCU->CON, RCU_CON_SWRDY_MSK));
|
||||
|
||||
//
|
||||
// Remember the system clock.
|
||||
//
|
||||
SystemCoreClock = 48000000;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name : SysTick_Configuration
|
||||
* Description : Configures the SysTick for OS tick.
|
||||
* Input : None
|
||||
* Output : None
|
||||
* Return : None
|
||||
*******************************************************************************/
|
||||
void SysTick_Configuration(void)
|
||||
{
|
||||
/* ticks = sysclk / RT_TICK_PER_SECOND */
|
||||
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
/**
|
||||
* This function will initial ES32F0 board.
|
||||
*/
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
/* NVIC Configuration */
|
||||
NVIC_Configuration();
|
||||
|
||||
/*System Clock Configuration */
|
||||
SystemClock_Config();
|
||||
|
||||
/* Configure the SysTick */
|
||||
SysTick_Configuration();
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
#ifdef RT_USING_CONSOLE
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "es32f0271.h"
|
||||
|
||||
#define ES32F0_SRAM_SIZE 0x2000
|
||||
#define ES32F0_SRAM_END (0x20000000 + ES32F0_SRAM_SIZE)
|
||||
|
||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN ((void *)&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END ES32F0_SRAM_END
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,148 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "board.h"
|
||||
#include "drv_adc.h"
|
||||
#include "md_gpio.h"
|
||||
#include "md_adc.h"
|
||||
#include "md_rcu.h"
|
||||
#include "md_syscfg.h"
|
||||
|
||||
#ifdef RT_USING_ADC
|
||||
|
||||
#define BSP_ADC_CHANNEL_NUM 8
|
||||
|
||||
/* define adc instance */
|
||||
static struct rt_adc_device _device_adc0;
|
||||
|
||||
/* enable or disable adc */
|
||||
static rt_err_t es32f0_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
|
||||
{
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
if (enabled)
|
||||
{
|
||||
md_adc_enable_ssen_ss0en(ADC);
|
||||
}
|
||||
else
|
||||
{
|
||||
md_adc_disable_ssen_ss0en(ADC);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static void _adc_channel_config(rt_uint32_t channel)
|
||||
{
|
||||
/* select gpio pin as adc function */
|
||||
switch (channel)
|
||||
{
|
||||
case 0:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_0, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 1:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_1, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 2:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_2, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 3:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_3, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 4:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_4, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 5:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_5, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 6:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_6, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
case 7:
|
||||
md_gpio_set_mode(GPIOA, MD_GPIO_PIN_7, MD_GPIO_MODE_ANALOG);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
|
||||
{
|
||||
rt_uint32_t chn_data[BSP_ADC_CHANNEL_NUM];
|
||||
rt_uint32_t i;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(value != RT_NULL);
|
||||
|
||||
/* config adc channel */
|
||||
_adc_channel_config(channel);
|
||||
|
||||
md_adc_set_swtri_ss0(ADC);
|
||||
|
||||
while ((ADC->RIF & ADC_RIF_SS0RIF_MSK) == 0);
|
||||
|
||||
for (i=0; i<BSP_ADC_CHANNEL_NUM; i++)
|
||||
chn_data[i] = md_adc_get_ss0_data(ADC);
|
||||
|
||||
*value = chn_data[channel];
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_adc_ops es32f0_adc_ops =
|
||||
{
|
||||
es32f0_adc_enabled,
|
||||
es32f0_get_adc_value,
|
||||
};
|
||||
|
||||
int rt_hw_adc_init(void)
|
||||
{
|
||||
int result = RT_EOK;
|
||||
|
||||
md_rcu_enable_apb2en_adcen(RCU);
|
||||
|
||||
md_syscfg_enable_cfg_currgen(SYSCFG);
|
||||
md_syscfg_enable_cfg_vrefen(SYSCFG);
|
||||
md_syscfg_set_cfg_vlrs(SYSCFG, 7);
|
||||
|
||||
md_adc_set_ss0_con_sel(ADC, MD_ADC_SS_CON_SEL_SW);
|
||||
md_adc_set_ss0_con_type(ADC, MD_ADC_SS_CON_TYPE_EDGE);
|
||||
md_adc_set_frf_ffrst(ADC);
|
||||
md_adc_set_ss0_mux0_mux7(ADC, MD_ADC_SS_MUX_ADIN7);
|
||||
md_adc_set_ss0_mux0_mux6(ADC, MD_ADC_SS_MUX_ADIN6);
|
||||
md_adc_set_ss0_mux0_mux5(ADC, MD_ADC_SS_MUX_ADIN5);
|
||||
md_adc_set_ss0_mux0_mux4(ADC, MD_ADC_SS_MUX_ADIN4);
|
||||
md_adc_set_ss0_mux0_mux3(ADC, MD_ADC_SS_MUX_ADIN3);
|
||||
md_adc_set_ss0_mux0_mux2(ADC, MD_ADC_SS_MUX_ADIN2);
|
||||
md_adc_set_ss0_mux0_mux1(ADC, MD_ADC_SS_MUX_ADIN1);
|
||||
md_adc_set_ss0_mux0_mux0(ADC, MD_ADC_SS_MUX_ADIN0);
|
||||
md_adc_enable_ier_ss0ie(ADC);
|
||||
md_adc_set_ss0_end_end(ADC, 7);
|
||||
md_adc_enable_ss0_end_ie7(ADC);
|
||||
md_adc_set_gainl_ch7pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch6pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch5pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch4pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch3pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch2pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch1pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_gainl_ch0pga(ADC, MD_ADC_GAIN_CHPGA_X2);
|
||||
md_adc_set_srate(ADC, MD_ADC_SRATE_CLKDIV1 | ADC_SRATE_CKEN_MSK);
|
||||
|
||||
rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, ADC);
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_adc_init);
|
||||
|
||||
#endif
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_ADC_H__
|
||||
#define DRV_ADC_H__
|
||||
|
||||
int rt_hw_adc_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_GPIO_H__
|
||||
#define DRV_GPIO_H__
|
||||
|
||||
int rt_hw_pin_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,174 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <drv_hwtimer.h>
|
||||
#include <board.h>
|
||||
#include "md_ad16c4t.h"
|
||||
#include "md_rcu.h"
|
||||
|
||||
#ifdef RT_USING_HWTIMER
|
||||
|
||||
/* Defien the hardware timer control struct */
|
||||
struct es32f0_hwtimer_dev
|
||||
{
|
||||
rt_hwtimer_t parent;
|
||||
AD16C4T_TypeDef *hwtimer_periph;
|
||||
IRQn_Type IRQn;
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_HWTIMER1
|
||||
static struct es32f0_hwtimer_dev hwtimer1;
|
||||
|
||||
void BS16T1_IRQHandler(void)
|
||||
{
|
||||
/* if BS16T1 IT */
|
||||
if (BS16T1->IFM & AD16C4T_RIF_UI_MSK)
|
||||
{
|
||||
SET_BIT(BS16T1->ICR, AD16C4T_ICR_UI_MSK);
|
||||
rt_device_hwtimer_isr(&hwtimer1.parent);
|
||||
|
||||
if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
|
||||
{
|
||||
CLEAR_BIT(BS16T1->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct rt_hwtimer_info es32f0_hwtimer_info =
|
||||
{
|
||||
48000000, /* maximum count frequency */
|
||||
1, /* minimum count frequency */
|
||||
65535, /* counter maximum value */
|
||||
HWTIMER_CNTMODE_UP
|
||||
};
|
||||
|
||||
static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
|
||||
{
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
if (1 == state)
|
||||
{
|
||||
/* Set frequency */
|
||||
WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/hwtimer->parent.freq - 1));
|
||||
/* Enable timer IT */
|
||||
SET_BIT(hwtimer->hwtimer_periph->IER, AD16C4T_IER_UI_MSK);
|
||||
NVIC_EnableIRQ(hwtimer->IRQn);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Dsiable timer IT */
|
||||
SET_BIT(hwtimer->hwtimer_periph->IDR, AD16C4T_IER_UI_MSK);
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
|
||||
rt_uint32_t cnt,
|
||||
rt_hwtimer_mode_t mode)
|
||||
{
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
WRITE_REG(hwtimer->hwtimer_periph->AR, cnt);
|
||||
SET_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static void es32f0_hwtimer_stop(rt_hwtimer_t *timer)
|
||||
{
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
}
|
||||
|
||||
static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer)
|
||||
{
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
uint32_t hwtimer_count = 0;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
hwtimer_count = READ_REG(hwtimer->hwtimer_periph->COUNT);
|
||||
|
||||
return hwtimer_count;
|
||||
}
|
||||
|
||||
static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
|
||||
rt_uint32_t cmd,
|
||||
void *args)
|
||||
{
|
||||
rt_err_t ret = RT_EOK;
|
||||
rt_uint32_t freq = 0;
|
||||
struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
|
||||
|
||||
RT_ASSERT(hwtimer != RT_NULL);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case HWTIMER_CTRL_FREQ_SET:
|
||||
freq = *(rt_uint32_t *)args;
|
||||
if ((freq < hwtimer->parent.info->minfreq) || (freq > hwtimer->parent.info->maxfreq))
|
||||
{
|
||||
ret = RT_EINVAL;
|
||||
}
|
||||
/* Set frequency */
|
||||
WRITE_REG(hwtimer->hwtimer_periph->PRES, (SystemCoreClock/freq - 1));
|
||||
break;
|
||||
|
||||
case HWTIMER_CTRL_STOP:
|
||||
CLEAR_BIT(hwtimer->hwtimer_periph->CON1, AD16C4T_CON1_CNTEN_MSK);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = RT_EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct rt_hwtimer_ops es32f0_hwtimer_ops =
|
||||
{
|
||||
es32f0_hwtimer_init,
|
||||
es32f0_hwtimer_start,
|
||||
es32f0_hwtimer_stop,
|
||||
es32f0_hwtimer_count_get,
|
||||
es32f0_hwtimer_control
|
||||
};
|
||||
|
||||
int rt_hw_hwtimer_init(void)
|
||||
{
|
||||
rt_err_t ret = RT_EOK;
|
||||
|
||||
#ifdef BSP_USING_HWTIMER1
|
||||
/*Open clock*/
|
||||
SET_BIT(RCU->APB1EN, RCU_APB1EN_BS16T1EN_MSK);
|
||||
|
||||
hwtimer1.hwtimer_periph = BS16T1;
|
||||
hwtimer1.IRQn = BS16T1_IRQn;
|
||||
hwtimer1.parent.info = &es32f0_hwtimer_info;
|
||||
hwtimer1.parent.ops = &es32f0_hwtimer_ops;
|
||||
ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
|
||||
|
||||
#endif
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_HWTIMER_H__
|
||||
#define DRV_HWTIMER_H__
|
||||
|
||||
int rt_hw_hwtimer_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_I2C_H__
|
||||
#define DRV_I2C_H__
|
||||
|
||||
int rt_hw_i2c_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_PWM_H__
|
||||
#define DRV_PWM_H__
|
||||
|
||||
int rt_hw_pwm_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_RTC_H__
|
||||
#define DRV_RTC_H__
|
||||
|
||||
int rt_hw_rtc_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,22 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_SPI_H__
|
||||
#define DRV_SPI_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
///* cannot be used before completion init */
|
||||
//rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name);
|
||||
int rt_hw_spi_init(void);
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-23 yuzrain the first version
|
||||
*/
|
||||
|
||||
#ifndef DRV_UART_H__
|
||||
#define DRV_UART_H__
|
||||
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
#endif
|
||||
@@ -1,14 +0,0 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x00000000 0x10000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x10000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x2000{ ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
Binary file not shown.
File diff suppressed because it is too large.
Load diff
-683
File diff suppressed because it is too large.
Load diff
-795
File diff suppressed because it is too large.
Load diff
-193
@@ -1,193 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_AES.h
|
||||
* @brief AES Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 11/16/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __AES_H__
|
||||
#define __AES_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for AES_CON register ************************/
|
||||
|
||||
#define AES_CON_READY_POS 22U
|
||||
#define AES_CON_READY_MSK BIT(AES_CON_READY_POS)
|
||||
|
||||
#define AES_CON_OT_DMA_ST_POS 21U
|
||||
#define AES_CON_OT_DMA_ST_MSK BIT(AES_CON_OT_DMA_ST_POS)
|
||||
|
||||
#define AES_CON_IT_DMA_ST_POS 20U
|
||||
#define AES_CON_IT_DMA_ST_MSK BIT(AES_CON_IT_DMA_ST_POS)
|
||||
|
||||
#define AES_CON_OT_DEPTH_POSS 18U
|
||||
#define AES_CON_OT_DEPTH_POSE 19U
|
||||
#define AES_CON_OT_DEPTH_MSK BITS(AES_CON_OT_DEPTH_POSS,AES_CON_OT_DEPTH_POSE)
|
||||
|
||||
#define AES_CON_IT_DEPTH_POSS 16U
|
||||
#define AES_CON_IT_DEPTH_POSE 17U
|
||||
#define AES_CON_IT_DEPTH_MSK BITS(AES_CON_IT_DEPTH_POSS,AES_CON_IT_DEPTH_POSE)
|
||||
|
||||
#define AES_CON_RE_INIT_POS 8U
|
||||
#define AES_CON_RE_INIT_MSK BIT(AES_CON_RE_INIT_POS)
|
||||
|
||||
#define AES_CON_DMA_EN_POSS 6U
|
||||
#define AES_CON_DMA_EN_POSE 7U
|
||||
#define AES_CON_DMA_EN_MSK BITS(AES_CON_DMA_EN_POSS,AES_CON_DMA_EN_POSE)
|
||||
|
||||
#define AES_CON_BL_POSS 3U
|
||||
#define AES_CON_BL_POSE 5U
|
||||
#define AES_CON_BL_MSK BITS(AES_CON_BL_POSS,AES_CON_BL_POSE)
|
||||
|
||||
#define AES_CON_REV_POS 2U
|
||||
#define AES_CON_REV_MSK BIT(AES_CON_REV_POS)
|
||||
|
||||
#define AES_CON_MODE_POS 1U
|
||||
#define AES_CON_MODE_MSK BIT(AES_CON_MODE_POS)
|
||||
|
||||
#define AES_CON_START_POS 0U
|
||||
#define AES_CON_START_MSK BIT(AES_CON_START_POS)
|
||||
|
||||
/****************** Bit definition for AES_IER register ************************/
|
||||
|
||||
#define AES_IER_DECIE_POS 1U
|
||||
#define AES_IER_DECIE_MSK BIT(AES_IER_DECIE_POS)
|
||||
|
||||
#define AES_IER_ENCIE_POS 0U
|
||||
#define AES_IER_ENCIE_MSK BIT(AES_IER_ENCIE_POS)
|
||||
|
||||
/****************** Bit definition for AES_IDR register ************************/
|
||||
|
||||
#define AES_IDR_DECID_POS 1U
|
||||
#define AES_IDR_DECID_MSK BIT(AES_IDR_DECID_POS)
|
||||
|
||||
#define AES_IDR_ENCID_POS 0U
|
||||
#define AES_IDR_ENCID_MSK BIT(AES_IDR_ENCID_POS)
|
||||
|
||||
/****************** Bit definition for AES_IVS register ************************/
|
||||
|
||||
#define AES_IVS_DECIVS_POS 1U
|
||||
#define AES_IVS_DECIVS_MSK BIT(AES_IVS_DECIVS_POS)
|
||||
|
||||
#define AES_IVS_ENCIVS_POS 0U
|
||||
#define AES_IVS_ENCIVS_MSK BIT(AES_IVS_ENCIVS_POS)
|
||||
|
||||
/****************** Bit definition for AES_RIF register ************************/
|
||||
|
||||
#define AES_RIF_DECRIF_POS 1U
|
||||
#define AES_RIF_DECRIF_MSK BIT(AES_RIF_DECRIF_POS)
|
||||
|
||||
#define AES_RIF_ENCRIF_POS 0U
|
||||
#define AES_RIF_ENCRIF_MSK BIT(AES_RIF_ENCRIF_POS)
|
||||
|
||||
/****************** Bit definition for AES_IFM register ************************/
|
||||
|
||||
#define AES_IFM_DECIFM_POS 1U
|
||||
#define AES_IFM_DECIFM_MSK BIT(AES_IFM_DECIFM_POS)
|
||||
|
||||
#define AES_IFM_ENCIFM_POS 0U
|
||||
#define AES_IFM_ENCIFM_MSK BIT(AES_IFM_ENCIFM_POS)
|
||||
|
||||
/****************** Bit definition for AES_ICR register ************************/
|
||||
|
||||
#define AES_ICR_DECICR_POS 1U
|
||||
#define AES_ICR_DECICR_MSK BIT(AES_ICR_DECICR_POS)
|
||||
|
||||
#define AES_ICR_ENCICR_POS 0U
|
||||
#define AES_ICR_ENCICR_MSK BIT(AES_ICR_ENCICR_POS)
|
||||
|
||||
/****************** Bit definition for AES_DIO register ************************/
|
||||
|
||||
#define AES_DIO_DIO_POSS 0U
|
||||
#define AES_DIO_DIO_POSE 31U
|
||||
#define AES_DIO_DIO_MSK BITS(AES_DIO_DIO_POSS,AES_DIO_DIO_POSE)
|
||||
|
||||
/****************** Bit definition for AES_KEY0 register ************************/
|
||||
|
||||
#define AES_KEY0_KEY0_POSS 0U
|
||||
#define AES_KEY0_KEY0_POSE 31U
|
||||
#define AES_KEY0_KEY0_MSK BITS(AES_KEY0_KEY0_POSS,AES_KEY0_KEY0_POSE)
|
||||
|
||||
/****************** Bit definition for AES_KEY1 register ************************/
|
||||
|
||||
#define AES_KEY1_KEY1_POSS 0U
|
||||
#define AES_KEY1_KEY1_POSE 31U
|
||||
#define AES_KEY1_KEY1_MSK BITS(AES_KEY1_KEY1_POSS,AES_KEY1_KEY1_POSE)
|
||||
|
||||
/****************** Bit definition for AES_KEY2 register ************************/
|
||||
|
||||
#define AES_KEY2_KEY2_POSS 0U
|
||||
#define AES_KEY2_KEY2_POSE 31U
|
||||
#define AES_KEY2_KEY2_MSK BITS(AES_KEY2_KEY2_POSS,AES_KEY2_KEY2_POSE)
|
||||
|
||||
/****************** Bit definition for AES_KEY3 register ************************/
|
||||
|
||||
#define AES_KEY3_KEY3_POSS 0U
|
||||
#define AES_KEY3_KEY3_POSE 31U
|
||||
#define AES_KEY3_KEY3_MSK BITS(AES_KEY3_KEY3_POSS,AES_KEY3_KEY3_POSE)
|
||||
|
||||
/****************** Bit definition for AES_IV0 register ************************/
|
||||
|
||||
#define AES_IV0_IV0_POSS 0U
|
||||
#define AES_IV0_IV0_POSE 31U
|
||||
#define AES_IV0_IV0_MSK BITS(AES_IV0_IV0_POSS,AES_IV0_IV0_POSE)
|
||||
|
||||
/****************** Bit definition for AES_IV1 register ************************/
|
||||
|
||||
#define AES_IV1_IV1_POSS 0U
|
||||
#define AES_IV1_IV1_POSE 31U
|
||||
#define AES_IV1_IV1_MSK BITS(AES_IV1_IV1_POSS,AES_IV1_IV1_POSE)
|
||||
|
||||
/****************** Bit definition for AES_IV2 register ************************/
|
||||
|
||||
#define AES_IV2_IV2_POSS 0U
|
||||
#define AES_IV2_IV2_POSE 31U
|
||||
#define AES_IV2_IV2_MSK BITS(AES_IV2_IV2_POSS,AES_IV2_IV2_POSE)
|
||||
|
||||
/****************** Bit definition for AES_IV3 register ************************/
|
||||
|
||||
#define AES_IV3_IV3_POSS 0U
|
||||
#define AES_IV3_IV3_POSE 31U
|
||||
#define AES_IV3_IV3_MSK BITS(AES_IV3_IV3_POSS,AES_IV3_IV3_POSE)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CON; /* 0x000 AES_CON AES Control Register */
|
||||
__O uint32_t IER; /* 0x004 AES_IER AES Interrupt Enable Register */
|
||||
__O uint32_t IDR; /* 0x008 AES_IDR AES Interrupt Disable Register */
|
||||
__I uint32_t IVS; /* 0x00C AES_IVS AES Interrupt Valid Status Register */
|
||||
__I uint32_t RIF; /* 0x010 AES_RIF AES Raw Interrupt Flag Status Register */
|
||||
__I uint32_t IFM; /* 0x014 AES_IFM AES Interrupt Flag Masked Register */
|
||||
__O uint32_t ICR; /* 0x018 AES_ICR AES Interrupt Clear Register */
|
||||
__IO uint32_t DIO; /* 0x01C AES_DIO AES 128-bit Input/Output Data Register */
|
||||
__IO uint32_t KEY0; /* 0x020 AES_KEY0 AES 256-bit Keyword Register 0 */
|
||||
__IO uint32_t KEY1; /* 0x024 AES_KEY1 AES 256-bit Keyword Register 1 */
|
||||
__IO uint32_t KEY2; /* 0x028 AES_KEY2 AES 256-bit Keyword Register 2 */
|
||||
__IO uint32_t KEY3; /* 0x02C AES_KEY3 AES 256-bit Keyword Register 3 */
|
||||
uint32_t RESERVED0[4] ;
|
||||
__IO uint32_t IV0; /* 0x040 AES_IV0 AES 128-bit Initial Vector Register 0 */
|
||||
__IO uint32_t IV1; /* 0x044 AES_IV1 AES 128-bit Initial Vector Register 1 */
|
||||
__IO uint32_t IV2; /* 0x048 AES_IV2 AES 128-bit Initial Vector Register 2 */
|
||||
__IO uint32_t IV3; /* 0x04C AES_IV3 AES 128-bit Initial Vector Register 3 */
|
||||
} AES_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-95
@@ -1,95 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_CMP.h
|
||||
* @brief CMP Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 12/3/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __CMP_H__
|
||||
#define __CMP_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for CMP_CON register ************************/
|
||||
|
||||
#define CMP_CON_REFON_POS 4U
|
||||
#define CMP_CON_REFON_MSK BIT(CMP_CON_REFON_POS)
|
||||
|
||||
#define CMP_CON_CMPON2_POS 1U
|
||||
#define CMP_CON_CMPON2_MSK BIT(CMP_CON_CMPON2_POS)
|
||||
|
||||
#define CMP_CON_CMPON1_POS 0U
|
||||
#define CMP_CON_CMPON1_MSK BIT(CMP_CON_CMPON1_POS)
|
||||
|
||||
/****************** Bit definition for CMP_CFG1 register ************************/
|
||||
|
||||
#define CMP_CFG1_RS_POSS 4U
|
||||
#define CMP_CFG1_RS_POSE 5U
|
||||
#define CMP_CFG1_RS_MSK BITS(CMP_CFG1_RS_POSS,CMP_CFG1_RS_POSE)
|
||||
|
||||
#define CMP_CFG1_FEN_POS 3U
|
||||
#define CMP_CFG1_FEN_MSK BIT(CMP_CFG1_FEN_POS)
|
||||
|
||||
#define CMP_CFG1_PSEN_POS 2U
|
||||
#define CMP_CFG1_PSEN_MSK BIT(CMP_CFG1_PSEN_POS)
|
||||
|
||||
#define CMP_CFG1_INSEL_POS 1U
|
||||
#define CMP_CFG1_INSEL_MSK BIT(CMP_CFG1_INSEL_POS)
|
||||
|
||||
#define CMP_CFG1_IPSEL_POS 0U
|
||||
#define CMP_CFG1_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS)
|
||||
|
||||
/****************** Bit definition for CMP_CFG2 register ************************/
|
||||
|
||||
#define CMP_CFG2_RS_POSS 4U
|
||||
#define CMP_CFG2_RS_POSE 5U
|
||||
#define CMP_CFG2_RS_MSK BITS(CMP_CFG2_RS_POSS,CMP_CFG2_RS_POSE)
|
||||
|
||||
#define CMP_CFG2_FEN_POS 3U
|
||||
#define CMP_CFG2_FEN_MSK BIT(CMP_CFG1_FEN_POS)
|
||||
|
||||
#define CMP_CFG2_PSEN_POS 2U
|
||||
#define CMP_CFG2_PSEN_MSK BIT(CMP_CFG1_PSEN_POS)
|
||||
|
||||
#define CMP_CFG2_INSEL_POS 1U
|
||||
#define CMP_CFG2_INSEL_MSK BIT(CMP_CFG1_INSEL_POS)
|
||||
|
||||
#define CMP_CFG2_IPSEL_POS 0U
|
||||
#define CMP_CFG2_IPSEL_MSK BIT(CMP_CFG1_IPSEL_POS)
|
||||
|
||||
/****************** Bit definition for CMP_RULT register ************************/
|
||||
|
||||
#define CMP_RULT_CMPO2_POS 1U
|
||||
#define CMP_RULT_CMPO2_MSK BIT(CMP_RULT_CMPO2_POS)
|
||||
|
||||
#define CMP_RULT_CMPO1_POS 0U
|
||||
#define CMP_RULT_CMPO1_MSK BIT(CMP_RULT_CMPO1_POS)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CON;
|
||||
__IO uint32_t CFG1;
|
||||
__IO uint32_t CFG2;
|
||||
uint32_t RESERVED0[2] ;
|
||||
__I uint32_t RULT;
|
||||
} CMP_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-125
@@ -1,125 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_CRC.h
|
||||
* @brief CRC Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 11/16/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __CRC_H__
|
||||
#define __CRC_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for CRC_INIT register ************************/
|
||||
|
||||
#define CRC_INIT_INIT_POSS 0U
|
||||
#define CRC_INIT_INIT_POSE 31U
|
||||
#define CRC_INIT_INIT_MSK BITS(CRC_INIT_INIT_POSS,CRC_INIT_INIT_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_POLY register ************************/
|
||||
|
||||
#define CRC_POLY_POLY_POSS 0U
|
||||
#define CRC_POLY_POLY_POSE 31U
|
||||
#define CRC_POLY_POLY_MSK BITS(CRC_POLY_POLY_POSS,CRC_POLY_POLY_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_DATA register ************************/
|
||||
|
||||
#define CRC_DATA_DATA_POSS 0U
|
||||
#define CRC_DATA_DATA_POSE 31U
|
||||
#define CRC_DATA_DATA_MSK BITS(CRC_DATA_DATA_POSS,CRC_DATA_DATA_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_COMP register ************************/
|
||||
|
||||
#define CRC_COMP_COMP_POSS 0U
|
||||
#define CRC_COMP_COMP_POSE 31U
|
||||
#define CRC_COMP_COMP_MSK BITS(CRC_COMP_COMP_POSS,CRC_COMP_COMP_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_REMA register ************************/
|
||||
|
||||
#define CRC_REMA_REMA_POSS 0U
|
||||
#define CRC_REMA_REMA_POSE 31U
|
||||
#define CRC_REMA_REMA_MSK BITS(CRC_REMA_REMA_POSS,CRC_REMA_REMA_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_CON register ************************/
|
||||
|
||||
#define CRC_CON_DMA_POS 16U
|
||||
#define CRC_CON_DMA_MSK BIT(CRC_CON_DMA_POS)
|
||||
|
||||
#define CRC_CON_MSB_POS 12U
|
||||
#define CRC_CON_MSB_MSK BIT(CRC_CON_MSB_POS)
|
||||
|
||||
#define CRC_CON_REOUT_POS 10U
|
||||
#define CRC_CON_REOUT_MSK BIT(CRC_CON_REOUT_POS)
|
||||
|
||||
#define CRC_CON_REIN_POS 8U
|
||||
#define CRC_CON_REIN_MSK BIT(CRC_CON_REIN_POS)
|
||||
|
||||
#define CRC_CON_SIZE_POSS 4U
|
||||
#define CRC_CON_SIZE_POSE 5U
|
||||
#define CRC_CON_SIZE_MSK BITS(CRC_CON_SIZE_POSS,CRC_CON_SIZE_POSE)
|
||||
|
||||
#define CRC_CON_MODE_POSS 2U
|
||||
#define CRC_CON_MODE_POSE 3U
|
||||
#define CRC_CON_MODE_MSK BITS(CRC_CON_MODE_POSS,CRC_CON_MODE_POSE)
|
||||
|
||||
#define CRC_CON_RESET_POS 0U
|
||||
#define CRC_CON_RESET_MSK BIT(CRC_CON_RESET_POS)
|
||||
|
||||
/****************** Bit definition for CRC_DOUT register ************************/
|
||||
|
||||
#define CRC_DOUT_DOUT_POSS 0U
|
||||
#define CRC_DOUT_DOUT_POSE 31U
|
||||
#define CRC_DOUT_DOUT_MSK BITS(CRC_DOUT_DOUT_POSS,CRC_DOUT_DOUT_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_DOUT_XOR register ************************/
|
||||
|
||||
#define CRC_DOUT_XOR_DOUT_XOR_POSS 0U
|
||||
#define CRC_DOUT_XOR_DOUT_XOR_POSE 31U
|
||||
#define CRC_DOUT_XOR_DOUT_XOR_MSK BITS(CRC_DOUT_XOR_DOUT_XOR_POSS,CRC_DOUT_XOR_DOUT_XOR_POSE)
|
||||
|
||||
/****************** Bit definition for CRC_STAT register ************************/
|
||||
|
||||
#define CRC_STAT_FAIL_POS 8U
|
||||
#define CRC_STAT_FAIL_MSK BIT(CRC_STAT_FAIL_POS)
|
||||
|
||||
#define CRC_STAT_EMPTY_POS 2U
|
||||
#define CRC_STAT_EMPTY_MSK BIT(CRC_STAT_EMPTY_POS)
|
||||
|
||||
#define CRC_STAT_BUSY_POS 1U
|
||||
#define CRC_STAT_BUSY_MSK BIT(CRC_STAT_BUSY_POS)
|
||||
|
||||
#define CRC_STAT_DONE_POS 0U
|
||||
#define CRC_STAT_DONE_MSK BIT(CRC_STAT_DONE_POS)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t INIT; /* 0x000 CRC_INIT CRC Iintial Value Register */
|
||||
__IO uint32_t POLY; /* 0x004 CRC_POLY CRC Polynomial Register */
|
||||
__IO uint32_t DATA; /* 0x008 CRC_DATA CRC Input Data Register */
|
||||
__IO uint32_t COMP; /* 0x00C CRC_COMP CRC Compare Data Register */
|
||||
__IO uint32_t REMA; /* 0x010 CRC_REMA CRC Remainder Register */
|
||||
__IO uint32_t CON; /* 0x014 CRC_CTRL CRC Control Register */
|
||||
__I uint32_t DOUT; /* 0x018 CRC_DOUT CRC Output Data Register */
|
||||
__I uint32_t DOUT_XOR; /* 0x01C CRC_DOUT_XOR CRC Output Data Register */
|
||||
__I uint32_t STAT; /* 0x020 CRC_STA CRC Status Register */
|
||||
} CRC_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-97
@@ -1,97 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_DAC.h
|
||||
* @brief DAC Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 1/14/2019
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __DAC_H__
|
||||
#define __DAC_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for DAC_CON register ************************/
|
||||
|
||||
#define DAC_CON_T_SEL_POSS 9U
|
||||
#define DAC_CON_T_SEL_POSE 13U
|
||||
#define DAC_CON_T_SEL_MSK BITS(DAC_CON_T_SEL_POSS,DAC_CON_T_SEL_POSE)
|
||||
|
||||
#define DAC_CON_TRIEN_POS 8U
|
||||
#define DAC_CON_TRIEN_MSK BIT(DAC_CON_TRIEN_POS)
|
||||
|
||||
#define DAC_CON_MAMP_POSS 3U
|
||||
#define DAC_CON_MAMP_POSE 6U
|
||||
#define DAC_CON_MAMP_MSK BITS(DAC_CON_MAMP_POSS,DAC_CON_MAMP_POSE)
|
||||
|
||||
#define DAC_CON_WAVE_POSS 1U
|
||||
#define DAC_CON_WAVE_POSE 2U
|
||||
#define DAC_CON_WAVE_MSK BITS(DAC_CON_WAVE_POSS,DAC_CON_WAVE_POSE)
|
||||
|
||||
#define DAC_CON_INVREN_POS 0U
|
||||
#define DAC_CON_INVREN_MSK BIT(DAC_CON_INVREN_POS)
|
||||
|
||||
/****************** Bit definition for DAC_DIV register ************************/
|
||||
|
||||
#define DAC_DIV_DIV_VALUE_POSS 0U
|
||||
#define DAC_DIV_DIV_VALUE_POSE 15U
|
||||
#define DAC_DIV_DIV_VALUE_MSK BITS(DAC_DIV_DIV_VALUE_POSS,DAC_DIV_DIV_VALUE_POSE)
|
||||
|
||||
/****************** Bit definition for DAC_STAT register ************************/
|
||||
|
||||
#define DAC_STAT_TX_FULL_POS 1U
|
||||
#define DAC_STAT_TX_FULL_MSK BIT(DAC_STAT_TX_FULL_POS)
|
||||
|
||||
#define DAC_STAT_BUSY_POS 0U
|
||||
#define DAC_STAT_BUSY_MSK BIT(DAC_STAT_BUSY_POS)
|
||||
|
||||
/****************** Bit definition for DAC_EN register ************************/
|
||||
|
||||
#define DAC_EN_DAC_EN_POS 0U
|
||||
#define DAC_EN_DAC_EN_MSK BIT(DAC_EN_DAC_EN_POS)
|
||||
|
||||
/****************** Bit definition for DAC_DMAC register ************************/
|
||||
|
||||
#define DAC_DMAC_TXDMAEN_POS 0U
|
||||
#define DAC_DMAC_TXDMAEN_MSK BIT(DAC_DMAC_TXDMAEN_POS)
|
||||
|
||||
/****************** Bit definition for DAC_TRIG register ************************/
|
||||
|
||||
#define DAC_TRIG_S_TRIG_POS 0U
|
||||
#define DAC_TRIG_S_TRIG_MSK BIT(DAC_TRIG_S_TRIG_POS)
|
||||
|
||||
/****************** Bit definition for DAC_DATA register ************************/
|
||||
|
||||
#define DAC_DATA_TXDATA_POSS 0U
|
||||
#define DAC_DATA_TXDATA_POSE 11U
|
||||
#define DAC_DATA_TXDATA_MSK BITS(DAC_DATA_TXDATA_POSS,DAC_DATA_TXDATA_POSE)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CON;
|
||||
__IO uint32_t DIV;
|
||||
__I uint32_t STAT;
|
||||
__IO uint32_t EN;
|
||||
__IO uint32_t DMAC;
|
||||
__O uint32_t TRIG;
|
||||
__IO uint32_t DATA;
|
||||
} DAC_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-825
File diff suppressed because it is too large.
Load diff
-809
File diff suppressed because it is too large.
Load diff
-181
@@ -1,181 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_FC.h
|
||||
* @brief FC Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 12/3/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __fc_H__
|
||||
#define __fc_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for FC_CMD register ************************/
|
||||
|
||||
#define FC_CMD_FC_CMD_POSS 0U
|
||||
#define FC_CMD_FC_CMD_POSE 7U
|
||||
#define FC_CMD_FC_CMD_MSK BITS(FC_CMD_FC_CMD_POSS,FC_CMD_FC_CMD_POSE)
|
||||
|
||||
/****************** Bit definition for FC_PA register ************************/
|
||||
|
||||
#define FC_PA_PCNT_POSS 25U
|
||||
#define FC_PA_PCNT_POSE 31U
|
||||
#define FC_PA_PCNT_MSK BITS(FC_PA_PCNT_POSS,FC_PA_PCNT_POSE)
|
||||
|
||||
#define FC_PA_IFREN_POS 24U
|
||||
#define FC_PA_IFREN_MSK BIT(FC_PA_IFREN_POS)
|
||||
|
||||
#define FC_PA_PROG_ADDR_POSS 0U
|
||||
#define FC_PA_PROG_ADDR_POSE 23U
|
||||
#define FC_PA_PROG_ADDR_MSK BITS(FC_PA_PROG_ADDR_POSS,FC_PA_PROG_ADDR_POSE)
|
||||
|
||||
/****************** Bit definition for FC_PLD register ************************/
|
||||
|
||||
#define FC_PLD_PROG_DATA_L_POSS 0U
|
||||
#define FC_PLD_PROG_DATA_L_POSE 31U
|
||||
#define FC_PLD_PROG_DATA_L_MSK BITS(FC_PLD_PROG_DATA_L_POSS,FC_PLD_PROG_DATA_L_POSE)
|
||||
|
||||
/****************** Bit definition for FC_PHD register ************************/
|
||||
|
||||
#define FC_PHD_PROG_DATA_H_POSS 0U
|
||||
#define FC_PHD_PROG_DATA_H_POSE 31U
|
||||
#define FC_PHD_PROG_DATA_H_MSK BITS(FC_PHD_PROG_DATA_H_POSS,FC_PHD_PROG_DATA_H_POSE)
|
||||
|
||||
/****************** Bit definition for FC_CON register ************************/
|
||||
|
||||
#define FC_CON_SLEEP_POS 9U
|
||||
#define FC_CON_SLEEP_MSK BIT(FC_CON_SLEEP_POS)
|
||||
|
||||
#define FC_CON_PFEN_POS 8U
|
||||
#define FC_CON_PFEN_MSK BIT(FC_CON_PFEN_POS)
|
||||
|
||||
#define FC_CON_WAIT_POSS 0U
|
||||
#define FC_CON_WAIT_POSE 1U
|
||||
#define FC_CON_WAIT_MSK BITS(FC_CON_WAIT_POSS,FC_CON_WAIT_POSE)
|
||||
|
||||
/****************** Bit definition for FC_STAT register ************************/
|
||||
|
||||
#define FC_STAT_OPVD_POS 2U
|
||||
#define FC_STAT_OPVD_MSK BIT(FC_STAT_OPVD_POS)
|
||||
|
||||
#define FC_STAT_MUNP2_POS 1U
|
||||
#define FC_STAT_MUNP2_MSK BIT(FC_STAT_MUNP2_POS)
|
||||
|
||||
#define FC_STAT_MUNP1_POS 0U
|
||||
#define FC_STAT_MUNP1_MSK BIT(FC_STAT_MUNP1_POS)
|
||||
|
||||
/****************** Bit definition for FC_UPL register ************************/
|
||||
|
||||
#define FC_UPL_UPL_POSS 0U
|
||||
#define FC_UPL_UPL_POSE 31U
|
||||
#define FC_UPL_UPL_MSK BITS(FC_UPL_UPL_POSS,FC_UPL_UPL_POSE)
|
||||
|
||||
/****************** Bit definition for FC_UPH register ************************/
|
||||
|
||||
#define FC_UPH_UPH_POSS 0U
|
||||
#define FC_UPH_UPH_POSE 31U
|
||||
#define FC_UPH_UPH_MSK BITS(FC_UPH_UPH_POSS,FC_UPH_UPH_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_TRIM register ************************/
|
||||
|
||||
#define FC_OP_TRIM_BGTRIMVD_POSS 24U
|
||||
#define FC_OP_TRIM_BGTRIMVD_POSE 31U
|
||||
#define FC_OP_TRIM_BGTRIMVD_MSK BITS(FC_OP_TRIM_BGTRIMVD_POSS,FC_OP_TRIM_BGTRIMVD_POSE)
|
||||
|
||||
#define FC_OP_TRIM_BGTRIM_POSS 16U
|
||||
#define FC_OP_TRIM_BGTRIM_POSE 23U
|
||||
#define FC_OP_TRIM_BGTRIM_MSK BITS(FC_OP_TRIM_BGTRIM_POSS,FC_OP_TRIM_BGTRIM_POSE)
|
||||
|
||||
#define FC_OP_TRIM_HRCTRIMVD_POSS 8U
|
||||
#define FC_OP_TRIM_HRCTRIMVD_POSE 15U
|
||||
#define FC_OP_TRIM_HRCTRIMVD_MSK BITS(FC_OP_TRIM_HRCTRIMVD_POSS,FC_OP_TRIM_HRCTRIMVD_POSE)
|
||||
|
||||
#define FC_OP_TRIM_HRCTRIM_POSS 0U
|
||||
#define FC_OP_TRIM_HRCTRIM_POSE 7U
|
||||
#define FC_OP_TRIM_HRCTRIM_MSK BITS(FC_OP_TRIM_HRCTRIM_POSS,FC_OP_TRIM_HRCTRIM_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_PRT2L register ************************/
|
||||
|
||||
#define FC_OP_PRT2L_PRTLV2L_POSS 0U
|
||||
#define FC_OP_PRT2L_PRTLV2L_POSE 31U
|
||||
#define FC_OP_PRT2L_PRTLV2L_MSK BITS(FC_OP_PRT2L_PRTLV2L_POSS,FC_OP_PRT2L_PRTLV2L_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_PRT2H register ************************/
|
||||
|
||||
#define FC_OP_PRT2H_PRTLV2H_POSS 0U
|
||||
#define FC_OP_PRT2H_PRTLV2H_POSE 31U
|
||||
#define FC_OP_PRT2H_PRTLV2H_MSK BITS(FC_OP_PRT2H_PRTLV2H_POSS,FC_OP_PRT2H_PRTLV2H_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_PRT1L register ************************/
|
||||
|
||||
#define FC_OP_PRT1L_PRTLV1L_POSS 0U
|
||||
#define FC_OP_PRT1L_PRTLV1L_POSE 31U
|
||||
#define FC_OP_PRT1L_PRTLV1L_MSK BITS(FC_OP_PRT1L_PRTLV1L_POSS,FC_OP_PRT1L_PRTLV1L_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_PRT1H register ************************/
|
||||
|
||||
#define FC_OP_PRT1H_PRTLV1H_POSS 0U
|
||||
#define FC_OP_PRT1H_PRTLV1H_POSE 31U
|
||||
#define FC_OP_PRT1H_PRTLV1H_MSK BITS(FC_OP_PRT1H_PRTLV1H_POSS,FC_OP_PRT1H_PRTLV1H_POSE)
|
||||
|
||||
/****************** Bit definition for FC_OP_REMAP register ************************/
|
||||
|
||||
#define FC_OP_REMAP_HREMAP_POSS 8U
|
||||
#define FC_OP_REMAP_HREMAP_POSE 15U
|
||||
#define FC_OP_REMAP_HREMAP_MSK BITS(FC_OP_REMAP_HREMAP_POSS,FC_OP_REMAP_HREMAP_POSE)
|
||||
|
||||
#define FC_OP_REMAP_SREMAP_POSS 4U
|
||||
#define FC_OP_REMAP_SREMAP_POSE 5U
|
||||
#define FC_OP_REMAP_SREMAP_MSK BITS(FC_OP_REMAP_SREMAP_POSS,FC_OP_REMAP_SREMAP_POSE)
|
||||
|
||||
#define FC_OP_REMAP_SEFBASE_POSS 0U
|
||||
#define FC_OP_REMAP_SEFBASE_POSE 3U
|
||||
#define FC_OP_REMAP_SEFBASE_MSK BITS(FC_OP_REMAP_SEFBASE_POSS,FC_OP_REMAP_SEFBASE_POSE)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CMD;
|
||||
__IO uint32_t PA;
|
||||
__IO uint32_t PLD;
|
||||
__IO uint32_t PHD;
|
||||
__IO uint32_t CON;
|
||||
__I uint32_t STAT;
|
||||
uint32_t RESERVED0[2] ;
|
||||
__IO uint32_t UPL;
|
||||
__IO uint32_t UPH;
|
||||
uint32_t RESERVED1[2] ;
|
||||
__I uint32_t OP_TRIM;
|
||||
uint32_t RESERVED2[4] ;
|
||||
// uint32_t ADCTRIM_1V;
|
||||
// uint32_t ADCTRIM_2V;
|
||||
// uint32_t RESERVED3;
|
||||
|
||||
uint32_t ADCTRIM_VDD5V_VREF5V;
|
||||
uint32_t ADCTRIM_VDD3V3_VREF3V3;
|
||||
uint32_t ADCTRIM_VDD5V_VREF2V5;
|
||||
__I uint32_t OP_PRT2L;
|
||||
__I uint32_t OP_PRT2H;
|
||||
__I uint32_t OP_PRT1L;
|
||||
__I uint32_t OP_PRT1H;
|
||||
__I uint32_t OP_REMAP;
|
||||
} FC_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-710
File diff suppressed because it is too large.
Load diff
-75
@@ -1,75 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_HDIV.h
|
||||
* @brief HDIV Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 12/3/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __hdiv_H__
|
||||
#define __hdiv_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for HDIV_DIVDR register ************************/
|
||||
|
||||
#define HDIV_DIVDR_DIVS_POSS 0U
|
||||
#define HDIV_DIVDR_DIVS_POSE 31U
|
||||
#define HDIV_DIVDR_DIVD_MSK BITS(HDIV_DIVDR_DIVD_POSS,HDIV_DIVDR_DIVD_POSE)
|
||||
|
||||
/****************** Bit definition for HDIV_DIVSR register ************************/
|
||||
|
||||
#define HDIV_DIVSR_DIVS_POSS 0U
|
||||
#define HDIV_DIVSR_DIVS_POSE 31U
|
||||
#define HDIV_DIVSR_DIVS_MSK BITS(HDIV_DIVSR_DIVS_POSS,HDIV_DIVSR_DIVS_POSE)
|
||||
|
||||
/****************** Bit definition for HDIV_DIVQR register ************************/
|
||||
|
||||
#define HDIV_DIVQR_DIVQ_POSS 0U
|
||||
#define HDIV_DIVQR_DIVQ_POSE 31U
|
||||
#define HDIV_DIVQR_DIVQ_MSK BITS(HDIV_DIVQR_DIVQ_POSS,HDIV_DIVQR_DIVQ_POSE)
|
||||
|
||||
/****************** Bit definition for HDIV_DIVRR register ************************/
|
||||
|
||||
#define HDIV_DIVRR_DIVR_POSS 0U
|
||||
#define HDIV_DIVRR_DIVR_POSE 31U
|
||||
#define HDIV_DIVRR_DIVR_MSK BITS(HDIV_DIVRR_DIVR_POSS,HDIV_DIVRR_DIVR_POSE)
|
||||
|
||||
/****************** Bit definition for HDIV_DIVSTAT register ************************/
|
||||
|
||||
#define HDIV_DIVSTAT_SIGN_POS 2U
|
||||
#define HDIV_DIVSTAT_SIGN_MSK BIT(HDIV_DIVSTAT_SIGN_POS)
|
||||
|
||||
#define HDIV_DIVSTAT_DIV0_POS 1U
|
||||
#define HDIV_DIVSTAT_DIV0_MSK BIT(HDIV_DIVSTAT_DIV0_POS)
|
||||
|
||||
#define HDIV_DIVSTAT_BUSY_POS 0U
|
||||
#define HDIV_DIVSTAT_BUSY_MSK BIT(HDIV_DIVSTAT_BUSY_POS)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t DIVDR;
|
||||
__IO uint32_t DIVSR;
|
||||
__I uint32_t DIVQR;
|
||||
__I uint32_t DIVRR;
|
||||
__I uint32_t DIVSTAT;
|
||||
} HDIV_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
-623
File diff suppressed because it is too large.
Load diff
-73
@@ -1,73 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file reg_IWDG.h
|
||||
* @brief IWDG Head File
|
||||
*
|
||||
* @version V1.00.01
|
||||
* @data 19/10/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __IWDG_H__
|
||||
#define __IWDG_H__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t KR ; /* 0x00 IWDG_KR - Key register */
|
||||
__IO uint32_t PR ; /* 0x04 IWDG_PR - Prescaler register */
|
||||
__IO uint32_t RLR ; /* 0x08 IWDG_RLR - Reload register */
|
||||
__I uint32_t FR ; /* 0x0C IWDG_SR - Status register */
|
||||
__IO uint32_t WINR; /* 0x10 IWDG_WINR - Window register */
|
||||
} IWDG_TypeDef;
|
||||
|
||||
/******************************************************************************/
|
||||
/* ¼È¦s¾¹¤º³¡¦ì¤¸©w¸q */
|
||||
/******************************************************************************/
|
||||
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for IWDG_KR register ************************/
|
||||
|
||||
#define IWDG_KR_KEY_POSS 0U
|
||||
#define IWDG_KR_KEY_POSE 15U
|
||||
#define IWDG_KR_KEY_MSK BITS(IWDG_KR_KEY_POSS,IWDG_KR_KEY_POSE)
|
||||
|
||||
/****************** Bit definition for IWDG_PR register ************************/
|
||||
|
||||
#define IWDG_PR_PR_POSS 0U
|
||||
#define IWDG_PR_PR_POSE 2U
|
||||
#define IWDG_PR_PR_MSK BITS(IWDG_PR_PR_POSS,IWDG_PR_PR_POSE)
|
||||
|
||||
/****************** Bit definition for IWDG_RLR register ************************/
|
||||
|
||||
#define IWDG_RLR_RL_POSS 0U
|
||||
#define IWDG_RLR_RL_POSE 12U
|
||||
#define IWDG_RLR_RL_MSK BITS(IWDG_RLR_RL_POSS,IWDG_RLR_RL_POSE)
|
||||
|
||||
/****************** Bit definition for IWDG_FR register ************************/
|
||||
|
||||
#define IWDG_FR_BUSY_POS 15U
|
||||
#define IWDG_FR_BUSY_MSK BIT(IWDG_FR_BUSY_POS)
|
||||
|
||||
#define IWDG_FR_STR_POS 12U
|
||||
#define IWDG_FR_STR_MSK BIT(IWDG_FR_STR_POS)
|
||||
|
||||
#define IWDG_FR_CNT_POSS 0U
|
||||
#define IWDG_FR_CNT_POSE 11U
|
||||
#define IWDG_FR_CNT_MSK BITS(IWDG_FR_CNT_POSS,IWDG_FR_CNT_POSE)
|
||||
|
||||
/****************** Bit definition for IWDG_WINR register ************************/
|
||||
|
||||
#define IWDG_WINR_WIN_POSS 0U
|
||||
#define IWDG_WINR_WIN_POSE 31U
|
||||
#define IWDG_WINR_WIN_MSK BITS(IWDG_WINR_WIN_POSS,IWDG_WINR_WIN_POSE)
|
||||
|
||||
|
||||
#else
|
||||
/* */
|
||||
#endif
|
||||
-211
File diff suppressed because it is too large.
Load diff
-58
@@ -1,58 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file reg_MSWD.h
|
||||
* @brief WWDG Head File
|
||||
*
|
||||
* @version V1.00.01
|
||||
* @data 19/10/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __MSWD_H__
|
||||
#define __MSWD_H__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CFG; // 0x00 SW_CFG Serial Wire Configure Register
|
||||
__IO uint32_t JTAG2SWD; // 0x04 SW_JTAG2SW Serial Wire JTAG2SWD Register
|
||||
__IO uint32_t LINERESET; // 0x08 SW_LINERESET Serial Wire LINERESET Resister
|
||||
__O uint32_t STS; // 0x0C SW_STS Serial Wire STATUS Register
|
||||
__IO uint32_t DP_IDR_ABORT; // 0x10 SW_DP_IDR_ABORT Serial Wire DP R-IDR W-ABORT Register
|
||||
__IO uint32_t DP_CSR_WCR; // 0x14 SW_DP_CSR_WCR Serial Wire DP R-CSR W-WCR Register
|
||||
__IO uint32_t DP_RESEND_SELECT; // 0x18 SW_DP_RESEND_SELECT Serial Wire DP R-RESEND W-SELECT Register
|
||||
__IO uint32_t DP_RDBUF_ROUTESEL; // 0x1C SW_DP_RDBUF_ROUTESEL Serial Wire DP R-RDBUF W-ROUTESEL Register
|
||||
__IO uint32_t AP_CSW; // 0x20 SW_AP_CSW Serial Wire AP CSW Register
|
||||
__IO uint32_t AP_TAR; // 0x24 SW_AP_TAR Serial Wire AP TAR Register
|
||||
__IO uint32_t AP_DRW; // 0x28 SW_AP_DRW Serial Wire AP DRW Register
|
||||
__IO uint32_t AP_BD0; // 0x2C SW_AP_BD0 Serial Wire AP BD0 Register
|
||||
__IO uint32_t AP_BD1; // 0x30 SW_AP_BD1 Serial Wire AP BD1 Register
|
||||
__IO uint32_t AP_BD2; // 0x34 SW_AP_BD2 Serial Wire AP BD2 Register
|
||||
__IO uint32_t AP_BD3; // 0x38 SW_AP_BD3 Serial Wire AP BD3 Register
|
||||
__IO uint32_t AP_CFG; // 0x3C SW_AP_CFG Serial Wire AP CFG Register
|
||||
__IO uint32_t AP_BASE; // 0x40 SW_AP_BASE Serial Wire AP BASE Register
|
||||
__IO uint32_t AP_IDR; // 0x44 SW_AP_IDR Serial Wire AP IDR Register
|
||||
uint32_t RES0; // 0x48
|
||||
uint32_t RES1; // 0x4C
|
||||
__IO uint32_t ISP_CMD; // 0x50 SW_ISP_CMD Serial Wire ISP Command Register
|
||||
__IO uint32_t ISP_DAT; // 0x54 SW_ISP_DAT Serial Wire ISP Data Register
|
||||
} MSWD_TypeDef;
|
||||
|
||||
/******************************************************************************/
|
||||
/* ¼È¦s¾¹¤º³¡¦ì¤¸©w¸q */
|
||||
/******************************************************************************/
|
||||
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for WWDG_CR register ************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#else
|
||||
/* */
|
||||
#endif
|
||||
-585
File diff suppressed because it is too large.
Load diff
-613
File diff suppressed because it is too large.
Load diff
-444
File diff suppressed because it is too large.
Load diff
-215
File diff suppressed because it is too large.
Load diff
-113
@@ -1,113 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file reg_TICK.h
|
||||
* @brief TICK Head File
|
||||
*
|
||||
* @version V1.00.01
|
||||
* @date 19/10/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __TICK_H__
|
||||
#define __TICK_H__
|
||||
|
||||
/******************************************************************************/
|
||||
/* ¼È¦s¾¹¤º³¡¦ì¤¸©w¸q */
|
||||
/******************************************************************************/
|
||||
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for TICK_CSR register ************************/
|
||||
|
||||
#define TICK_CSR_ENABLE_POS 0U
|
||||
#define TICK_CSR_ENABLE_MSK BIT(TICK_CSR_ENABLE_POS)
|
||||
|
||||
#define TICK_CSR_TICKINT_POS 1U
|
||||
#define TICK_CSR_TICKINT_MSK BIT(TICK_CSR_TICKINT_POS)
|
||||
|
||||
#define TICK_CSR_CLKSOURCE_POS 2U
|
||||
#define TICK_CSR_CLKSOURCE_MSK BIT(TICK_CSR_CLKSOURCE_POS)
|
||||
|
||||
#define TICK_CSR_COUNTFLAG_POS 16U
|
||||
#define TICK_CSR_COUNTFLAG_MSK BIT(TICK_CSR_COUNTFLAG_POS)
|
||||
|
||||
/****************** Bit definition for TICK_RVR register ************************/
|
||||
|
||||
#define TICK_RVR_RELOAD_POSS 0U
|
||||
#define TICK_RVR_RELOAD_POSE 23U
|
||||
#define TICK_RVR_RELOAD_MSK BITS(TICK_RVR_RELOAD_POSS,TICK_RVR_RELOAD_POSE)
|
||||
|
||||
/****************** Bit definition for TICK_CVR register ************************/
|
||||
|
||||
#define TICK_CVR_CURRENT_POSS 0U
|
||||
#define TICK_CVR_CURRENT_POSE 23U
|
||||
#define TICK_CVR_CURRENT_MSK BITS(TICK_CVR_CURRENT_POSS,TICK_CVR_CURRENT_POSE)
|
||||
|
||||
|
||||
/****************** Bit definition for TICK_CALIB register ************************/
|
||||
|
||||
#define TICK_CALIB_TENMS_POSS 0U
|
||||
#define TICK_CALIB_TENMS_POSE 23U
|
||||
#define TICK_CALIB_TENMS_MSK BITS(TICK_CALIB_TENMS_POSS,TICK_CALIB_TENMS_POSE)
|
||||
|
||||
#define TICK_CALIB_SKEW_POS 30U
|
||||
#define TICK_CALIB_SKEW_MSK BIT(TICK_CALIB_SKEW_POS)
|
||||
|
||||
#define TICK_CALIB_NOREF_POS 31U
|
||||
#define TICK_CALIB_NOREF_MSK BIT(TICK_CALIB_NOREF_POS)
|
||||
|
||||
|
||||
/* TICK Register */
|
||||
#define pTICK TICK
|
||||
|
||||
/* TICK CSR Register(TICK_CSR) */
|
||||
#define CSR_COUNTFLAG(x) (x<<16) /* Indicates whether the counter has counted to 0 since the last read of this register
|
||||
0 timer has not counted to 0
|
||||
1 timer has counted to 0 */
|
||||
#define CSR_CLKSOURCE(x) (x<<2) /* Indicates the SysTick clock source:
|
||||
0 SysTick uses the optional external reference clock
|
||||
1 SysTick uses the processor clock */
|
||||
#define CSR_TICKINT(x) (x<<1) /* Indicates whether counting to 0 causes the status of the SysTick exception to change to pending:
|
||||
0 count to 0 does not affect the SysTick exception status
|
||||
1 count to 0 changes the SysTick exception status to pending */
|
||||
#define CSR_ENABLE(x) (x<<0) /* /Indicates the enabled status of the SysTick counter:
|
||||
0 counter is disabled
|
||||
1 counter is operating */
|
||||
|
||||
|
||||
/* TICK RVR Register(TICK_RVR) */
|
||||
#define RVR_RELOAD(x) (x<<0) /* The value to load into the SYST_CVR register when the counter reaches 0 */
|
||||
|
||||
|
||||
/* TICK CVR Register(TICK_CVR) */
|
||||
#define CVR_CURRENT(x) (x<<0) /* Current counter value
|
||||
This is the value of the counter at the time it is sampled */
|
||||
|
||||
|
||||
/* TICK CALIB Register(TICK_CALIB) */
|
||||
#define CALIB_NOREF(x) (x<<31) /* Indicates whether the IMPLEMENTATION DEFINED reference clock is provided:
|
||||
0 the reference clock is implemented
|
||||
1 the reference clock is not implemented
|
||||
When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot be cleared to 0 */
|
||||
#define CALIB_SKEW(x) (x<<30) /* Indicates whether the 10ms calibration value is exact:
|
||||
0 10ms calibration value is exact
|
||||
1 10ms calibration value is inexact, because of the clock frequency */
|
||||
#define CALIB_TENMS(x) (x<<0) /* Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors.
|
||||
If this field is zero, the calibration value is not known */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CSR; /* 0x0, Control and Status */
|
||||
__IO uint32_t RVR; /* 0x4, Reload Value */
|
||||
__IO uint32_t CVR; /* 0x8, Current Value */
|
||||
__I uint32_t CALIB; /* 0xC, Calibration */
|
||||
} TICK_TypeDef;
|
||||
|
||||
|
||||
#else
|
||||
/* */
|
||||
#endif
|
||||
-606
File diff suppressed because it is too large.
Load diff
-873
File diff suppressed because it is too large.
Load diff
-88
@@ -1,88 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file reg_WWDG.h
|
||||
* @brief WWDG Head File
|
||||
*
|
||||
* @version V1.00.01
|
||||
* @data 19/10/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __WWDG_H__
|
||||
#define __WWDG_H__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CR; /* 0x00 WWDG_CR Control register */
|
||||
__IO uint32_t CFR; /* 0x04 WWDG_CFR Configuration register */
|
||||
__O uint32_t IER; /* 0x08 WWDG_IER Interrupt enable register */
|
||||
__O uint32_t IDR; /* 0x0C WWDG_IDR Interrupt disable register */
|
||||
__I uint32_t IVS; /* 0x10 WWDG_IVS Interrupt valid status */
|
||||
__I uint32_t RIF; /* 0x14 WWDG_RIF Raw interrupt flag */
|
||||
__I uint32_t IFM; /* 0x18 WWDG_IFM Interrupt flag masked */
|
||||
__O uint32_t ICR; /* 0x1C WWDG_ICR Interrupt clear register */
|
||||
} WWDG_TypeDef;
|
||||
|
||||
/******************************************************************************/
|
||||
/* ¼È¦s¾¹¤º³¡¦ì¤¸©w¸q */
|
||||
/******************************************************************************/
|
||||
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for WWDG_CR register ************************/
|
||||
|
||||
#define WWDG_CR_WDGA_POS 7U
|
||||
#define WWDG_CR_WDGA_MSK BIT(WWDG_CR_WDGA_POS)
|
||||
|
||||
#define WWDG_CR_T_POSS 0U
|
||||
#define WWDG_CR_T_POSE 6U
|
||||
#define WWDG_CR_T_MSK BITS(WWDG_CR_T_POSS,WWDG_CR_T_POSE)
|
||||
|
||||
/****************** Bit definition for WWDG_CFR register ************************/
|
||||
|
||||
#define WWDG_CFR_WDGTB_POS 7U
|
||||
#define WWDG_CFR_WDGTB_MSK BIT(WWDG_CFR_WDGTB_POS)
|
||||
|
||||
#define WWDG_CFR_W_POSS 0U
|
||||
#define WWDG_CFR_W_POSE 6U
|
||||
#define WWDG_CFR_W_MSK BITS(WWDG_CFR_W_POSS,WWDG_CFR_W_POSE)
|
||||
|
||||
/****************** Bit definition for WWDG_IER register ************************/
|
||||
|
||||
#define WWDG_IER_EWIS_POS 7U
|
||||
#define WWDG_IER_EWIS_MSK BIT(WWDG_IER_EWIS_POS)
|
||||
|
||||
/****************** Bit definition for WWDG_IDR register ************************/
|
||||
|
||||
#define WWDG_IDR_EWIS_POS 7U
|
||||
#define WWDG_IDR_EWIS_MSK BIT(WWDG_IER_EWIS_POS)
|
||||
|
||||
/****************** Bit definition for WWDG_IVS register ************************/
|
||||
|
||||
#define WWDG_IVS_EWIS_POS 7U
|
||||
#define WWDG_IVS_EWIS_MSK BIT(WWDG_IER_EWIS_POS)
|
||||
|
||||
/****************** Bit definition for WWDG_RIF register ************************/
|
||||
|
||||
#define WWDG_RIF_EWIS_POS 7U
|
||||
#define WWDG_RIF_EWIS_MSK BIT(WWDG_IER_EWIS_POS)
|
||||
|
||||
/****************** Bit definition for WWDG_IFM register ************************/
|
||||
|
||||
#define WWDG_IFM_EWIS_POS 7U
|
||||
#define WWDG_IFM_EWIS_MSK BIT(WWDG_IER_EWIS_POS)
|
||||
|
||||
/****************** Bit definition for WWDG_ICR register ************************/
|
||||
|
||||
#define WWDG_ICR_EWIS_POS 7U
|
||||
#define WWDG_ICR_EWIS_MSK BIT(WWDG_IER_EWIS_POS)
|
||||
|
||||
|
||||
#else
|
||||
/* */
|
||||
#endif
|
||||
-92
@@ -1,92 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file REG_WWDT.h
|
||||
* @brief WWDT Head File
|
||||
*
|
||||
* @version V0.01
|
||||
* @date 4/12/2018
|
||||
* @author Eastsoft MCU Software Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __REG_WWDT_H__
|
||||
#define __REG_WWDT_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* 设备特殊寄存器结构定义 */
|
||||
/******************************************************************************/
|
||||
|
||||
/* 允许匿名结构和匿名联合 */
|
||||
/* #pragma anon_unions */
|
||||
|
||||
/****************** Bit definition for WWDT_CON register ************************/
|
||||
|
||||
#define WWDT_CON_WDGA_POS 7U
|
||||
#define WWDT_CON_WDGA_MSK BIT(WWDT_CON_WDGA_POS)
|
||||
|
||||
#define WWDT_CON_T_POSS 0U
|
||||
#define WWDT_CON_T_POSE 6U
|
||||
#define WWDT_CON_T_MSK BITS(WWDT_CON_T_POSS,WWDT_CON_T_POSE)
|
||||
|
||||
/****************** Bit definition for WWDT_CFG register ************************/
|
||||
|
||||
#define WWDT_CFG_WDGTB_POSS 7U
|
||||
#define WWDT_CFG_WDGTB_POSE 8U
|
||||
#define WWDT_CFG_WDGTB_MSK BITS(WWDT_CFG_WDGTB_POSS,WWDT_CFG_WDGTB_POSE)
|
||||
|
||||
#define WWDT_CFG_W_POSS 0U
|
||||
#define WWDT_CFG_W_POSE 6U
|
||||
#define WWDT_CFG_W_MSK BITS(WWDT_CFG_W_POSS,WWDT_CFG_W_POSE)
|
||||
|
||||
/****************** Bit definition for WWDT_IER register ************************/
|
||||
|
||||
#define WWDT_IER_EWIS_POS 0U
|
||||
#define WWDT_IER_EWIS_MSK BIT(WWDT_IER_EWIS_POS)
|
||||
|
||||
/****************** Bit definition for WWDT_IDR register ************************/
|
||||
|
||||
#define WWDT_IDR_EWIS_POS 0U
|
||||
#define WWDT_IDR_EWIS_MSK BIT(WWDT_IDR_EWIS_POS)
|
||||
|
||||
/****************** Bit definition for WWDT_IVS register ************************/
|
||||
|
||||
#define WWDT_IVS_EWIS_POS 0U
|
||||
#define WWDT_IVS_EWIS_MSK BIT(WWDT_IVS_EWIS_POS)
|
||||
|
||||
/****************** Bit definition for WWDT_RIF register ************************/
|
||||
|
||||
#define WWDT_RIF_EWIF_POS 0U
|
||||
#define WWDT_RIF_EWIF_MSK BIT(WWDT_RIF_EWIF_POS)
|
||||
|
||||
/****************** Bit definition for WWDT_IFM register ************************/
|
||||
|
||||
#define WWDT_IFM_EWIM_POS 0U
|
||||
#define WWDT_IFM_EWIM_MSK BIT(WWDT_IFM_EWIM_POS)
|
||||
|
||||
/****************** Bit definition for WWDT_ICR register ************************/
|
||||
|
||||
#define WWDT_ICR_EWIC_POS 0U
|
||||
#define WWDT_ICR_EWIC_MSK BIT(WWDT_ICR_EWIC_POS)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CON;
|
||||
__IO uint32_t CFG;
|
||||
__O uint32_t IER;
|
||||
__O uint32_t IDR;
|
||||
__I uint32_t IVS;
|
||||
__I uint32_t RIF;
|
||||
__I uint32_t IFM;
|
||||
__O uint32_t ICR;
|
||||
} WWDT_TypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large.
Load diff
@@ -1,183 +0,0 @@
|
||||
/* rt_misc.h: definitions for miscellaneous retargetable functions
|
||||
*
|
||||
* Copyright 1999,2013-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* RCS $Revision$
|
||||
* Checkin $Date$
|
||||
* Revising $Author$
|
||||
*/
|
||||
|
||||
#ifndef __RT_MISC_H
|
||||
#define __RT_MISC_H
|
||||
#define __ARMCLIB_VERSION 5060019
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* This will be called during startup if it's defined, in order to
|
||||
* allow a user reimplementation of getenv() to initialise itself.
|
||||
*/
|
||||
extern void _getenv_init(void);
|
||||
|
||||
/*
|
||||
* This will be called during startup if it's defined, in order to
|
||||
* allow a user reimplementation of clock() to initialise itself.
|
||||
*/
|
||||
extern void _clock_init(void);
|
||||
|
||||
/*
|
||||
* This must return a pointer to __USER_LIBSPACE_SIZE bytes of
|
||||
* zero-initialised space, used to store vital static data such as
|
||||
* errno, the heap state, and the FP status word.
|
||||
*/
|
||||
#define __USER_LIBSPACE_SIZE 96
|
||||
extern void *__user_libspace(void);
|
||||
|
||||
/*
|
||||
* This is the library init function itself, provided just in case
|
||||
* a user needs to call it directly. It is called just after
|
||||
* __rt_stackheap_init(), and passed an initial chunk of memory to
|
||||
* use as a heap. It returns argc and argv ready to be passed to
|
||||
* main(). (The __argc_argv structure contains four words rather
|
||||
* than just two, in case you need to pass anything else to main()
|
||||
* such as the Unix envp. For AArch64 struct __argc_argv is 8 words
|
||||
* (4 registers) and explicit padding is used to ensure argc is in w0.)
|
||||
*/
|
||||
struct __argc_argv {
|
||||
#if (defined(__ARM_64BIT_STATE) || defined(__TARGET_ARCH_AARCH64)) && \
|
||||
(defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN))
|
||||
int padding;
|
||||
#endif
|
||||
int argc;
|
||||
#if (defined(__ARM_64BIT_STATE) || defined(__TARGET_ARCH_AARCH64)) && \
|
||||
!(defined(__ARM_BIG_ENDIAN) || defined(__BIG_ENDIAN))
|
||||
int padding;
|
||||
#endif
|
||||
char **argv;
|
||||
void *r2;
|
||||
void *r3;
|
||||
};
|
||||
extern __value_in_regs struct __argc_argv
|
||||
__rt_lib_init(unsigned /*heapbase*/, unsigned /*heaptop*/);
|
||||
|
||||
/*
|
||||
* This function is responsible for constructing argc and argv to
|
||||
* be passed to main(). Normally it works by calling
|
||||
* _sys_command_string() and then splitting up the returned command
|
||||
* line. If you define main() without arguments, the compiler also
|
||||
* defines an empty version of this function to save time. In
|
||||
* special circumstances, you might need to redefine this function
|
||||
* explicitly yourself.
|
||||
*/
|
||||
__value_in_regs struct __argc_argv __ARM_get_argv(void */*internal use only*/);
|
||||
|
||||
/*
|
||||
* This is the library shutdown function, analogous to
|
||||
* __rt_lib_init().
|
||||
*/
|
||||
extern void __rt_lib_shutdown(void);
|
||||
|
||||
/*
|
||||
* The medium-level exit function. exit() calls atexit()-registered
|
||||
* functions and shuts down the library; _sys_exit() does neither
|
||||
* of those things; __rt_exit() shuts down the library but doesn't
|
||||
* call atexit() functions.
|
||||
*/
|
||||
extern void __rt_exit(int /*returncode*/); /* never returns */
|
||||
|
||||
/*
|
||||
* This can be defined to override the standard memory models' way
|
||||
* of determining where to put the initial stack and heap.
|
||||
*
|
||||
* The input parameters R0 and R2 contain nothing useful. The input
|
||||
* parameters SP and SL are the values that were in SP and SL when
|
||||
* the program began execution (so you can return them if you want
|
||||
* to keep that stack).
|
||||
*
|
||||
* The two `limit' fields in the return structure are ignored if
|
||||
* you are using the one-region memory model: the memory region is
|
||||
* taken to be all the space between heap_base and stack_base.
|
||||
*/
|
||||
struct __initial_stackheap {
|
||||
unsigned heap_base; /* low-address end of initial heap */
|
||||
unsigned stack_base; /* high-address end of initial stack */
|
||||
unsigned heap_limit; /* high-address end of initial heap */
|
||||
unsigned stack_limit; /* low-address end of initial stack */
|
||||
};
|
||||
extern __value_in_regs struct __initial_stackheap
|
||||
__user_initial_stackheap(unsigned /*R0*/, unsigned /*SP*/,
|
||||
unsigned /*R2*/, unsigned /*SL*/);
|
||||
|
||||
/*
|
||||
* This can be defined to give bounds on the address space the heap
|
||||
* will ever use.
|
||||
*/
|
||||
struct __heap_extent {
|
||||
uintptr_t base;
|
||||
size_t range;
|
||||
};
|
||||
extern __value_in_regs struct __heap_extent
|
||||
__user_heap_extent(uintptr_t /*ignore*/, size_t /*ignore*/);
|
||||
|
||||
/*
|
||||
* This can be defined to specify how much spare stack is needed
|
||||
* below SL in addition to the 256 bytes required by ATPCS:
|
||||
* `always' gives the number of bytes of extra stack required at
|
||||
* all instants (so that an interrupt handler has space to run in,
|
||||
* for example), while `cleanup' gives the number of bytes of extra
|
||||
* stack required to be available after a stack overflow has
|
||||
* occurred, so that the stack overflow routine (e.g. SIGSTAK
|
||||
* handler) has room to tidy up.
|
||||
*/
|
||||
struct __stack_slop {
|
||||
unsigned always, cleanup;
|
||||
};
|
||||
extern __value_in_regs struct __stack_slop
|
||||
__user_stack_slop(unsigned /*ignore*/, unsigned /*ignore*/);
|
||||
|
||||
/*
|
||||
* This can be defined to return extra blocks of memory, separate
|
||||
* from the initial one, to be used by the heap. It should place a
|
||||
* pointer to a block of at least the requested size in `*base',
|
||||
* and return the size of the block. It should return 0 if no such
|
||||
* block can be returned, in which case the value stored at `*base'
|
||||
* is never used.
|
||||
*/
|
||||
extern size_t __user_heap_extend(int /*ignore*/,
|
||||
void ** /*base*/,
|
||||
size_t /*requestedsize*/);
|
||||
|
||||
/*
|
||||
* Redefine this to completely override the C handling of signals
|
||||
* (bypassing the signal() mechanism). Return values are 0 to
|
||||
* continue execution, or a non-zero value to cause an exit with
|
||||
* that return code.
|
||||
*/
|
||||
int __raise(int /*sig*/, intptr_t /*type*/);
|
||||
|
||||
/*
|
||||
* Redefine this to change the default handling of signals. The
|
||||
* interface is the same as __raise(), but this function will only
|
||||
* get called after the C signal handling mechanism has declined to
|
||||
* process the signal.
|
||||
*/
|
||||
int __default_signal_handler(int /*sig*/, intptr_t /*type*/);
|
||||
|
||||
/*
|
||||
* Redefine this to replace the library's entire signal handling
|
||||
* mechanism in the most efficient possible way. The default
|
||||
* implementation of this is what calls __raise (above).
|
||||
*/
|
||||
void __rt_raise(int /*sig*/, intptr_t /*type*/);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,16 +0,0 @@
|
||||
<!doctype html>
|
||||
<html>
|
||||
<head>
|
||||
<meta charset='UTF-8'><meta name='viewport' content='width=device-width initial-scale=1'>
|
||||
<title>ReleaseNote</title></head>
|
||||
<body><h1>ES32F0271 Device Release Note</h1>
|
||||
<h2>V1.00 2019-1-4</h2>
|
||||
<p>初版发布</p>
|
||||
<h2>V1.03 2019-09-23</h2>
|
||||
<ol>
|
||||
<li>Drivers\CMSIS\Device\EastSoft\ES32F0271\Startup\iar\ : 增加startup_es32f027x.s</li>
|
||||
|
||||
</ol>
|
||||
<p> </p>
|
||||
</body>
|
||||
</html>
|
||||
-256
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
-244
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -1,55 +0,0 @@
|
||||
/******************************************************************************/
|
||||
/* RETARGET.C: 'Retarget' layer for target-dependent low level functions */
|
||||
/******************************************************************************/
|
||||
/* This file is part of the uVision/ARM development tools. */
|
||||
/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
|
||||
/* This software may only be used under the terms of a valid, current, */
|
||||
/* end user licence from KEIL for a compatible version of KEIL software */
|
||||
/* development tools. Nothing else gives you the right to use this software. */
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <rt_misc.h>
|
||||
|
||||
//#pragma import(__use_no_semihosting_swi)
|
||||
|
||||
__weak uint8_t sendchar(uint8_t ui8char)
|
||||
{
|
||||
(void) ui8char;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int ITM_fputc(int ch); /* ITM debug */
|
||||
|
||||
struct __FILE
|
||||
{
|
||||
int handle; /* Add whatever you need here */
|
||||
};
|
||||
FILE __stdout;
|
||||
|
||||
|
||||
int fputc(int ch, FILE *f)
|
||||
{
|
||||
return (sendchar(ch));
|
||||
}
|
||||
|
||||
|
||||
int ferror(FILE *f)
|
||||
{
|
||||
/* Your implementation of ferror */
|
||||
return EOF;
|
||||
}
|
||||
|
||||
|
||||
void _ttywrch(int ch)
|
||||
{
|
||||
sendchar(ch);
|
||||
}
|
||||
|
||||
|
||||
void _sys_exit(int return_code)
|
||||
{
|
||||
label:
|
||||
goto label; /* endless loop */
|
||||
}
|
||||
-79
@@ -1,79 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file system_es32f027x.c
|
||||
* @brief System File.
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 5/17/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
/* Incudes--------------------------------------------------------*/
|
||||
#include "system_es32f027x.h"
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup System_ES32F027X
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Public Functions -----------------------------------------------------------*/
|
||||
/* Public Init Structure ------------------------------------------------------*/
|
||||
/* Public Macros --------------------------------------------------------------*/
|
||||
/* Public Constants -----------------------------------------------------------*/
|
||||
/* Private Macros -------------------------------------------------------------*/
|
||||
/* Private Constants-----------------------------------------------------------*/
|
||||
|
||||
/* Private Variables ----------------------------------------------------------*/
|
||||
/** @addtogroup Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief update the value of SystemCoreClock after changing the system clock.
|
||||
*/
|
||||
unsigned int SystemCoreClock = 4000000;
|
||||
unsigned int SystemFrequency_SysClk = 4000000;
|
||||
unsigned int SystemFrequency_AHBClk = 4000000;
|
||||
unsigned int SystemFrequency_APBClk = 4000000;
|
||||
unsigned int PLL1Frequency = 48000000;
|
||||
unsigned int PLL0Frequency = 4000000;
|
||||
|
||||
/**
|
||||
* @} Private_Variables
|
||||
*/
|
||||
|
||||
/* Private Functions ----------------------------------------------------------*/
|
||||
/** @addtogroup Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief:SystemInit.
|
||||
* @param:none
|
||||
* @retval:none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @} Private_Functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* @} System_ES32F072X
|
||||
*/
|
||||
|
||||
/**
|
||||
* @} CMSIS
|
||||
*/
|
||||
/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE SYSTEM_ES32F027X.H **********/
|
||||
|
||||
-83
@@ -1,83 +0,0 @@
|
||||
/**
|
||||
**************************************************************************************
|
||||
* @file SYSTEM_ES32F027x.H
|
||||
* @brief es32f0271 system head file.
|
||||
*
|
||||
* @version V0.01
|
||||
* @data 5/17/2018
|
||||
* @author Eastsoft AE Team
|
||||
* @note
|
||||
*
|
||||
* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. ALL rights reserved.
|
||||
*
|
||||
**************************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
||||
#ifndef __SYSTEM_ES32F027x_H__
|
||||
#define __SYSTEM_ES32F027x_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes -------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup System_ES32F027x
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Public Functions -----------------------------------------------------------*/
|
||||
/* Public Init Structure ------------------------------------------------------*/
|
||||
/* Public Macros --------------------------------------------------------------*/
|
||||
/* Public Constants -----------------------------------------------------------*/
|
||||
/* Private Variables ----------------------------------------------------------*/
|
||||
/* Private Macros -------------------------------------------------------------*/
|
||||
/* Private Constants-----------------------------------------------------------*/
|
||||
|
||||
/* Public Types ---------------------------------------------------------------*/
|
||||
/** @addtogroup Public_Types
|
||||
* @{
|
||||
*/
|
||||
extern unsigned int SystemCoreClock;
|
||||
extern unsigned int SystemFrequency_SysClk;
|
||||
extern unsigned int SystemFrequency_AHBClk;
|
||||
extern unsigned int SystemFrequency_APBClk;
|
||||
extern unsigned int PLL1Frequency;
|
||||
extern unsigned int PLL0Frequency;
|
||||
|
||||
/* Exported function -------------------------------------------------*/
|
||||
/** @addtogroup Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @} Public_Functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* @} Public_Types
|
||||
*/
|
||||
|
||||
/**
|
||||
* @} System_ES32F027x
|
||||
*/
|
||||
|
||||
/**
|
||||
* @} CMSIS
|
||||
*/
|
||||
/********** (C) COPYRIGHT Eastsoft Microelectronics END OF FILE SYSTEM_ES32F027x.H **********/
|
||||
@@ -1,121 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
@@ -1,66 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
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@@ -1,39 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large.
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Load diff
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Load diff
File diff suppressed because it is too large.
Load diff
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Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
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Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -1,197 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U
|
||||
#define ARM_MPU_AP_PRIV 1U
|
||||
#define ARM_MPU_AP_URO 2U
|
||||
#define ARM_MPU_AP_FULL 3U
|
||||
#define ARM_MPU_AP_PRO 5U
|
||||
#define ARM_MPU_AP_RO 6U
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(MPU_RASR_ENABLE_Msk))
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
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@@ -1,70 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
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|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>Redirect to the CMSIS main page after 0 seconds</title>
|
||||
<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
|
||||
<meta name="keywords" content="automatic redirection">
|
||||
</head>
|
||||
|
||||
<body>
|
||||
|
||||
If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
|
||||
|
||||
</body>
|
||||
</html>
|
||||
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Reference in new issue
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