fix eth/lcd io conflict

This commit is contained in:
tanek liang committed 2017-08-30 11:10:54 +08:00
1 parent 09f698a209
commit ea2a9db341
7 files changed
+2463 -3679

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+1
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@@ -12,6 +12,7 @@ drv_usart.c
gd32f450z_lcd_eval.c
drv_lcd.c
drv_enet.c
synopsys_emac.c
""")
CPPPATH = [cwd]
-30
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@@ -30,7 +30,6 @@
#define ETHERNET_MAC0 ((struct rt_synopsys_eth *)(0x40020000U + 0x00008000U))
//#define EMAC_DEBUG
//#define EMAC_RX_DUMP
//#define EMAC_TX_DUMP
@@ -62,7 +61,6 @@ struct gd32_emac
IRQn_Type ETHER_MAC_IRQ;
ALIGN(RT_ALIGN_SIZE)
PRAGMA(data_alignment=RT_ALIGN_SIZE)
EMAC_DMADESCTypeDef DMARxDscrTab[EMAC_RXBUFNB], DMATxDscrTab[EMAC_TXBUFNB];
ALIGN(RT_ALIGN_SIZE)
rt_uint8_t Rx_Buff[EMAC_RXBUFNB][EMAC_MAX_PACKET_SIZE];
@@ -520,33 +518,6 @@ struct pbuf * gd32_emac_rx(rt_device_t dev)
return p;
}
/*
GPIO RMII0 RMII1 MII
PC0/E_RXER0_RXDV1 ch. 1 CRS_DV ch. 0 RX_ER
PC1/E_RX03_RX11 ch. 1 RXD [1] ch. 0 RXD [3]
PC2/E_RX02_RX10 ch. 1 RXD [0] ch. 0 RXD [2]
PC3/E_RX01 ch. 0 RXD [1] ch. 0 RXD [1]
PC4/E_RX00 ch. 0 RXD [0] ch. 0 RXD [0]
PC5/E_RXDV0 ch. 0 CRS_DV ch. 0 RX_DV
PC6/E_MDIO0 ch. 0 MDIO ch. 0 MDIO
PC7/E_MDC0 ch. 0 MDC ch. 0 MDC
PC8/E_RXCK0_REFCK ch. 0 REF_CLK ch. 1 REF_CLK ch. 0 RX_CLK
PC9/E_COL0 ch. 0 COL
PCA/E_CRS0 ch. 0 CRS
PCB/E_COUT REF_CLK output(??).
PCC/E_MDIO1 ch. 1 MDIO
PCD/E_TCK0_MDC1 ch. 1 MDC ch. 0 TX_CLK
PCE/E_TXER0_TXEN1 ch. 1 TX_EN ch. 0 TX_ER
PCF/E_TX03_TX11 ch. 1 TXD [1] ch. 0 TXD [3]
PD0/E_TX02_TX10 ch. 1 TXD [0] ch. 0 TXD [2]
PD1/E_TX01 ch. 0 TXD [1] ch. 0 TXD [1]
PD2/E_TX00 ch. 0 TXD [0] ch. 0 TXD [0]
PD3/E_TXEN0 ch. 0 TX_EN ch. 0 TX_EN
*/
/*!
\brief configures the nested vectored interrupt controller
\param[in] none
@@ -651,7 +622,6 @@ int rt_hw_gd32_eth_init(void)
/* configure the GPIO ports for ethernet pins */
enet_gpio_config();
/* set autonegotiation mode */
gd32_emac_device0.phy_mode = EMAC_PHY_AUTO;
gd32_emac_device0.ETHERNET_MAC = ETHERNET_MAC0;
+7 -5
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@@ -16,9 +16,11 @@
#include <gd32f4xx.h>
#include <drv_usart.h>
#include <board.h>
#include <finsh.h>
#ifdef RT_USING_GUIENGINE
#define RT_HW_LCD_WIDTH ((uint16_t)320) /* LCD PIXEL WIDTH */
#define RT_HW_LCD_HEIGHT ((uint16_t)480) /* LCD PIXEL HEIGHT */
@@ -67,7 +69,7 @@ static void tli_gpio_config(void)
gpio_af_set(GPIOB,GPIO_AF_9,GPIO_PIN_0);
gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_10);
gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11);
//gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_11);
gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_8);
gpio_af_set(GPIOB,GPIO_AF_14,GPIO_PIN_9);
@@ -90,9 +92,9 @@ static void tli_gpio_config(void)
|GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_11|GPIO_PIN_12);
gpio_mode_set(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
|GPIO_PIN_11);
/*|GPIO_PIN_11*/);
gpio_output_options_set(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, GPIO_PIN_0|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
|GPIO_PIN_11);
/*|GPIO_PIN_11*/);
gpio_mode_set(GPIOC, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_6|GPIO_PIN_7);
gpio_output_options_set(GPIOC, GPIO_OTYPE_PP,GPIO_OSPEED_50MHZ, GPIO_PIN_6|GPIO_PIN_7);
@@ -144,7 +146,6 @@ static void tli_config(void)
tli_layer_parameter_struct tli_layer_init_struct;
rcu_periph_clock_enable(RCU_TLI);
tli_gpio_config();
/* configure the PLLSAI clock to generate lcd clock */
if(ERROR == rcu_pllsai_config(192, 2, 3, 3)){
@@ -264,3 +265,4 @@ int gd32_hw_lcd_init(void)
return 0;
}
INIT_DEVICE_EXPORT(gd32_hw_lcd_init);
#endif
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+2345 -2468
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+3 -2
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@@ -22,6 +22,7 @@
/* Using Hook */
#define RT_USING_HOOK
#define RT_USING_TRACE
#define IDLE_THREAD_STACK_SIZE 1024
@@ -182,7 +183,7 @@
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 10
#define RT_LWIP_IPADDR3 222
#define RT_LWIP_IPADDR3 241
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
@@ -236,6 +237,6 @@
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_CPU_FFS
//#define RT_USING_CPU_FFS
#endif