Merge pull request #826 from ArcherChang/master

[BSP] Add Andes N1068 porting and simple bsp.
2026-10-07 00:59:00 +08:00 · 2017-10-06 11:03:02 +08:00
parent 49aa0c468a 9bbf538753
commit ea18ef60ed
58 changed files with 17853 additions and 0 deletions
@@ -0,0 +1,76 @@
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+							<builder buildPath="${workspace_loc:/rtt_master/bsp/AE210P}" cleanBuildTarget="APP=rtthread AE210P=1 USING_CLI=1 DEBUG=1 clean" id="target.nds.builder.base.798580194" incrementalBuildTarget="APP=rtthread AE210P=1 USING_CLI=1 DEBUG=1 all" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Andes Make Builder" superClass="target.nds.builder.base"/>
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@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>rtt_master</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
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@@ -0,0 +1,2 @@
+   text (code + rodata)	   data	    bss	    dec	    hex	filename
+  67240 (58320 +   8920)	    408	  10168	  77816	  12ff8	rtthread.elf
@@ -0,0 +1,136 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2013-07-12     aozima       update for auto initial.
+ */
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+#include <board.h>
+#include <rtthread.h>
+#include <rthw.h>
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+#ifdef RT_USING_DFS
+/* dfs filesystem:ELM filesystem init */
+#include <dfs_elm.h>
+/* dfs Filesystem APIs */
+#include <dfs_fs.h>
+#endif
+
+#ifdef RT_USING_RTGUI
+#include <rtgui/rtgui.h>
+#include <rtgui/rtgui_server.h>
+#include <rtgui/rtgui_system.h>
+#include <rtgui/driver.h>
+#include <rtgui/calibration.h>
+#endif
+
+void rt_init_thread_entry(void* parameter)
+{
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization RT-Thread Components */
+    rt_components_init();
+#endif
+
+    /* Filesystem Initialization */
+#if defined(RT_USING_DFS) && defined(RT_USING_DFS_ELMFAT)
+    /* mount sd card fat partition 1 as root directory */
+    if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+    {
+        rt_kprintf("File System initialized!\n");
+    }
+    else
+        rt_kprintf("File System initialzation failed!\n");
+#endif  /* RT_USING_DFS */
+
+#ifdef RT_USING_RTGUI
+    {
+        extern void rt_hw_lcd_init();
+        extern void rtgui_touch_hw_init(void);
+
+        rt_device_t lcd;
+
+        /* init lcd */
+        rt_hw_lcd_init();
+
+        /* init touch panel */
+        rtgui_touch_hw_init();
+
+        /* find lcd device */
+        lcd = rt_device_find("lcd");
+
+        /* set lcd device as rtgui graphic driver */
+        rtgui_graphic_set_device(lcd);
+
+#ifndef RT_USING_COMPONENTS_INIT
+        /* init rtgui system server */
+        rtgui_system_server_init();
+#endif
+
+        calibration_set_restore(cali_setup);
+        calibration_set_after(cali_store);
+        calibration_init();
+    }
+#endif /* #ifdef RT_USING_RTGUI */
+}
+
+//#include "debug.h"
+//
+//rt_thread_t test_thread[2];
+//
+//void rt_test_thread_entry(void *parameter)
+//{
+//	uint32_t num = (uint32_t)parameter;
+//	uint32_t schedule_times = 0;
+//
+//	while (1)
+//	{
+//		DEBUG(1, 0, "%d:%d\r\n", num, schedule_times++);
+//		rt_thread_delay(1);
+//	}
+//}
+
+int rt_application_init(void)
+{
+    rt_thread_t init_thread;
+	
+#if (RT_THREAD_PRIORITY_MAX == 32)
+    init_thread = rt_thread_create("init",
+                                   rt_init_thread_entry, RT_NULL,
+                                   2048, 8, 20);
+#else
+    init_thread = rt_thread_create("init",
+                                   rt_init_thread_entry, RT_NULL,
+                                   2048, 80, 20);
+#endif
+
+    if (init_thread != RT_NULL)
+        rt_thread_startup(init_thread);
+
+//    test_thread[0] = rt_thread_create("t1", rt_test_thread_entry, (void *)1, 1024, 26, 5);
+//    test_thread[1] = rt_thread_create("t2", rt_test_thread_entry, (void *)2, 1024, 26, 5);
+//	if (test_thread[0] != RT_NULL)
+//		rt_thread_startup(test_thread[0]);
+//	if (test_thread[1] != RT_NULL)
+//		rt_thread_startup(test_thread[1]);
+
+    return 0;
+}
+
+/*@}*/
@@ -0,0 +1,95 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2013-07-12     aozima       update for auto initial.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "nds32.h"
+#include "bsp_hal.h"
+#include "ae210p.h"
+#include "debug.h"
+//#include "uart/uart.h"
+#include "uart_dev.h"
+
+#include "board.h"
+#include "rtconfig.h"
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+	/* clean timer device pending*/
+	hal_timer_irq_clear(1);
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/***********************************************************
+ * Set timer 1 as system tick by default
+ ***********************************************************/
+
+void BSP_Tmr_TickInit(uint32_t tmrId, uint32_t period, uint32_t vecId, void *isr)
+{
+	/* set tick  period */
+	hal_timer_set_period(tmrId, period);
+
+	/* enable timer1 interrupt */
+	hal_timer_irq_control(tmrId, 1);
+
+	/******************************
+ 	 * tick ISR init
+ 	 ******************************/
+	/* init trigger mode */
+	/* Set edge trigger, falling edge */
+	hal_intc_irq_config(vecId, 1, 0);
+	/* clean pending */
+	hal_intc_irq_clean(vecId);
+	/* enable timer interrupt */
+	hal_intc_irq_enable(vecId);
+
+	if (isr)
+		OS_CPU_Vector_Table[vecId] = isr;
+	else
+		DEBUG(1, 1, "Invalid tick handler!!\r\n");
+
+	/* start timer */
+	hal_timer_start(tmrId);
+}
+
+/*
+ * Setup system tick for OS required.
+ */
+void bsp_init(void)
+{
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+//	drv_uart_init();
+	rt_hw_usart_init();
+	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+	/* System tick init */
+	BSP_Tmr_TickInit(0x1, (MB_PCLK / RT_TICK_PER_SECOND), IRQ_SYS_TICK_VECTOR, SysTick_Handler);
+}
+
+/*@}*/
@@ -0,0 +1,28 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "nds32.h"
+
+/* board configuration */
+
+//#define RT_USING_UART01 1
+#define RT_USING_UART02 1
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
@@ -0,0 +1,74 @@
+/*****************************************************************************
+ *
+ *            Copyright Andes Technology Corporation 2014
+ *                         All Rights Reserved.
+ *
+ ****************************************************************************/
+
+#ifndef __AE210P_H__
+#define __AE210P_H__
+
+#ifndef __ASSEMBLER__
+#include <inttypes.h>
+#include <nds32_intrinsic.h>
+#endif
+
+/*****************************************************************************
+ * System clock
+ ****************************************************************************/
+#define KHz                     1000
+#define MHz                     1000000
+
+#define MB_OSCCLK               (20 * MHz)
+#define MB_CPUCLK               (40 * MHz)
+#define MB_HCLK                 (MB_CPUCLK)
+#define MB_PCLK                 (MB_CPUCLK)
+#define MB_UCLK                 (MB_OSCCLK)
+
+/*****************************************************************************
+ * IRQ Vector
+ ****************************************************************************/
+#define IRQ_RTCPERIOD_VECTOR    0
+#define IRQ_RTCALARM_VECTOR     1
+#define IRQ_PIT_VECTOR          2
+#define IRQ_SPI1_VECTOR         3
+#define IRQ_SPI2_VECTOR         4
+#define IRQ_I2C_VECTOR          5
+#define IRQ_GPIO_VECTOR         6
+#define IRQ_UART1_VECTOR        7
+#define IRQ_UATR2_VECTOR        8
+#define IRQ_DMA_VECTOR          9
+#define IRQ_BMC_VECTOR          10
+#define IRQ_SWI_VECTOR          11
+
+/* EXT_INT_0~19 are reserved for vendor IPs */
+#define IRQ_EXTINT0_VECTOR      12
+#define IRQ_EXTINT1_VECTOR      13
+#define IRQ_EXTINT2_VECTOR      14
+#define IRQ_EXTINT3_VECTOR      15
+#define IRQ_EXTINT4_VECTOR      16
+#define IRQ_EXTINT5_VECTOR      17
+#define IRQ_EXTINT6_VECTOR      18
+#define IRQ_EXTINT7_VECTOR      19
+#define IRQ_EXTINT8_VECTOR      20
+#define IRQ_EXTINT9_VECTOR      21
+#define IRQ_EXTINT10_VECTOR     22
+#define IRQ_EXTINT11_VECTOR     23
+#define IRQ_EXTINT12_VECTOR     24
+#define IRQ_EXTINT13_VECTOR     25
+#define IRQ_EXTINT14_VECTOR     26
+#define IRQ_EXTINT15_VECTOR     27
+#define IRQ_EXTINT16_VECTOR     28
+#define IRQ_EXTINT17_VECTOR     29
+#define IRQ_EXTINT18_VECTOR     30
+#define IRQ_EXTINT19_VECTOR     31
+
+/* The system tick IRQ for OS */
+#define IRQ_SYS_TICK_VECTOR     IRQ_PIT_VECTOR
+#define IRQ_SYS_TICK2_VECTOR    IRQ_PIT_VECTOR
+
+/* Include ae210p memory mapping and register definition */
+#include "ae210p_defs.h"
+#include "ae210p_regs.h"
+
+#endif	/* __AE210P_H__ */
@@ -0,0 +1,68 @@
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+FLASH1 0x0
+{
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+		. = ALIGN(4);
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+		* KEEP( .rti_fn.0 )
+		* KEEP( .rti_fn.0.end )
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+		* KEEP( .rti_fn.7 )
+		* KEEP( .rti_fn.7.end )
+		. = ALIGN(4);
+		ADDR __rt_init_end
+	}
+	
+;	RAM 0x200000 0x80000 ; EDLM_SIZE <= 512KB
+	RAM 0x200000 0x50000 ; EDLM_SIZE <= 320KB
+	{
+		LOADADDR NEXT __rw_lma_start
+		ADDR NEXT __rw_vma_start
+		*(+RW)
+		LOADADDR NEXT __rw_lma_end
+		*(+ZI)
+;		STACK = 0x27fff8 ; 512KB
+		STACK = 0x24fff8 ; 320KB
+	}	
+}
@@ -0,0 +1,23 @@
+/*
+ * File      : uart_dev.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+#ifndef __UART_DEV_H__
+#define __UART_DEV_H__
+
+#include "rthw.h"
+#include "rtthread.h"
+
+void rt_hw_usart_init(void);
+
+#endif // end of "__UART_DEV_H__"
@@ -0,0 +1,77 @@
+#ifndef __PLAT_HAL_H_
+#define __PLAT_HAL_H_
+
+#include "inttypes.h"
+
+
+/********************************
+ * 	INTC HAL DEFINE
+ ********************************/
+
+#define IRQ_EDGE_TRIGGER	1
+#define IRQ_LEVEL_TRIGGER	0
+
+#define IRQ_ACTIVE_HIGH		1
+#define IRQ_ACTIVE_LOW		0
+
+void hal_intc_init();
+void hal_intc_swi_enable();
+void hal_intc_swi_disable();
+void hal_intc_swi_clean();
+void hal_intc_swi_trigger();
+
+/* Call by HISR.
+ * Since our mask/unmask are not atomic. 
+ * And HISR is task level ISR in RTOS, we need make sure it is atomic. 
+ *
+ * TODO remove gie if atomic 
+ */
+#define HAL_INTC_IRQ_ATOMIC_DISABLE(_irq_) \
+		do \
+		{ \
+			unsigned long _gie_; \
+			GIE_SAVE(&_gie_); \
+			hal_intc_irq_disable(_irq_); \
+			GIE_RESTORE(_gie_); \
+		} while(0)
+
+#define HAL_INTC_IRQ_ATOMIC_ENABLE(_irq_) \
+		do \
+		{ \
+			unsigned long _gie_; \
+			GIE_SAVE(&_gie_); \
+			hal_intc_irq_enable(_irq_); \
+			GIE_RESTORE(_gie_); \
+		} while(0)
+
+
+uint32_t hal_intc_irq_mask(int _irqs_);
+void     hal_intc_irq_unmask(int _irqs_);
+void     hal_intc_irq_clean(int _irqs_);
+void     hal_intc_irq_clean_all();
+void     hal_intc_irq_enable(uint32_t _irqs_);
+void     hal_intc_irq_disable(uint32_t _irqs_);
+void     hal_intc_irq_disable_all();
+void     hal_intc_irq_set_priority(uint32_t _prio_ );
+void     hal_intc_irq_config(uint32_t _irqs_, uint32_t _edge_, uint32_t _falling_);
+uint32_t hal_intc_get_all_pend();
+
+/********************************
+ * 	TIMER HAL DEFINE	
+ ********************************/
+
+uint32_t hal_timer_irq_mask(uint32_t _tmr_ );
+void     hal_timer_irq_unmask(uint32_t _msk_ );
+void     hal_timer_irq_clear(uint32_t _tmr_ );
+void     hal_timer_start(uint32_t _tmr_);
+void     hal_timer_stop(uint32_t _tmr_ );
+uint32_t hal_timer_read(uint32_t _tmr_ );
+void     hal_timer_set_period(uint32_t _tmr_, uint32_t _period_ );
+void     hal_timer_set_upward(uint32_t _tmr_ ,uint32_t up);
+void     hal_timer_init(uint32_t _tmr_ );
+void     hal_timer_irq_control(uint32_t _tmr_, uint32_t enable );
+uint32_t hal_timer_irq_status(uint32_t _tmr_);
+void     hal_timer_set_match1(uint32_t _tmr_ , uint32_t match );
+uint32_t hal_timer_count_read(uint32_t _tmr_);
+
+#endif
@@ -0,0 +1,45 @@
+#ifndef __CACHE_H__
+#define __CACHE_H__
+
+#include "nds32_intrinsic.h"
+#include "nds32.h"
+
+enum cache_t{ICACHE, DCACHE};
+
+static inline unsigned long CACHE_SET(enum cache_t cache){
+
+	if(cache == ICACHE)
+		return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >> ICM_CFG_offISET);
+	else
+		return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >> DCM_CFG_offDSET);
+}
+
+static inline unsigned long CACHE_WAY(enum cache_t cache){
+
+	if(cache == ICACHE)
+		return 1 + ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);
+	else
+		return 1 + ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);
+}
+
+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache){
+
+	if(cache == ICACHE)
+		return 8 << (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);
+	else
+		return 8 << (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);
+}
+
+extern void nds32_dcache_invalidate(void);
+extern void nds32_dcache_flush(void);
+extern void nds32_icache_flush(void);
+extern void nds32_dcache_clean_range(unsigned long start, unsigned long end);
+extern void nds32_dma_clean_range(unsigned long start, unsigned long end);
+extern void nds32_dcache_invalidate_range(unsigned long start, unsigned long end);
+extern void nds32_dcache_flush_range(unsigned long start, unsigned long end);
+extern void nds32_dcache_writeback_range(unsigned long start, unsigned long end);
+extern void nds32_dma_inv_range(unsigned long start, unsigned long end);
+extern void nds32_dma_flush_range(unsigned long start, unsigned long end);
+extern void nds32_icache_invalidate_range(unsigned long start, unsigned long end);
+
+#endif /* __CACHE_H__ */
@@ -0,0 +1,48 @@
+#define CONFIG_HEARTBEAT_LED 1
+
+/*
+ * Select Platform
+ */
+#ifdef AE210P
+#define CONFIG_PLAT_AE210P 1
+#define IRQ_STACK_SIZE     5120 /* IRQ stack size */
+#else
+#error "No valid platform is defined!"
+#endif
+
+/*
+ * Platform Option
+ */
+#define VECTOR_BASE 0x00000000
+
+#define VECTOR_NUMINTRS 32
+#define NO_EXTERNAL_INT_CTL 1
+#define XIP_MODE 1
+
+#ifdef CONFIG_OSC_SUPPORT
+#define OSC_EILM_SIZE 0x10000	// 64KB
+#undef XIP_MODE
+#endif
+
+#undef CONFIG_HW_PRIO_SUPPORT
+
+/*
+ * Cache Option
+ */
+#if (!defined(__NDS32_ISA_V3M__)  && defined(CONFIG_CACHE_SUPPORT))
+#define CONFIG_CPU_ICACHE_ENABLE 1
+#define CONFIG_CPU_DCACHE_ENABLE 1
+//#define CONFIG_CPU_DCACHE_WRITETHROUGH 1
+#endif
+
+#undef CONFIG_CHECK_RANGE_ALIGNMENT
+#undef CONFIG_CACHE_L2
+#undef CONFIG_FULL_ASSOC
+
+/*
+ * Debugging Options
+ */
+#undef CONFIG_DEBUG
+#undef CONFIG_WERROR
+
+#include "ae210p.h"
@@ -0,0 +1,78 @@
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+#include <stdio.h>
+
+#define DEBUG(enable, tagged, ...) \
+		do \
+		{ \
+			if (enable) \
+			{ \
+				if (tagged) \
+					fprintf(stderr, "[ %25s() ] ", __func__); \
+				fprintf(stderr, __VA_ARGS__); \
+			} \
+		} while( 0)
+
+#define ERROR(...) DEBUG(1, 1, "ERROR:"__VA_ARGS__)
+
+#define KASSERT(cond)						\
+{										    \
+	if (!(cond))                            \
+	{								        \
+		ERROR("Failed assertion in %s:\n"	\
+				"%s at %s\n"				\
+				"line %d\n"					\
+				"RA=%lx\n",					\
+				__func__,					\
+				#cond,						\
+				__FILE__,					\
+				__LINE__,					\
+				(unsigned long)__builtin_return_address(0));	\
+		                                    \
+		while (1)							\
+			;							    \
+	}									    \
+}
+
+#define KPANIC(args, ...)		\
+{					            \
+	ERROR(args, __VA_ARGS__);	\
+	while (1) ;			        \
+}
+
+static inline void dump_mem(const void *mem, int count)
+{
+	const unsigned char *p = mem;
+	int i = 0;
+
+	for(i = 0; i < count; i++)
+	{
+		if( i % 16 == 0)
+			DEBUG(1, 0, "\n");
+
+		DEBUG(1, 0, "%02x ", p[i]);
+	}
+}
+
+/* help to trace back */
+static inline void dump_stack(void)
+{
+	unsigned long *stack;
+	unsigned long addr;
+
+	__asm__ __volatile__ ("\tori\t%0, $sp, #0\n" : "=r" (stack));
+
+	printf("Call Trace:\n");
+	addr = *stack;
+	while (addr)
+	{
+		addr = *stack++;
+		printf("[<%08lx>] ", addr);
+	}		
+	printf("\n");
+
+	return;
+}
+
+#endif /* __DEBUG_H__ */
@@ -0,0 +1,2 @@
+lib-y		:=
+lib-y		+= dmad.o
@@ -0,0 +1,86 @@
+#include "gpio.h"
+//#include "hal.h"
+#include "bsp_hal.h"
+
+struct gpio_dev_t *gpio_p;
+
+//static void _gpio_lisr(int vector)
+//{
+//	DEBUG(0, 1, "Enter\n");
+//	if (vector != IRQ_GPIO_VECTOR)
+//		hal_system_error(HAL_ERR_UNHANDLED_INTERRUPT);
+//
+//	/* Disable GPIO interrupt */
+//	uint32_t prv_msk = hal_intc_irq_mask(IRQ_GPIO_VECTOR);
+//
+//	/* Get int state and then clear it */
+//	unsigned int int_sr = IN32(GPIOC_INT_RAW_STATE);
+//	gpio_p->int_data = int_sr;
+//	OUT32(GPIOC_INT_CLEAR, int_sr);
+//
+//	/* Clean GPIO pending */
+//	hal_intc_irq_clean(IRQ_GPIO_VECTOR);
+//
+//	/* Enable higher priority interrupt */
+//	/* comment it to disable nested interrupt */
+//	GIE_ENABLE();
+//	hal_raise_bh(&gpio_p->hisr);
+//
+//	GIE_DISABLE();
+//	/* - Enable GPIO interrupt */
+//	hal_intc_irq_unmask(prv_msk);
+//}
+
+int gpio_init(struct gpio_dev_t *gpio)
+{
+//	int  status = HAL_SUCCESS;
+//	int  core_intl;
+//
+//	/* initialize global gpio pointer */
+//	gpio_p = gpio;
+//	core_intl = hal_global_int_ctl(HAL_DISABLE_INTERRUPTS);
+//
+//	/* INTC */
+//	// - Disable GPIO interrupt
+//	hal_intc_irq_disable(IRQ_GPIO_VECTOR);
+//	// - Clear GPIO interrupt status
+//	hal_intc_irq_clean(IRQ_GPIO_VECTOR);
+//	// - Setup #PENIRQ trigger mode - edge trigger
+//	// - Setup #PENIRQ trigger level - active high
+//	hal_intc_irq_config(IRQ_GPIO_VECTOR, IRQ_EDGE_TRIGGER, IRQ_ACTIVE_HIGH);
+//
+//
+//	/* GPIO */
+//	/* falling, interrupt when pressed */
+//        //OUT32(GPIOC_INT_RISE_NEG, 0xFFFFFFFF);
+//	/* rising, interrupt when released */
+//        OUT32(GPIOC_INT_RISE_NEG, 0x0);
+//	/* enable all gpio interrupt GPIO1-5*/
+//        OUT32(GPIOC_INT_ENABLE, 0x3E);
+//	/* set the max value to debounce */
+//	OUT32(GPIOC_INT_BOUNCE_PRESCALE, 0xFFFF);
+//	/* enable debounce */
+//	OUT32(GPIOC_INT_BOUNCE_ENABLE, 0x3E);
+//
+//	status = hal_register_isr(IRQ_GPIO_VECTOR, _gpio_lisr, (void*)0);
+//
+//	if (status != HAL_SUCCESS){
+//		DEBUG(1, 1, "Failed to register GPIO driver LISR!\n");
+//		return status;
+//	}
+//
+//	status = hal_create_bh(&gpio->hisr);
+//	if (status != HAL_SUCCESS){
+//		DEBUG(1, 1, "Failed to create GPIO driver HISR!\n");
+//		return status;
+//	}
+//
+//	// - Enable GPIO interrupt
+//	hal_intc_irq_enable(IRQ_GPIO_VECTOR);
+//
+//	/* Restore CPU interrupt controller to previous level */
+//	hal_global_int_ctl(core_intl);
+//	return status;
+
+	return 0;
+}
@@ -0,0 +1,52 @@
+#ifndef __AG101_GPIOC_INC__
+#define __AG101_GPIOC_INC__
+
+//#include "hal.h"
+
+// GPIO port name definition
+typedef enum GPIOD_PORTS
+{
+    GPIO0       = 0x00000001,
+    GPIO1       = 0x00000002,
+    GPIO2       = 0x00000004,
+    GPIO3       = 0x00000008,
+    GPIO4       = 0x00000010,
+    GPIO5       = 0x00000020,
+    GPIO6       = 0x00000040,
+    GPIO7       = 0x00000080,
+
+    GPIO8       = 0x00000100,
+    GPIO9       = 0x00000200,
+    GPIO10      = 0x00000400,
+    GPIO11      = 0x00000800,
+    GPIO12      = 0x00001000,
+    GPIO13      = 0x00002000,
+    GPIO14      = 0x00004000,
+    GPIO15      = 0x00008000,
+
+    GPIO16      = 0x00010000,
+    GPIO17      = 0x00020000,
+    GPIO18      = 0x00040000,
+    GPIO19      = 0x00080000,
+    GPIO20      = 0x00100000,
+    GPIO21      = 0x00200000,
+    GPIO22      = 0x00400000,
+    GPIO23      = 0x00800000,
+
+    GPIO24      = 0x01000000,
+    GPIO25      = 0x02000000,
+    GPIO26      = 0x04000000,
+    GPIO27      = 0x08000000,
+    GPIO28      = 0x10000000,
+    GPIO29      = 0x20000000,
+    GPIO30      = 0x40000000,
+    GPIO31      = 0x80000000,
+
+} GPIOD_PORTS;
+
+struct gpio_dev_t
+{
+//	hal_bh_t     hisr;
+	unsigned int int_data;
+};
+#endif // __AG101_GPIOC_INC__
@@ -0,0 +1 @@
+lib-${CONFIG_FB_FTLCDC100}	+= font.o lcd.o
@@ -0,0 +1,114 @@
+#ifndef __LCD_INFO_H__
+#define __LCD_INFO_H__
+
+/*
+ * HBP : Horizontal Back Porch
+ * HFP : Horizontal Front Porch
+ * HSPW: Horizontal Sync. Pulse Width
+ * PPL : Pixels-per-line = 16(PPL+1)
+ */
+#define ENC_PARAM_TIME0(HBP, HFP, HSPW, PPL)	\
+	((((HBP)         - 1) << 24) |		\
+	 (((HFP)         - 1) << 16) |		\
+	 (((HSPW)        - 1) << 8 ) |		\
+	 ((((PPL) >> 4) - 1) << 2 ))
+
+/*
+ * HBP : Vertical Back Porch
+ * HFP : Vertical Front Porch
+ * HSPW: Vertical Sync. Pulse Width
+ * LPP : Lines-per-panel = LPP + 1
+ */
+#define ENC_PARAM_TIME1(VBP, VFP, VSPW, LPP)	\
+	((((VBP)     ) << 24) |			\
+	 (((VFP)     ) << 16) |			\
+	 (((VSPW) - 1) << 10) |			\
+	 (((LPP)  - 1) ))
+
+/*
+ * PRA : Pixel Rate Adaptive
+ * IOE : Invert Panel Output Enable
+ * IPC : Invert Panel Clock (Test Chip Testing)
+ * IHS : Invert Horisontal Sync.
+ * IVS : Invert Versical Sync.
+ * PCD : Panel Clock Divisor
+ */
+#define ENC_PARAM_TIME2(PRA, IOE, IPC, IHS, IVS, PCD)	\
+	(((PRA)     << 15) |				\
+	 ((IOE)     << 14) |				\
+	 ((IPC)     << 13) |				\
+	 ((IHS)     << 12) |				\
+	 ((IVS)     << 11) |				\
+	 (((PCD) - 1) ))
+
+/*
+ * Enable YCbCr
+ * Enable YCbCr422
+ * FIFO threadhold
+ * Panel type, 0-6bit, 1-8bit
+ * LcdVComp, when to generate interrupt, 1: start of back_porch
+ * Power Enable
+ * Big Endian Pixel/Byte Ordering
+ * BGR
+ * TFT
+ * LCD bits per pixel
+ * Controller Enable
+ */
+#define ENC_PARAM_CTRL(ENYUV, ENYUV422, FIFOTH, PTYPE, VCOMP, LCD_ON, ENDIAN, BGR, TFT, BPP, LCD_EN) \
+	((ENYUV        << 18) |			\
+	 (ENYUV422     << 17) |			\
+	 (FIFOTH       << 16) |			\
+	 (PTYPE        << 15) |			\
+	 (VCOMP        << 12) |			\
+	 (LCD_ON       << 11) |			\
+	 (ENDIAN       <<  9) |			\
+	 (BGR          <<  8) |			\
+	 (TFT          <<  5) |			\
+	 (BPP          <<  1) |			\
+	 (LCD_EN))
+
+#if defined(CONFIG_COLOR_DEPTH16)
+#define LCD_COLOR_DEPTH		0x4
+#define LCD_PANEL_BPP		16
+#elif defined(CONFIG_COLOR_DEPTH24)
+#define LCD_COLOR_DEPTH		0x5
+#define LCD_PANEL_BPP		24
+#else
+#define LCD_COLOR_DEPTH		0x5
+#define LCD_PANEL_BPP		24
+#endif
+
+#ifdef CONFIG_PANEL_AUA036QN01
+
+#define LCD_PANEL_WIDTH		320
+#define LCD_PANEL_HEIGHT	240
+
+#define LCD_TIME0		ENC_PARAM_TIME0(7, 6, 1, 320) /* 0x0605004c */
+#define LCD_TIME1		ENC_PARAM_TIME1(1, 1, 1, 240) /* 0x010100ef */
+#define LCD_TIME2		ENC_PARAM_TIME2(0, 0, 1, 1, 1, 0x7) /* 0x00003806 */
+#define LCD_CTRL		ENC_PARAM_CTRL(0, 0, 1, 1, 0x3, 1, 0x0, 1, 1, LCD_COLOR_DEPTH, 1) /* 0x0001b928 */
+
+#endif
+
+#ifdef CONFIG_PANEL_AUA070VW04
+
+#define LCD_PANEL_WIDTH		800
+#define LCD_PANEL_HEIGHT	480
+
+#define LCD_TIME0		ENC_PARAM_TIME0(88, 40, 128, 800)
+#define LCD_TIME1		ENC_PARAM_TIME1(21, 1, 3, 480)
+#define LCD_TIME2		ENC_PARAM_TIME2(0, 1, 1, 1, 1, 0x7)
+#define LCD_CTRL		ENC_PARAM_CTRL(0, 0, 1, 1, 0x3, 1, 0x0, 1, 1, LCD_COLOR_DEPTH, 1)
+
+#endif
+
+#ifdef CONFIG_PANEL_CH7013A
+
+#define LCD_TIME0		ENC_PARAM_TIME0(42, 10, 96, 640)
+#define LCD_TIME1		ENC_PARAM_TIME1(28, 5, 2, 480)
+#define LCD_TIME2		ENC_PARAM_TIME2(0, 1, 1, 0, 0, 0x3)
+#define LCD_CTRL		ENC_PARAM_CTRL(0, 0, 1, 0, 0x3, 1, 0x0, 1, 1, LCD_COLOR_DEPTH, 1)
+
+#endif /* CONFIG_CH7013A */
+
+#endif /* __LCD_INFO_H__ */
@@ -0,0 +1,142 @@
+#include "hal.h"
+#include "lcd/lcd.h"
+#include "lcd-info.h"
+
+#ifdef CONFIG_PLAT_AG101P_16MB
+	#define LCD_BASE		0x00e10000
+#else
+	#define LCD_BASE		0x90600000
+#endif
+
+#define LCD_TIME0_OFFSET	0x00
+#define LCD_TIME1_OFFSET	0x04
+#define LCD_TIME2_OFFSET	0x08
+#define LCD_BASE_OFFSET		0x10
+#define LCD_INT_EN_OFFSET	0x18
+#define LCD_CTRL_OFFSET		0x1C
+#define LCD_INT_CLR_OFFSET	0x20
+#define LCD_INT_MSK_OFFSET	0x24
+
+static pixel_t _drv_lcd_fb[ LCD_PANEL_WIDTH * LCD_PANEL_HEIGHT] __attribute__((aligned (64)));
+static pixel_t _drv_lcd_bg[ LCD_PANEL_WIDTH * LCD_PANEL_HEIGHT] __attribute__((aligned (64)));
+
+static pixel_t *drv_lcd_fb = _drv_lcd_fb;
+static pixel_t *drv_lcd_bg = _drv_lcd_bg;
+extern void nds32_dcache_flush();
+
+void drv_lcd_flip(void)
+{
+	pixel_t *tmp = drv_lcd_fb;
+
+	drv_lcd_fb = drv_lcd_bg;
+	drv_lcd_bg = tmp;
+
+	OUT32(LCD_BASE + LCD_BASE_OFFSET, drv_lcd_fb);
+}
+
+pixel_t *drv_lcd_get_fb(void)
+{
+	return drv_lcd_fb;
+}
+
+pixel_t *drv_lcd_get_bg(void)
+{
+	return drv_lcd_bg;
+}
+
+void drv_lcd_get_param(int *width, int *height, int *bpp)
+{
+	if (width)
+		*width = LCD_PANEL_WIDTH;
+
+	if (height)
+		*height = LCD_PANEL_HEIGHT;
+
+	if (bpp)
+		*bpp = LCD_PANEL_BPP;
+}
+
+void drv_lcd_fill_bg(void)
+{
+	pixel_t *base = drv_lcd_bg;
+
+	int i, j;
+	for (i = j = 0; j < LCD_PANEL_HEIGHT; j++) {
+		for (i = 0; i < LCD_PANEL_WIDTH; i++) {
+#if defined(CONFIG_COLOR_DEPTH16)
+			if (i == 0 || i == (LCD_PANEL_WIDTH - 1) || j == 0 || j == (LCD_PANEL_HEIGHT - 1))
+				*base++ = 0xFFFFu;
+			else
+				*base++ = 0x0000u;
+#elif defined(CONFIG_COLOR_DEPTH24)
+			if (i == 0 || i == (LCD_PANEL_WIDTH - 1) || j == 0 || j == (LCD_PANEL_HEIGHT - 1))
+				*base++ = 0x00FFFFFFu;
+			else
+				*base++ = 0x00000000u;
+#else
+#error "COLOR DEPTH not supported!"
+#endif
+		}
+	}
+}
+
+void drv_lcd_draw_bg(void)
+{
+	pixel_t *src = drv_lcd_bg;
+	pixel_t *dst = drv_lcd_fb;
+
+	int i = 0;
+	while (i++ < LCD_PANEL_WIDTH * LCD_PANEL_HEIGHT)
+		*dst++ = *src++;
+}
+
+static void _drv_lcd_init(void)
+{
+	OUT32(LCD_BASE + LCD_TIME0_OFFSET, LCD_TIME0);
+	OUT32(LCD_BASE + LCD_TIME1_OFFSET, LCD_TIME1);
+	OUT32(LCD_BASE + LCD_TIME2_OFFSET, LCD_TIME2);
+	OUT32(LCD_BASE + LCD_CTRL_OFFSET, LCD_CTRL);
+
+	OUT32(LCD_BASE + LCD_BASE_OFFSET, drv_lcd_fb);
+}
+
+void drv_lcd_draw_rect(int x, int w, int y, int h, int r, int g, int b)
+{
+	pixel_t *base = drv_lcd_fb;
+
+	int i, j;
+	for (i = y; i < y + h; i++)
+		for (j = x; j < x + w; j++)
+#if defined(CONFIG_COLOR_DEPTH16)
+			base[ i * LCD_PANEL_WIDTH + j] = (pixel_t)(((r >> 3)  << 11) | ((g >> 2) << 5) | ((b >> 3)  << 0));
+#elif defined(CONFIG_COLOR_DEPTH24)
+			base[ i * LCD_PANEL_WIDTH + j] = (pixel_t)((r << 16) | (g << 8) | b);
+#endif
+	nds32_dcache_flush(); /* undefine CONFIG_CPU_DCACHE_WRITETHROUGH ,flush DCACHE for lcd screen */
+}
+
+void drv_lcd_erase_rect(int x, int w, int y, int h)
+{
+	pixel_t *base = drv_lcd_fb;
+
+	int i, j;
+	for (i = y; i < y + h; i++)
+		for (j = x; j < x + w; j++)
+			base[ i * LCD_PANEL_WIDTH + j] = drv_lcd_bg[ i * LCD_PANEL_WIDTH + j];
+}
+
+void draw_blk(int x, int y, int sz, int border, int r, int g, int b)
+{
+	drv_lcd_draw_rect(x, sz, y, sz, r, g, b);
+	drv_lcd_draw_rect(x + border, sz - 2 * border, y + border, sz - 2 * border, r ^ 0xff, g ^ 0xff, b ^ 0xff);
+}
+
+int drv_lcd_init(void)
+{
+	_drv_lcd_init();
+	drv_lcd_fill_bg();
+	drv_lcd_draw_bg();
+	drv_lcd_flip();
+
+	return 0;
+}
@@ -0,0 +1,29 @@
+#ifndef __LCD_H__
+#define __LCD_H__
+
+#include <inttypes.h>
+#include "lcd-info.h"
+
+#if defined(CONFIG_COLOR_DEPTH16)
+	typedef uint16_t pixel_t;
+#elif defined(CONFIG_COLOR_DEPTH24)
+	typedef uint32_t pixel_t;
+#else
+	#error "Unsupported COLOR_DEPTH!"
+	typedef int pixel_t;
+#endif
+
+extern void	drv_lcd_flip(void);
+extern pixel_t *drv_lcd_get_fb(void);
+extern pixel_t *drv_lcd_get_bg(void);
+extern void	drv_lcd_get_param(int *width, int *height, int *bpp);
+extern void	drv_lcd_fill_bg(void);
+extern void	drv_lcd_draw_bg(void);
+extern void	drv_lcd_draw_rect(int x, int w, int y, int h, int r, int g, int b);
+extern void	drv_lcd_erase_rect(int x, int w, int y, int h);
+extern void	draw_blk(int x, int y, int sz, int border, int r, int g, int b);
+extern int	drv_lcd_init(void);
+
+extern void	draw_font(int x, int y, int ascii);
+
+#endif /* __LCD_H__ */
@@ -0,0 +1,74 @@
+#include "hal.h"
+#include "uart/uart.h"
+#include "osc.h"
+#include "os_except.h"
+
+#define osc_hisr_TASK_PRIORITY 31	// osc_hisr must be the highest priority task of all tasks.
+
+/*
+ *********************************************************************************************************
+ *                                      Overlay SRAM Controller (OSC) initialize
+ *
+ * Description : This function is called to initialize overlay SRAM controller,
+ *               including setting upfixed region size and overlay region base.
+ *
+ * Arguments   :
+ *
+ * Notes       :
+ *********************************************************************************************************
+ */
+void _osc_init(void)
+{
+	register unsigned int ovly_region_szie;
+	register unsigned int fix_regiion_size;
+	register unsigned int ovly_region_base_addr;
+
+	/* Read the initial OSC overlay region size. */
+	ovly_region_szie = (REG32(OSC_CTRL) & OSC_CTRL_OVL_SZ_MASK) >> 12;
+
+	/* Initialize OSC fix region size */
+	fix_regiion_size = OSC_EILM_SIZE - ovly_region_szie;
+	REG32(OSC_OVLFS) = fix_regiion_size;
+
+	/* Initialize OSC overlay region to the end of all overlay text. */
+	ovly_region_base_addr = fix_regiion_size + ovly_region_szie * _novlys;
+	REG32(OSC_OVLBASE) = ovly_region_base_addr;
+}
+
+int _osc_drv_init(void (*handler)(unsigned int ipc),
+                   void (*osc_hisr)(void *arg),
+                   OSC_DRV_INFO *osc_info)
+{
+	hal_queue_t     *queue = &osc_info->queue;
+	hal_thread_t    *th    = &osc_info->th;
+
+	// Initial the Fixed/Overlap regions.
+	_osc_init();
+
+	// Register a user-define handler which is called from OSC exception handler.
+	register_exception_handler(GE_RESERVED_INST, handler);
+
+	// Register a user-define hisr which will be woken up by lisr sending msg to queue.
+	th->fn             = osc_hisr;
+        th->name           = "bh_osc";
+        th->stack_size     = 0x400;
+        th->arg            = queue;
+        th->prio           = osc_hisr_TASK_PRIORITY;
+        th->task           = NULL;
+        th->ptos           = NULL;
+
+	// Create a bottom half.
+	// The bottom half is a thread task with a sync queue.
+	queue->size = 1;
+
+        if(hal_create_queue(queue) == HAL_FAILURE)
+                return HAL_FAILURE;
+
+	if(hal_create_thread(th) != HAL_SUCCESS)
+		return HAL_FAILURE;
+
+	puts("OSC driver init success!\n");
+
+	return HAL_SUCCESS;
+}
+
@@ -0,0 +1,77 @@
+#ifndef __OSC_H__
+#define __OSC_H__
+
+#include "hal.h"
+
+#define OVLY_SEG(NAME)  __attribute__((section(#NAME)))
+
+/*
+        TYPES OF GENERAL EXCEPTION
+*/
+#define GE_ALIGN_CHECK                          0
+#define GE_RESERVED_INST                        1
+#define GE_TRAP                                 2
+#define GE_ARITHMETIC                           3
+#define GE_PRECISE_BUS_ERR                      4
+#define GE_INPRECISE_BUS_ERR                    5
+#define GE_COPROCESSOR                          6
+#define GE_PRIVILEGE_INST                       7
+#define GE_RESERVED_VALUE                       8
+#define GE_NON_EXIST_LOCAL_MEM                  9
+#define GE_MPZIU_CTRL                           10
+
+/*
+        structure of overlay control registers
+        Please define this structure based on your hardware design
+*/
+typedef struct
+{
+        unsigned int reserved ;
+        unsigned int root_size ;
+        unsigned int base_addr ;
+        unsigned int end_addr ;
+        volatile unsigned int dma ;
+} OVLY_REGS ;
+
+typedef struct
+{
+        unsigned long vma;
+        unsigned long size;
+        unsigned long lma;
+        unsigned long mapped;
+} OVLY_TABLE ;
+
+typedef struct
+{
+	unsigned int            ipc;
+        OVLY_REGS               *povl;
+
+} OVL_CTRL;
+
+typedef struct {
+
+        hal_queue_t     queue;
+        hal_thread_t    th;
+
+	OVL_CTRL		povl_ctrl;
+
+} OSC_DRV_INFO;
+
+/* _novlys from overlay table in linker script stands for number of overlay regions. */
+extern int   _novlys;
+extern OVLY_TABLE    _ovly_table[] ;
+extern char __ovly_lmastart_OVL_RAM;
+
+static volatile int overlay_busy = 0;
+
+void __attribute__((no_prologue)) osc_init();
+int _osc_drv_init(void (*handler)(unsigned int ipc),
+                   void (*osc_hisr)(void *arg),
+                   OSC_DRV_INFO *osc_info);
+
+#ifdef CONFIG_OSC_DEBUG_SUPPORT
+#define OVLY_DEBUG
+#endif
+
+
+#endif
@@ -0,0 +1,3 @@
+lib-y		+=
+lib-y		+= sdd.o
+lib-y		+= sdd_sd.o
@@ -0,0 +1,143 @@
+/*****************************************************************************
+ *
+ *            Copyright Andes Technology Corporation 2007-2008
+ *                         All Rights Reserved.
+ *
+ *  Revision History:
+ *
+ *    Aug.21.2007     Created.
+ ****************************************************************************/
+
+/*****************************************************************************
+ *
+ * FILE NAME                                         VERSION
+ *
+ *   sd.h                     
+ *
+ * DESCRIPTION
+ *
+ *   SD controller driver interfaces for client applications.
+ *   (Nucleus I/O Driver Architecture)
+ *
+ * DATA STRUCTURES
+ *
+ *   None
+ *
+ * DEPENDENCIES
+ *
+ *   ag101regs.h
+ *   ag101defs.h
+ *
+ ****************************************************************************/
+#ifndef __SD_H__
+#define __SD_H__
+
+#include <inttypes.h>
+/*
+ * SDD I/O control code, used for clients not using driver wrapper routines,
+ * i.e., when not using middle-ware interfaces.  Driver implementation target
+ * is that almost every IOCTL should exist a corresponding wrapper routine.
+ */
+typedef enum SDD_IOCTL {
+	SDD_IOCTL_READ_SECTORS,		/* Parameter: pointer to SDD_IOCTL_READ_SECTORS_PARAM struct */
+	SDD_IOCTL_WRITE_SECTORS,	/* Parameter: pointer to SDD_IOCTL_WRITE_SECTORS_PARAM struct */
+} SDD_IOCTL;
+
+/* Parameter struct for SDD_IOCTL_ */
+typedef struct _SDD_IOCTL_READ_SECTORS_PARAM {
+
+	uint32_t lba_sector;	/* start sector number */
+	uint32_t sector_count;	/* number of sectors included in this operation */
+	uint32_t sector_size;	/* sector size in bytes */
+	void *io_buff;		/* buffer pointer */
+
+} SDD_IOCTL_READ_SECTORS_PARAM;
+
+typedef struct _SDD_IOCTL_WRITE_SECTORS_PARAM {
+
+	uint32_t lba_sector;	/* start sector number */
+	uint32_t sector_count;	/* number of sectors included in this operation */
+	uint32_t sector_size;	/* sector size in bytes */
+	void *io_buff;		/* buffer pointer */
+
+} SDD_IOCTL_WRITE_SECTORS_PARAM;
+
+typedef enum SDD_EVENTS {
+
+	SDD_EVENT_CD = 0x00000001,	/* Card-detection event. Event parameter: SDD_CD_EVENT */
+
+} SDD_EVENTS;
+
+typedef enum SDD_CD_EVENT_PARAM {
+	SDD_CD_CARD_INSERTED = 1,
+	SDD_CD_CARD_REMOVED = 0,
+
+} SDD_CD_EVENT_PARAM;
+
+typedef enum SDD_DMA_MODE {
+	SDD_DMA_NONE = 0,	/* no dma, deivce i/o is through pio */
+	SDD_DMA_DCH = 1,	/* dma channel is dynamically allocated on i/o request and get free after dma. */
+	SDD_DMA_SCH = 2,	/* dma channel is allocated and occupied during device initialization. */
+
+} SDD_DMA_MODE;
+
+/* Define data structures for management of CF device. */
+typedef struct SDD_DEVICE_STRUCT {
+
+	void *bdev_id;		/* (reserved) The block device context. This field is reserved by the driver. */
+	uint8_t dma;		/* (in)  one of the enum value in SDD_DMA_MODE. */
+	uint8_t func;		/* (in)  (Reserved currently) Preferred SD card function mode (SD Memory, SD/IO, SPI) */
+	uint8_t padding[2];	/* stuff bytes */
+
+} SDD_DEVICE;
+
+/*****************************************************************************
+ * Note: Everything below is designed as an interface wrapper to access 
+ *       SD driver.
+ *
+ * [Structures]
+ *
+ * [Functions]
+ *
+ *
+ ****************************************************************************/
+
+/* driver generic error code for SDC */
+#define SDD_SUCCESS              0x00
+#define SDD_INVALID_INIT         0x01
+#define SDD_INVALID_REQUEST      0x02
+#define SDD_NOT_SUPPORTED        0x03
+
+#define SDD_INVALID_FUNCTION     0x11
+#define SDD_INVALID_PARAMETER    0x12
+#define SDD_CARD_REMOVED         0x13
+#define SDD_INVALID_MEDIA        0x14
+#define SDD_INVALID_IOCTL        0x15
+#define SDD_WRITE_DATA_ERROR     0x16
+#define SDD_READ_DATA_ERROR      0x17
+#define SDD_INVLAID_ADDRESS      0x18
+#define SDD_INVLAID_ADDR_RANGE   0x19
+
+#define SDD_CMD_TIMEOUT          0x21
+#define SDD_CMD_ERROR            0x22
+#define SDD_RSP_TIMEOUT          0x23
+#define SDD_RSP_CRC_ERROR        0x24
+#define SDD_NOT_SUPPORT_ACMD     0x25
+#define SDD_CSR_ERROR            0x26
+#define SDD_INVALID_STATE        0x27
+#define SDD_WAIT_TIMEOUT         0x28
+#define SDD_WRITE_PROTECTED      0x29
+#define SDD_CARD_LOCKED          0x30
+
+extern void _sdd_lisr(int vector);
+extern void _sdd_hisr(void *param);
+extern uint32_t NDS_SD_Init(SDD_DEVICE * sdd_dev);
+extern void NDS_SD_Unload(void);
+extern uint32_t NDS_SD_ReadSectors(SDD_DEVICE * sdd_dev, uint32_t sector,
+				   uint32_t sector_count, uint32_t sector_size,
+				   void *buffer);
+extern uint32_t NDS_SD_WriteSectors(SDD_DEVICE * sdd_dev, uint32_t sector,
+				    uint32_t sector_count, uint32_t sector_size,
+				    void *buffer);
+
+#endif /* __SD_H__ */
@@ -0,0 +1 @@
+lib-${CONFIG_FTSSP010}		:= sspd_ac97.o sspd_rts.o
@@ -0,0 +1,199 @@
+/*****************************************************************************
+ *
+ *            Copyright Andes Technology Corporation 2007-2008
+ *                         All Rights Reserved.
+ *
+ *  Revision History:
+ *
+ *    Mar.16.2008     Created.
+ ****************************************************************************/
+
+/*****************************************************************************
+ *
+ * FILE NAME                                         VERSION
+ *
+ *      sspd_rts.h
+ *
+ * DESCRIPTION
+ *
+ *      SPI digital serial interface protocol header for resistive
+ *      touch screen controller.
+ *
+ * DATA STRUCTURES
+ *
+ *   None
+ *
+ * DEPENDENCIES
+ *
+ *   None
+ *
+ ****************************************************************************/
+#ifndef __SSPD_RTS_H__
+#define __SSPD_RTS_H__
+
+/*****************************************************************************
+ * Configuration Options
+ ****************************************************************************/
+
+/* Non-zero to enable 16-clock per conversion mode, otherwise 24-clock cycle is applied. */
+#define RTS_16CLK_CONV_CYCLE    1
+
+#define RTS_LISR_VECTOR		INTC_HW0_BIT		/* AG101 connects #PENIRQ to hw0 vector */
+
+/* polling loop counter for waiting hw-reset */
+#define RTS_RESET_WAIT		(0x300000)
+
+/* CPU polling counter to avoid bouncing signals of previous RTS operation */
+#define RTS_DEBOUNCE_WAIT	(0x30000)
+
+/* polling counter for serial data in */
+#define RTS_DIN_TIMEOUT		(0x30000)
+
+/* HISR definitions */
+#define RTS_HISR_PRIORITY	0		/* 0: highest, 2: lowest */
+#define RTS_HISR_STACK_SIZE	2048		/* Please align to 32-bit */
+
+#define RTS_HISR_AS_TOUCHED	0x00000001	/* Activate HISR for touched interrupt */
+
+
+/*****************************************************************************
+ * Resistive Touch Screen Digital Interface Definitions
+ ****************************************************************************/
+
+/* Definitions for ADS7846 */
+
+/* Control Byte Bits */
+#define RTS_ADS7846_PD_MASK	0x03		/* Start Bit (MSB) */
+#define RTS_ADS7846_PD_SHIFT	0
+    #define RTS_ADS7846_PD	0x00		/* power down between conversion, #penirq enabled */
+    #define RTS_ADS7846_ADC	0x01		/* ref off, adc on, #penirq disabled */
+    #define RTS_ADS7846_REF	0x02		/* ref on, adc off, #penirq enabled */
+    #define RTS_ADS7846_PW	0x03		/* power on, ref on, adc on, #penirq disabled */
+
+#define RTS_ADS7846_SER_MASK	0x04		/* Single-Ended/#Differential-Reference Register */
+#define RTS_ADS7846_SER_SHIFT	2
+    #define RTS_ADS7846_DF	0x00		/* differential */
+    #define RTS_ADS7846_SE	0x01		/* single-ended */
+
+#define RTS_ADS7846_MODE_MASK	0x08		/* Conversion Selection Bit */
+#define RTS_ADS7846_MODE_SHIFT	3
+    #define RTS_ADS7846_12_BITS	0x00		/* 12 bits conversion */
+    #define RTS_ADS7846_8_BITS	0x01		/* 8 bits conversion */
+
+#define RTS_ADS7846_MUX_MASK	0x70		/* (A2 ~ A0) Control the setting of multiplexer input */
+#define RTS_ADS7846_MUX_SHIFT	4
+
+    #define RTS_ADS7846_DF_X	0x05		/* [A2:A0] 101b, Driver: X+ X-, Measure Y+ */
+    #define RTS_ADS7846_DF_Y	0x01		/* [A2:A0] 001b, Driver: Y+ Y-, Measure X+ */
+    #define RTS_ADS7846_DF_Z1	0x03		/* [A2:A0] 011b, Driver: Y+ X-, Measure X+ */
+    #define RTS_ADS7846_DF_Z2	0x04		/* [A2:A0] 100b, Driver: Y+ X-, Measure Y- */
+
+    #define RTS_ADS7846_SE_X	0x05		/* [A2:A0] 101b */
+    #define RTS_ADS7846_SE_Y	0x01		/* [A2:A0] 001b */
+    #define RTS_ADS7846_SE_Z1	0x03		/* [A2:A0] 011b */
+    #define RTS_ADS7846_SE_Z2	0x04		/* [A2:A0] 100b */
+    #define RTS_ADS7846_SE_BAT	0x02		/* [A2:A0] 010b */
+    #define RTS_ADS7846_SE_AUX	0x06		/* [A2:A0] 110b */
+    #define RTS_ADS7846_SE_TEMP0	0x00	/* [A2:A0] 000b */
+    #define RTS_ADS7846_SE_TEMP1	0x07	/* [A2:A0] 111b */
+
+#define RTS_ADS7846_START_MASK	0x80            /* Start Bit (MSB) */
+#define RTS_ADS7846_START_BIT	7
+    #define RTS_ADS7846_START	1
+
+/* Supplimental Macros */
+#define RTS_ADS7846_PADDING_BYTE	0	/* Padding byte feed after the command byte to continue serial clocking */
+
+#define RTS_ADS7846_CTRL_BYTE(mux, mode, ser, pd)                            \
+    ((((uint32_t)(mux) << RTS_ADS7846_MUX_SHIFT) & RTS_ADS7846_MUX_MASK) |    \
+     (((uint32_t)(mode) << RTS_ADS7846_MODE_SHIFT) & RTS_ADS7846_MODE_MASK) | \
+     (((uint32_t)(ser) << RTS_ADS7846_SER_SHIFT) & RTS_ADS7846_SER_MASK) |    \
+     (((uint32_t)(pd) << RTS_ADS7846_PD_SHIFT) & RTS_ADS7846_PD_MASK) |       \
+     (uint32_t)RTS_ADS7846_START_MASK)
+
+/* this is correct */
+#define RTS_ADS7846_8BITS_DATA(msb, lsb)    ((((uint32_t)(msb) & 0x07) << 5) | (((uint32_t)(lsb) & 0xff) >> 3))
+#ifndef CONFIG_PLAT_QEMU
+#define RTS_ADS7846_12BITS_DATA(msb, lsb)   ((((uint32_t)(msb) & 0x7f) << 5) | (((uint32_t)(lsb) & 0xff) >> 3))
+#else
+#define RTS_ADS7846_12BITS_DATA(msb, lsb)   msb
+//#define RTS_ADS7846_12BITS_DATA(msb, lsb)   ((msb >> 19) & 0xfff)
+#endif
+
+/* Pre-defined Control-Byte Constants */
+#define RTS_ADS7846_CTL_RY  RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_Y, RTS_ADS7846_12_BITS,    \
+                                                  RTS_ADS7846_DF, RTS_ADS7846_PW)
+#define RTS_ADS7846_CTL_RX  RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_X, RTS_ADS7846_12_BITS,    \
+                                                  RTS_ADS7846_DF, RTS_ADS7846_PW)
+#define RTS_ADS7846_CTL_RZ1 RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_Z1, RTS_ADS7846_12_BITS,   \
+                                                  RTS_ADS7846_DF, RTS_ADS7846_PW)
+#define RTS_ADS7846_CTL_RZ2 RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_Z2, RTS_ADS7846_12_BITS,   \
+                                                  RTS_ADS7846_DF, RTS_ADS7846_PW)
+
+#define RTS_ADS7846_CTL_RY_PD   RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_Y, RTS_ADS7846_12_BITS,    \
+                                                      RTS_ADS7846_DF, RTS_ADS7846_PD)
+#define RTS_ADS7846_CTL_RX_PD   RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_X, RTS_ADS7846_12_BITS,    \
+                                                      RTS_ADS7846_DF, RTS_ADS7846_PD)
+#define RTS_ADS7846_CTL_RZ1_PD  RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_Z1, RTS_ADS7846_12_BITS,   \
+                                                      RTS_ADS7846_DF, RTS_ADS7846_PD)
+#define RTS_ADS7846_CTL_RZ2_PD  RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_Z2, RTS_ADS7846_12_BITS,   \
+                                                      RTS_ADS7846_DF, RTS_ADS7846_PD)
+#define RTS_ADS7846_CTL_PD      RTS_ADS7846_CTRL_BYTE(RTS_ADS7846_DF_Y, RTS_ADS7846_12_BITS,    \
+                                                      RTS_ADS7846_DF, RTS_ADS7846_PD)
+/*
+ * DCLK
+ * ---------------
+ * From pp3:
+ *   125 kHz max throughput rate, so ...
+ *     DCLK_max = 125k * 16(16-clock-per-conversion mode) = 2.0MHz
+ *
+ * From table VI (p.p.14):
+ *   (tch + tcl) = 400ns minimum, so ...
+ *     DCLK_max = 1/400ns = 2.5MHz ?
+ */
+#define RTS_ADS7846_DCLK_MAX                2000000     /* adopt 2.0MHz for safe */
+#define RTS_ADS7846_DCLK_DEFAULT            125000      /* 7812 data per second (3906 x-y/sec, or 1953 x-y-z1-z2/sec) */
+
+
+/*****************************************************************************
+ * SSP Controller Resistive Touch Screen Driver-Supplement Interfaces
+ ****************************************************************************/
+struct ts_data {
+
+	int	x;
+	int	y;
+	int	z1;
+	int	z2;
+	int	pressed;
+
+};
+
+struct ts_dev {
+
+	int left;
+	int right;
+	int top;
+	int bottom;
+
+	int lcd_width;
+	int lcd_height;
+
+	int			penirq;		/* initialize touch screen driver in #penirq mode or polling mode */
+	int			penirq_en;	/* enable #penirq after initialization if penirq is non-zero */
+
+	void			*event_obj;	/* (in) Event object to notify app about the interrupt. */
+	struct ts_data		*event_data;	/* Client specified struct pointer to receive {x,y,touched} states */
+
+	hal_semaphore_t		sem;
+	struct ts_data		data;
+};
+
+extern int _sspd_rts_init(struct ts_dev *ts);
+extern int _sspd_rts_probe(int *x, int *y, int *z1, int *z2, int *pressed);
+
+extern void ts_adjust(struct ts_dev *ts, int ts_x, int ts_y, int *x, int *y);
+extern void ts_raw_value(struct ts_dev *ts, int *x, int *y);
+extern void ts_value(struct ts_dev *ts, int *x, int *y);
+extern void ts_init(struct ts_dev *ts);
+extern void ts_calibrate(struct ts_dev *ts, void (*draw_cross)(void *param, int x, int y), int count);
+#endif /* __SSPD_RTS_H__ */
@@ -0,0 +1,2 @@
+lib-y		:=
+lib-y		+= uart.o
@@ -0,0 +1,143 @@
+#include <nds32_intrinsic.h>
+
+#define DEFAULT_BAUDRATE	115200 /* 8n1 */
+
+#define IN8(reg) 		(uint8_t)((*(volatile unsigned long *)(reg)) & 0x000000FF)
+#define READ_CLR(reg) 	(*(volatile unsigned long *)(reg))
+
+int drv_uart_set_baudrate(int baudrate)
+{
+	unsigned long baud_div;	/* baud rate divisor */
+	unsigned long temp_word;
+
+	baud_div = (MB_UCLK / (16 * baudrate));
+
+	/* Save LCR temporary */
+	temp_word = IN8(STUARTC_BASE + UARTC_LCR_OFFSET);
+
+	/* Setup dlab bit for baud rate setting */
+	OUT8(STUARTC_BASE + UARTC_LCR_OFFSET, (temp_word | UARTC_LCR_DLAB));
+
+	/* Apply baud rate */
+	OUT8(STUARTC_BASE + UARTC_DLM_OFFSET, (unsigned char)(baud_div >> 8));
+	OUT8(STUARTC_BASE + UARTC_DLL_OFFSET, (unsigned char)baud_div);
+	OUT8(STUARTC_BASE + UARTC_PSR_OFFSET, (unsigned char)1);
+
+	/* Restore LCR */
+	OUT8(STUARTC_BASE + UARTC_LCR_OFFSET, temp_word);
+	
+	return 0;
+}
+
+int drv_uart_is_kbd_hit(void)
+{
+	return IN8(STUARTC_BASE + UARTC_LSR_OFFSET) & UARTC_LSR_RDR;
+}
+
+int drv_uart_get_char(void)
+{
+	while (!(IN8(STUARTC_BASE + UARTC_LSR_OFFSET) & UARTC_LSR_RDR))
+		;
+
+	return IN8(STUARTC_BASE + UARTC_RBR_OFFSET);
+}
+
+void drv_uart_put_char(int ch)
+{
+	while (!(IN8(STUARTC_BASE + UARTC_LSR_OFFSET) & UARTC_LSR_THRE))
+		;
+
+	OUT8(STUARTC_BASE + UARTC_THR_OFFSET, ch);
+}
+
+int drv_uart_init(void)
+{
+	/* Clear everything */
+	OUT8(STUARTC_BASE + UARTC_IER_OFFSET, 0x0);
+	OUT8(STUARTC_BASE + UARTC_LCR_OFFSET, 0x0);
+
+	/* Setup baud rate */
+	drv_uart_set_baudrate(DEFAULT_BAUDRATE);
+
+	/* Setup parity, data bits, and stop bits */
+	OUT8(STUARTC_BASE + UARTC_LCR_OFFSET, \
+			(UARTC_LCR_PARITY_NONE | UARTC_LCR_BITS8 | UARTC_LCR_STOP1));
+
+	return 0;
+}
+
+/**********************************************
+ *
+ * Archer Chang
+ *
+ * driver API with reg base
+ *
+***********************************************/
+int __drv_uart_set_baudrate(unsigned int regbase, int baudrate)
+{
+	unsigned long baud_div;	/* baud rate divisor */
+	unsigned long temp_word;
+
+	baud_div = (MB_UCLK / (16 * baudrate));
+
+	/* Save LCR temporary */
+	temp_word = IN8(regbase + UARTC_LCR_OFFSET);
+
+	/* Setup dlab bit for baud rate setting */
+	OUT8(regbase + UARTC_LCR_OFFSET, (temp_word | UARTC_LCR_DLAB));
+
+	/* Apply baud rate */
+	OUT8(regbase + UARTC_DLM_OFFSET, (unsigned char)(baud_div >> 8));
+	OUT8(regbase + UARTC_DLL_OFFSET, (unsigned char)baud_div);
+	OUT8(regbase + UARTC_PSR_OFFSET, (unsigned char)1);
+
+	/* Restore LCR */
+	OUT8(regbase + UARTC_LCR_OFFSET, temp_word);
+
+	return 0;
+}
+
+int __drv_uart_is_kbd_hit(unsigned int regbase)
+{
+	return IN8(regbase + UARTC_LSR_OFFSET) & UARTC_LSR_RDR;
+}
+
+int __drv_uart_get_char(unsigned int regbase)
+{
+	while (!(IN8(regbase + UARTC_LSR_OFFSET) & UARTC_LSR_RDR))
+		;
+
+	return IN8(regbase + UARTC_RBR_OFFSET);
+}
+
+void __drv_uart_put_char(unsigned int regbase, int ch)
+{
+	while (!(IN8(regbase + UARTC_LSR_OFFSET) & UARTC_LSR_THRE))
+		;
+
+	OUT8(regbase + UARTC_THR_OFFSET, ch);
+}
+
+int __drv_uart_put_char_nowait(unsigned int regbase, int ch)
+{
+	OUT8(regbase + UARTC_THR_OFFSET, ch);
+
+	return 1;
+}
+
+int __drv_uart_init(unsigned int regbase, int baudrate)
+{
+	/* Clear everything */
+	OUT8(regbase + UARTC_IER_OFFSET, 0x0);
+	OUT8(regbase + UARTC_LCR_OFFSET, 0x0);
+
+	/* Setup baud rate */
+	__drv_uart_set_baudrate(regbase, baudrate);
+
+	/* Setup parity, data bits, and stop bits */
+	OUT8(regbase + UARTC_LCR_OFFSET, \
+			(UARTC_LCR_PARITY_NONE | UARTC_LCR_BITS8 | UARTC_LCR_STOP1));
+
+	return 0;
+}
+
@@ -0,0 +1,17 @@
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+extern int drv_uart_init(void);
+extern int drv_uart_set_baudrate(int baudrate);
+extern int drv_uart_is_kbd_hit(void);
+extern int drv_uart_get_char(void);
+extern void drv_uart_put_char(int ch);
+
+extern int  __drv_uart_init           (unsigned int regbase, int baudrate);
+extern int  __drv_uart_set_baudrate   (unsigned int regbase, int baudrate);
+extern int  __drv_uart_is_kbd_hit     (unsigned int regbase);
+extern int  __drv_uart_get_char       (unsigned int regbase);
+extern void __drv_uart_put_char       (unsigned int regbase, int ch);
+extern void __drv_uart_put_char_nowait(unsigned int regbase, int ch);
+
+#endif /* __DRV_UART_H__ */
@@ -0,0 +1,80 @@
+#ifndef __NDS32_H__
+#define __NDS32_H__
+
+#include "nds32_defs.h"
+
+/* Support FPU */
+#if defined(__NDS32_EXT_FPU_DP__) || defined(__NDS32_EXT_FPU_SP__)
+#define __TARGET_FPU_EXT
+#if defined(__NDS32_EXT_FPU_CONFIG_0__)
+#define FPU_REGS        8
+#elif defined(__NDS32_EXT_FPU_CONFIG_1__)
+#define FPU_REGS        16
+#elif defined(__NDS32_EXT_FPU_CONFIG_2__)
+#define FPU_REGS        32
+#elif defined(__NDS32_EXT_FPU_CONFIG_3__)
+#define FPU_REGS        64
+#else
+#error FPU register numbers no defined
+#endif
+#endif
+
+/* Support IFC */
+#ifdef __NDS32_EXT_IFC__
+#ifndef CONFIG_NO_NDS32_EXT_IFC
+#define __TARGET_IFC_EXT
+#endif
+#endif
+
+/* Support ZOL */
+#ifdef CONFIG_HWZOL
+#define __TARGET_ZOL_EXT
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include "nds32_intrinsic.h"
+
+#define GIE_ENABLE()                    __nds32__gie_en()
+#define GIE_DISABLE()                   __nds32__gie_dis()
+
+#ifdef CONFIG_CPU_DCACHE_ENABLE
+
+#define NDS_DCache_Flush                nds32_dcache_flush
+#define NDS_DCache_Invalidate_Flush     nds32_dcache_invalidate
+#define NDS_DCache_Writeback            nds32_dcache_flush_range
+
+#else
+
+#define NDS_DCache_Flush()              ((void)0)
+#define NDS_DCache_Invalidate_Flush()   ((void)0)
+#define NDS_DCache_Writeback()          ((void)0)
+
+#endif
+
+static inline void GIE_SAVE(unsigned long *var)
+{
+	*var = __nds32__mfsr(NDS32_SR_PSW);
+	GIE_DISABLE();
+}
+
+static inline void GIE_RESTORE(unsigned long var)
+{
+	if (var & PSW_mskGIE)
+		GIE_ENABLE();
+}
+
+extern void *OS_CPU_Vector_Table[32];
+typedef void (*isr_t)(int vector);
+
+static inline void register_isr(int vector, isr_t isr, isr_t *old)
+{
+	if (old)
+		*old = OS_CPU_Vector_Table[vector];
+
+	OS_CPU_Vector_Table[vector] = isr;
+}
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __NDS32_H__ */
@@ -0,0 +1,54 @@
+#include "hal.h"
+#include "uart/uart.h"
+#include "osc/osc.h"
+#include "os_except.h"
+
+/*
+ *********************************************************************************************************
+ *                                      Register Exception Handlers
+ *
+ * Description : This function is called to register general exception handler.
+ *               The total number of general exception is 16.
+ *
+ * Arguments   : ipc
+ *
+ * Notes       :
+ *********************************************************************************************************
+ */
+inline void register_exception_handler(int genneral_except_num, void (*handler)(unsigned int ipc))
+{
+	if (genneral_except_num >= 16)
+	{
+		puts("Non-exist general exception number.\n");
+		while (1);
+	}
+
+        General_Exception_Handler_Table[genneral_except_num] = handler;
+}
+
+/*
+ *********************************************************************************************************
+ *                                      Exception Dispatcher
+ *
+ * Description : This function is called from exception handler to dispatch different
+ *               exception handler according to register itype.
+ *
+ * Arguments   : ipc
+ *
+ * Notes       :
+ *********************************************************************************************************
+ */
+void OS_CPU_EXCEPTION_Dispatcher(unsigned int ipc)
+{
+    /* Interrupt is still disabled at this point */
+    /* get all needed system registers' values before re-enable interrupt */
+    unsigned int itype = __nds32__mfsr (NDS32_SR_ITYPE);
+    unsigned int exception_num;
+    void (*pHandler)(unsigned int ipc);
+
+    exception_num = itype & 0xf;
+
+    pHandler = General_Exception_Handler_Table[exception_num];
+
+    pHandler(ipc);
+}
@@ -0,0 +1,23 @@
+#ifndef __OS_EXCEPT_H__
+#define __OS_EXCEPT_H__
+
+/***********************************
+        TYPES OF GENERAL EXCEPTION
+ ***********************************/
+#define GE_ALIGN_CHECK                          0
+#define GE_RESERVED_INST                        1
+#define GE_TRAP                                 2
+#define GE_ARITHMETIC                           3
+#define GE_PRECISE_BUS_ERR                      4
+#define GE_INPRECISE_BUS_ERR                    5
+#define GE_COPROCESSOR                          6
+#define GE_PRIVILEGE_INST                       7
+#define GE_RESERVED_VALUE                       8
+#define GE_NON_EXIST_LOCAL_MEM                  9
+#define GE_MPZIU_CTRL                           10
+
+void *General_Exception_Handler_Table[16];
+
+inline void register_exception_handler(int genneral_except_num, void (*handler)(unsigned int ipc));
+
+#endif
@@ -0,0 +1,49 @@
+E-Mail : Archer Zhang <archer.zhang@wh-mx.com>
+
+******************************
+文件（夹）添加和修改
+******************************
+[1] 在bsp目录下，添加AE210P目录，这是Andes AE210P EVB（N1068A）的主目录；
+[2] 在libcpu目录下，添加nds32目录，这是Andes N10系列Core的体系目录；
+[3] 由于编译器的原因，修改了finsh.h文件的Line：74～75，如下
+	#if !(defined(__GNUC__) && defined(__x86_64__))
+	//typedef unsigned int size_t; // 注释这个typedef
+	#include <stddef.h> // 添加两个头文件包含
+	#include <string.h>
+	#else
+[4] 由于串口未使用中断接收，而是使用了查询接收，所以修改了shell.c文件，如下
+	a. Line：316～317
+	//rt_device_set_rx_indicate(shell->device, finsh_rx_ind);
+	//rt_device_open(shell->device, (RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX));
+	rt_device_open(shell->device, (RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_STREAM));
+
+	b. Line：326，注释该行
+	// if (rt_sem_take(&shell->rx_sem, RT_WAITING_FOREVER) != RT_EOK) continue;
+
+	c. Line：553，添加CPU占用的释放
+
+	rt_thread_delay(1); // 或者rt-schedule();
+
+******************************
+工程管理
+******************************
+[1] 该工程使用Makefile管理，Makefile即文件AE210P/Makefile；
+      编译如下：
+	make APP=rtthread AE210P=1 USING_CLI=1 DEBUG=1 all
+	make APP=rtthread AE210P=1 USING_CLI=1 DEBUG=1 clean
+
+******************************
+Tool Chain/IDE
+******************************
+[1] IDE：AndeSight_V300_STD
+
+这是一个基于Eclipse和GNU、GDB的环境，参阅对应工具/环境的标准文档即可。
+
+关于创建工程和调试，请参阅《Andes工程创建和调试.docx》。
+
+******************************
+测试目标板（PCBA）
+******************************
+[1] AE210P EVB
+
+
@@ -0,0 +1,138 @@
+#include "nds32_intrinsic.h"
+#include "nds32.h"
+
+#ifndef VECTOR_BASE
+#define VECTOR_BASE	0x00000000
+#endif
+
+#define PSW_MSK                                         \
+        (PSW_mskGIE | PSW_mskINTL | PSW_mskPOM | PSW_mskIFCON | PSW_mskCPL)
+#define PSW_INIT                                        \
+        (0x0UL << PSW_offGIE                            \
+         | 0x0UL << PSW_offINTL                         \
+         | 0x1UL << PSW_offPOM                          \
+         | 0x0UL << PSW_offIFCON                        \
+         | 0x7UL << PSW_offCPL)
+
+#define IVB_MSK                                         \
+        (IVB_mskEVIC | IVB_mskESZ | IVB_mskIVBASE)
+#define IVB_INIT                                        \
+        ((VECTOR_BASE >> IVB_offIVBASE) << IVB_offIVBASE\
+         | 0x1UL << IVB_offESZ                          \
+         | 0x0UL << IVB_offEVIC)
+
+
+#pragma weak c_startup = c_startup_common
+
+void c_startup(void);
+
+/*
+ * Default c_startup() function which used for those relocation from LMA to VMA.
+ */
+static void c_startup_common(void)
+{
+#ifdef XIP_MODE
+	/* Data section initialization */
+#define MEMCPY(des, src, n)     __builtin_memcpy ((des), (src), (n))
+	extern char __rw_lma_start, __rw_lma_end, __rw_vma_start;
+	unsigned int size = &__rw_lma_end - &__rw_lma_start;
+
+	/* Copy data section from LMA to VMA */
+	MEMCPY(&__rw_vma_start, &__rw_lma_start, size);
+#else
+	/* We do nothing for those LMA equal to VMA */
+#endif
+}
+
+static void cpu_init(void)
+{
+	unsigned int reg;
+
+	/* Set PSW GIE/INTL to 0, superuser & CPL to 7 */
+	reg = (__nds32__mfsr(NDS32_SR_PSW) & ~PSW_MSK) | PSW_INIT;
+	__nds32__mtsr(reg, NDS32_SR_PSW);
+	__nds32__isb();
+
+	/* Set vector size: 16 byte, base: VECTOR_BASE, mode: IVIC */
+	reg = (__nds32__mfsr(NDS32_SR_IVB) & ~IVB_MSK) | IVB_INIT;
+	__nds32__mtsr(reg, NDS32_SR_IVB);
+
+	/*
+	* Check interrupt priority programmable (IVB.PROG_PRI_LVL)
+	* 0: Fixed priority, 1: Programmable priority
+	*/
+	if (reg & IVB_mskPROG_PRI_LVL)
+	{
+		/* Set PPL2FIX_EN to 0 to enable Programmable Priority Level */
+		__nds32__mtsr(0x0, NDS32_SR_INT_CTRL);
+	}
+
+	/* Mask and clear hardware interrupts */
+	if (reg & IVB_mskIVIC_VER)
+	{
+		/* IVB.IVIC_VER >= 1*/
+		__nds32__mtsr(0x0, NDS32_SR_INT_MASK2);
+		__nds32__mtsr(-1, NDS32_SR_INT_PEND2);
+	}
+	else
+	{
+		__nds32__mtsr(__nds32__mfsr(NDS32_SR_INT_MASK) & ~0xFFFF, NDS32_SR_INT_MASK);
+	}
+}
+
+/*
+ * Vectors initialization. This means to copy exception handler code to
+ * vector entry base address.
+ */
+static void vector_init(void)
+{
+	extern unsigned int OS_Int_Vectors, OS_Int_Vectors_End;
+
+	if ((unsigned int)&OS_Int_Vectors != VECTOR_BASE)
+	{
+		volatile unsigned int *vector_srcptr = &OS_Int_Vectors;
+		volatile unsigned int *vector_dstptr = (unsigned int *)VECTOR_BASE;
+
+		/* copy vector table to VECTOR_BASE */
+		while (vector_srcptr != &OS_Int_Vectors_End)
+			*vector_dstptr++ = *vector_srcptr++;
+	}
+}
+
+/*
+ * NDS32 reset handler to reset all devices sequentially and call application
+ * entry function.
+ */
+void reset(void)
+{
+	extern void hardware_init(void);
+	extern void bsp_init(void);
+	extern void rtthread_startup(void);
+
+	/*
+	 * Initialize CPU to a post-reset state, ensuring the ground doesn't
+	 * shift under us while we try to set things up.
+	*/
+	cpu_init();
+
+	/*
+	 * Initialize LMA/VMA sections.
+	 * Relocation for any sections that need to be copied from LMA to VMA.
+	 */
+	c_startup();
+
+	/* Copy vector table to vector base address */
+	vector_init();
+
+	/* Call platform specific hardware initialization */
+	hardware_init();
+
+	/* Setup the OS system required initialization */
+	bsp_init();
+
+	/* Application enrty function */
+	rtthread_startup();
+
+	/* Never go back here! */
+	while(1);
+}
@@ -0,0 +1,199 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	(100)
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_THREAD_DEBUG
+
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+//#define RT_PRINTF_LONGLONG
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+//#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
+#define RT_USING_SERIAL
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+//#define RT_KPRINTF
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE 260
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME "uart02"
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: MSH, a bash shell */
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+
+/* SECTION: MXCLI, modified base-on MSH */
+//#define FINSH_USING_MXCLI
+
+/* SECTION: device filesystem */
+//#define RT_USING_DFS
+//#define DFS_USING_WORKDIR
+//#define RT_USING_DFS_DEVFS
+
+//#define RT_USING_DFS_JFFS2
+/* Reentrancy (thread safe) of the FatFs module.  */
+#define RT_DFS_ELM_REENTRANT
+/* Number of volumes (logical drives) to be used. */
+#define RT_DFS_ELM_DRIVES			2
+/* #define RT_DFS_ELM_USE_LFN			1 */
+/* #define RT_DFS_ELM_CODE_PAGE			936 */
+#define RT_DFS_ELM_MAX_LFN			255
+/* Maximum sector size to be handled. */
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  512
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX			2
+/* the max number of opened files 		*/
+#define DFS_FD_MAX					4
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* #define RT_USING_LWIP */
+/* LwIP uses RT-Thread Memory Management */
+#define RT_LWIP_USING_RT_MEM
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+/* Enable DNS */
+#define RT_LWIP_DNS
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM	5
+
+/* Using DHCP */
+/* #define RT_LWIP_DHCP */
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0	192
+#define RT_LWIP_IPADDR1	168
+#define RT_LWIP_IPADDR2	1
+#define RT_LWIP_IPADDR3	30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		10
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		10
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+/* TCP sender buffer space */
+#define RT_LWIP_TCP_SND_BUF	8192
+/* TCP receive window. */
+#define RT_LWIP_TCP_WND		8192
+
+/* SECTION: RT-Thread/GUI */
+/* #define RT_USING_RTGUI */
+
+/* name length of RTGUI object */
+#define RTGUI_NAME_MAX		12
+/* support 16 weight font */
+#define RTGUI_USING_FONT16
+/* support Chinese font */
+#define RTGUI_USING_FONTHZ
+/* use DFS as file interface */
+#define RTGUI_USING_DFS_FILERW
+/* use font file as Chinese font */
+#define RTGUI_USING_HZ_FILE
+/* use Chinese bitmap font */
+#define RTGUI_USING_HZ_BMP
+/* use small size in RTGUI */
+#define RTGUI_USING_SMALL_SIZE
+/* use mouse cursor */
+/* #define RTGUI_USING_MOUSE_CURSOR */
+/* default font size in RTGUI */
+#define RTGUI_DEFAULT_FONT_SIZE	16
+
+/* image support */
+/* #define RTGUI_IMAGE_XPM */
+/* #define RTGUI_IMAGE_BMP */
+
+// <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" />
+// #define RT_USING_CMSIS_OS
+// <bool name="RT_USING_RTT_CMSIS" description="Using CMSIS in RTT" default="true" />
+#define RT_USING_RTT_CMSIS
+// <bool name="RT_USING_BSP_CMSIS" description="Using CMSIS in BSP" default="true" />
+// #define RT_USING_BSP_CMSIS
+
+#endif
@@ -0,0 +1,197 @@
+!********************************************************************************************************
+!
+!                               (c) Copyright 2005-2014, Andes Techonology
+!                                          All Rights Reserved
+!
+!                                           NDS32 Generic Port
+!                                            GNU C Compiler
+!
+!********************************************************************************************************
+!********************************************************************************************************
+! INCLUDE ASSEMBLY CONSTANTS
+!********************************************************************************************************
+
+#include <nds32_init.inc>
+#include "nds32_defs.h"
+#include "os_cpu_common.h"
+
+#ifndef VECTOR_NUMINTRS
+#define VECTOR_NUMINTRS		32
+#endif
+
+	.global OS_Init_Nds32
+	.global OS_Int_Vectors
+	.global OS_Int_Vectors_End
+
+	.macro WEAK_DEFAULT weak_sym, default_handler
+	.weak \weak_sym
+	.set \weak_sym ,\default_handler
+	.endm
+
+	! Define standard NDS32 vector table entry point of
+	! exception/interruption vectors
+	.macro VECTOR handler
+	WEAK_DEFAULT \handler, OS_Default_Exception
+	.align 4
+__\handler:
+#ifdef MPU_SUPPORT
+		la	$p0, \handler
+		jr5	$p0
+#else
+		pushm	$r0, $r5
+		la	$r0, \handler
+		jr5	$r0
+#endif
+	.endm
+
+	.macro INTERRUPT_VECTOR num
+	WEAK_DEFAULT OS_Trap_Interrupt_HW\num, OS_Default_Interrupt
+	.align 4
+__OS_Trap_Interrupt_HW\num:
+#ifdef MPU_SUPPORT
+		la	$p1, OS_Trap_Interrupt_HW\num
+		li	$p0, \num
+		jr5	$p1
+#else
+		pushm	$r0, $r5
+		la	$r1, OS_Trap_Interrupt_HW\num
+		li	$r0, \num
+		jr5	$r1
+#endif
+	.endm
+
+!********************************************************************************************************
+! 	Vector Entry Table
+!********************************************************************************************************
+	.section .nds32_init, "ax"
+
+OS_Int_Vectors:
+	b	    OS_Init_Nds32			    !  (0) Trap Reset/NMI
+	VECTOR	OS_Trap_TLB_Fill		    !  (1) Trap TLB fill
+	VECTOR	OS_Trap_PTE_Not_Present		!  (2) Trap PTE not present
+	VECTOR	OS_Trap_TLB_Misc		    !  (3) Trap TLB misc
+	VECTOR	OS_Trap_TLB_VLPT_Miss		!  (4) Trap TLB VLPT miss
+	VECTOR	OS_Trap_Machine_Error		!  (5) Trap Machine error
+	VECTOR	OS_Trap_Debug_Related		!  (6) Trap Debug related
+	VECTOR	OS_Trap_General_Exception	!  (7) Trap General exception
+	VECTOR	OS_Trap_Syscall			    !  (8) Syscall
+
+	! Interrupt vectors
+	.altmacro
+	.set	irqno, 0
+	.rept	VECTOR_NUMINTRS
+	INTERRUPT_VECTOR %irqno
+	.set	irqno, irqno+1
+	.endr
+
+	.align 4
+OS_Int_Vectors_End:
+
+!******************************************************************************************************
+! 	Start Entry
+!******************************************************************************************************
+	.section .text
+	.global _start
+OS_Init_Nds32:
+_start:
+	!************************** Begin of do-not-modify **************************
+	! Please don't modify this code
+	! Initialize the registers used by the compiler
+
+	nds32_init	! NDS32 startup initial macro in <nds32_init.inc>
+
+	!*************************** End of do-not-modify ***************************
+
+#ifdef CONFIG_HWZOL
+	! enable AEN
+	mfsr	$r0, $PSW
+	ori	$r0, $r0, (1 << PSW_offAEN)
+	mtsr	$r0, $PSW
+#endif
+
+#if (defined(CONFIG_CPU_ICACHE_ENABLE) || defined(CONFIG_CPU_DCACHE_ENABLE))
+	! disable cache
+	mfsr	$r0, $CACHE_CTL
+	li	$r1, ~(CACHE_CTL_mskIC_EN | CACHE_CTL_mskDC_EN)
+	and	$r0, $r0, $r1
+	mtsr	$r0, $CACHE_CTL
+#endif
+
+	! Do system low level setup. It must be a leaf function.
+	bal	_nds32_init_mem
+
+#if 1	/* Speed prefer */
+	! We do this on a word basis.
+	! Currently, the default linker script guarantee
+	! the __bss_start/_end boundary word-aligned.
+
+	! Clear bss
+	la	$r0, __bss_start
+	la	$r1, _end
+	sub	$r2, $r1, $r0		    ! $r2: Size of .bss
+	beqz	$r2, clear_end
+
+	andi	$r7, $r2, 0x1f		! $r7 = $r2 mod 32
+	movi	$r3, 0
+	movi	$r4, 0
+	movi	$r5, 0
+	movi	$r6, 0
+	movi	$r8, 0
+	movi	$r9, 0
+	movi	$r10, 0
+	beqz	$r7, clear_loop     ! if $r7 == 0, bss_size%32 == 0
+	sub	$r2, $r2, $r7
+
+first_clear:
+	swi.bi	$r3, [$r0], #4		! clear each word
+	addi	$r7, $r7, -4
+	bnez	$r7, first_clear
+	li	$r1, 0xffffffe0
+	and	$r2, $r2, $r1           ! check bss_size/32 == 0 or not
+	beqz	$r2, clear_end      ! if bss_size/32 == 0 , needless to clear
+
+clear_loop:
+	smw.bim	$r3, [$r0], $r10    !clear each 8 words
+	addi	$r2, $r2, -32
+	bgez	$r2, clear_loop
+
+clear_end:
+#else	/* Size prefer */
+	! Clear bss
+	la	$r0, _edata
+	la	$r1, _end
+	beq	$r0, $r1, 2f
+	li	$r2, #0
+1:
+	swi.bi	$r2, [$r0], #4
+	bne	$r0, $r1, 1b
+2:
+#endif
+	! Set-up the stack pointer
+	la	$sp, _stack
+
+	! System reset handler
+	bal	reset
+
+        ! Default exceptions / interrupts handler
+OS_Default_Exception:
+OS_Default_Interrupt:
+die:
+        b die
+
+!********************************************************************************************************
+!       Interrupt vector Table
+!********************************************************************************************************
+
+	.data
+	.align 2
+
+	! These tables contain the isr pointers used to deliver interrupts
+	.global	OS_CPU_Vector_Table
+OS_CPU_Vector_Table:
+	.rept   32
+	.long	OS_Default_Interrupt
+	.endr
+
+	.end
+
@@ -0,0 +1,113 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-31     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+#include "board.h"
+
+extern int  rt_application_init(void); // define in application/application.c
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+extern int _stack;
+#endif
+
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(char* file, int line)
+{
+    rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+    rt_kprintf("       file  %s\r\n", file);
+    rt_kprintf("       line  %d\r\n", line);
+
+    while (1) ;
+}
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* show version */
+    rt_show_version();
+
+#ifdef RT_USING_HEAP
+#if STM32_EXT_SRAM
+    rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END);
+#else
+#ifdef __CC_ARM
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)MXT_IRAM_END);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);
+#else
+    /* init memory system */
+    rt_system_heap_init((void *)0x00250000, (void *)0x00280000);
+#endif
+#endif  /* STM32_EXT_SRAM */
+#endif /* RT_USING_HEAP */
+
+#ifdef RT_USING_COMPONENTS_INIT
+	rt_components_board_init();
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize timer */
+    rt_system_timer_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+//int main(void)
+//{
+//    /* disable interrupt first */
+//    rt_hw_interrupt_disable();
+//
+//    /* startup RT-Thread RTOS */
+//    rtthread_startup();
+//
+//    return 0;
+//}
+
+/*@}*/
@@ -0,0 +1,188 @@
+#include "nds32.h"
+#include "os_cpu_common.h"
+#include "config.h"
+
+	.align 4
+! void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+! R0 --> from
+! R1 --> to
+    .section .text
+    .global rt_hw_context_switch_interrupt
+    .global rt_hw_context_switch
+rt_hw_context_switch_interrupt:
+rt_hw_context_switch:
+	push25 $r6,#8    ! {$r6, $fp, $gp, $lp}
+
+    la     $r2, rt_thread_switch_interrupt_flag
+    lw     $r3, [$r2]
+    movi   $r4, #1
+    beq    $r3, $r4, _reswitch
+    sw     $r4, [$r2]                           ! set rt_thread_switch_interrupt_flag to 1
+
+    la     $r2, rt_interrupt_from_thread
+    sw     $r0, [$r2]                           ! set rt_interrupt_from_thread
+_reswitch:
+	la     $r2, rt_interrupt_to_thread
+    sw     $r1, [$r2]                           ! set rt_interrupt_to_thread
+    bal    hal_intc_swi_trigger                 ! trigger the swi exception (causes context switch)
+
+	pop25  $r6,#8    ! {$r6, $fp, $gp, $lp}
+
+! R0 --> switch from thread stack
+! R1 --> switch to thread stack
+! psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
+
+	.align 4
+	.global OS_Trap_Interrupt_SWI
+OS_Trap_Interrupt_SWI:
+!	pushm $r0, $r5
+    setgie.d                                     ! disable interrupt to protect context switch
+	dsb
+
+    IntlDescend                                  ! Descend interrupt level
+
+	movi	$r0, 0x0
+	mtsr	$r0, $INT_PEND                       ! clean SWI pending
+
+	la      $r0, rt_thread_switch_interrupt_flag ! get rt_thread_switch_interrupt_flag
+	lw      $r1, [$r0]
+	beqz    $r1, pendsv_exit                     ! swi has already been handled
+
+	movi    $r1, #0
+	sw      $r1, [$r0]                           ! clear rt_thread_switch_interrupt_flag to 0
+
+	la      $r0, rt_interrupt_from_thread
+	lw      $r1, [$r0]
+	beqz    $r1, switch_to_thread                ! skip register save at the first time(os startup phase)
+
+	SAVE_ALL
+
+	move    $r1, $sp
+	la      $r0, rt_interrupt_from_thread
+	lw      $r0, [$r0]
+	sw      $r1, [$r0]
+
+switch_to_thread:
+    la     $r1, rt_interrupt_to_thread
+    lw     $r1, [$r1]
+    lw     $r1, [$r1]                            ! load thread stack pointer
+	move   $sp, $r1                              ! update stack pointer
+	RESTORE_ALL                                  ! pop registers
+
+pendsv_exit:
+	setgie.e
+	iret
+
+	.align 4
+! void rt_hw_context_switch_to(rt_uint32 to);
+! R0 --> to
+    .global rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    la     $r1, rt_interrupt_to_thread
+    sw     $r0, [$r1]
+
+    ! set from thread to 0
+    la     $r1, rt_interrupt_from_thread
+    movi   $r0, #0
+    sw     $r0, [$r1]
+
+    ! set interrupt flag to 1
+    la     $r1, rt_thread_switch_interrupt_flag
+    movi   $r0, #1
+    sw     $r0, [$r1]
+
+    ! set the SWI exception priority(must be the lowest level)
+	! todo
+
+    ! trigger the SWI exception (causes context switch)
+    jal    hal_intc_swi_trigger
+
+    setgie.e            ! enable interrupts at processor level
+
+1:
+	b   1b              ! never reach here
+
+#ifndef VECTOR_NUMINTRS
+#define VECTOR_NUMINTRS		32
+#endif
+
+	.global OS_Trap_Int_Common
+
+	! Set up Interrupt vector ISR
+	! HW#IRQ_SWI_VECTOR : OS_Trap_Interrupt_SWI (SWI)
+	! HW#n : OS_Trap_Int_Common
+
+	.macro	SET_HWISR num
+	.global OS_Trap_Interrupt_HW\num
+	.if	\num == IRQ_SWI_VECTOR
+	.set	OS_Trap_Interrupt_HW\num, OS_Trap_Interrupt_SWI
+	.else
+	.set	OS_Trap_Interrupt_HW\num, OS_Trap_Int_Common
+	.endif
+	.endm
+
+	.altmacro
+	.set	irqno, 0
+	.rept	VECTOR_NUMINTRS
+	SET_HWISR %irqno
+	.set	irqno, irqno+1
+	.endr
+	.noaltmacro
+
+!	.global OS_Trap_Int_Common
+OS_Trap_Int_Common:
+#ifdef MPU_SUPPORT
+	mfsr	$p1, $PSW
+	ori	$p1, $p1, (PSW_mskIT | PSW_mskDT)
+	mtsr	$p1, $PSW                       ! enable IT/DT
+	dsb
+	pushm	$r0, $r5
+	move	$r0, $p0                        ! IRQ number
+#endif
+	! $r0 : HW Interrupt vector number
+	SAVE_CALLER
+
+	IntlDescend                             ! Descend interrupt level
+
+	mfsr	$r1, $IPSW                      ! Use IPSW.CPL to check come from thread or ISR
+	srli45	$r1, #PSW_offCPL
+	fexti33	$r1, #0x2                       ! IPSW.CPL
+	bnec	$r1, #0x7, 2f                   ! IPSW.CPL != 7, come form ISR, reentrant
+
+	move	$fp, $sp                        ! save old stack pointer
+	la	    $sp, __OS_Int_Stack             ! switch to interrupt stack
+2:
+	setgie.e                                ! allow nested now
+
+	! The entire CPU state is now stashed on the stack,
+	! and the stack is also 8-byte alignment.
+	! We can call C program based interrupt handler now.
+	la	    $r1, OS_CPU_Vector_Table
+	lw	    $r1, [$r1+($r0<<2)]             ! ISR function pointer
+	jral	$r1                             ! Call ISR
+
+	la	    $r1, __OS_Int_Stack             ! Check for nested interruption return
+	bne	    $r1, $sp, 3f                    ! $sp != __OS_Int_Stack?
+
+	move	$sp, $fp                        ! Move back to the thread stack
+3:
+	RESTORE_CALLER
+
+	iret
+
+!	.set	OS_Trap_Interrupt_HW9, OS_Trap_Interrupt_SWI
+!	.set	OS_Trap_Interrupt_HW19, OS_Trap_Int_Common
+
+!*********************************************
+! POINTERS TO VARIABLES
+!*********************************************
+#ifdef MPU_SUPPORT
+	.section privileged_data
+#else
+	.section .bss
+#endif
+	.skip IRQ_STACK_SIZE
+	.align 3
+__OS_Int_Stack:
+
+	.end
				`@@ -0,0 +1 @@`
				`lib-${CONFIG_FTSSP010} := sspd_ac97.o sspd_rts.o`