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[imxrt1060] Update 1060 sdk 2.12.1 (#6892)

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更新的SDK2.12.1更新imxrt1060的驱动
This commit is contained in:
xiao xie authored and GitHub committed 2023-02-06 22:17:31 -05:00
1 parent 53dcac6f68
commit e94a3bf52c
139 files changed
+36373 -13386
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bsp/imxrt/imxrt1060-nxp-evk/.config
+61 -11
View File
@@ -73,6 +73,7 @@ CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50000
CONFIG_RT_USING_CACHE=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
@@ -105,7 +106,39 @@ CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
# CONFIG_RT_USING_DFS is not set
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
@@ -127,7 +160,7 @@ CONFIG_RT_USING_I2C=y
# CONFIG_RT_I2C_DEBUG is not set
CONFIG_RT_USING_I2C_BITOPS=y
# CONFIG_RT_I2C_BITOPS_DEBUG is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PHY=y
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
@@ -157,9 +190,13 @@ CONFIG_RT_USING_PIN=y
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
CONFIG_RT_USING_USB=y
CONFIG_RT_USING_USB_HOST=y
CONFIG_RT_USBH_MSTORAGE=y
CONFIG_UDISK_MOUNTPOINT="/"
# CONFIG_RT_USBH_HID is not set
# CONFIG_RT_USING_USB_DEVICE is not set
CONFIG_RT_USBD_THREAD_STACK_SZ=4096
#
# C/C++ and POSIX layer
@@ -192,7 +229,15 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
@@ -297,6 +342,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -1013,19 +1059,23 @@ CONFIG_SOC_MIMXRT1062DVL6A=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDRAM is not set
CONFIG_BSP_USING_SDRAM=y
# CONFIG_BSP_USING_ETH is not set
# CONFIG_BSP_USING_LCD is not set
# CONFIG_BSP_USING_TOUCHPAD is not set
# CONFIG_BSP_USING_LVGL is not set
# CONFIG_BSP_USING_FS is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_I2C=y
CONFIG_BSP_USING_I2C1=y
CONFIG_HW_I2C1_BADURATE_100kHZ=y
# CONFIG_HW_I2C1_BADURATE_400kHZ is not set
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USING_SDIO is not set
CONFIG_BSP_USING_USB=y
CONFIG_BSP_USB0_HOST=y
# CONFIG_BSP_USB1_HOST is not set
# CONFIG_BSP_USING_I2C is not set
CONFIG_BSP_USING_LPUART=y
CONFIG_BSP_USING_LPUART1=y
# CONFIG_BSP_USING_LPUART2 is not set
@@ -1035,7 +1085,7 @@ CONFIG_BSP_USING_LPUART1=y
# CONFIG_BSP_USING_LPUART6 is not set
# CONFIG_BSP_USING_LPUART7 is not set
# CONFIG_BSP_USING_LPUART8 is not set
CONFIG_BSP_USING_PXP=y
# CONFIG_BSP_USING_PXP is not set
CONFIG_BSP_USING_CACHE=y
#
bsp/imxrt/imxrt1060-nxp-evk/applications/main.c
+1 -1
View File
@@ -14,7 +14,7 @@
#include "core_cm7.h"
/* defined the LED pin: GPIO1_IO9 */
#define LED0_PIN GET_PIN(1, 8)
#define LED0_PIN GET_PIN(1, 9)
int main(void)
{
bsp/imxrt/imxrt1060-nxp-evk/applications/mnt.c
+61
View File
@@ -0,0 +1,61 @@
/*
* Copyright (c) 2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-09-19 Gavin first version
*
*/
#include <rtthread.h>
#ifdef RT_USING_DFS_RAMFS
#include <dfs_fs.h>
extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
int mnt_init(void)
{
rt_uint8_t *pool = RT_NULL;
rt_size_t size = 8*1024*1024;
pool = rt_malloc(size);
if (pool == RT_NULL)
return 0;
if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
rt_kprintf("RAM file system initializated!\n");
else
rt_kprintf("RAM file system initializate failed!\n");
return 0;
}
INIT_ENV_EXPORT(mnt_init);
#endif
#ifdef BSP_USING_SDCARD_FATFS
#include <dfs_fs.h>
#include <dfs_file.h>
#define DBG_TAG "app.filesystem"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
static int filesystem_mount(void)
{
while(rt_device_find("sd0") == RT_NULL)
{
rt_thread_mdelay(1);
}
int ret = dfs_mount("sd0", "/", "elm", 0, 0);
if (ret != 0)
{
rt_kprintf("ret: %d\n",ret);
LOG_E("sd0 mount to '/' failed!");
return ret;
}
return RT_EOK;
}
INIT_ENV_EXPORT(filesystem_mount);
#endif
bsp/imxrt/imxrt1060-nxp-evk/board/Kconfig
+86
View File
@@ -23,6 +23,44 @@ menu "Onboard Peripheral Drivers"
bool "Enable SDRAM"
default n
menuconfig BSP_USING_ETH
bool "Enable Ethernet"
select RT_USING_NETDEV
select RT_USING_LWIP
default n
if BSP_USING_ETH
config BSP_USING_PHY
select RT_USING_PHY
bool "Enable ethernet phy"
default y
if BSP_USING_PHY
config PHY_USING_KSZ8081
bool "i.MX RT1060EVK uses ksz8081 phy"
default y
if PHY_USING_KSZ8081
config PHY_KSZ8081_ADDRESS
int "Specify address of phy device"
default 2
config PHY_RESET_KSZ8081_PORT
int "indicate port of reset"
default 1
config PHY_RESET_KSZ8081_PIN
int "indicate pin of reset"
default 9
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
bool "Enable the PHY ksz8081 RMII50M mode"
depends on PHY_USING_KSZ8081
default y
endif
endif
endif
menuconfig BSP_USING_LCD
bool "Enable LCD"
default n
@@ -108,6 +146,20 @@ menu "Onboard Peripheral Drivers"
select PKG_USING_GUI_GUIDER_DEMO
default n
endif
menuconfig BSP_USING_FS
bool "Enable File System"
select RT_USING_DFS_DEVFS
select RT_USING_DFS
default n
if BSP_USING_FS
config BSP_USING_SDCARD_FATFS
bool "Enable SDCARD (FATFS)"
select BSP_USING_SDIO
select RT_USING_DFS_ELMFAT
default n
endif
endmenu
menu "On-chip Peripheral Drivers"
@@ -117,6 +169,40 @@ menu "On-chip Peripheral Drivers"
select RT_USING_PIN
default y
config BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
if BSP_USING_SDIO
config CODE_STORED_ON_SDCARD
bool "Enable Code STORED On SDCARD"
default n
help
"SD CARD work as boot devive"
endif
config BSP_USING_USB
bool "Enable USB"
select RT_USING_USB_HOST
default n
if BSP_USING_USB
config BSP_USB0_HOST
bool "Enable USB0"
default n
config BSP_USB1_HOST
bool "Enable USB1"
default n
endif
menuconfig BSP_USING_I2C
bool "Enable I2C"
select RT_USING_I2C
bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/MCUX_Config.mex
+21 -18
View File
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding= "UTF-8" ?>
<configuration name="MIMXRT1062xxxxA" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8 http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8.xsd" uuid="22c3ac06-9f09-4f14-9c74-93bdfd15fb8a" version="1.8" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<configuration name="MIMXRT1062xxxxA" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_12 http://mcuxpresso.nxp.com/XSD/mex_configuration_12.xsd" uuid="22c3ac06-9f09-4f14-9c74-93bdfd15fb8a" version="12" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_12" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<common>
<processor>MIMXRT1062xxxxA</processor>
<package>MIMXRT1062DVL6A</package>
@@ -14,11 +14,16 @@
<validate_boot_init_only>true</validate_boot_init_only>
<generate_extended_information>false</generate_extended_information>
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
<update_include_paths>true</update_include_paths>
<generate_registers_defines>false</generate_registers_defines>
</preferences>
<tools>
<pins name="Pins" version="8.0" enabled="true" update_project_code="true">
<pins name="Pins" version="12.0" enabled="true" update_project_code="true">
<pins_profile>
<processor_version>0.8.11</processor_version>
<processor_version>12.0.1</processor_version>
<pin_labels>
<pin_label pin_num="F13" pin_signal="GPIO_AD_B0_08" label="GPIO1_08" identifier="gpio1_08"/>
</pin_labels>
<power_domains/>
</pins_profile>
<functions_list>
@@ -35,11 +40,6 @@
<data>true</data>
</feature>
</dependency>
<dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
<feature name="initialized" evaluation="equal">
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
@@ -50,6 +50,11 @@
<data>true</data>
</feature>
</dependency>
<dependency resourceType="SWComponent" resourceId="platform.drivers.igpio" description="Pins initialization requires the IGPIO Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
<feature name="enabled" evaluation="equal" configuration="core0">
<data>true</data>
</feature>
</dependency>
</dependencies>
<pins>
<pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
@@ -78,21 +83,23 @@
<pin_feature name="slew_rate" value="Slow"/>
</pin_features>
</pin>
<pin peripheral="ARM" signal="arm_trace_swo" pin_num="G13" pin_signal="GPIO_AD_B0_10">
<pin peripheral="GPIO1" signal="gpio_io, 08" pin_num="F13" pin_signal="GPIO_AD_B0_08">
<pin_features>
<pin_feature name="slew_rate" value="Fast"/>
<pin_feature name="direction" value="OUTPUT"/>
</pin_features>
</pin>
<pin peripheral="GPIO1" signal="gpio_io, 09" pin_num="F14" pin_signal="GPIO_AD_B0_09"/>
<pin peripheral="GPIO1" signal="gpio_io, 10" pin_num="G13" pin_signal="GPIO_AD_B0_10"/>
</pins>
</function>
</functions_list>
</pins>
<clocks name="Clocks" version="7.0" enabled="true" update_project_code="true">
<clocks name="Clocks" version="10.0" enabled="true" update_project_code="true">
<clocks_profile>
<processor_version>0.8.11</processor_version>
<processor_version>12.0.1</processor_version>
</clocks_profile>
<clock_configurations>
<clock_configuration name="BOARD_BootClockRUN">
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
<description></description>
<options/>
<dependencies>
@@ -157,9 +164,7 @@
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
<clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
<clock_output id="ENET1_TX_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
<clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
<clock_output id="ENET2_TX_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
<clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
@@ -240,7 +245,7 @@
</clocks>
<dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
<dcdx_profile>
<processor_version>0.8.11</processor_version>
<processor_version>12.0.1</processor_version>
<output_format>c_array</output_format>
</dcdx_profile>
<dcdx_configurations>
@@ -392,8 +397,6 @@
<tee_profile>
<processor_version>N/A</processor_version>
</tee_profile>
<global_options/>
<user_memory_regions/>
</tee>
</tools>
</configuration>
bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.c
+17 -14
View File
@@ -1,3 +1,10 @@
/*
* Copyright 2018-2020 ,2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
@@ -15,11 +22,11 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v7.0
product: Clocks v8.0
processor: MIMXRT1062xxxxA
package_id: MIMXRT1062DVL6A
mcu_data: ksdk2_0
processor_version: 8.0.3
processor_version: 10.0.0
board: MIMXRT1060-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
@@ -58,9 +65,7 @@ outputs:
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
@@ -100,6 +105,8 @@ settings:
- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.LCDIF_PODF.scale, value: '4', locked: true}
- {id: CCM.LCDIF_PRED.scale, value: '2', locked: true}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
@@ -128,8 +135,8 @@ settings:
- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
- {id: CCM_ANALOG.PLL5.num, value: '0'}
- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2', locked: true}
- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4', locked: true}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
@@ -491,14 +498,10 @@ void BOARD_BootClockRUN(void)
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET1 Tx clock source. */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
/* Set ENET2 Tx clock source. */
#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
#else
IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
#endif
/* Set ENET Ref clock source. */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
/* Set ENET2 Ref clock source. */
IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK;
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/clock_config.h
+11 -2
View File
@@ -1,3 +1,10 @@
/*
* Copyright 2018-2020 ,2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
@@ -44,11 +51,13 @@ void BOARD_InitBootClocks(void);
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.c
+269 -269
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/imxrt1060-nxp-evk/board/MCUX_Config/dcd.h
+1 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2021 NXP
* Copyright 2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/imxrt1060-nxp-evk/board/SConscript
+6 -1
View File
@@ -17,7 +17,12 @@ if GetDepend(['BSP_USING_TOUCHPAD']):
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', 'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'DATA_SECTION_IS_CACHEABLE=1']
# CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1',
# 'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1','DATA_SECTION_IS_CACHEABLE=1']
CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1',
'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1','DATA_SECTION_IS_CACHEABLE=0', 'XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1']
if rtconfig.PLATFORM in ['armcc', 'armclang']:
CPPDEFINES.append('__FPU_PRESENT=1')
bsp/imxrt/imxrt1060-nxp-evk/board/board.c
+221 -78
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bsp/imxrt/imxrt1060-nxp-evk/board/board.h
+1 -1
View File
@@ -41,7 +41,7 @@ extern int heap_end;
/*! @brief The board flash size */
#define BOARD_FLASH_SIZE (0x400000U)
#define BOARD_FLASH_SIZE (0x800000U)
void rt_hw_board_init(void);
bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.icf
+47 -31
View File
@@ -1,20 +1,22 @@
/*
** ###################################################################
** Processors: MIMXRT1052CVJ5B
** MIMXRT1052CVL5B
** MIMXRT1052DVJ6B
** MIMXRT1052DVL6B
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1050RM Rev.1, 03/2018
** Version: rev. 1.0, 2018-09-21
** Build: b180921
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -25,45 +27,57 @@
** ###################################################################
*/
define symbol m_interrupts_start = 0x70002000;
define symbol m_interrupts_end = 0x700023FF;
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
define symbol m_text_start = 0x70002400;
define symbol m_text_end = 0x73FFFFFF;
define symbol m_interrupts_start = 0x60002000;
define symbol m_interrupts_end = 0x600023FF;
define symbol m_data_start = 0x20000000;
define symbol m_text_start = 0x60002400;
define symbol m_text_end = 0x607FFFFF;
define symbol m_interrupts_ram_start = 0x20000000;
define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_data_end = 0x2001FFFF;
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x2023FFFF;
define symbol m_data2_end = 0x202BFFFF;
define exported symbol m_boot_hdr_conf_start = 0x70000000;
define symbol m_boot_hdr_ivt_start = 0x70001000;
define symbol m_boot_hdr_boot_data_start = 0x70001020;
define symbol m_boot_hdr_dcd_data_start = 0x70001030;
define symbol m_qacode_start = 0x00000000;
define symbol m_qacode_end = 0x0001FFFF;
define exported symbol m_boot_hdr_conf_start = 0x60000000;
define symbol m_boot_hdr_ivt_start = 0x60001000;
define symbol m_boot_hdr_boot_data_start = 0x60001020;
define symbol m_boot_hdr_dcd_data_start = 0x60001030;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
define symbol __size_cstack__ = 0x2000;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
define symbol __size_heap__ = 0x2000;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define exported symbol __NCACHE_REGION_START = m_data2_start;
define exported symbol __NCACHE_REGION_SIZE = 0x0;
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
define exported symbol __RTT_HEAP_END = m_data2_end;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
@@ -73,16 +87,17 @@ define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
define block QACCESS_CODE { section CodeQuickAccess };
define block QACCESS_DATA { section DataQuickAccess };
initialize by copy { readwrite, section .textrw };
initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess};
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
place at address mem: m_boot_hdr_conf_start { section .boot_hdr.conf };
place at address mem: m_boot_hdr_ivt_start { section .boot_hdr.ivt };
place at address mem: m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
place at address mem: m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
@@ -92,4 +107,5 @@ place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in DATA_region { block NCACHE_VAR };
place in CSTACK_region { block CSTACK };
place in QACODE_region { block QACCESS_CODE };
place in DATA_region { block QACCESS_DATA };
bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.lds
+70 -65
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bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link.sct
+2 -2
View File
@@ -60,13 +60,13 @@
#if (defined(__stack_size__))
#define Stack_Size __stack_size__
#else
#define Stack_Size 0x0400
#define Stack_Size 0x2000
#endif
#if (defined(__heap_size__))
#define Heap_Size __heap_size__
#else
#define Heap_Size 0x0400
#define Heap_Size 0x2000
#endif
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_ram.icf
+91
View File
@@ -0,0 +1,91 @@
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000003FF;
define symbol m_text_start = 0x00000400;
define symbol m_text_end = 0x0001FFFF;
define symbol m_data_start = 0x20000000;
define symbol m_data_end = 0x2001FFFF;
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x202BFFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x2000;
}
define exported symbol __NCACHE_REGION_START = m_data2_start;
define exported symbol __NCACHE_REGION_SIZE = 0x0;
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define exported symbol __RTT_HEAP_END = m_data2_end;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
define block QACCESS_CODE { section CodeQuickAccess };
define block QACCESS_DATA { section DataQuickAccess };
initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in DATA_region { block NCACHE_VAR };
place in TEXT_region { block QACCESS_CODE };
place in DATA_region { block QACCESS_DATA };
place in CSTACK_region { block CSTACK };
bsp/imxrt/imxrt1060-nxp-evk/board/linker_scripts/link_sdram_txt.icf
+106
View File
@@ -0,0 +1,106 @@
/*
** ###################################################################
** Processors: MIMXRT1062CVJ5A
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
define symbol m_interrupts_start = 0x80000000;
define symbol m_interrupts_end = 0x800003FF;
define symbol m_text_start = 0x80000400;
define symbol m_text_end = 0x801FFFFF;
define symbol m_data_start = 0x20000000;
define symbol m_data_end = 0x2001FFFF;
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x202BFFFF;
define symbol m_data3_start = 0x80200000;
define symbol m_data3_end = 0x81DFFFFF;
define symbol m_ncache_start = 0x81E00000;
define symbol m_ncache_end = 0x81FFFFFF;
define symbol m_qacode_start = 0x00000000;
define symbol m_qacode_end = 0x0001FFFF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __NCACHE_REGION_START = m_ncache_start;
define exported symbol __NCACHE_REGION_SIZE = m_ncache_end - m_ncache_start + 1;
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
define exported symbol __RTT_HEAP_END = m_data2_end-__size_cstack__;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
define region DATA_region = mem:[from m_data_start to m_data_end];
define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__];
define region DATA3_region = mem:[from m_data3_start to m_data3_end];
define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end];
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { first readwrite, section m_usb_dma_init_data };
define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
define block QACCESS_CODE { section CodeQuickAccess };
define block QACCESS_DATA { section DataQuickAccess };
initialize by copy { readwrite, section .textrw, section CodeQuickAccess, section DataQuickAccess };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly };
place in DATA2_region { block RW };
place in DATA2_region { block ZI };
if (isdefinedsymbol(__heap_noncacheable__)) {
place in NCACHE_region { last block HEAP };
} else {
place in DATA2_region { last block HEAP };
}
place in NCACHE_region { block NCACHE_VAR };
place in QACODE_region { block QACCESS_CODE };
place in DATA_region { block QACCESS_DATA };
place in CSTACK_region { block CSTACK };
bsp/imxrt/imxrt1060-nxp-evk/evkmimxrt1060_sdram_init.mac
+258
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bsp/imxrt/imxrt1060-nxp-evk/project.ewd
+1546
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bsp/imxrt/imxrt1060-nxp-evk/project.ewp
+1613
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bsp/imxrt/imxrt1060-nxp-evk/project.eww
+10
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@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\project.ewp</path>
</project>
<batchBuild/>
</workspace>
bsp/imxrt/imxrt1060-nxp-evk/rtconfig.h
+43 -7
View File
@@ -45,6 +45,7 @@
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x50000
#define RT_USING_CACHE
#define RT_USING_CPU_FFS
#define ARCH_ARM
@@ -52,6 +53,7 @@
#define ARCH_ARM_CORTEX_FPU
#define ARCH_ARM_CORTEX_M7
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
@@ -71,6 +73,28 @@
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
/* Device Drivers */
@@ -81,10 +105,16 @@
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_PHY
#define RT_USING_PIN
/* Using USB */
#define RT_USING_USB
#define RT_USING_USB_HOST
#define RT_USBH_MSTORAGE
#define UDISK_MOUNTPOINT "/"
#define RT_USBD_THREAD_STACK_SZ 4096
/* C/C++ and POSIX layer */
@@ -101,6 +131,13 @@
/* Network */
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
/* Utilities */
@@ -215,7 +252,6 @@
/* Device Control */
/* Other */
/* Signal IO */
@@ -226,13 +262,14 @@
/* Privated Packages of RealThread */
/* Network Utilities */
/* Other */
/* RT-Thread Smart */
/* Signal IO */
#define SOC_IMXRT1060_SERIES
/* Hardware Drivers Config */
#define BSP_USING_4MFLASH
@@ -240,16 +277,15 @@
/* Onboard Peripheral Drivers */
#define BSP_USING_SDRAM
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_I2C
#define BSP_USING_I2C1
#define HW_I2C1_BADURATE_100kHZ
#define BSP_USING_USB
#define BSP_USB0_HOST
#define BSP_USING_LPUART
#define BSP_USING_LPUART1
#define BSP_USING_PXP
#define BSP_USING_CACHE
/* Board extended module Drivers */
bsp/imxrt/imxrt1060-nxp-evk/template.ewd
+1546
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bsp/imxrt/imxrt1060-nxp-evk/template.ewp
+1074
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bsp/imxrt/imxrt1060-nxp-evk/template.ewt
+1426
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bsp/imxrt/imxrt1060-nxp-evk/template.eww
+10
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@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>
bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.c
-48
View File
@@ -1,48 +0,0 @@
/*
* Copyright 2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkbmimxrt1060_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */
bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.c
+70
View File
@@ -0,0 +1,70 @@
/*
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "evkmimxrt1060_flexspi_nor_config.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
/*******************************************************************************
* Code
******************************************************************************/
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.conf"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.conf"
#endif
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
.controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable),
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_120MHz,
.sflashA1Size = 8u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
// Read Status LUTs
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
// Write Enable LUTs
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
// Erase Sector LUTs
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Erase Block LUTs
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Pape Program LUTs
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
// Erase Chip LUTs
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = 1u,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
#endif /* XIP_BOOT_HEADER_ENABLE */
bsp/imxrt/imxrt1060-nxp-evk/xip/evkbmimxrt1060_flexspi_nor_config.h → bsp/imxrt/imxrt1060-nxp-evk/xip/evkmimxrt1060_flexspi_nor_config.h
+4 -4
View File
@@ -1,12 +1,12 @@
/*
* Copyright 2021 NXP
* Copyright 2018-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__
#define __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__
#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
#include <stdint.h>
#include <stdbool.h>
@@ -265,4 +265,4 @@ extern "C" {
#ifdef __cplusplus
}
#endif
#endif /* __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
bsp/imxrt/imxrt1060-nxp-evk/xip/fsl_flexspi_nor_boot.h
+13 -6
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -9,13 +9,15 @@
#define __FLEXSPI_NOR_BOOT_H__
#include <stdint.h>
#include "board.h"
#include "fsl_common.h"
#ifndef BOARD_FLASH_SIZE
#include "board.h"
#endif
/*! @name Driver version */
/*@{*/
/*! @brief XIP_DEVICE driver version 2.0.2. */
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*! @brief XIP_DEVICE driver version 2.0.3. */
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
/*************************************
@@ -75,8 +77,8 @@ extern uint32_t __Vectors[];
extern uint32_t __VECTOR_TABLE[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
#elif defined(__GNUC__)
extern uint32_t __isr_vector[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__isr_vector)
extern uint32_t __VECTOR_TABLE[];
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
#endif
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
@@ -100,7 +102,12 @@ typedef struct _boot_data_
uint32_t placeholder; /* placehoder to make even 0x10 size */
} BOOT_DATA_T;
#ifdef FlexSPI1_AMBA_BASE
#define FLASH_BASE FlexSPI1_AMBA_BASE
#else
#define FLASH_BASE FlexSPI_AMBA_BASE
#endif
#if defined(BOARD_FLASH_SIZE)
#define FLASH_SIZE BOARD_FLASH_SIZE
#else
bsp/imxrt/imxrt1170-nxp-evk/m7/.config
+12 -2
View File
@@ -84,8 +84,10 @@ CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x50000
# CONFIG_RT_USING_CACHE is not set
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
@@ -160,9 +162,12 @@ CONFIG_RT_USING_PIN=y
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
CONFIG_RT_USING_USB=y
CONFIG_RT_USING_USB_HOST=y
# CONFIG_RT_USBH_MSTORAGE is not set
# CONFIG_RT_USBH_HID is not set
# CONFIG_RT_USING_USB_DEVICE is not set
CONFIG_RT_USBD_THREAD_STACK_SZ=4096
#
# C/C++ and POSIX layer
@@ -308,6 +313,7 @@ CONFIG_NETDEV_IPV6=0
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -955,6 +961,7 @@ CONFIG_NETDEV_IPV6=0
# Uncategorized
#
#
# Privated Packages of RealThread
#
@@ -1012,6 +1019,7 @@ CONFIG_NETDEV_IPV6=0
# CONFIG_PKG_USING_UKERNEL is not set
# CONFIG_PKG_USING_TRACE_AGENT is not set
#
# Hardware Drivers Config
#
@@ -1024,7 +1032,9 @@ CONFIG_SOC_MIMXRT1176DVMAA=y
# CONFIG_BSP_USING_DMA is not set
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_RTC is not set
# CONFIG_BSP_USB1_HOST is not set
# CONFIG_BSP_USING_USB is not set
# CONFIG_BSP_USING_SDIO is not set
CONFIG_BSP_USING_LPUART=y
CONFIG_BSP_USING_LPUART1=y
bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewd
+7 -7
View File
@@ -76,7 +76,7 @@
</option>
<option>
<name>OCDownloadVerifyAll</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>OCProductVersion</name>
@@ -84,15 +84,15 @@
</option>
<option>
<name>OCDynDriverList</name>
<state>CMSISDAP_ID</state>
<state>JLINK_ID</state>
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>9.20.4.46976</state>
<state>9.30.1.50052</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>CLowLevel</name>
@@ -112,7 +112,7 @@
</option>
<option>
<name>FlashLoadersV3</name>
<state>$TOOLKIT_DIR$\config\flashloader\NXP\FlashIMXRT1170_FlexSPI.board</state>
<state>$TOOLKIT_DIR$/config/flashloader/NXP/FlashIMXRT1170_FlexSPI.board</state>
</option>
<option>
<name>OCImagesSuppressCheck1</name>
@@ -429,7 +429,7 @@
</option>
<option>
<name>OCProbeConfig</name>
<state>$TOOLKIT_DIR$\config\debugger\NXP\IMXRT1170.ProbeConfig</state>
<state>$TOOLKIT_DIR$/config/debugger/NXP/IMXRT1170.ProbeConfig</state>
</option>
<option>
<name>CMSISDAPProbeConfigRadio</name>
@@ -1417,7 +1417,7 @@
</option>
<option>
<name>CCXds100ResetList</name>
<version>1</version>
<version>0</version>
<state>0</state>
</option>
<option>
bsp/imxrt/imxrt1170-nxp-evk/m7/project.ewp
+229 -146
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/imxrt1170-nxp-evk/m7/rtconfig.h
+6 -10
View File
@@ -80,6 +80,9 @@
/* Using USB */
#define RT_USING_USB
#define RT_USING_USB_HOST
#define RT_USBD_THREAD_STACK_SZ 4096
/* C/C++ and POSIX layer */
@@ -217,23 +220,14 @@
/* Device Control */
/* Privated Packages of RealThread */
/* Other */
/* Signal IO */
/* Uncategorized */
/* Privated Packages of RealThread */
/* Network Utilities */
/* RT-Thread Smart */
/* Hardware Drivers Config */
#define BSP_USING_QSPIFLASH
@@ -242,6 +236,8 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_USB
#define BSP_USB0_HOST
#define BSP_USING_LPUART
#define BSP_USING_LPUART1
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.h
+1244 -335
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062.xml
+18249 -9658
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/MIMXRT1062_features.h
+18 -4
View File
@@ -1,13 +1,13 @@
/*
** ###################################################################
** Version: rev. 1.0, 2018-11-16
** Build: b211108
** Version: rev. 2.0, 2022-03-25
** Build: b220426
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -20,6 +20,8 @@
** Initial version.
** - rev. 1.0 (2018-11-16)
** Update feature files to align with IMXRT1060RM Rev.0.
** - rev. 2.0 (2022-03-25)
** Add RT1060X device
**
** ###################################################################
*/
@@ -72,7 +74,7 @@
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (3)
/* @brief IGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_IGPIO_COUNT (9)
#define FSL_FEATURE_SOC_IGPIO_COUNT (10)
/* @brief IOMUXC availability on the SoC. */
#define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
/* @brief IOMUXC_GPR availability on the SoC. */
@@ -89,6 +91,8 @@
#define FSL_FEATURE_SOC_LPSPI_COUNT (4)
/* @brief LPUART availability on the SoC. */
#define FSL_FEATURE_SOC_LPUART_COUNT (8)
/* @brief MPU availability on the SoC. */
#define FSL_FEATURE_SOC_MPU_COUNT (1)
/* @brief OCOTP availability on the SoC. */
#define FSL_FEATURE_SOC_OCOTP_COUNT (1)
/* @brief PIT availability on the SoC. */
@@ -338,6 +342,8 @@
#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0)
/* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */
#define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (0)
/* @brief ENET Has Extra Clock Gate.(RW610). */
#define FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE (0)
/* EWM module features */
@@ -392,6 +398,12 @@
#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0)
/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */
#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1)
/* @brief FLEXSPI has no IP parallel mode. */
#define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0)
/* @brief FLEXSPI has no AHB parallel mode. */
#define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0)
/* @brief FLEXSPI support address shift. */
#define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0)
/* GPC module features */
@@ -648,6 +660,8 @@
#define FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT (1)
/* @brief If SEMC has register DBICR2 (register DBICR2). */
#define FSL_FEATURE_SEMC_HAS_DBICR2 (0)
/* @brief SEMC supports hardware ECC on NAND flash interface. */
#define FSL_FEATURE_SEMC_HAS_NAND_HW_ECC (0)
/* SNVS module features */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor.scf
+6 -4
View File
@@ -5,17 +5,19 @@
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b210709
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_flexspi_nor_sdram.scf
+6 -4
View File
@@ -5,17 +5,19 @@
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b210709
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_ram.scf
+6 -4
View File
@@ -5,17 +5,19 @@
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b210709
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram.scf
+6 -4
View File
@@ -5,17 +5,19 @@
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b210709
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/MIMXRT1062xxxxx_sdram_txt.scf
+6 -4
View File
@@ -5,17 +5,19 @@
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b210709
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/arm/startup_MIMXRT1062.S
+11 -11
View File
@@ -2,13 +2,13 @@
/* @file: startup_MIMXRT1062.s */
/* @purpose: CMSIS Cortex-M7 Core Device Startup File */
/* MIMXRT1062 */
/* @version: 1.2 */
/* @date: 2019-4-29 */
/* @build: b210419 */
/* @version: 1.4 */
/* @date: 2022-3-25 */
/* @build: b220425 */
/* ------------------------------------------------------------------------- */
/* */
/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
/* Copyright 2016-2021 NXP */
/* Copyright 2016-2022 NXP */
/* All rights reserved. */
/* */
/* SPDX-License-Identifier: BSD-3-Clause */
@@ -112,7 +112,7 @@ __Vectors:
.long ADC2_IRQHandler /* ADC2 interrupt*/
.long DCDC_IRQHandler /* DCDC interrupt*/
.long Reserved86_IRQHandler /* Reserved interrupt*/
.long Reserved87_IRQHandler /* Reserved interrupt*/
.long GPIO10_Combined_0_31_IRQHandler /* Combined interrupt indication for GPIO10 signal 0 throughout 31*/
.long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/
.long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/
.long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/
@@ -150,7 +150,7 @@ __Vectors:
.long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/
.long FLEXSPI2_IRQHandler /* FlexSPI2 interrupt*/
.long FLEXSPI_IRQHandler /* FlexSPI0 interrupt*/
.long SEMC_IRQHandler /* Reserved interrupt*/
.long SEMC_IRQHandler /* SEMC interrupt*/
.long USDHC1_IRQHandler /* USDHC1 interrupt*/
.long USDHC2_IRQHandler /* USDHC2 interrupt*/
.long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/
@@ -301,11 +301,11 @@ Reset_Handler:
str r1, [r0]
ldr r2, [r1]
msr msp, r2
ldr r0,=SystemInit
blx r0
ldr r0,=SystemInit
blx r0
cpsie i /* Unmask interrupts */
ldr r0,=__main
bx r0
ldr r0,=__main
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
@@ -916,7 +916,7 @@ FLEXIO3_IRQHandler:
def_irq_handler ADC2_IRQHandler
def_irq_handler DCDC_IRQHandler
def_irq_handler Reserved86_IRQHandler
def_irq_handler Reserved87_IRQHandler
def_irq_handler GPIO10_Combined_0_31_IRQHandler
def_irq_handler GPIO1_INT0_IRQHandler
def_irq_handler GPIO1_INT1_IRQHandler
def_irq_handler GPIO1_INT2_IRQHandler
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.c
+5 -11
View File
@@ -21,13 +21,14 @@ typedef struct _mem_align_control_block
#define FSL_COMPONENT_ID "platform.drivers.common"
#endif
#if !((defined(__DSC__) && defined(__CW__)))
void *SDK_Malloc(size_t size, size_t alignbytes)
{
mem_align_cb_t *p_cb = NULL;
uint32_t alignedsize;
/* Check overflow. */
alignedsize = SDK_SIZEALIGN(size, alignbytes);
alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
if (alignedsize < size)
{
return NULL;
@@ -38,19 +39,15 @@ void *SDK_Malloc(size_t size, size_t alignbytes)
return NULL;
}
alignedsize += alignbytes + sizeof(mem_align_cb_t);
alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
union
{
void *pointer_value;
#if (defined(__DSC__) && defined(__CW__))
uint32_t unsigned_value;
#else
uintptr_t unsigned_value;
#endif
} p_align_addr, p_addr;
p_addr.pointer_value = malloc(alignedsize);
p_addr.pointer_value = malloc((size_t)alignedsize);
if (p_addr.pointer_value == NULL)
{
@@ -71,11 +68,7 @@ void SDK_Free(void *ptr)
union
{
void *pointer_value;
#if (defined(__DSC__) && defined(__CW__))
uint32_t unsigned_value;
#else
uintptr_t unsigned_value;
#endif
} p_free;
p_free.pointer_value = ptr;
mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
@@ -89,3 +82,4 @@ void SDK_Free(void *ptr)
free(p_free.pointer_value);
}
#endif
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_common.h
+8 -1
View File
@@ -59,7 +59,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief common driver version. */
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
/*@}*/
/* Debug console type definition. */
@@ -190,6 +190,11 @@ enum _status_groups
kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */
kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */
kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */
kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */
kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */
kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */
kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */
kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */
};
/*! \public
@@ -264,6 +269,7 @@ typedef int32_t status_t;
extern "C" {
#endif
#if !((defined(__DSC__) && defined(__CW__)))
/*!
* @brief Allocate memory with given alignment and aligned size.
*
@@ -281,6 +287,7 @@ void *SDK_Malloc(size_t size, size_t alignbytes);
* @param ptr The memory to be release.
*/
void SDK_Free(void *ptr);
#endif
/*!
* @brief Delay at least for some time.
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.c
+22 -13
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -314,19 +314,19 @@ void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edm
*
* param base eDMA peripheral base address.
* param channel eDMA channel number.
* param type A channel link type, which can be one of the following:
* param linkType A channel link type, which can be one of the following:
* arg kEDMA_LinkNone
* arg kEDMA_MinorLink
* arg kEDMA_MajorLink
* param linkedChannel The linked channel number.
* note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
*/
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel)
{
assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], type, linkedChannel);
EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], linkType, linkedChannel);
}
/*!
@@ -458,7 +458,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd)
tcd->CITER = 0U;
tcd->DLAST_SGA = 0U;
/* Enable auto disable request feature */
tcd->CSR = DMA_CSR_DREQ(true);
tcd->CSR = DMA_CSR_DREQ(1U);
tcd->BITER = 0U;
}
@@ -466,7 +466,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd)
* brief Configures the eDMA TCD transfer attribute.
*
* The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
* The STCD is used in the scatter-gather mode.
* The TCD is used in the scatter-gather mode.
* This function configures the TCD transfer attribute, including source address, destination address,
* transfer size, address offset, and so on. It also configures the scatter gather feature if the
* user supplies the next TCD address.
@@ -592,19 +592,19 @@ void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t
*
* note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
* param tcd Point to the TCD structure.
* param type Channel link type, it can be one of:
* param linkType Channel link type, it can be one of:
* arg kEDMA_LinkNone
* arg kEDMA_MinorLink
* arg kEDMA_MajorLink
* param linkedChannel The linked channel number.
*/
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel)
{
assert(tcd != NULL);
assert(((uint32_t)tcd & 0x1FU) == 0U);
assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL);
if (type == kEDMA_MinorLink) /* Minor link config */
if (linkType == kEDMA_MinorLink) /* Minor link config */
{
uint16_t tmpreg;
@@ -619,7 +619,7 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
tcd->BITER = tmpreg;
}
else if (type == kEDMA_MajorLink) /* Major link config */
else if (linkType == kEDMA_MajorLink) /* Major link config */
{
uint16_t tmpreg;
@@ -1044,7 +1044,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config,
* param destWidth eDMA transfer destination address width(bytes).
* param bytesEachRequest eDMA transfer bytes per channel request.
* param transferBytes eDMA transfer bytes to be transferred.
* param type eDMA transfer type.
* param transferType eDMA transfer type.
* note The data address and the data width must be consistent. For example, if the SRC
* is 4 bytes, the source address must be 4 bytes aligned, or it results in
* source address error (SAE).
@@ -1056,13 +1056,13 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
uint32_t destWidth,
uint32_t bytesEachRequest,
uint32_t transferBytes,
edma_transfer_type_t type)
edma_transfer_type_t transferType)
{
assert(config != NULL);
int16_t srcOffset = 0, destOffset = 0;
switch (type)
switch (transferType)
{
case kEDMA_MemoryToMemory:
destOffset = (int16_t)destWidth;
@@ -1468,6 +1468,15 @@ void EDMA_HandleIRQ(edma_handle_t *handle)
{
tcds_done += handle->tcdSize;
}
/*
* While code run to here, it means a TCD transfer Done and a new TCD has loaded to the hardware
* so clear DONE here to allow submit scatter gather transfer request in the callback to avoid TCD
* overwritten.
*/
if (transfer_done)
{
handle->base->CDNE = handle->channel;
}
}
/* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
handle->header = (int8_t)new_header;
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_edma.h
+8 -8
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -438,14 +438,14 @@ void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edm
*
* @param base eDMA peripheral base address.
* @param channel eDMA channel number.
* @param type A channel link type, which can be one of the following:
* @param linkType A channel link type, which can be one of the following:
* @arg kEDMA_LinkNone
* @arg kEDMA_MinorLink
* @arg kEDMA_MajorLink
* @param linkedChannel The linked channel number.
* @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
*/
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel);
void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t linkType, uint32_t linkedChannel);
/*!
* @brief Sets the bandwidth for the eDMA transfer.
@@ -563,7 +563,7 @@ void EDMA_TcdReset(edma_tcd_t *tcd);
* @brief Configures the eDMA TCD transfer attribute.
*
* The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
* The STCD is used in the scatter-gather mode.
* The TCD is used in the scatter-gather mode.
* This function configures the TCD transfer attribute, including source address, destination address,
* transfer size, address offset, and so on. It also configures the scatter gather feature if the
* user supplies the next TCD address.
@@ -608,13 +608,13 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi
*
* @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
* @param tcd Point to the TCD structure.
* @param type Channel link type, it can be one of:
* @param linkType Channel link type, it can be one of:
* @arg kEDMA_LinkNone
* @arg kEDMA_MinorLink
* @arg kEDMA_MajorLink
* @param linkedChannel The linked channel number.
*/
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel);
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t linkType, uint32_t linkedChannel);
/*!
* @brief Sets the bandwidth for the eDMA TCD.
@@ -890,7 +890,7 @@ void EDMA_PrepareTransferConfig(edma_transfer_config_t *config,
* @param destWidth eDMA transfer destination address width(bytes).
* @param bytesEachRequest eDMA transfer bytes per channel request.
* @param transferBytes eDMA transfer bytes to be transferred.
* @param type eDMA transfer type.
* @param transferType eDMA transfer type.
* @note The data address and the data width must be consistent. For example, if the SRC
* is 4 bytes, the source address must be 4 bytes aligned, or it results in
* source address error (SAE).
@@ -902,7 +902,7 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
uint32_t destWidth,
uint32_t bytesEachRequest,
uint32_t transferBytes,
edma_transfer_type_t type);
edma_transfer_type_t transferType);
/*!
* @brief Submits the eDMA transfer request.
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.c
+17 -4
View File
@@ -44,6 +44,9 @@ enum
/*! @brief Pointers to enet clocks for each instance. */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
const clock_ip_name_t s_enetClock[] = ENET_CLOCKS;
#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
const clock_ip_name_t s_enetExtraClock[] = ENET_EXTRA_CLOCKS;
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief Pointers to enet transmit IRQ number for each instance. */
@@ -329,6 +332,11 @@ status_t ENET_Init(ENET_Type *base,
/* Ungate ENET clock. */
(void)CLOCK_EnableClock(s_enetClock[instance]);
#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
/* Ungate ENET extra clock. */
(void)CLOCK_EnableClock(s_enetExtraClock[instance]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset ENET module. */
ENET_Reset(base);
@@ -374,6 +382,11 @@ void ENET_Deinit(ENET_Type *base)
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disables the clock source. */
(void)CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]);
#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
/* Disables ENET extra clock. */
(void)CLOCK_DisableClock(s_enetExtraClock[ENET_GetInstance(base)]);
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
@@ -3906,14 +3919,14 @@ void ENET_1G_1588_Timer_DriverIRQHandler(void)
#endif /* ENET_1G */
#if defined(ENET1)
void ENET1_MAC0_Rx_Tx_Done0_DriverIRQHandler(void);
void ENET1_MAC0_Rx_Tx_Done0_DriverIRQHandler(void)
void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void);
void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void)
{
ENET_CommonFrame1IRQHandler(ENET1);
SDK_ISR_EXIT_BARRIER;
}
void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void);
void ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler(void)
void ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler(void);
void ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler(void)
{
ENET_CommonFrame2IRQHandler(ENET1);
SDK_ISR_EXIT_BARRIER;
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_enet.h
+4 -1
View File
@@ -24,7 +24,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief Defines the driver version. */
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 5, 3))
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 5, 4))
/*@}*/
/*! @name ENET DESCRIPTOR QUEUE */
@@ -776,6 +776,9 @@ typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
/*! @brief Pointers to enet clocks for each instance. */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
extern const clock_ip_name_t s_enetClock[];
#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
extern const clock_ip_name_t s_enetExtraClock[];
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.c
+43 -35
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -96,10 +96,10 @@
/* Define the range of memory that needs to be initialized when the device has memory error detection feature. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
#define CAN_INIT_RXFIR ((uint32_t)base + 0x4Cu)
#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uint32_t)base + (uint32_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1)
#define CAN_INIT_RXFIR ((uintptr_t)base + 0x4Cu)
#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1)
#define CAN_INIT_MEMORY_SIZE_1 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1
#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uint32_t)base + (uint32_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2)
#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2)
#define CAN_INIT_MEMORY_SIZE_2 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2
#endif
@@ -365,6 +365,23 @@ static flexcan_isr_t s_flexcanIsr = (flexcan_isr_t)DefaultISR;
static flexcan_isr_t s_flexcanIsr;
#endif
/*******************************************************************************
* Implementation of 32-bit memset
******************************************************************************/
static void flexcan_memset(void *s, uint32_t c, size_t n)
{
size_t m;
uint32_t *ptr = s;
m = n / sizeof(*ptr);
while ((m--) != (size_t)0)
{
*ptr++ = c;
}
}
/*******************************************************************************
* Code
******************************************************************************/
@@ -733,8 +750,8 @@ static void FLEXCAN_Reset(CAN_Type *base)
/* Do memory initialization for all FlexCAN RAM in order to have the parity bits in memory properly
updated. */
*(volatile uint32_t *)CAN_INIT_RXFIR = 0x0U;
(void)memset((void *)CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1);
(void)memset((void *)CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2);
flexcan_memset(CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1);
flexcan_memset(CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2);
/* Disable unrestricted write access to FlexCAN memory. */
base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK;
@@ -742,7 +759,7 @@ static void FLEXCAN_Reset(CAN_Type *base)
FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_AllMemoryErrorFlag);
#else
/* Only need clean all Message Buffer memory. */
(void)memset((void *)&base->MB[0], 0, sizeof(base->MB));
flexcan_memset((void *)&base->MB[0], 0, sizeof(base->MB));
#endif
/* Clean all individual Rx Mask of Message Buffers. */
@@ -818,7 +835,7 @@ static void FLEXCAN_SetBitRate(CAN_Type *base,
}
/* Update actual timing characteristic. */
FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig);
FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uintptr_t)&timingConfig);
}
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
@@ -869,7 +886,7 @@ static void FLEXCAN_SetFDBitRate(CAN_Type *base,
}
/* Update actual timing characteristic. */
FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig);
FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uintptr_t)&timingConfig);
}
#endif
@@ -2692,17 +2709,12 @@ void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_rep
*/
static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr)
{
uint32_t dbg_temp = 0U;
uint32_t u32TempCS = 0U;
uint32_t u32Timeout = DELAY_BUSIDLE;
uint32_t u32TempIMASK1 = base->IMASK1;
/*after backup all interruption, disable ALL interruption*/
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
uint32_t u32TempIMASK2 = base->IMASK2;
base->IMASK2 = 0;
#endif
base->IMASK1 = 0;
dbg_temp = (uint32_t)(base->DBG1);
uint32_t dbg_temp = 0U;
uint32_t u32TempCS = 0U;
uint32_t u32Timeout = DELAY_BUSIDLE;
/*disable ALL interrupts to prevent any context switching*/
uint32_t irqMask = DisableGlobalIRQ();
dbg_temp = (uint32_t)(base->DBG1);
switch (dbg_temp & CAN_DBG1_CFSM_MASK)
{
case RXINTERMISSION:
@@ -2743,10 +2755,7 @@ static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr)
*mbCSAddr = u32TempCS;
}
/*restore interruption*/
base->IMASK1 = u32TempIMASK1;
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
base->IMASK2 = u32TempIMASK2;
#endif
EnableGlobalIRQ(irqMask);
}
#endif
@@ -2776,12 +2785,12 @@ status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t
uint32_t cs_temp = 0;
status_t status;
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS));
#endif
/* Check if Message Buffer is available. */
if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK))
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS));
#endif
/* Inactive Tx Message Buffer. */
base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
@@ -2862,14 +2871,13 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra
volatile uint32_t *mbAddr = &(base->MB[0].CS);
uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
FLEXCAN_ERRATA_6032(base, &(mbAddr[offset]));
#endif
can_cs = mbAddr[offset];
/* Check if Message Buffer is available. */
if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK))
{
#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032)
FLEXCAN_ERRATA_6032(base, &(mbAddr[offset]));
#endif
/* Inactive Tx Message Buffer and Fill Message ID field. */
mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
mbAddr[offset + 1U] = pTxFrame->id;
@@ -3226,7 +3234,7 @@ status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fra
status_t status;
/* Write Tx Message Buffer to initiate a data sending. */
if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uint32_t)pTxFrame))
if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame))
{
/* Wait until CAN Message send out. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
@@ -3311,7 +3319,7 @@ status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_f
status_t status;
/* Write Tx Message Buffer to initiate a data sending. */
if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pTxFrame))
if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTxFrame))
{
/* Wait until CAN Message send out. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
@@ -3563,7 +3571,7 @@ status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handl
}
if (kStatus_Success ==
FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uint32_t)pMbXfer->frame))
FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame))
{
/* Enable Message Buffer Interrupt. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
@@ -3680,7 +3688,7 @@ status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *han
}
if (kStatus_Success ==
FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pMbXfer->framefd))
FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd))
{
/* Enable Message Buffer Interrupt. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan.h
+7 -9
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexCAN driver version. */
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 8, 2))
#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 8, 6))
/*@}*/
#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
@@ -396,7 +396,7 @@ enum _flexcan_interrupt_enable
kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< CAN Error interrupt, use bit 14. */
kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */
kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */
kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 22. */
kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 26. */
#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */
#endif
@@ -1607,8 +1607,7 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
/* Solve interrupt enable bits in CTRL1 register. */
base->CTRL1 |=
(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable |
(uint32_t)kFLEXCAN_WakeUpInterruptEnable));
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
}
/*!
@@ -1656,8 +1655,7 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
/* Solve interrupt enable bits in CTRL1 register. */
base->CTRL1 &=
~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable |
(uint32_t)kFLEXCAN_WakeUpInterruptEnable));
(uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
}
/*!
@@ -1730,9 +1728,9 @@ void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable);
* @param base FlexCAN peripheral base address.
* @return FlexCAN Rx FIFO Head address.
*/
static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
{
return (uint32_t) & (base->MB[0].CS);
return (uintptr_t) & (base->MB[0].CS);
}
/* @} */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.c
+7 -5
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -34,9 +34,11 @@ enum _flexcan_edma_tansfer_state
/*******************************************************************************
* Variables
******************************************************************************/
/* Array of FlexCAN peripheral base address. */
static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS;
/*<! Private handle only used for internally. */
static flexcan_edma_private_handle_t s_flexcanEdmaPrivateHandle[FSL_FEATURE_SOC_FLEXCAN_COUNT];
/* Private handle only used for internally. */
static flexcan_edma_private_handle_t s_flexcanEdmaPrivateHandle[ARRAY_SIZE(s_flexcanBases)];
/*******************************************************************************
* Prototypes
@@ -77,9 +79,9 @@ static void FLEXCAN_ReceiveFifoEDMACallback(edma_handle_t *handle, void *param,
idHitIndex = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U;
framefd->idhit = framefd->dataWord[idHitIndex];
/* Clear the unused frame data. */
for (uint32_t i = idHitIndex; i < 16U; i++)
for (uint32_t j = idHitIndex; j < 16U; j++)
{
framefd->dataWord[i] = 0x0U;
framefd->dataWord[j] = 0x0U;
}
framefd++;
}
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexcan_edma.h
+2 -2
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -23,7 +23,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexCAN EDMA driver version. */
#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 8, 1))
#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 8, 6))
/*@}*/
/* Forward declaration of the handle typedef. */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.c
+268 -45
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi.h
+32 -15
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* Copyright 2016-2020, 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -23,13 +23,13 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO SPI driver version 2.2.1. */
#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
/*! @brief FlexIO SPI driver version. */
#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*@}*/
#ifndef FLEXIO_SPI_DUMMYDATA
/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
#define FLEXIO_SPI_DUMMYDATA (0xFFFFU)
#define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU)
#endif
/*! @brief Retry times for waiting flag. */
@@ -37,6 +37,9 @@
#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
#endif
/*! @brief Get the transfer data format of width and bit order. */
#define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U))
/*! @brief Error codes for the FlexIO SPI driver. */
enum
{
@@ -68,6 +71,7 @@ typedef enum _flexio_spi_data_bitcount_mode
{
kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */
kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */
kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */
} flexio_spi_data_bitcount_mode_t;
/*! @brief Define FlexIO SPI interrupt mask. */
@@ -92,20 +96,25 @@ enum _flexio_spi_dma_enable
kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/
};
/*! @brief Define FlexIO SPI transfer flags. */
/*! @brief Define FlexIO SPI transfer flags.
* @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */
enum _flexio_spi_transfer_flags
{
kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */
kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */
kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */
kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */
kFLEXIO_SPI_8bitMsb = 0x0U, /*!< FlexIO SPI 8-bit MSB first */
kFLEXIO_SPI_8bitLsb = 0x1U, /*!< FlexIO SPI 8-bit LSB first */
kFLEXIO_SPI_16bitMsb = 0x2U, /*!< FlexIO SPI 16-bit MSB first */
kFLEXIO_SPI_16bitLsb = 0x3U, /*!< FlexIO SPI 16-bit LSB first */
kFLEXIO_SPI_32bitMsb = 0x4U, /*!< FlexIO SPI 32-bit MSB first */
kFLEXIO_SPI_32bitLsb = 0x5U, /*!< FlexIO SPI 32-bit LSB first */
kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */
};
/*! @brief Define FlexIO SPI access structure typedef. */
typedef struct _flexio_spi_type
{
FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */
uint8_t SDOPinIndex; /*!< Pin select for data output. */
uint8_t SDOPinIndex; /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as
GPIO input and disable all pull up/down in application. */
uint8_t SDIPinIndex; /*!< Pin select for data input. */
uint8_t SCKPinIndex; /*!< Pin select for clock. */
uint8_t CSnPinIndex; /*!< Pin select for enable. */
@@ -477,9 +486,9 @@ void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps,
*
* @param base Pointer to the FLEXIO_SPI_Type structure.
* @param direction Shift direction of MSB first or LSB first.
* @param data 8 bit/16 bit data.
* @param data 8/16/32 bit data.
*/
static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data)
static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data)
{
if (direction == kFLEXIO_SPI_MsbFirst)
{
@@ -501,15 +510,15 @@ static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_
* @param direction Shift direction of MSB first or LSB first.
* @return 8 bit/16 bit data received.
*/
static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction)
{
if (direction == kFLEXIO_SPI_MsbFirst)
{
return (uint16_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]);
}
else
{
return (uint16_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]);
}
}
@@ -560,6 +569,14 @@ status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
*/
status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer);
/*!
* @brief Flush tx/rx shifters.
*
* @param base Pointer to the FLEXIO_SPI_Type structure.
*/
void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base);
/*@}*/
/*Transactional APIs*/
/*!
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.c
+120 -29
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexio_spi_edma.h
+2 -2
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* Copyright 2016-2020, 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -23,7 +23,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief FlexIO SPI EDMA driver version. */
#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*@}*/
/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.c
+50 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2017-2021 NXP
* Copyright 2017-2022 NXP
* All rights reserved.
*
*
@@ -128,6 +128,55 @@ void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnabl
}
}
void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error)
{
assert(error != NULL);
switch (memory)
{
case kFLEXRAM_OCRAM:
base->OCRAM_ECC_ERROR_INJEC =
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR1BIT(error->SingleBitPos) |
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR2BIT(error->SecondBitPos) |
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR11BI(error->Fource1BitDataInversion) |
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR1NCI(error->FourceOneNCDataInversion) |
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRC1BI(error->FourceConti1BitDataInversion) |
FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRCNCI(error->FourceContiNCDataInversion);
break;
case kFLEXRAM_ITCM:
base->ITCM_ECC_ERROR_INJEC = FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR1BIT(error->SingleBitPos) |
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR2BIT(error->SecondBitPos) |
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR11BI(error->Fource1BitDataInversion) |
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR1NCI(error->FourceOneNCDataInversion) |
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRC1BI(error->FourceConti1BitDataInversion) |
FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRCNCI(error->FourceContiNCDataInversion);
break;
case kFLEXRAM_D0TCM:
base->D0TCM_ECC_ERROR_INJEC =
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR1BIT(error->SingleBitPos) |
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR2BIT(error->SecondBitPos) |
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR11BI(error->Fource1BitDataInversion) |
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR1NCI(error->FourceOneNCDataInversion) |
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRC1BI(error->FourceConti1BitDataInversion) |
FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRCNCI(error->FourceContiNCDataInversion);
break;
case kFLEXRAM_D1TCM:
base->D1TCM_ECC_ERROR_INJEC =
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR1BIT(error->SingleBitPos) |
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR2BIT(error->SecondBitPos) |
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR11BI(error->Fource1BitDataInversion) |
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR1NCI(error->FourceOneNCDataInversion) |
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRC1BI(error->FourceConti1BitDataInversion) |
FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRCNCI(error->FourceContiNCDataInversion);
break;
default:
assert(NULL);
break;
}
__DSB();
}
void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info)
{
assert(NULL != info);
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexram.h
+34 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2017-2021 NXP
* Copyright 2017-2022 NXP
* All rights reserved.
*
*
@@ -23,8 +23,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief Driver version 2.1.0. */
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U))
/*! @brief Driver version. */
#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 0U))
/*@}*/
/*! @brief Get ECC error detailed information. */
@@ -108,6 +108,29 @@ enum
};
#if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
/*! @brief FLEXRAM memory type, such as OCRAM/ITCM/D0TCM/D1TCM */
typedef enum _flexram_memory_type
{
kFLEXRAM_OCRAM = 0U, /*!< Memory type OCRAM */
kFLEXRAM_ITCM = 1U, /*!< Memory type ITCM */
kFLEXRAM_D0TCM = 2U, /*!< Memory type D0TCM */
kFLEXRAM_D1TCM = 3U, /*!< Memory type D1TCM */
} flexram_memory_type_t;
/*! @brief FLEXRAM error type, such as single bit error position, multi-bit error position */
typedef struct _flexram_ecc_error_type
{
uint8_t SingleBitPos; /*!< Bit position of the bit to inject ECC Error. */
uint8_t SecondBitPos; /*!< Bit position of the second bit to inject multi-bit ECC Error */
bool Fource1BitDataInversion; /*!< Force One 1-Bit Data Inversion (single-bit ECC error) on memory write access */
bool FourceOneNCDataInversion; /*!< Force One Non-correctable Data Inversion(multi-bit ECC error) on memory write
access */
bool FourceConti1BitDataInversion; /*!< Force Continuous 1-Bit Data Inversions (single-bit ECC error) on memory
write access */
bool FourceContiNCDataInversion; /*!< Force Continuous Non-correctable Data Inversions (multi-bit ECC error) on
memory write access */
} flexram_ecc_error_type_t;
/*! @brief FLEXRAM ocram ecc single error information, including single error information, error address, error data */
typedef struct _flexram_ocram_ecc_single_error_info
{
@@ -422,6 +445,14 @@ static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAd
*/
void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable);
/*!
* @brief FLEXRAM ECC error injection.
* @param base FLEXRAM base address.
* @param memory memory type, such as OCRAM/ITCM/DTCM.
* @param error ECC error type.
*/
void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error);
/*!
* @brief FLEXRAM get ocram ecc single error information.
* @param base FLEXRAM base address.
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.c
+35 -12
View File
@@ -33,10 +33,14 @@ enum
FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */
kFLEXSPI_FlashASampleClockRefDelayLocked =
FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK))
kFLEXSPI_FlashBSampleClockSlaveDelayLocked =
FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */
#endif
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BREFLOCK))
kFLEXSPI_FlashBSampleClockRefDelayLocked =
FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */
#endif
};
/*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */
@@ -293,10 +297,15 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
/* Configure MCR2 configurations. */
configValue = base->MCR2;
configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK |
FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK |
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
FLEXSPI_MCR2_SCKBDIFFOPT_MASK |
#endif
FLEXSPI_MCR2_SAMEDEVICEEN_MASK | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) |
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) |
#endif
FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) |
FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt);
@@ -354,9 +363,11 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
config->enableCombination = false;
#endif
config->enableDoze = true;
config->enableHalfSpeedAccess = false;
config->enableSckBDiffOpt = false;
config->enableDoze = true;
config->enableHalfSpeedAccess = false;
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
config->enableSckBDiffOpt = false;
#endif
config->enableSameConfigForAll = false;
config->seqTimeoutCycle = 0xFFFFU;
config->ipGrantTimeoutCycle = 0xFFU;
@@ -432,12 +443,18 @@ void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config,
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
/* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
statusValue =
(index == 0U) ?
((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked |
(uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked) :
if (index == 0U)
{
statusValue =
((uint32_t)kFLEXSPI_FlashASampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashASampleClockRefDelayLocked);
}
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS2_BSLVLOCK))
else
{
statusValue =
((uint32_t)kFLEXSPI_FlashBSampleClockSlaveDelayLocked | (uint32_t)kFLEXSPI_FlashBSampleClockRefDelayLocked);
}
#endif
if (0U != (configValue & FLEXSPI_DLLCR_DLLEN_MASK))
{
/* Wait slave delay line locked and slave reference delay line locked. */
@@ -527,11 +544,13 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK;
base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask);
}
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_FLSHCR4_WMENB))
else
{
base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK;
base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask);
}
#endif
/* Exit stop mode. */
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
@@ -564,8 +583,10 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
}
/* Unlock LUT for update. */
#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO))
base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
base->LUTCR = 0x02;
#endif
base->LUTCR = 0x02;
lutBase = &base->LUT[index];
for (i = 0; i < count; i++)
@@ -574,8 +595,10 @@ void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd,
}
/* Lock LUT. */
#if !((defined(FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO)) && (FSL_FEATURE_FLEXSPI_LUTKEY_IS_RO))
base->LUTKEY = FLEXSPI_LUT_KEY_VAL;
base->LUTCR = 0x01;
#endif
base->LUTCR = 0x01;
}
/*! brief Update read sample clock source
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_flexspi.h
+18 -8
View File
@@ -25,7 +25,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief FLEXSPI driver version 2.3.5. */
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 5))
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6))
/*@}*/
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
@@ -190,8 +190,10 @@ typedef enum _flexspi_port
{
kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
kFLEXSPI_PortA2, /*!< Access flash on A2 port. */
kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB))
kFLEXSPI_PortB1, /*!< Access flash on B1 port. */
kFLEXSPI_PortB2, /*!< Access flash on B2 port. */
#endif
kFLEXSPI_PortCount
} flexspi_port_t;
@@ -231,11 +233,13 @@ typedef struct _flexspi_config
bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins
(SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */
#endif
bool enableDoze; /*!< Enable/disable doze mode support. */
bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
speed commands. */
bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
output, when enable, Port B flash access is not available. */
bool enableDoze; /*!< Enable/disable doze mode support. */
bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
speed commands. */
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
output, when enable, Port B flash access is not available. */
#endif
bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
when enabled, same configuration in FLASHA1CRx is applied to all. */
uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution,
@@ -615,10 +619,12 @@ static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *por
*portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT);
}
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB))
if (portBPhase != NULL)
{
*portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT);
}
#endif
}
#endif
@@ -683,6 +689,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
*/
void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_IPCR1_IPAREN))
/*! @brief Enables/disables the FLEXSPI IP command parallel mode.
*
* @param base FLEXSPI peripheral base address.
@@ -699,7 +706,9 @@ static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
}
}
#endif
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_AHBCR_APAREN))
/*! @brief Enables/disables the FLEXSPI AHB command parallel mode.
*
* @param base FLEXSPI peripheral base address.
@@ -716,6 +725,7 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
}
}
#endif
/*! @brief Updates the LUT table.
*
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.c
+5 -1
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017, 2020 NXP
* Copyright 2016-2017, 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -17,8 +17,10 @@
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Array of GPIO peripheral base address. */
static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
#endif
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Array of GPIO clock name. */
@@ -29,6 +31,7 @@ static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS;
* Prototypes
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*!
* @brief Gets the GPIO instance according to the GPIO base
*
@@ -58,6 +61,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base)
return instance;
}
#endif
/*!
* brief Initializes the GPIO peripheral according to the specified
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpio.h
+1 -1
View File
@@ -23,7 +23,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief GPIO driver version. */
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
/*@}*/
/*! @brief GPIO direction definition. */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_gpt.h
+1 -1
View File
@@ -22,7 +22,7 @@
/*! @name Driver version */
/*@{*/
#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
/*@}*/
/*!
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_iomuxc.h
+64 -1
View File
@@ -1,6 +1,6 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -1144,6 +1144,69 @@
#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U
#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U
#define IOMUXC_GPIO_SPI_B0_00_GPIO10_IO00 0x401F865CU, 0x5U, 0, 0, 0x401F86B4U
#define IOMUXC_GPIO_SPI_B0_01_FLEXSPI2_B_SCLK 0x401F8660U, 0x0U, 0x401F8754U, 0x1U, 0x401F86B8U
#define IOMUXC_GPIO_SPI_B0_01_GPIO10_IO01 0x401F8660U, 0x5U, 0, 0, 0x401F86B8U
#define IOMUXC_GPIO_SPI_B0_02_FLEXSPI2_A_DATA00 0x401F8664U, 0x0U, 0x401F8730U, 0x2U, 0x401F86BCU
#define IOMUXC_GPIO_SPI_B0_02_GPIO10_IO02 0x401F8664U, 0x5U, 0, 0, 0x401F86BCU
#define IOMUXC_GPIO_SPI_B0_03_FLEXSPI2_B_DATA02 0x401F8668U, 0x0U, 0x401F8748U, 0x1U, 0x401F86C0U
#define IOMUXC_GPIO_SPI_B0_03_GPIO10_IO03 0x401F8668U, 0x5U, 0, 0, 0x401F86C0U
#define IOMUXC_GPIO_SPI_B0_04_FLEXSPI2_B_DATA03 0x401F866CU, 0x0U, 0x401F874CU, 0x1U, 0x401F86C4U
#define IOMUXC_GPIO_SPI_B0_04_GPIO10_IO04 0x401F866CU, 0x5U, 0, 0, 0x401F86C4U
#define IOMUXC_GPIO_SPI_B0_05_FLEXSPI2_A_SS0_B 0x401F8670U, 0x0U, 0, 0, 0x401F86C8U
#define IOMUXC_GPIO_SPI_B0_05_GPIO10_IO05 0x401F8670U, 0x5U, 0, 0, 0x401F86C8U
#define IOMUXC_GPIO_SPI_B0_06_FLEXSPI2_A_DATA02 0x401F8674U, 0x0U, 0x401F8738U, 0x2U, 0x401F86CCU
#define IOMUXC_GPIO_SPI_B0_06_GPIO10_IO06 0x401F8674U, 0x5U, 0, 0, 0x401F86CCU
#define IOMUXC_GPIO_SPI_B0_07_FLEXSPI2_B_DATA01 0x401F8678U, 0x0U, 0x401F8744U, 0x1U, 0x401F86D0U
#define IOMUXC_GPIO_SPI_B0_07_GPIO10_IO07 0x401F8678U, 0x5U, 0, 0, 0x401F86D0U
#define IOMUXC_GPIO_SPI_B0_08_FLEXSPI2_A_SCLK 0x401F867CU, 0x0U, 0x401F8750U, 0x2U, 0x401F86D4U
#define IOMUXC_GPIO_SPI_B0_08_GPIO10_IO08 0x401F867CU, 0x5U, 0, 0, 0x401F86D4U
#define IOMUXC_GPIO_SPI_B0_09_FLEXSPI2_A_DQS 0x401F8680U, 0x0U, 0x401F872CU, 0x2U, 0x401F86D8U
#define IOMUXC_GPIO_SPI_B0_09_GPIO10_IO09 0x401F8680U, 0x5U, 0, 0, 0x401F86D8U
#define IOMUXC_GPIO_SPI_B0_10_FLEXSPI2_A_DATA03 0x401F8684U, 0x0U, 0x401F873CU, 0x2U, 0x401F86DCU
#define IOMUXC_GPIO_SPI_B0_10_GPIO10_IO10 0x401F8684U, 0x5U, 0, 0, 0x401F86DCU
#define IOMUXC_GPIO_SPI_B0_11_FLEXSPI2_B_DATA00 0x401F8688U, 0x0U, 0x401F8740U, 0x1U, 0x401F86E0U
#define IOMUXC_GPIO_SPI_B0_11_GPIO10_IO11 0x401F8688U, 0x5U, 0, 0, 0x401F86E0U
#define IOMUXC_GPIO_SPI_B0_12_FLEXSPI2_A_DATA01 0x401F868CU, 0x0U, 0x401F8734U, 0x2U, 0x401F86E4U
#define IOMUXC_GPIO_SPI_B0_12_GPIO10_IO12 0x401F868CU, 0x5U, 0, 0, 0x401F86E4U
#define IOMUXC_GPIO_SPI_B0_13_GPIO10_IO13 0x401F8690U, 0x5U, 0, 0, 0x401F86E8U
#define IOMUXC_GPIO_SPI_B1_00_FLEXSPI2_A_DQS 0x401F8694U, 0x0U, 0x401F872CU, 0x0U, 0x401F86ECU
#define IOMUXC_GPIO_SPI_B1_00_GPIO10_IO14 0x401F8694U, 0x5U, 0, 0, 0x401F86ECU
#define IOMUXC_GPIO_SPI_B1_01_FLEXSPI2_A_DATA03 0x401F8698U, 0x0U, 0x401F873CU, 0x0U, 0x401F86F0U
#define IOMUXC_GPIO_SPI_B1_01_GPIO10_IO15 0x401F8698U, 0x5U, 0, 0, 0x401F86F0U
#define IOMUXC_GPIO_SPI_B1_02_FLEXSPI2_A_DATA02 0x401F869CU, 0x0U, 0x401F8738U, 0x0U, 0x401F86F4U
#define IOMUXC_GPIO_SPI_B1_02_GPIO10_IO16 0x401F869CU, 0x5U, 0, 0, 0x401F86F4U
#define IOMUXC_GPIO_SPI_B1_03_FLEXSPI2_A_DATA01 0x401F86A0U, 0x0U, 0x401F8734U, 0x0U, 0x401F86F8U
#define IOMUXC_GPIO_SPI_B1_03_GPIO10_IO17 0x401F86A0U, 0x5U, 0, 0, 0x401F86F8U
#define IOMUXC_GPIO_SPI_B1_04_FLEXSPI2_A_DATA00 0x401F86A4U, 0x0U, 0x401F8730U, 0x0U, 0x401F86FCU
#define IOMUXC_GPIO_SPI_B1_04_GPIO10_IO18 0x401F86A4U, 0x5U, 0, 0, 0x401F86FCU
#define IOMUXC_GPIO_SPI_B1_05_FLEXSPI2_A_SCLK 0x401F86A8U, 0x0U, 0x401F8750U, 0x0U, 0x401F8700U
#define IOMUXC_GPIO_SPI_B1_05_GPIO10_IO19 0x401F86A8U, 0x5U, 0, 0, 0x401F8700U
#define IOMUXC_GPIO_SPI_B1_06_FLEXSPI2_A_SS0_B 0x401F86ACU, 0x0U, 0, 0, 0x401F8704U
#define IOMUXC_GPIO_SPI_B1_06_GPIO10_IO20 0x401F86ACU, 0x5U, 0, 0, 0x401F8704U
#define IOMUXC_GPIO_SPI_B1_07_GPIO10_IO21 0x401F86B0U, 0x5U, 0, 0, 0x401F8708U
#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U
#define IOMUXC_SNVS_WAKEUP_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.c
+125
View File
@@ -0,0 +1,125 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_lpi2c_freertos.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.lpi2c_freertos"
#endif
static void LPI2C_RTOS_Callback(LPI2C_Type *base, lpi2c_master_handle_t *drv_handle, status_t status, void *userData)
{
lpi2c_rtos_handle_t *handle = (lpi2c_rtos_handle_t *)userData;
BaseType_t reschedule;
handle->async_status = status;
(void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule);
portYIELD_FROM_ISR(reschedule);
}
/*!
* brief Initializes LPI2C.
*
* This function initializes the LPI2C module and related RTOS context.
*
* param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context.
* param base The pointer base address of the LPI2C instance to initialize.
* param masterConfig Configuration structure to set-up LPI2C in master mode.
* param srcClock_Hz Frequency of input clock of the LPI2C module.
* return status of the operation.
*/
status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle,
LPI2C_Type *base,
const lpi2c_master_config_t *masterConfig,
uint32_t srcClock_Hz)
{
if (handle == NULL)
{
return kStatus_InvalidArgument;
}
if (base == NULL)
{
return kStatus_InvalidArgument;
}
(void)memset(handle, 0, sizeof(lpi2c_rtos_handle_t));
handle->mutex = xSemaphoreCreateMutex();
if (handle->mutex == NULL)
{
return kStatus_Fail;
}
handle->semaphore = xSemaphoreCreateBinary();
if (handle->semaphore == NULL)
{
vSemaphoreDelete(handle->mutex);
return kStatus_Fail;
}
handle->base = base;
LPI2C_MasterInit(handle->base, masterConfig, srcClock_Hz);
LPI2C_MasterTransferCreateHandle(base, &handle->drv_handle, LPI2C_RTOS_Callback, (void *)handle);
return kStatus_Success;
}
/*!
* brief Deinitializes the LPI2C.
*
* This function deinitializes the LPI2C module and related RTOS context.
*
* param handle The RTOS LPI2C handle.
*/
status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle)
{
LPI2C_MasterDeinit(handle->base);
vSemaphoreDelete(handle->semaphore);
vSemaphoreDelete(handle->mutex);
return kStatus_Success;
}
/*!
* brief Performs I2C transfer.
*
* This function performs an I2C transfer using LPI2C module according to data given in the transfer structure.
*
* param handle The RTOS LPI2C handle.
* param transfer Structure specifying the transfer parameters.
* return status of the operation.
*/
status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer)
{
status_t status;
/* Lock resource mutex */
if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE)
{
return kStatus_LPI2C_Busy;
}
status = LPI2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer);
if (status != kStatus_Success)
{
(void)xSemaphoreGive(handle->mutex);
return status;
}
/* Wait for transfer to finish */
(void)xSemaphoreTake(handle->semaphore, portMAX_DELAY);
/* Unlock resource mutex */
(void)xSemaphoreGive(handle->mutex);
/* Return status captured by callback function */
return handle->async_status;
}
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpi2c_freertos.h
+107
View File
@@ -0,0 +1,107 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_LPI2C_FREERTOS_H__
#define __FSL_LPI2C_FREERTOS_H__
#include "FreeRTOS.h"
#include "portable.h"
#include "semphr.h"
#include "fsl_lpi2c.h"
/*!
* @addtogroup lpi2c_freertos_driver LPI2C FreeRTOS Driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief LPI2C FreeRTOS driver version. */
#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
/*@}*/
/*!
* @cond RTOS_PRIVATE
* @brief LPI2C FreeRTOS handle
*/
typedef struct _lpi2c_rtos_handle
{
LPI2C_Type *base; /*!< LPI2C base address */
lpi2c_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */
status_t async_status;
SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */
SemaphoreHandle_t semaphore; /*!< Semaphore to notify and unblock task when transfer ends */
} lpi2c_rtos_handle_t;
/*! \endcond */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name LPI2C RTOS Operation
* @{
*/
/*!
* @brief Initializes LPI2C.
*
* This function initializes the LPI2C module and related RTOS context.
*
* @param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context.
* @param base The pointer base address of the LPI2C instance to initialize.
* @param masterConfig Configuration structure to set-up LPI2C in master mode.
* @param srcClock_Hz Frequency of input clock of the LPI2C module.
* @return status of the operation.
*/
status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle,
LPI2C_Type *base,
const lpi2c_master_config_t *masterConfig,
uint32_t srcClock_Hz);
/*!
* @brief Deinitializes the LPI2C.
*
* This function deinitializes the LPI2C module and related RTOS context.
*
* @param handle The RTOS LPI2C handle.
*/
status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle);
/*!
* @brief Performs I2C transfer.
*
* This function performs an I2C transfer using LPI2C module according to data given in the transfer structure.
*
* @param handle The RTOS LPI2C handle.
* @param transfer Structure specifying the transfer parameters.
* @return status of the operation.
*/
status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer);
/*!
* @}
*/
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* __FSL_LPI2C_FREERTOS_H__ */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_edma.h
+4 -4
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -163,11 +163,11 @@ extern "C" {
* This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a
* specified LPSPI instance, call this API once to get the initialized handle.
*
* Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx and Tx are the same source) DMA
* Note that the LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx are the same source) DMA
* request source.
* (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and
* Tx DMAMUX source for edmaIntermediaryToTxRegHandle.
* (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle.
* Tx DMAMUX source for edmaTxDataToTxRegHandle.
* (2) For a shared DMA request source, enable and set the Rx/Tx DMAMUX source for edmaRxRegToRxDataHandle.
*
* @param base LPSPI peripheral base address.
* @param handle LPSPI handle pointer to lpspi_master_edma_handle_t.
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.c
+127
View File
@@ -0,0 +1,127 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_lpspi_freertos.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.lpspi_freertos"
#endif
static void LPSPI_RTOS_Callback(LPSPI_Type *base, lpspi_master_handle_t *drv_handle, status_t status, void *userData)
{
lpspi_rtos_handle_t *handle = (lpspi_rtos_handle_t *)userData;
BaseType_t reschedule;
handle->async_status = status;
(void)xSemaphoreGiveFromISR(handle->event, &reschedule);
portYIELD_FROM_ISR(reschedule);
}
/*!
* brief Initializes LPSPI.
*
* This function initializes the LPSPI module and related RTOS context.
*
* param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context.
* param base The pointer base address of the LPSPI instance to initialize.
* param masterConfig Configuration structure to set-up LPSPI in master mode.
* param srcClock_Hz Frequency of input clock of the LPSPI module.
* return status of the operation.
*/
status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle,
LPSPI_Type *base,
const lpspi_master_config_t *masterConfig,
uint32_t srcClock_Hz)
{
if (handle == NULL)
{
return kStatus_InvalidArgument;
}
if (base == NULL)
{
return kStatus_InvalidArgument;
}
(void)memset(handle, 0, sizeof(lpspi_rtos_handle_t));
handle->mutex = xSemaphoreCreateMutex();
if (handle->mutex == NULL)
{
return kStatus_Fail;
}
handle->event = xSemaphoreCreateBinary();
if (handle->event == NULL)
{
vSemaphoreDelete(handle->mutex);
return kStatus_Fail;
}
handle->base = base;
LPSPI_MasterInit(handle->base, masterConfig, srcClock_Hz);
LPSPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, LPSPI_RTOS_Callback, (void *)handle);
return kStatus_Success;
}
/*!
* brief Deinitializes the LPSPI.
*
* This function deinitializes the LPSPI module and related RTOS context.
*
* param handle The RTOS LPSPI handle.
*/
status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle)
{
LPSPI_Deinit(handle->base);
vSemaphoreDelete(handle->event);
vSemaphoreDelete(handle->mutex);
return kStatus_Success;
}
/*!
* brief Performs SPI transfer.
*
* This function performs an SPI transfer according to data given in the transfer structure.
*
* param handle The RTOS LPSPI handle.
* param transfer Structure specifying the transfer parameters.
* return status of the operation.
*/
status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer)
{
status_t status;
/* Lock resource mutex */
if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE)
{
return kStatus_LPSPI_Busy;
}
status = LPSPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer);
if (status != kStatus_Success)
{
(void)xSemaphoreGive(handle->mutex);
return status;
}
/* Wait for transfer to finish */
if (xSemaphoreTake(handle->event, portMAX_DELAY) != pdTRUE)
{
return kStatus_LPSPI_Error;
}
/* Unlock resource mutex */
(void)xSemaphoreGive(handle->mutex);
/* Return status captured by callback function */
return handle->async_status;
}
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpspi_freertos.h
+107
View File
@@ -0,0 +1,107 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_LPSPI_FREERTOS_H__
#define __FSL_LPSPI_FREERTOS_H__
#include "FreeRTOS.h"
#include "portable.h"
#include "semphr.h"
#include "fsl_lpspi.h"
/*!
* @addtogroup lpspi_freertos_driver LPSPI FreeRTOS Driver
* @{
*/
/**********************************************************************************************************************
* Definitions
*********************************************************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief LPSPI FreeRTOS driver version 2.0.5. */
#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
/*@}*/
/*!
* @cond RTOS_PRIVATE
* @brief LPSPI FreeRTOS handle
*/
typedef struct _lpspi_rtos_handle
{
LPSPI_Type *base; /*!< LPSPI base address */
lpspi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */
status_t async_status;
SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */
SemaphoreHandle_t event; /*!< Semaphore to notify and unblock task when transfer ends */
} lpspi_rtos_handle_t;
/*! \endcond */
/**********************************************************************************************************************
* API
*********************************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name LPSPI RTOS Operation
* @{
*/
/*!
* @brief Initializes LPSPI.
*
* This function initializes the LPSPI module and related RTOS context.
*
* @param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context.
* @param base The pointer base address of the LPSPI instance to initialize.
* @param masterConfig Configuration structure to set-up LPSPI in master mode.
* @param srcClock_Hz Frequency of input clock of the LPSPI module.
* @return status of the operation.
*/
status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle,
LPSPI_Type *base,
const lpspi_master_config_t *masterConfig,
uint32_t srcClock_Hz);
/*!
* @brief Deinitializes the LPSPI.
*
* This function deinitializes the LPSPI module and related RTOS context.
*
* @param handle The RTOS LPSPI handle.
*/
status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle);
/*!
* @brief Performs SPI transfer.
*
* This function performs an SPI transfer according to data given in the transfer structure.
*
* @param handle The RTOS LPSPI handle.
* @param transfer Structure specifying the transfer parameters.
* @return status of the operation.
*/
status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer);
/*!
* @}
*/
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* __FSL_LPSPI_FREERTOS_H__ */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.c
+4 -4
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -700,7 +700,7 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address)
* endcode
*
* param base LPUART peripheral base address.
* param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable.
* param mask The interrupts to enable. Logical OR of ref _lpuart_interrupt_enable.
*/
void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
{
@@ -727,7 +727,7 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
#endif
/* Check int enable bits in base->CTRL */
/* Set int enable bits in base->CTRL */
base->CTRL |= mask;
}
@@ -851,7 +851,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base)
* can't be cleared by this function.
* Flags that can only cleared or set by hardware are:
* kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
* kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
* kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag,
* kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
* Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
*
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart.h
+4 -4
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief LPUART driver version. */
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 5, 3))
/*@}*/
/*! @brief Retry times for waiting flag. */
@@ -564,7 +564,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
* can't be cleared by this function.
* Flags that can only cleared or set by hardware are:
* kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag,
* kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag,
* kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag,
* kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag
* Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects.
*
@@ -595,7 +595,7 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
* @endcode
*
* @param base LPUART peripheral base address.
* @param mask The interrupts to enable. Logical OR of the enumeration _uart_interrupt_enable.
* @param mask The interrupts to enable. Logical OR of @ref _lpuart_interrupt_enable.
*/
void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask);
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_edma.c
+17 -1
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -38,6 +38,18 @@ enum
******************************************************************************/
/* Array of LPUART handle. */
#if (defined(LPUART12))
#define LPUART_HANDLE_ARRAY_SIZE 13
#else /* LPUART12 */
#if (defined(LPUART11))
#define LPUART_HANDLE_ARRAY_SIZE 12
#else /* LPUART11 */
#if (defined(LPUART10))
#define LPUART_HANDLE_ARRAY_SIZE 11
#else /* LPUART10 */
#if (defined(LPUART9))
#define LPUART_HANDLE_ARRAY_SIZE 10
#else /* LPUART9 */
#if (defined(LPUART8))
#define LPUART_HANDLE_ARRAY_SIZE 9
#else /* LPUART8 */
@@ -75,6 +87,10 @@ enum
#endif /* LPUART 6 */
#endif /* LPUART 7 */
#endif /* LPUART 8 */
#endif /* LPUART 9 */
#endif /* LPUART 10 */
#endif /* LPUART 11 */
#endif /* LPUART 12 */
/*<! Private handle only used for internally. */
static lpuart_edma_private_handle_t s_lpuartEdmaPrivateHandle[LPUART_HANDLE_ARRAY_SIZE];
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.c
+477
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_lpuart_freertos.h
+192
View File
@@ -0,0 +1,192 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_LPUART_RTOS_H__
#define __FSL_LPUART_RTOS_H__
#include "fsl_lpuart.h"
#include <FreeRTOS.h>
#include <event_groups.h>
#include <semphr.h>
/*!
* @addtogroup lpuart_freertos_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief LPUART FreeRTOS driver version. */
#define FSL_LPUART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
/*@}*/
/*! @brief LPUART RTOS configuration structure. */
typedef struct _lpuart_rtos_config
{
LPUART_Type *base; /*!< UART base address */
uint32_t srcclk; /*!< UART source clock in Hz*/
uint32_t baudrate; /*!< Desired communication speed */
lpuart_parity_mode_t parity; /*!< Parity setting */
lpuart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */
uint8_t *buffer; /*!< Buffer for background reception */
uint32_t buffer_size; /*!< Size of buffer for background reception */
/* Zero in constant and multiplier is interpreted as infinit timeout. */
uint32_t rx_timeout_constant_ms; /*!< RX timeout applied per receive */
uint32_t rx_timeout_multiplier_ms; /*!< RX timeout added for each byte of the receive. */
uint32_t tx_timeout_constant_ms; /*!< TX timeout applied per transmition */
uint32_t tx_timeout_multiplier_ms; /*!< TX timeout added for each byte of the transmition. */
#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
bool enableRxRTS; /*!< RX RTS enable */
bool enableTxCTS; /*!< TX CTS enable */
lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
#endif
} lpuart_rtos_config_t;
/*!
* @cond RTOS_PRIVATE
* @name LPUART event flags
*
* This are only valid states for txEvent and rxEvent (lpuart_rtos_handle_t).
*/
/*@{*/
/*! @brief Event flag - uart transmit complete. */
#define RTOS_LPUART_TX_COMPLETE 0x1U
/*! @brief Event flag - uart receive complete. */
#define RTOS_LPUART_RX_COMPLETE 0x2U
/*! @brief Event flag - ring buffer overrun. */
#define RTOS_LPUART_RING_BUFFER_OVERRUN 0x4U
/*! @brief Event flag - hardware buffer overrun. */
#define RTOS_LPUART_HARDWARE_BUFFER_OVERRUN 0x8U
/*@}*/
/*! @brief LPUART FreeRTOS transfer structure. */
typedef struct _lpuart_rtos_handle
{
LPUART_Type *base; /*!< UART base address */
lpuart_transfer_t txTransfer; /*!< TX transfer structure */
lpuart_transfer_t rxTransfer; /*!< RX transfer structure */
SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */
SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */
EventGroupHandle_t rxEvent; /*!< RX completion event */
EventGroupHandle_t txEvent; /*!< TX completion event */
uint32_t rx_timeout_constant_ms; /*!< RX Timeout applied per transfer */
uint32_t rx_timeout_multiplier_ms; /*!< RX Timeout added for each byte of the transfer. */
uint32_t tx_timeout_constant_ms; /*!< TX Timeout applied per transfer */
uint32_t tx_timeout_multiplier_ms; /*!< TX Timeout added for each byte of the transfer. */
void *t_state; /*!< Transactional state of the underlying driver */
#if (configSUPPORT_STATIC_ALLOCATION == 1)
StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */
StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */
StaticEventGroup_t txEventBuffer; /*!< Statically allocated memory for txEvent */
StaticEventGroup_t rxEventBuffer; /*!< Statically allocated memory for rxEvent */
#endif
} lpuart_rtos_handle_t;
/*! \endcond */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name LPUART RTOS Operation
* @{
*/
/*!
* @brief Initializes an LPUART instance for operation in RTOS.
*
* @param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context.
* @param t_handle The pointer to an allocated space to store the transactional layer internal state.
* @param cfg The pointer to the parameters required to configure the LPUART after initialization.
* @return 0 succeed, others failed
*/
int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg);
/*!
* @brief Deinitializes an LPUART instance for operation.
*
* This function deinitializes the LPUART module, sets all register value to the reset value,
* and releases the resources.
*
* @param handle The RTOS LPUART handle.
*/
int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle);
/*!
* @name LPUART transactional Operation
* @{
*/
/*!
* @brief Sends data in the background.
*
* This function sends data. It is an synchronous API.
* If the hardware buffer is full, the task is in the blocked state.
*
* @param handle The RTOS LPUART handle.
* @param buffer The pointer to buffer to send.
* @param length The number of bytes to send.
*/
int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length);
/*!
* @brief Receives data.
*
* This function receives data from LPUART. It is an synchronous API. If any data is immediately available
* it is returned immediately and the number of bytes received.
*
* @param handle The RTOS LPUART handle.
* @param buffer The pointer to buffer where to write received data.
* @param length The number of bytes to receive.
* @param received The pointer to a variable of size_t where the number of received data is filled.
*/
int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received);
/*!
* @brief Set RX timeout in runtime
*
* This function can modify RX timeout between initialization and receive.
*
* param handle The RTOS LPUART handle.
* param rx_timeout_constant_ms RX timeout applied per receive.
* param rx_timeout_multiplier_ms RX timeout added for each byte of the receive.
*/
int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle,
uint32_t rx_timeout_constant_ms,
uint32_t rx_timeout_multiplier_ms);
/*!
* @brief Set TX timeout in runtime
*
* This function can modify TX timeout between initialization and send.
*
* param handle The RTOS LPUART handle.
* param tx_timeout_constant_ms TX timeout applied per transmition.
* param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition.
*/
int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle,
uint32_t tx_timeout_constant_ms,
uint32_t tx_timeout_multiplier_ms);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* __FSL_LPUART_RTOS_H__ */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_nic301.h
+15 -15
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -26,8 +26,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief NIC301 driver version 2.0.0. */
#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
/*! @brief NIC301 driver version 2.0.1. */
#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
/*@}*/
#define GPV0_BASE (0x41000000UL)
@@ -177,7 +177,7 @@ extern "C" {
*/
static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
{
*(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET) = (value & NIC_QOS_MASK);
*(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
__DSB();
}
@@ -189,7 +189,7 @@ static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
*/
static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
{
return (nic_qos_t)((*(volatile uint32_t *)(base + NIC_READ_QOS_OFFSET)) & NIC_QOS_MASK);
return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
}
/*!
@@ -200,7 +200,7 @@ static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
*/
static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
{
*(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET) = (value & NIC_QOS_MASK);
*(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
__DSB();
}
@@ -212,7 +212,7 @@ static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
*/
static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
{
return (nic_qos_t)((*(volatile uint32_t *)(base + NIC_WRITE_QOS_OFFSET)) & NIC_QOS_MASK);
return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
}
/*!
@@ -223,7 +223,7 @@ static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
*/
static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v)
{
*(volatile uint32_t *)(base + NIC_FN_MOD_AHB_OFFSET) = v;
*(volatile uint32_t *)(base) = v;
__DSB();
}
@@ -235,7 +235,7 @@ static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v)
*/
static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
{
return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base + NIC_FN_MOD_AHB_OFFSET)) & NIC_FN_MOD_AHB_MASK);
return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK);
}
/*!
@@ -246,7 +246,7 @@ static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
*/
static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
{
*(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET) = (value & NIC_WR_TIDEMARK_MASK);
*(volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK);
__DSB();
}
@@ -258,7 +258,7 @@ static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
*/
static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
{
return (uint8_t)((*(volatile uint32_t *)(base + NIC_WR_TIDEMARK_OFFSET)) & NIC_WR_TIDEMARK_MASK);
return (uint8_t)((*(volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK);
}
/*!
@@ -269,7 +269,7 @@ static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
*/
static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
{
*(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET) = value;
*(volatile uint32_t *)(base) = value;
__DSB();
}
@@ -281,7 +281,7 @@ static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
*/
static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
{
return (nic_fn_mod_t)((*(volatile uint32_t *)(base + NIC_FN_MOD_OFFSET)) & NIC_FN_MOD_MASK);
return (nic_fn_mod_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_MASK);
}
/*!
@@ -292,7 +292,7 @@ static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
*/
static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value)
{
*(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET) = value;
*(volatile uint32_t *)(base) = value;
__DSB();
}
@@ -304,7 +304,7 @@ static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value)
*/
static inline nic_fn_mod2_t NIC_GetFnMod2(nic_reg_t base)
{
return (nic_fn_mod2_t)((*(volatile uint32_t *)(base + NIC_FN_MOD2_OFFSET)) & NIC_FN_MOD2_MASK);
return (nic_fn_mod2_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD2_MASK);
}
#if defined(__cplusplus)
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction.h
+812
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bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_config.h
+36
View File
@@ -0,0 +1,36 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_
#define _FSL_OS_ABSTRACTION_CONFIG_H_
#ifndef gMainThreadStackSize_c
#define gMainThreadStackSize_c 1024
#endif
#ifndef gMainThreadPriority_c
#define gMainThreadPriority_c 1
#endif
#ifndef gTaskMultipleInstancesManagement_c
#define gTaskMultipleInstancesManagement_c 0
#endif
/*! @brief Definition to determine whether enable OSA's TASK module. */
#ifndef OSA_USED
#ifndef FSL_OSA_TASK_ENABLE
#define FSL_OSA_TASK_ENABLE 0U
#endif
#else
#if defined(FSL_OSA_TASK_ENABLE)
#undef FSL_OSA_TASK_ENABLE
#endif
#define FSL_OSA_TASK_ENABLE 1U
#endif /* OSA_USED */
#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.c
+917
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File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_os_abstraction_rtthread.h
+130
View File
@@ -0,0 +1,130 @@
/*! *********************************************************************************
* Copyright (c) 2013-2014, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* ile
*
* SPDX-License-Identifier: BSD-3-Clause
********************************************************************************** */
#if !defined(__FSL_OS_ABSTRACTION_RTTHREAD_H__)
#define __FSL_OS_ABSTRACTION_RTTHREAD_H__
#if defined(__IAR_SYSTEMS_ICC__)
/**
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
*/
// http://supp.iar.com/Support/?note=24725
#define MISRAC_DISABLE \
_Pragma( \
"diag_suppress= \
Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
Pm155")
#define MISRAC_ENABLE \
_Pragma( \
"diag_default= \
Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\
Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\
Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\
Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\
Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\
Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\
Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\
Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\
Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\
Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\
Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\
Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\
Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\
Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\
Pm155")
#else
/* Empty MISRA C macros for other toolchains. */
#define MISRAC_DISABLE
#define MISRAC_ENABLE
#endif
MISRAC_DISABLE
#include <rtthread.h>
MISRAC_ENABLE
/*!
* @addtogroup os_abstraction_free_rtos
* @{
*/
/*******************************************************************************
* Declarations
******************************************************************************/
/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */
typedef rt_thread_t task_handler_t;
/*! @brief Type for a task stack.*/
typedef rt_uint32_t task_stack_t;
/*! @brief Type for task parameter */
typedef void *task_param_t;
/*! @brief Type for an event flags object.*/
typedef rt_uint32_t event_flags_t;
/*! @brief Constant to pass as timeout value in order to wait indefinitely. */
#define OSA_WAIT_FOREVER 0xFFFFFFFFU
/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */
#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU
/*! @brief The default interrupt handler installed in vector table. */
#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR))
extern void DefaultISR(void);
/*!
* @name Thread management
* @{
*/
/*!
* @brief To provide unified task piority for upper layer, OSA layer makes conversion.
*/
#define PRIORITY_OSA_TO_RTOS(osa_prio) ((UBaseType_t)configMAX_PRIORITIES - (osa_prio)-2U)
#define PRIORITY_RTOS_TO_OSA(rtos_prio) ((UBaseType_t)configMAX_PRIORITIES - (rtos_prio)-2U)
/* @}*/
/*!
* @name Message queues
* @{
*/
/*!
* @brief This macro statically reserves the memory required for the queue.
*
* @param name Identifier for the memory region.
* @param number Number of elements in the queue.
* @param size Size of every elements in words.
*/
#define MSG_QUEUE_DECLARE(name, number, size) msg_queue_t *name = NULL
/* @}*/
/*! @}*/
/*! @}*/
/*! @}*/
#endif // __FSL_OS_ABSTRACTION_RTTHREAD_H__
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.c
+1216 -77
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_pxp.h
+1301 -54
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.c
+31 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -525,6 +525,8 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin
* depending on the count direction
* 2. User can call the utility macros provided in fsl_common.h to convert to ticks
* 3. This function supports cases, providing only primary source clock without secondary source clock.
* 4. The load register is reset before the counter is reinitialized to the value
specified in the load register.
*
* param base Quad Timer peripheral base address
* param channel Quad Timer channel number
@@ -535,6 +537,34 @@ void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint1
/* Set the length bit to reinitialize the counters on a match */
base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK;
/* Reset LOAD register to reinitialize the counters */
base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK);
if ((base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) != 0U)
{
/* Counting down */
base->CHANNEL[channel].COMP2 = ticks - 1U;
}
else
{
/* Counting up */
base->CHANNEL[channel].COMP1 = ticks - 1U;
}
}
/*!
* brief Set compare value.
*
* This function sets the value used for comparison with the counter value.
*
* param base Quad Timer peripheral base address
* param channel Quad Timer channel number
* param ticks Timer period in units of ticks.
*/
void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)
{
base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK;
if ((base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) != 0U)
{
/* Counting down */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_qtmr.h
+28 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -20,7 +20,7 @@
/*! @name Driver version */
/*@{*/
#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version */
#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version */
/*@}*/
/*! @brief Quad Timer primary clock source selection*/
@@ -348,6 +348,32 @@ void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uin
*/
void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks);
/*!
* @brief Set compare value.
*
* This function sets the value used for comparison with the counter value.
*
* @param base Quad Timer peripheral base address
* @param channel Quad Timer channel number
* @param ticks Timer period in units of ticks.
*/
void QTMR_SetCompareValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks);
/*!
* @brief Set load value.
*
* This function sets the value used to initialize the counter after a counter comparison.
*
* @param base Quad Timer peripheral base address
* @param channel Quad Timer channel number
* @param value Load register initialization value.
*/
static inline void QTMR_SetLoadValue(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t value)
{
base->CHANNEL[channel].LOAD &= (uint16_t)(~TMR_LOAD_LOAD_MASK);
base->CHANNEL[channel].LOAD = value;
}
/*!
* @brief Reads the current timer counting value.
*
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.c
+18 -18
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -363,7 +363,7 @@ static void SAI_GetCommonConfig(sai_transceiver_t *config,
/* frame sync default configurations */
config->frameSync.frameSyncWidth = (uint8_t)bitWidth;
config->frameSync.frameSyncEarly = true;
#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
config->frameSync.frameSyncGenerateOnDemand = false;
#endif
config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow;
@@ -865,11 +865,11 @@ void SAI_RxEnable(I2S_Type *base, bool enable)
* This function will also clear all the error flags such as FIFO error, sync error etc.
*
* param base SAI base pointer
* param type Reset type, FIFO reset or software reset
* param resetType Reset type, FIFO reset or software reset
*/
void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)
{
base->TCSR |= (uint32_t)type;
base->TCSR |= (uint32_t)resetType;
/* Clear the software reset */
base->TCSR &= ~I2S_TCSR_SR_MASK;
@@ -884,11 +884,11 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
* This function will also clear all the error flags such as FIFO error, sync error etc.
*
* param base SAI base pointer
* param type Reset type, FIFO reset or software reset
* param resetType Reset type, FIFO reset or software reset
*/
void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type)
void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType)
{
base->RCSR |= (uint32_t)type;
base->RCSR |= (uint32_t)resetType;
/* Clear the software reset */
base->RCSR &= ~I2S_RCSR_SR_MASK;
@@ -1318,7 +1318,7 @@ void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sa
tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK);
#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
tcr4 &= ~I2S_TCR4_ONDEM_MASK;
tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand);
#endif
@@ -1347,7 +1347,7 @@ void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sa
rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK);
#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
rcr4 &= ~I2S_RCR4_ONDEM_MASK;
rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand);
#endif
@@ -2133,7 +2133,7 @@ void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint
}
SAI_WriteNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord);
buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord);
buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord);
i += bytesPerWord;
}
@@ -2188,7 +2188,7 @@ void SAI_WriteMultiChannelBlocking(
SAI_WriteNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer,
bytesPerWord * channelNums);
buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord * channelNums);
buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums);
j += bytesPerWord * channelNums;
}
@@ -2241,7 +2241,7 @@ void SAI_ReadMultiChannelBlocking(
SAI_ReadNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer,
bytesPerWord * channelNums);
buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord * channelNums);
buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums);
j += bytesPerWord * channelNums;
}
}
@@ -2273,7 +2273,7 @@ void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8
}
SAI_ReadNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord);
buffer = (uint8_t *)((uint32_t)buffer + bytesPerWord);
buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord);
i += bytesPerWord;
}
}
@@ -2745,7 +2745,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
/* Update the internal counter */
handle->saiQueue[handle->queueDriver].dataSize -= size;
handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size);
handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
}
#else
if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))
@@ -2757,7 +2757,7 @@ void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
/* Update internal counter */
handle->saiQueue[handle->queueDriver].dataSize -= size;
handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size);
handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
}
#endif /* FSL_FEATURE_SAI_FIFO_COUNT */
@@ -2821,7 +2821,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
/* Update the internal counter */
handle->saiQueue[handle->queueDriver].dataSize -= size;
handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size);
handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
}
#else
if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK))
@@ -2833,7 +2833,7 @@ void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
/* Update internal state */
handle->saiQueue[handle->queueDriver].dataSize -= size;
handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uint32_t)buffer + size);
handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size);
}
#endif /* FSL_FEATURE_SAI_FIFO_COUNT */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai.h
+11 -11
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2020 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
/*! @name Driver version */
/*@{*/
#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4)) /*!< Version 2.3.4 */
#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) /*!< Version 2.3.6 */
/*@}*/
/*! @brief _sai_status_t, SAI return status.*/
@@ -365,7 +365,7 @@ typedef struct _sai_frame_sync
bool frameSyncEarly; /*!< TRUE is frame sync assert one bit before the first bit of frame
FALSE is frame sync assert with the first bit of the frame */
#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND
#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */
#endif
@@ -940,9 +940,9 @@ static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)
* This function will also clear all the error flags such as FIFO error, sync error etc.
*
* @param base SAI base pointer
* @param type Reset type, FIFO reset or software reset
* @param tresetType Reset type, FIFO reset or software reset
*/
void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type);
void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType);
/*!
* @brief Do software reset or FIFO reset .
@@ -953,9 +953,9 @@ void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type);
* This function will also clear all the error flags such as FIFO error, sync error etc.
*
* @param base SAI base pointer
* @param type Reset type, FIFO reset or software reset
* @param resetType Reset type, FIFO reset or software reset
*/
void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type);
void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType);
/*!
* @brief Set the Tx channel FIFO enable mask.
@@ -1218,9 +1218,9 @@ static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
* @param channel Which data channel used.
* @return data register address.
*/
static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
{
return (uint32_t)(&(base->TDR)[channel]);
return (uintptr_t)(&(base->TDR)[channel]);
}
/*!
@@ -1232,9 +1232,9 @@ static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t cha
* @param channel Which data channel used.
* @return data register address.
*/
static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
{
return (uint32_t)(&(base->RDR)[channel]);
return (uintptr_t)(&(base->RDR)[channel]);
}
/*! @} */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.c
+1 -1
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_sai_edma.h
+1 -1
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* Copyright 2016-2021 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.c
+21 -18
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -24,11 +24,15 @@
#else
#define SEMC_IOCR_PINMUXBITWIDTH (0x3UL)
#endif /* FSL_FEATURE_SEMC_SUPPORT_SRAM_COUNT */
#define SEMC_IOCR_NAND_CE (4UL)
#define SEMC_IOCR_NOR_CE (5UL)
#define SEMC_IOCR_NOR_CE_A8 (2UL)
#define SEMC_IOCR_PSRAM_CE (6UL)
#define SEMC_IOCR_PSRAM_CE_A8 (3UL)
#define SEMC_IOCR_NAND_CE (4UL)
#define SEMC_IOCR_NOR_CE (5UL)
#define SEMC_IOCR_NOR_CE_A8 (2UL)
#define SEMC_IOCR_PSRAM_CE (6UL)
#if defined(SEMC_IOCR_PINMUXBITWIDTH) && (SEMC_IOCR_PINMUXBITWIDTH == 0x4UL)
#define SEMC_IOCR_PSRAM_CE_A8 (6UL)
#else
#define SEMC_IOCR_PSRAM_CE_A8 (3UL)
#endif /* SEMC_IOCR_PINMUXBITWIDTH */
#define SEMC_IOCR_DBI_CSX (7UL)
#define SEMC_IOCR_DBI_CSX_A8 (4UL)
#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U)
@@ -63,12 +67,11 @@ static uint32_t SEMC_GetInstance(SEMC_Type *base);
/*!
* @brief Covert the input memory size to internal register set value.
*
* @param base SEMC peripheral base address
* @param size_kbytes SEMC memory size in unit of kbytes.
* @param sizeConverted SEMC converted memory size to 0 ~ 0x1F.
* @return Execution status.
*/
static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted);
static status_t SEMC_CovertMemorySize(uint32_t size_kbytes, uint8_t *sizeConverted);
/*!
* @brief Covert the external timing nanosecond to internal clock cycle.
@@ -131,7 +134,7 @@ static uint32_t SEMC_GetInstance(SEMC_Type *base)
return instance;
}
static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted)
static status_t SEMC_CovertMemorySize(uint32_t size_kbytes, uint8_t *sizeConverted)
{
assert(sizeConverted != NULL);
uint32_t memsize;
@@ -408,7 +411,7 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
uint32_t iocReg = base->IOCR & (~(SEMC_IOCR_PINMUXBITWIDTH << (uint32_t)config->csxPinMux));
/* Base control. */
result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize);
if (result != kStatus_Success)
{
return result;
@@ -541,14 +544,14 @@ status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_
{
base->MCR &= ~SEMC_MCR_WPOL1_MASK;
}
result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize);
result = SEMC_CovertMemorySize(config->axiMemsize_kbytes, &memsize);
if (result != kStatus_Success)
{
return result;
}
base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK;
result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize);
result = SEMC_CovertMemorySize(config->ipgMemsize_kbytes, &memsize);
if (result != kStatus_Success)
{
return result;
@@ -689,7 +692,7 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t
{
base->MCR &= ~SEMC_MCR_WPOL0_MASK;
}
result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize);
if (result != kStatus_Success)
{
return result;
@@ -843,7 +846,7 @@ status_t SEMC_ConfigureSRAMWithChipSelection(SEMC_Type *base,
}
}
/* Base control. */
result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize);
if (result != kStatus_Success)
{
return result;
@@ -1076,7 +1079,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t
/* IOMUX setting. */
base->IOCR = iocReg | (muxCsx << (uint32_t)config->csxPinMux);
/* Base control. */
result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize);
result = SEMC_CovertMemorySize(config->memsize_kbytes, &memsize);
if (result != kStatus_Success)
{
return result;
@@ -1114,7 +1117,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t
* brief SEMC IP command access.
*
* param base SEMC peripheral base address.
* param type SEMC memory type. refer to "semc_mem_type_t"
* param memType SEMC memory type. refer to "semc_mem_type_t"
* param address SEMC device address.
* param command SEMC IP command.
* For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
@@ -1125,7 +1128,7 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t
* param read Data pointer for read data out.
*/
status_t SEMC_SendIPCommand(
SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)
SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read)
{
uint32_t cmdMode;
bool readCmd = false;
@@ -1139,7 +1142,7 @@ status_t SEMC_SendIPCommand(
/* Check command mode. */
cmdMode = (uint32_t)command & 0x0FU;
switch (type)
switch (memType)
{
case kSEMC_MemType_NAND:
readCmd = (cmdMode == (uint32_t)kSEMC_NANDCM_CommandAddressRead) ||
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_semc.h
+6 -6
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -20,8 +20,8 @@
/*! @name Driver version */
/*@{*/
/*! @brief SEMC driver version 2.3.1. */
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
/*! @brief SEMC driver version. */
#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 4, 3))
/*@}*/
/*! @brief SEMC status, _semc_status. */
@@ -479,7 +479,7 @@ typedef struct _semc_nor_config
uint8_t latencyCount; /*!< Latency count for sync mode. */
#endif
#if defined(FSL_FEATURE_SEMC_HAS_NOR_RD_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_RD_TIME)
uint8_t readCycle; /*!< Read cycle time for sync mode. */
uint8_t readCycle; /*!< Read cycle time for sync mode. */
#endif
#if defined(FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL) && (FSL_FEATURE_SEMC_HAS_DELAY_CHAIN_CONTROL)
uint8_t delayChain; /*!< Delay chain, which adds delays on DQS clock to compensate timings while DQS is faster than
@@ -832,7 +832,7 @@ static inline bool SEMC_IsInIdle(SEMC_Type *base)
* @brief SEMC IP command access.
*
* @param base SEMC peripheral base address.
* @param type SEMC memory type. refer to "semc_mem_type_t"
* @param memType SEMC memory type. refer to "semc_mem_type_t"
* @param address SEMC device address.
* @param command SEMC IP command.
* For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
@@ -843,7 +843,7 @@ static inline bool SEMC_IsInIdle(SEMC_Type *base)
* @param read Data pointer for read data out.
*/
status_t SEMC_SendIPCommand(
SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
SEMC_Type *base, semc_mem_type_t memType, uint32_t address, uint32_t command, uint32_t write, uint32_t *read);
/*!
* @brief Build SEMC IP command for NAND.
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.c
+3 -11
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2017-2019, 2021 NXP
* Copyright 2017-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -278,11 +278,7 @@ void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config)
{
assert(config != NULL);
#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
defined(SNVS_HP_CLOCKS))
uint32_t instance = SNVS_HP_GetInstance(base);
CLOCK_EnableClock(s_snvsHpClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
SNVS_HP_Init(base);
base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK;
@@ -304,11 +300,7 @@ void SNVS_HP_RTC_Deinit(SNVS_Type *base)
{
base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK;
#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
defined(SNVS_HP_CLOCKS))
uint32_t instance = SNVS_HP_GetInstance(base);
CLOCK_DisableClock(s_snvsHpClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
SNVS_HP_Deinit(base);
}
/*!
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_hp.h
+2 -2
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2017-2021, NXP
* Copyright 2017-2022, NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
/*! @name Driver version */
/*@{*/
#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */
#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) /*!< Version 2.3.2 */
/*@}*/
/*! @brief List of SNVS interrupts */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.c
+3 -11
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2017-2021, NXP
* Copyright 2017-2022, NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -285,11 +285,7 @@ void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config)
{
assert(config != NULL);
#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
defined(SNVS_LP_CLOCKS))
uint32_t instance = SNVS_LP_GetInstance(base);
CLOCK_EnableClock(s_snvsLpClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
SNVS_LP_Init(base);
if (config->srtcCalEnable)
{
@@ -318,11 +314,7 @@ void SNVS_LP_SRTC_Deinit(SNVS_Type *base)
{
base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK;
#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \
defined(SNVS_LP_CLOCKS))
uint32_t instance = SNVS_LP_GetInstance(base);
CLOCK_DisableClock(s_snvsLpClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
SNVS_LP_Deinit(base);
}
/*!
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_snvs_lp.h
+2 -2
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2017-2021, NXP
* Copyright 2017-2022, NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,7 +22,7 @@
/*! @name Driver version */
/*@{*/
#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 4, 3)) /*!< Version 2.4.3 */
#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4 */
/*@}*/
/*! @brief Define of SNVS_LP Zeroizable Master Key registers */
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/fsl_xbara.h
+5 -2
View File
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* Copyright 2016-2019, 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -28,6 +28,9 @@
/* Set the XBARA_SELx_SELx field to a new value. */
#define XBARA_WR_SELx_SELx(base, input, output) XBARA_SetSignalsConnection((base), (input), (output))
/* For driver backward compatibility. */
#define kXBARA_RequestInterruptEnalbe kXBARA_RequestInterruptEnable
/*!
* @brief XBARA active edge for detection
*/
@@ -46,7 +49,7 @@ typedef enum _xbar_request
{
kXBARA_RequestDisable = 0U, /*!< Interrupt and DMA are disabled. */
kXBARA_RequestDMAEnable = 1U, /*!< DMA enabled, interrupt disabled. */
kXBARA_RequestInterruptEnalbe = 2U /*!< Interrupt enabled, DMA disabled. */
kXBARA_RequestInterruptEnable = 2U /*!< Interrupt enabled, DMA disabled. */
} xbara_request_t;
/*!
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.c
+475
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/drivers/generic_list.h
+203
View File
File diff suppressed because it is too large. Load diff
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/fsl_device_registers.h
+2 -2
View File
@@ -1,6 +1,6 @@
/*
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2021 NXP
* Copyright 2016-2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -16,7 +16,7 @@
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_MIMXRT1062CVJ5A) || defined(CPU_MIMXRT1062CVL5A) || defined(CPU_MIMXRT1062DVJ6A) || \
defined(CPU_MIMXRT1062DVL6A))
defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1062DVN6B) || defined(CPU_MIMXRT1062XVN5B))
#define MIMXRT1062_SERIES
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor.ld
+6 -4
View File
@@ -4,17 +4,19 @@
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b210709
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
bsp/imxrt/libraries/MIMXRT1060/MIMXRT1060/gcc/MIMXRT1062xxxxx_flexspi_nor_sdram.ld
+6 -4
View File
@@ -4,17 +4,19 @@
** MIMXRT1062CVL5A
** MIMXRT1062DVJ6A
** MIMXRT1062DVL6A
** MIMXRT1062DVN6B
** MIMXRT1062XVN5B
**
** Compiler: GNU C Compiler
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
** Version: rev. 0.1, 2017-01-10
** Build: b210709
** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
** Version: rev. 0.2, 2022-03-25
** Build: b220401
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
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