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[smart/aarch64] code sync (#6750)

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* [smart/aarch64] sync aarch64
This commit is contained in:
Shell authored and GitHub committed 2022-12-20 17:49:37 +08:00
1 parent f0ef8ada33
commit e8504c7cf1
114 files changed
+6099 -9092
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bsp/qemu-virt64-aarch64/.config
+67 -286
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bsp/qemu-virt64-aarch64/Kconfig
+6 -2
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@@ -21,10 +21,14 @@ source "$PKGS_DIR/Kconfig"
config SOC_VIRT64_AARCH64
bool
select ARCH_ARMV8
select RT_USING_CACHE
select ARCH_CPU_64BIT
select ARCH_ARM_MMU
select RT_USING_CACHE
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select RT_USING_GIC
select BSP_USING_GIC
select ARCH_MM_MMU
default y
source "$BSP_DIR/driver/Kconfig"
source "$BSP_DIR/drivers/Kconfig"
bsp/qemu-virt64-aarch64/SConstruct
+18 -4
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@@ -1,19 +1,33 @@
import os
import sys
import rtconfig
import re
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.join(os.getcwd(), '..', '..')
from rtconfig import RTT_ROOT
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
TRACE_CONFIG = ""
content = ""
with open("rtconfig.h") as f:
for line in f.readlines():
if line.find("RT_BACKTRACE_FUNCTION_NAME") != -1:
for token in line.split(" "):
if re.match(r'RT_BACKTRACE_FUNCTION_NAME$', token, flags=0):
TRACE_CONFIG = " "
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS + TRACE_CONFIG,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS + TRACE_CONFIG,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS + TRACE_CONFIG,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
bsp/qemu-virt64-aarch64/applications/console.c
+21 -1
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@@ -10,9 +10,13 @@
#include <rtthread.h>
#if defined(RT_USING_POSIX_DEVIO) && defined(RT_USING_SMART)
#include <console.h>
#endif
#include <virtio_console.h>
int console_init()
static int console_init()
{
rt_err_t status = RT_EOK;
rt_device_t device = rt_device_find("virtio-console0");
@@ -44,7 +48,23 @@ static int console(int argc, char **argv)
{
rt_kprintf("console change to %s\n", argv[2]);
rt_console_set_device(argv[2]);
#ifdef RT_USING_POSIX_DEVIO
{
rt_device_t dev = rt_device_find(argv[2]);
if (dev != RT_NULL)
{
#ifdef RT_USING_SMART
console_set_iodev(dev);
#else
rt_kprintf("TODO not supported\n");
#endif
}
}
#else
finsh_set_device(argv[2]);
#endif /* RT_USING_POSIX_DEVIO */
}
else
{
bsp/qemu-virt64-aarch64/applications/graphic.c
+1 -1
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@@ -114,7 +114,7 @@ void graphic_thread(void *param)
rt_device_control(device, RTGRAPHIC_CTRL_RECT_UPDATE, &rect_info);
while (i < sizeof(cursor) / sizeof(rt_uint32_t))
while (i < sizeof(cursor) / 4)
{
/* R: 0x4c G: 0xaf B: 0x50 A: 0.8 */
((rt_uint32_t *)cursor)[i] = 0xcc4caf50;
bsp/qemu-virt64-aarch64/applications/main.c
+4 -4
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@@ -5,14 +5,14 @@
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
* 2020/10/7 bernard the first version
*/
#include <rtthread.h>
#include <stdio.h>
int main(int argc, char** argv)
int main(void)
{
rt_kprintf("Hi, this is RT-Thread!!\n");
printf("hello rt-thread\n");
return 0;
}
bsp/qemu-virt64-aarch64/applications/mnt.c
+2 -2
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@@ -5,7 +5,7 @@
*
* Change Logs:
* Date Author Notes
* 2017-5-30 bernard the first version
* 2021/08/19 bernard the first version
*/
#include <rtthread.h>
@@ -15,7 +15,7 @@
int mnt_init(void)
{
if(rt_device_find("virtio-blk0"))
if (rt_device_find("virtio-blk0"))
{
/* mount virtio-blk as root directory */
if (dfs_mount("virtio-blk0", "/", "elm", 0, RT_NULL) == 0)
bsp/qemu-virt64-aarch64/applications/pin.c
+1 -1
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@@ -21,7 +21,7 @@ void qemu_gpio3_key_poweroff(void *args)
rt_hw_cpu_shutdown();
}
int pin_init()
static int pin_init()
{
rt_pin_attach_irq(3, PIN_IRQ_MODE_FALLING, qemu_gpio3_key_poweroff, RT_NULL);
rt_pin_irq_enable(3, RT_TRUE);
bsp/qemu-virt64-aarch64/driver/SConscript
-19
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@@ -1,19 +0,0 @@
# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
list = os.listdir(cwd)
CPPPATH = [cwd]
objs = []
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
objs = objs + group
Return('objs')
bsp/qemu-virt64-aarch64/driver/board.c
-147
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@@ -1,147 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-07-29 zdzn first version
* 2021-07-31 GuEe-GUI config the memory/io address map
* 2021-09-11 GuEe-GUI remove do-while in rt_hw_timer_isr
* 2021-12-28 GuEe-GUI add smp support
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include <mmu.h>
#include <gic.h>
#include <gicv3.h>
#include <psci.h>
#include <gtimer.h>
#include <cpuport.h>
#include <interrupt.h>
#include "drv_uart.h"
struct mem_desc platform_mem_desc[] =
{
{0x40000000, 0x80000000, 0x40000000, NORMAL_MEM},
{PL031_RTC_BASE, PL031_RTC_BASE + 0x1000, PL031_RTC_BASE, DEVICE_MEM},
{PL061_GPIO_BASE, PL061_GPIO_BASE + 0x1000, PL061_GPIO_BASE, DEVICE_MEM},
{PL011_UART0_BASE, PL011_UART0_BASE + 0x1000, PL011_UART0_BASE, DEVICE_MEM},
{VIRTIO_MMIO_BASE, VIRTIO_MMIO_BASE + VIRTIO_MAX_NR * VIRTIO_MMIO_SIZE, VIRTIO_MMIO_BASE, DEVICE_MEM},
#ifdef BSP_USING_GICV2
{GIC_PL390_DISTRIBUTOR_PPTR, GIC_PL390_DISTRIBUTOR_PPTR + 0x1000, GIC_PL390_DISTRIBUTOR_PPTR, DEVICE_MEM},
#endif
#ifdef BSP_USING_GICV3
{GIC_PL500_DISTRIBUTOR_PPTR, GIC_PL500_DISTRIBUTOR_PPTR + 0x1000, GIC_PL500_DISTRIBUTOR_PPTR, DEVICE_MEM},
{GIC_PL500_REDISTRIBUTOR_PPTR, GIC_PL500_REDISTRIBUTOR_PPTR + 0xf60000, GIC_PL500_REDISTRIBUTOR_PPTR, DEVICE_MEM},
#endif
};
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
void idle_wfi(void)
{
asm volatile ("wfi");
}
/**
* Initialize the Hardware related stuffs. Called from rtthread_startup()
* after interrupt disabled.
*/
void rt_hw_board_init(void)
{
rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size);
rt_hw_mmu_init();
/* initialize hardware interrupt */
rt_hw_interrupt_init();
/* initialize uart */
rt_hw_uart_init();
/* initialize timer for os tick */
rt_hw_gtimer_init();
rt_thread_idle_sethook(idle_wfi);
arm_psci_init(PSCI_METHOD_HVC, RT_NULL, RT_NULL);
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_HEAP
/* initialize memory system */
rt_kprintf("heap: [0x%08x - 0x%08x]\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_SMP
/* install IPI handle */
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
arm_gic_umask(0, IRQ_ARM_IPI_KICK);
#endif
}
void poweroff(void)
{
arm_psci_system_off();
}
MSH_CMD_EXPORT(poweroff, poweroff...);
void rt_hw_cpu_shutdown()
{
rt_kprintf("shutdown...\n");
poweroff();
}
void reboot(void)
{
arm_psci_system_reboot();
}
MSH_CMD_EXPORT(reboot, reboot...);
#ifdef RT_USING_SMP
void rt_hw_secondary_cpu_up(void)
{
int i;
extern void secondary_cpu_start(void);
extern rt_uint64_t rt_cpu_mpidr_early[];
for (i = 1; i < RT_CPUS_NR; ++i)
{
arm_psci_cpu_on(rt_cpu_mpidr_early[i], (uint64_t)(secondary_cpu_start));
}
}
void secondary_cpu_c_start(void)
{
rt_hw_mmu_init();
rt_hw_spin_lock(&_cpus_lock);
arm_gic_cpu_init(0, platform_get_gic_cpu_base());
#ifdef BSP_USING_GICV3
arm_gic_redist_init(0, platform_get_gic_redist_base());
#endif
rt_hw_vector_init();
rt_hw_gtimer_local_enable();
arm_gic_umask(0, IRQ_ARM_IPI_KICK);
rt_kprintf("\rcall cpu %d on success\n", rt_hw_cpu_id());
rt_system_scheduler_start();
}
void rt_hw_secondary_cpu_idle_exec(void)
{
__WFE();
}
#endif
bsp/qemu-virt64-aarch64/driver/board.h
-24
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@@ -1,24 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <virt.h>
extern unsigned char __bss_start;
extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
void rt_hw_board_init(void);
#endif
bsp/qemu-virt64-aarch64/driver/drv_rtc.c
-206
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bsp/qemu-virt64-aarch64/driver/virtio/virtio.c
-324
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bsp/qemu-virt64-aarch64/driver/virtio/virtio.h
-141
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@@ -1,141 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-9-16 GuEe-GUI the first version
* 2021-11-11 GuEe-GUI modify to virtio common interface
*/
#ifndef __VIRTIO_H__
#define __VIRTIO_H__
#include <rthw.h>
#include <rtdef.h>
#ifndef RT_USING_VIRTIO_VERSION
#define RT_USING_VIRTIO_VERSION 0x1
#endif
#include <virtio_mmio.h>
#include <virtio_queue.h>
#define VIRTIO_MAGIC_VALUE 0x74726976 /* "virt" */
#define VIRTIO_STATUS_ACKNOWLEDGE (1 << 0)
#define VIRTIO_STATUS_DRIVER (1 << 1)
#define VIRTIO_STATUS_DRIVER_OK (1 << 2)
#define VIRTIO_STATUS_FEATURES_OK (1 << 3)
#define VIRTIO_STATUS_NEEDS_RESET (1 << 6)
#define VIRTIO_STATUS_FAILED (1 << 7)
#define VIRTIO_F_NOTIFY_ON_EMPTY 24
#define VIRTIO_F_ANY_LAYOUT 27
#define VIRTIO_F_RING_INDIRECT_DESC 28
#define VIRTIO_F_RING_EVENT_IDX 29
#define VIRTIO_F_VERSION_1 32
#define VIRTIO_F_RING_PACKED 34
#define VIRTIO_VA2PA(vaddr) ((rt_ubase_t)vaddr)
#define VIRTIO_PA2VA(paddr) ((rt_ubase_t)paddr)
#define VIRTIO_PAGE_SHIFT 12
#define VIRTIO_PAGE_SIZE (1 << VIRTIO_PAGE_SHIFT)
#define VIRTIO_PAGE_ALIGN(addr) (RT_ALIGN(addr, VIRTIO_PAGE_SIZE))
enum
{
/* virtio 1.0 */
VIRTIO_DEVICE_ID_INVALID = 0, /* Invalid device */
VIRTIO_DEVICE_ID_NET = 1, /* Net */
VIRTIO_DEVICE_ID_BLOCK = 2, /* Block */
VIRTIO_DEVICE_ID_CONSOLE = 3, /* Console */
VIRTIO_DEVICE_ID_RNG = 4, /* Rng */
VIRTIO_DEVICE_ID_BALLOON = 5, /* Balloon */
VIRTIO_DEVICE_ID_IOMEM = 6, /* IO memory */
VIRTIO_DEVICE_ID_RPMSG = 7, /* Remote processor messaging */
VIRTIO_DEVICE_ID_SCSI = 8, /* SCSI */
VIRTIO_DEVICE_ID_9P = 9, /* 9p console */
VIRTIO_DEVICE_ID_MAC80211_WLAN = 10, /* Mac80211 wlan */
VIRTIO_DEVICE_ID_RPROC_SERIAL = 11, /* Remoteproc serial link */
VIRTIO_DEVICE_ID_CAIF = 12, /* CAIF */
VIRTIO_DEVICE_ID_MEM_BALLOON = 13, /* Memory balloon */
VIRTIO_DEVICE_ID_GPU = 16, /* GPU */
VIRTIO_DEVICE_ID_TIME = 17, /* Timer/clock device */
VIRTIO_DEVICE_ID_INPUT = 18, /* Input */
/* virtio 1.1 */
VIRTIO_DEVICE_ID_SOCKET = 19, /* Socket device */
VIRTIO_DEVICE_ID_CRYPTO = 20, /* Crypto device */
VIRTIO_DEVICE_ID_SIG_DIS_MOD = 21, /* Signal Distribution Module */
VIRTIO_DEVICE_ID_PSTORE = 22, /* Pstore device */
VIRTIO_DEVICE_ID_IOMMU = 23, /* IOMMU device */
VIRTIO_DEVICE_ID_MEM = 24, /* Memory device */
/* virtio 1.2 */
VIRTIO_DEVICE_ID_AUDIO = 25, /* Audio device */
VIRTIO_DEVICE_ID_FS = 26, /* File system device */
VIRTIO_DEVICE_ID_PMEM = 27, /* PMEM device */
VIRTIO_DEVICE_ID_RPMB = 28, /* RPMB device */
VIRTIO_DEVICE_ID_MAC80211_HWSIM = 29, /* Mac80211 hwsim wireless simulation device */
VIRTIO_DEVICE_ID_VIDEO_ENCODER = 30, /* Video encoder device */
VIRTIO_DEVICE_ID_VIDEO_DECODER = 31, /* Video decoder device */
VIRTIO_DEVICE_ID_SCMI = 32, /* SCMI device */
VIRTIO_DEVICE_ID_NITRO_SEC_MOD = 33, /* NitroSecureModule */
VIRTIO_DEVICE_ID_I2C_ADAPTER = 34, /* I2C adapter */
VIRTIO_DEVICE_ID_WATCHDOG = 35, /* Watchdog */
VIRTIO_DEVICE_ID_CAN = 36, /* CAN device */
VIRTIO_DEVICE_ID_DMABUF = 37, /* Virtio dmabuf */
VIRTIO_DEVICE_ID_PARAM_SERV = 38, /* Parameter Server */
VIRTIO_DEVICE_ID_AUDIO_POLICY = 39, /* Audio policy device */
VIRTIO_DEVICE_ID_BT = 40, /* Bluetooth device */
VIRTIO_DEVICE_ID_GPIO = 41, /* GPIO device */
VIRTIO_DEVICE_ID_RDMA = 42, /* RDMA device */
VIRTIO_DEVICE_TYPE_SIZE
};
struct virtio_device
{
rt_uint32_t irq;
struct virtq *queues;
rt_size_t queues_num;
union
{
rt_ubase_t *mmio_base;
struct virtio_mmio_config *mmio_config;
};
#ifdef RT_USING_SMP
struct rt_spinlock spinlock;
#endif
void *priv;
};
typedef rt_err_t (*virtio_device_init_handler)(rt_ubase_t *mmio_base, rt_uint32_t irq);
void virtio_reset_device(struct virtio_device *dev);
void virtio_status_acknowledge_driver(struct virtio_device *dev);
void virtio_status_driver_ok(struct virtio_device *dev);
void virtio_interrupt_ack(struct virtio_device *dev);
rt_bool_t virtio_has_feature(struct virtio_device *dev, rt_uint32_t feature_bit);
rt_err_t virtio_queues_alloc(struct virtio_device *dev, rt_size_t queues_num);
void virtio_queues_free(struct virtio_device *dev);
rt_err_t virtio_queue_init(struct virtio_device *dev, rt_uint32_t queue_index, rt_size_t ring_size);
void virtio_queue_destroy(struct virtio_device *dev, rt_uint32_t queue_index);
void virtio_queue_notify(struct virtio_device *dev, rt_uint32_t queue_index);
void virtio_submit_chain(struct virtio_device *dev, rt_uint32_t queue_index, rt_uint16_t desc_index);
rt_uint16_t virtio_alloc_desc(struct virtio_device *dev, rt_uint32_t queue_index);
void virtio_free_desc(struct virtio_device *dev, rt_uint32_t queue_index, rt_uint16_t desc_index);
rt_err_t virtio_alloc_desc_chain(struct virtio_device *dev, rt_uint32_t queue_index, rt_size_t count,
rt_uint16_t *indexs);
void virtio_free_desc_chain(struct virtio_device *dev, rt_uint32_t queue_index, rt_uint16_t desc_index);
void virtio_fill_desc(struct virtio_device *dev, rt_uint32_t queue_index, rt_uint16_t desc_index,
rt_uint64_t addr, rt_uint32_t len, rt_uint16_t flags, rt_uint16_t next);
#endif /* __VIRTIO_H__ */
bsp/qemu-virt64-aarch64/driver/virtio/virtio_blk.c
-240
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bsp/qemu-virt64-aarch64/driver/virtio/virtio_blk.h
-106
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@@ -1,106 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-9-16 GuEe-GUI the first version
* 2021-11-11 GuEe-GUI using virtio common interface
*/
#ifndef __VIRTIO_BLK_H__
#define __VIRTIO_BLK_H__
#include <rtdef.h>
#include <virtio.h>
#define VIRTIO_BLK_QUEUE 0
#define VIRTIO_BLK_BUF_DATA_SIZE 512
#define VIRTIO_BLK_BYTES_PER_SECTOR 512
#define VIRTIO_BLK_BLOCK_SIZE 512
#define VIRTIO_BLK_QUEUE_RING_SIZE 4
#define VIRTIO_BLK_F_RO 5 /* Disk is read-only */
#define VIRTIO_BLK_F_SCSI 7 /* Supports scsi command passthru */
#define VIRTIO_BLK_F_CONFIG_WCE 11 /* Writeback mode available in config */
#define VIRTIO_BLK_F_MQ 12 /* Support more than one vq */
#define VIRTIO_BLK_T_IN 0 /* Read the blk */
#define VIRTIO_BLK_T_OUT 1 /* Write the blk */
#define VIRTIO_BLK_T_SCSI_CMD 2
#define VIRTIO_BLK_T_SCSI_CMD_OUT 3
#define VIRTIO_BLK_T_FLUSH 4
#define VIRTIO_BLK_T_FLUSH_OUT 5
struct virtio_blk_req
{
rt_uint32_t type;
rt_uint32_t ioprio;
rt_uint64_t sector;
};
struct virtio_blk_config
{
rt_uint64_t capacity;
rt_uint32_t size_max;
rt_uint32_t seg_max;
struct virtio_blk_geometry
{
rt_uint16_t cylinders;
rt_uint8_t heads;
rt_uint8_t sectors;
} geometry;
rt_uint32_t blk_size;
struct virtio_blk_topology
{
/* # Of logical blocks per physical block (log2) */
rt_uint8_t physical_block_exp;
/* Offset of first aligned logical block */
rt_uint8_t alignment_offset;
/* Suggested minimum I/O size in blocks */
rt_uint16_t min_io_size;
/* Optimal (suggested maximum) I/O size in blocks */
rt_uint32_t opt_io_size;
} topology;
rt_uint8_t writeback;
rt_uint8_t unused0;
rt_uint16_t num_queues;
rt_uint32_t max_discard_sectors;
rt_uint32_t max_discard_seg;
rt_uint32_t discard_sector_alignment;
rt_uint32_t max_write_zeroes_sectors;
rt_uint32_t max_write_zeroes_seg;
rt_uint8_t write_zeroes_may_unmap;
rt_uint8_t unused1[3];
rt_uint32_t max_secure_erase_sectors;
rt_uint32_t max_secure_erase_seg;
rt_uint32_t secure_erase_sector_alignment;
} __attribute__((packed));
struct virtio_blk_device
{
struct rt_device parent;
struct virtio_device virtio_dev;
struct virtio_blk_config *config;
struct
{
rt_bool_t valid;
rt_uint8_t status;
struct virtio_blk_req req;
} info[VIRTIO_BLK_QUEUE_RING_SIZE];
};
rt_err_t rt_virtio_blk_init(rt_ubase_t *mmio_base, rt_uint32_t irq);
#endif /* __VIRTIO_BLK_H__ */
bsp/qemu-virt64-aarch64/driver/virtio/virtio_console.c
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bsp/qemu-virt64-aarch64/driver/virtio/virtio_console.h
-96
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@@ -1,96 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-11 GuEe-GUI the first version
*/
#ifndef __VIRTIO_CONSOLE_H__
#define __VIRTIO_CONSOLE_H__
#include <rtdef.h>
#include <virtio.h>
#ifndef RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR
#define RT_USING_VIRTIO_CONSOLE_PORT_MAX_NR 4
#endif
#define VIRTIO_CONSOLE_QUEUE_DATA_RX 0
#define VIRTIO_CONSOLE_QUEUE_DATA_TX 1
#define VIRTIO_CONSOLE_QUEUE_CTRL_RX 2
#define VIRTIO_CONSOLE_QUEUE_CTRL_TX 3
#define VIRTIO_CONSOLE_QUEUE_SIZE 64
/* Every port has data rx & tx, and port0 has ctrl rx & tx in multiport */
#define VIRTIO_CONSOLE_PORT_QUEUE_INDEX(id, queue) ((id) * 2 + (!!(id)) * 2 + (queue))
#define VIRTIO_CONSOLE_PORT_BAD_ID (~(rt_uint32_t)0)
#define VIRTIO_CONSOLE_F_SIZE 0 /* Does host provide console size? */
#define VIRTIO_CONSOLE_F_MULTIPORT 1 /* Does host provide multiple ports? */
#define VIRTIO_CONSOLE_F_EMERG_WRITE 2 /* Does host support emergency write? */
struct virtio_console_config
{
rt_uint16_t cols;
rt_uint16_t rows;
rt_uint32_t max_nr_ports;
rt_uint32_t emerg_wr;
} __attribute__((packed));
struct virtio_console_control
{
rt_uint32_t id; /* Port number */
rt_uint16_t event; /* The kind of control event */
rt_uint16_t value; /* Extra information for the event */
};
enum virtio_console_control_event
{
VIRTIO_CONSOLE_DEVICE_READY = 0,
VIRTIO_CONSOLE_PORT_ADD,
VIRTIO_CONSOLE_PORT_REMOVE,
VIRTIO_CONSOLE_PORT_READY,
VIRTIO_CONSOLE_CONSOLE_PORT,
VIRTIO_CONSOLE_RESIZE,
VIRTIO_CONSOLE_PORT_OPEN,
VIRTIO_CONSOLE_PORT_NAME,
};
struct virtio_console_resize
{
rt_uint16_t cols;
rt_uint16_t rows;
};
struct virtio_console_device
{
struct rt_device parent;
struct virtio_device virtio_dev;
rt_uint32_t console_id;
rt_size_t port_nr;
rt_size_t max_port_nr;
rt_list_t port_head;
struct virtio_console_config *config;
struct
{
struct virtio_console_control rx_ctrl, tx_ctrl;
} info[VIRTIO_CONSOLE_QUEUE_SIZE];
};
rt_err_t rt_virtio_console_init(rt_ubase_t *mmio_base, rt_uint32_t irq);
enum
{
VIRTIO_DEVICE_CTRL_CONSOLE_PORT_CREATE = 0x20,
VIRTIO_DEVICE_CTRL_CONSOLE_PORT_DESTROY,
};
#endif /* __VIRTIO_CONSOLE_H__ */
bsp/qemu-virt64-aarch64/driver/virtio/virtio_gpu.c
-923
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bsp/qemu-virt64-aarch64/driver/virtio/virtio_gpu.h
-412
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File diff suppressed because it is too large. Load diff
bsp/qemu-virt64-aarch64/driver/virtio/virtio_input.c
-438
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bsp/qemu-virt64-aarch64/driver/virtio/virtio_input.h
-145
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@@ -1,145 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-11 GuEe-GUI the first version
*/
#ifndef __VIRTIO_INPUT_H__
#define __VIRTIO_INPUT_H__
#include <rtdef.h>
#include <virtio.h>
#include <virtio_input_event_codes.h>
#define VIRTIO_INPUT_QUEUE_EVENT 0
#define VIRTIO_INPUT_QUEUE_STATUS 1
#define VIRTIO_INPUT_EVENT_QUEUE_SIZE 64
#define VIRTIO_INPUT_STATUS_QUEUE_SIZE 8
#define VIRTIO_INPUT_QUEUE_MAX_SIZE (VIRTIO_INPUT_EVENT_QUEUE_SIZE > VIRTIO_INPUT_STATUS_QUEUE_SIZE ? \
VIRTIO_INPUT_EVENT_QUEUE_SIZE : VIRTIO_INPUT_STATUS_QUEUE_SIZE)
#define VIRTIO_INPUT_ABS_AXIS_X 0
#define VIRTIO_INPUT_ABS_AXIS_Y 1
enum virtio_input_type
{
VIRTIO_INPUT_TYPE_KEYBOARD,
VIRTIO_INPUT_TYPE_MOUSE,
VIRTIO_INPUT_TYPE_TABLET,
VIRTIO_INPUT_TYPE_SIZE,
};
enum virtio_input_config_select
{
VIRTIO_INPUT_CFG_UNSET = 0x00,
VIRTIO_INPUT_CFG_ID_NAME = 0x01,
VIRTIO_INPUT_CFG_ID_SERIAL = 0x02,
VIRTIO_INPUT_CFG_ID_DEVIDS = 0x03,
VIRTIO_INPUT_CFG_PROP_BITS = 0x10,
VIRTIO_INPUT_CFG_EV_BITS = 0x11,
VIRTIO_INPUT_CFG_ABS_INFO = 0x12,
};
struct virtio_input_absinfo
{
rt_uint32_t min; /* Minimum value for the axis */
rt_uint32_t max; /* Maximum value for the axis */
rt_uint32_t fuzz; /* Fuzz value that is used to filter noise from the event stream */
rt_uint32_t flat; /* Within this value will be discarded by joydev interface and reported as 0 instead */
rt_uint32_t res; /* Resolution for the values reported for the axis */
};
struct virtio_input_devids
{
rt_uint16_t bustype;
rt_uint16_t vendor;
rt_uint16_t product;
rt_uint16_t version;
};
struct virtio_input_config
{
rt_uint8_t select;
rt_uint8_t subsel;
rt_uint8_t size;
rt_uint8_t reserved[5];
union
{
char string[128];
rt_uint8_t bitmap[128];
struct virtio_input_absinfo abs;
struct virtio_input_devids ids;
};
} __attribute__((packed));
struct virtio_input_event
{
rt_uint16_t type;
rt_uint16_t code;
rt_uint32_t value;
};
#ifdef ARCH_CPU_64BIT
#define BITS_PER_LONG 64
#else
#define BITS_PER_LONG 32
#endif
#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#define BITS_PER_BYTE 8
#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE)
#define BITS_TO_BYTES(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(char))
#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(long))
struct virtio_input_device
{
struct rt_device parent;
struct virtio_device virtio_dev;
rt_ubase_t ev_bit[BITS_TO_LONGS(EV_CNT)];
rt_ubase_t key_bit[BITS_TO_LONGS(KEY_CNT)];
rt_ubase_t rel_bit[BITS_TO_LONGS(REL_CNT)];
rt_ubase_t abs_bit[BITS_TO_LONGS(ABS_CNT)];
enum virtio_input_type type;
struct virtio_input_config *config;
/* Broadcast events */
struct rt_mutex rw_mutex;
void (*bsct_handler)(struct virtio_input_event event);
struct virtio_input_event bcst_events[VIRTIO_INPUT_EVENT_QUEUE_SIZE];
/* Receive events */
struct virtio_input_event recv_events[VIRTIO_INPUT_EVENT_QUEUE_SIZE];
/* Transmit status */
struct virtio_input_event xmit_events[VIRTIO_INPUT_STATUS_QUEUE_SIZE];
};
enum
{
VIRTIO_DEVICE_CTRL_INPUT_GET_TYPE = 0x20,
VIRTIO_DEVICE_CTRL_INPUT_BIND_BSCT_HANDLER,
VIRTIO_DEVICE_CTRL_INPUT_GET_ABS_X_INFO,
VIRTIO_DEVICE_CTRL_INPUT_GET_ABS_Y_INFO,
VIRTIO_DEVICE_CTRL_INPUT_SET_STATUS,
VIRTIO_DEVICE_CTRL_INPUT_GET_EV_BIT,
VIRTIO_DEVICE_CTRL_INPUT_GET_KEY_BIT,
VIRTIO_DEVICE_CTRL_INPUT_GET_REL_BIT,
VIRTIO_DEVICE_CTRL_INPUT_GET_ABS_BIT,
};
rt_err_t rt_virtio_input_init(rt_ubase_t *mmio_base, rt_uint32_t irq);
#endif /* __VIRTIO_INPUT_H__ */
bsp/qemu-virt64-aarch64/driver/virtio/virtio_input_event_codes.h
-932
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bsp/qemu-virt64-aarch64/driver/virtio/virtio_mmio.h
-57
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@@ -1,57 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-9-16 GuEe-GUI the first version
* 2021-11-11 GuEe-GUI modify to virtio common interface
*/
#ifndef __VIRTIO_MMIO_H__
#define __VIRTIO_MMIO_H__
#include <rtdef.h>
struct virtio_mmio_config
{
rt_uint32_t magic; /* [0x00]<RO> Magic value */
rt_uint32_t version; /* [0x04]<RO> Device version number */
rt_uint32_t device_id; /* [0x08]<RO> Virtio Subsystem Device ID */
rt_uint32_t vendor_id; /* [0x0c]<RO> Virtio Subsystem Vendor ID */
rt_uint32_t device_features; /* [0x10]<RO> Flags representing features the device supports */
rt_uint32_t device_features_sel; /* [0x14]<WO> Device (host) features word selection. */
rt_uint32_t res0[2]; /* [0x18] */
rt_uint32_t driver_features; /* [0x20]<WO> Device features understood and activated by the driver */
rt_uint32_t driver_features_sel; /* [0x24]<WO> Activated (guest) features word selection */
rt_uint32_t guest_page_size; /* [0x28]<WO> Guest page size, this value should be a power of 2 */
rt_uint32_t res1[1]; /* [0x2c] */
rt_uint32_t queue_sel; /* [0x30]<WO> Virtual queue index */
rt_uint32_t queue_num_max; /* [0x34]<RO> Maximum virtual queue size */
rt_uint32_t queue_num; /* [0x38]<WO> Virtual queue size */
rt_uint32_t queue_align; /* [0x3c]<WO> Used Ring alignment in the virtual queue */
rt_uint32_t queue_pfn; /* [0x40]<RW> Guest physical page number of the virtual queue */
rt_uint32_t queue_ready; /* [0x44]<RW> Virtual queue ready bit */
rt_uint32_t res2[2]; /* [0x48] */
rt_uint32_t queue_notify; /* [0x50]<WO> Queue notifier */
rt_uint32_t res3[3]; /* [0x54] */
rt_uint32_t interrupt_status; /* [0x60]<RO> Interrupt status */
rt_uint32_t interrupt_ack; /* [0x64]<WO> Interrupt acknowledge */
rt_uint32_t res4[2]; /* [0x68] */
rt_uint32_t status; /* [0x70]<RW> Device status */
rt_uint32_t res5[3]; /* [0x74] */
rt_uint32_t queue_desc_low; /* [0x80]<WO> Virtual queue’s Descriptor Area 64 bit long physical address */
rt_uint32_t queue_desc_high; /* [0x84]<WO> */
rt_uint32_t res6[2]; /* [0x88] */
rt_uint32_t queue_driver_low; /* [0x90]<WO> Virtual queue’s Driver Area 64 bit long physical address */
rt_uint32_t queue_driver_high; /* [0x94]<WO> */
rt_uint32_t res7[2]; /* [0x98] */
rt_uint32_t queue_device_low; /* [0xa0]<WO> Virtual queue’s Device Area 64 bit long physical address */
rt_uint32_t queue_device_high; /* [0xa4]<WO> */
rt_uint32_t res8[21]; /* [0xa8] */
rt_uint32_t config_generation; /* [0xfc]<RO> Configuration atomicity value */
rt_uint32_t config[]; /* [0x100+]<RO> Configuration space */
} __attribute__((packed));
#endif /* __VIRTIO_MMIO_H__ */
bsp/qemu-virt64-aarch64/driver/virtio/virtio_net.c
-303
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bsp/qemu-virt64-aarch64/driver/virtio/virtio_net.h
-115
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@@ -1,115 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-11 GuEe-GUI the first version
*/
#ifndef __VIRTIO_NET_H__
#define __VIRTIO_NET_H__
#include <rtdef.h>
#include <netif/ethernetif.h>
#include <virtio.h>
#define VIRTIO_NET_QUEUE_RX 0
#define VIRTIO_NET_QUEUE_TX 1
#define VIRTIO_NET_RTX_QUEUE_SIZE 16
#define VIRTIO_NET_RTX_BUF_SIZE 2048
#define VIRTIO_NET_F_CSUM 0 /* Host handles pkts w/ partial csum */
#define VIRTIO_NET_F_GUEST_CSUM 1 /* Guest handles pkts w/ partial csum */
#define VIRTIO_NET_F_CTRL_GUEST_OFFLOADS 2 /* Dynamic offload configuration */
#define VIRTIO_NET_F_MTU 3 /* Initial MTU advice */
#define VIRTIO_NET_F_MAC 5 /* Host has given MAC address */
#define VIRTIO_NET_F_GUEST_TSO4 7 /* Guest can handle TSOv4 in */
#define VIRTIO_NET_F_GUEST_TSO6 8 /* Guest can handle TSOv6 in */
#define VIRTIO_NET_F_GUEST_ECN 9 /* Guest can handle TSO[6] w/ ECN in */
#define VIRTIO_NET_F_GUEST_UFO 10 /* Guest can handle UFO in */
#define VIRTIO_NET_F_HOST_TSO4 11 /* Host can handle TSOv4 in */
#define VIRTIO_NET_F_HOST_TSO6 12 /* Host can handle TSOv6 in */
#define VIRTIO_NET_F_HOST_ECN 13 /* Host can handle TSO[6] w/ ECN in */
#define VIRTIO_NET_F_HOST_UFO 14 /* Host can handle UFO in */
#define VIRTIO_NET_F_MRG_RXBUF 15 /* Host can merge receive buffers. */
#define VIRTIO_NET_F_STATUS 16 /* virtio_net_config.status available */
#define VIRTIO_NET_F_CTRL_VQ 17 /* Control channel available */
#define VIRTIO_NET_F_CTRL_RX 18 /* Control channel RX mode support */
#define VIRTIO_NET_F_CTRL_VLAN 19 /* Control channel VLAN filtering */
#define VIRTIO_NET_F_CTRL_RX_EXTRA 20 /* Extra RX mode control support */
#define VIRTIO_NET_F_GUEST_ANNOUNCE 21 /* Guest can announce device on the network */
#define VIRTIO_NET_F_MQ 22 /* Device supports Receive Flow Steering */
#define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */
#define VIRTIO_NET_F_HASH_REPORT 57 /* Supports hash report */
#define VIRTIO_NET_F_RSS 60 /* Supports RSS RX steering */
#define VIRTIO_NET_F_RSC_EXT 61 /* Extended coalescing info */
#define VIRTIO_NET_F_STANDBY 62 /* Act as standby for another device with the same MAC */
#define VIRTIO_NET_F_SPEED_DUPLEX 63 /* Device set linkspeed and duplex */
#define VIRTIO_NET_S_LINK_UP (1 << 0)
#define VIRTIO_NET_S_ANNOUNCE (1 << 1)
#define VIRTIO_NET_HDR_F_NEEDS_CSUM 1
#define VIRTIO_NET_HDR_F_DATA_VALID 2
#define VIRTIO_NET_HDR_F_RSC_INFO 4
#define VIRTIO_NET_HDR_GSO_NONE 0
#define VIRTIO_NET_HDR_GSO_TCPV4 1
#define VIRTIO_NET_HDR_GSO_UDP 3
#define VIRTIO_NET_HDR_GSO_TCPV6 4
#define VIRTIO_NET_HDR_GSO_ECN 0x80
struct virtio_net_hdr
{
rt_uint8_t flags;
rt_uint8_t gso_type;
rt_uint16_t hdr_len;
rt_uint16_t gso_size;
rt_uint16_t csum_start;
rt_uint16_t csum_offset;
rt_uint16_t num_buffers;
} __attribute__ ((packed));
#define VIRTIO_NET_MSS 1514
#define VIRTIO_NET_HDR_SIZE (sizeof(struct virtio_net_hdr))
#define VIRTIO_NET_PAYLOAD_MAX_SIZE (VIRTIO_NET_HDR_SIZE + VIRTIO_NET_MSS)
struct virtio_net_config
{
rt_uint8_t mac[6];
rt_uint16_t status;
rt_uint16_t max_virtqueue_pairs;
rt_uint16_t mtu;
rt_uint32_t speed;
rt_uint8_t duplex;
rt_uint8_t rss_max_key_size;
rt_uint16_t rss_max_indirection_table_length;
rt_uint32_t supported_hash_types;
} __attribute__((packed));
struct virtio_net_device
{
struct eth_device parent;
struct virtio_device virtio_dev;
struct virtio_net_config *config;
struct
{
/* Transmit hdr */
struct virtio_net_hdr hdr;
/* Transmit buffer */
rt_uint8_t tx_buffer[VIRTIO_NET_PAYLOAD_MAX_SIZE];
/* Receive buffer */
rt_uint8_t rx_buffer[VIRTIO_NET_PAYLOAD_MAX_SIZE];
} info[VIRTIO_NET_RTX_QUEUE_SIZE];
};
rt_err_t rt_virtio_net_init(rt_ubase_t *mmio_base, rt_uint32_t irq);
#endif /* __VIRTIO_NET_H__ */
bsp/qemu-virt64-aarch64/driver/virtio/virtio_queue.h
-97
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@@ -1,97 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-11 GuEe-GUI the first version
*/
#ifndef __VIRTIO_QUEUE_H__
#define __VIRTIO_QUEUE_H__
#include <rtdef.h>
#define VIRTQ_DESC_F_NEXT 1 /* This marks a buffer as continuing via the next field. */
#define VIRTQ_DESC_F_WRITE 2 /* This marks a buffer as write-only (otherwise read-only). */
#define VIRTQ_DESC_F_INDIRECT 4 /* This means the buffer contains a list of buffer descriptors. */
/*
* The device uses this in used->flags to advise the driver: don't kick me
* when you add a buffer. It's unreliable, so it's simply an optimization.
*/
#define VIRTQ_USED_F_NO_NOTIFY 1
/*
* The driver uses this in avail->flags to advise the device: don't
* interrupt me when you consume a buffer. It's unreliable, so it's
* simply an optimization.
*/
#define VIRTQ_AVAIL_F_NO_INTERRUPT 1
/* Virtqueue descriptors: 16 bytes. These can chain together via "next". */
struct virtq_desc
{
rt_uint64_t addr; /* Address (guest-physical). */
rt_uint32_t len; /* Length. */
rt_uint16_t flags; /* The flags as indicated above. */
rt_uint16_t next; /* We chain unused descriptors via this, too */
};
struct virtq_avail
{
rt_uint16_t flags; /* Notifications */
rt_uint16_t idx; /* Where the driver would put the next descriptor entry in the ring (modulo the queue size) */
rt_uint16_t ring[];
/*
* Only if VIRTIO_F_RING_EVENT_IDX
* rt_uint16_t used_event;
*/
};
struct virtq_used_elem
{
rt_uint32_t id; /* Index of start of used descriptor chain. */
rt_uint32_t len; /* Total length of the descriptor chain which was written to. */
};
struct virtq_used
{
rt_uint16_t flags;
rt_uint16_t idx;
struct virtq_used_elem ring[];
/*
* Only if VIRTIO_F_RING_EVENT_IDX
* rt_uint16_t avail_event;
*/
};
struct virtq
{
rt_uint32_t num;
struct virtq_desc *desc;
struct virtq_avail *avail;
struct virtq_used *used;
/* Helper of driver */
rt_uint32_t used_idx;
rt_bool_t *free;
rt_size_t free_count;
};
#define VIRTQ_DESC_TOTAL_SIZE(ring_size) (sizeof(struct virtq_desc) * (ring_size))
/* flags, idx, used_event + ring * ring_size */
#define VIRTQ_AVAIL_TOTAL_SIZE(ring_size) (sizeof(rt_uint16_t) * 3 + sizeof(rt_uint16_t) * (ring_size))
/* flags, idx, avail_event + ring * ring_size */
#define VIRTQ_USED_TOTAL_SIZE(ring_size) (sizeof(rt_uint16_t) * 3 + sizeof(struct virtq_used_elem) * (ring_size))
#define VIRTQ_AVAIL_RES_SIZE (sizeof(rt_uint16_t)) /* used_event */
#define VIRTQ_USED_RES_SIZE (sizeof(rt_uint16_t)) /* avail_event */
#define VIRTQ_INVALID_DESC_ID RT_UINT16_MAX
#endif /* __VIRTIO_QUEUE_H__ */
bsp/qemu-virt64-aarch64/driver/Kconfig → bsp/qemu-virt64-aarch64/drivers/Kconfig
+14 -1
View File
@@ -1,4 +1,8 @@
menu "AARCH64 qemu virt64 configs"
menuconfig BSP_SUPPORT_FPU
bool "Using Float"
default y
menuconfig BSP_USING_UART
bool "Using UART"
@@ -11,7 +15,6 @@ menu "AARCH64 qemu virt64 configs"
default y
endif
menuconfig BSP_USING_RTC
bool "Using RTC"
select RT_USING_RTC
@@ -31,22 +34,32 @@ menu "AARCH64 qemu virt64 configs"
config BSP_USING_VIRTIO_BLK
bool "Using VirtIO BLK"
select RT_USING_VIRTIO
select RT_USING_VIRTIO_BLK
default y
config BSP_USING_VIRTIO_NET
bool "Using VirtIO NET"
select RT_USING_VIRTIO
select RT_USING_VIRTIO_NET
default y
config BSP_USING_VIRTIO_CONSOLE
bool "Using VirtIO Console"
select RT_USING_VIRTIO
select RT_USING_VIRTIO_CONSOLE
default y
config BSP_USING_VIRTIO_GPU
bool "Using VirtIO GPU"
select RT_USING_VIRTIO
select RT_USING_VIRTIO_GPU
default y
config BSP_USING_VIRTIO_INPUT
bool "Using VirtIO Input"
select RT_USING_VIRTIO
select RT_USING_VIRTIO_INPUT
default y
config BSP_USING_GIC
bsp/qemu-virt64-aarch64/driver/virtio/SConscript → bsp/qemu-virt64-aarch64/drivers/SConscript
+1 -1
View File
@@ -3,7 +3,7 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
bsp/qemu-virt64-aarch64/drivers/board.c
+120
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@@ -0,0 +1,120 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-11-20 Bernard the first version
* 2018-11-22 Jesven add rt_hw_spin_lock
* add rt_hw_spin_unlock
* add smp ipi init
*/
#include <rthw.h>
#include <rtthread.h>
#include <mmu.h>
#ifdef RT_USING_SMART
#include <page.h>
#include <lwp_arch.h>
#endif
#include "board.h"
#ifdef RT_USING_FDT
#include "interrupt.h"
#include "dtb_node.h"
#include <psci_api.h>
#include <cpu.h>
#endif
#ifdef RT_USING_SMART
struct mem_desc platform_mem_desc[] = {
{KERNEL_VADDR_START, KERNEL_VADDR_START + 0x0fffffff, KERNEL_VADDR_START + PV_OFFSET, NORMAL_MEM}
};
#else
struct mem_desc platform_mem_desc[] =
{
{0x40000000, 0x80000000 - 1, 0x40000000, NORMAL_MEM},
// {PL031_RTC_BASE, PL031_RTC_BASE + 0x1000 - 1, PL031_RTC_BASE, DEVICE_MEM},
// {PL061_GPIO_BASE, PL061_GPIO_BASE + 0x1000 - 1, PL061_GPIO_BASE, DEVICE_MEM},
{PL011_UART0_BASE, PL011_UART0_BASE + ARCH_SECTION_SIZE - 1, PL011_UART0_BASE, DEVICE_MEM},
{VIRTIO_MMIO_BASE, RT_ALIGN(VIRTIO_MMIO_BASE + VIRTIO_MAX_NR * VIRTIO_MMIO_SIZE, ARCH_SECTION_SIZE) - 1, VIRTIO_MMIO_BASE, DEVICE_MEM},
#ifdef BSP_USING_GICV2
{GIC_PL390_DISTRIBUTOR_PPTR, GIC_PL390_DISTRIBUTOR_PPTR + ARCH_SECTION_SIZE - 1, GIC_PL390_DISTRIBUTOR_PPTR, DEVICE_MEM},
#endif
#ifdef BSP_USING_GICV3
{GIC_PL500_DISTRIBUTOR_PPTR, GIC_PL500_DISTRIBUTOR_PPTR + 0x1000 - 1, GIC_PL500_DISTRIBUTOR_PPTR, DEVICE_MEM},
{GIC_PL500_REDISTRIBUTOR_PPTR, GIC_PL500_REDISTRIBUTOR_PPTR + 0xf60000 - 1, GIC_PL500_REDISTRIBUTOR_PPTR, DEVICE_MEM},
#endif
};
#endif
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]);
void idle_wfi(void)
{
asm volatile ("wfi");
}
/**
* This function will initialize board
*/
rt_mmu_info mmu_info;
extern size_t MMUTable[];
#ifdef RT_USING_SMART
rt_region_t init_page_region = {
PAGE_START,
PAGE_END,
};
#endif
void rt_hw_board_init(void)
{
#ifdef RT_USING_SMART
rt_page_init(init_page_region);
rt_hw_mmu_setup(platform_mem_desc, platform_mem_desc_size);
rt_hw_mmu_map_init(&mmu_info, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
arch_kuser_init(&mmu_info, (void*)0xffffffffffff0000);
#else
rt_hw_mmu_setup(platform_mem_desc, platform_mem_desc_size);
rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0);
rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000);
#endif
/* initialize hardware interrupt */
rt_hw_interrupt_init();
/* initialize system heap */
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
/* support debug feature before components init */
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#ifdef RT_USING_FDT
// TODO 0x44000000 should be replace by a variable
void * fdt_start = (void *)0x44000000 - PV_OFFSET;
device_tree_setup(fdt_start);
#ifdef RT_USING_SMP
rt_hw_cpu_init();
#else
psci_init();
#endif /* RT_USING_SMP */
#endif
rt_components_board_init();
rt_thread_idle_sethook(idle_wfi);
#ifdef RT_USING_SMP
/* install IPI handle */
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
#endif
}
bsp/qemu-virt64-aarch64/drivers/board.h
+36
View File
@@ -0,0 +1,36 @@
/*
* File : board.h
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-06 Bernard the first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <virt.h>
extern unsigned char __bss_start;
extern unsigned char __bss_end;
#define HEAP_BEGIN (void *)&__bss_end
#ifdef RT_USING_SMART
#define HEAP_END (rt_size_t)(KERNEL_VADDR_START + 64 * 1024 * 1024)
#define PAGE_START HEAP_END + 1 * 1024 * 1024
#define PAGE_END ((rt_size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
#else
#define HEAP_END ((void *)HEAP_BEGIN + 64 * 1024 * 1024)
#define KERNEL_VADDR_START 0x40000000
#define PV_OFFSET 0
#endif
void rt_hw_board_init(void);
int rt_hw_uart_init(void);
#endif
bsp/qemu-virt64-aarch64/driver/drv_gpio.c → bsp/qemu-virt64-aarch64/drivers/drv_gpio.c
+8 -2
View File
@@ -39,14 +39,16 @@ static struct pl061
void *args[PL061_GPIO_NR];
} _pl061;
static rt_ubase_t pl061_gpio_base = PL061_GPIO_BASE;
rt_inline rt_uint8_t pl061_read8(rt_ubase_t offset)
{
return HWREG8(PL061_GPIO_BASE + offset);
return HWREG8(pl061_gpio_base + offset);
}
rt_inline void pl061_write8(rt_ubase_t offset, rt_uint8_t value)
{
HWREG8(PL061_GPIO_BASE + offset) = value;
HWREG8(pl061_gpio_base + offset) = value;
}
static void pl061_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
@@ -303,6 +305,10 @@ int rt_hw_gpio_init(void)
rt_spin_lock_init(&_pl061.spinlock);
#endif
#ifdef RT_USING_LWP
pl061_gpio_base = (rt_size_t)rt_ioremap((void *)pl061_gpio_base, PL061_GPIO_SIZE);
#endif
rt_device_pin_register("gpio", &ops, RT_NULL);
rt_hw_interrupt_install(PL061_GPIO_IRQNUM, rt_hw_gpio_isr, RT_NULL, "gpio");
rt_hw_interrupt_umask(PL061_GPIO_IRQNUM);
bsp/qemu-virt64-aarch64/driver/drv_gpio.h → bsp/qemu-virt64-aarch64/drivers/drv_gpio.h
View File
File renamed without changes.
bsp/qemu-virt64-aarch64/drivers/drv_rtc.c
+123
View File
@@ -0,0 +1,123 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-11-4 GuEe-GUI first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <sys/time.h>
#include <board.h>
#include "drv_rtc.h"
#ifdef BSP_USING_RTC
#define RTC_DR 0x00 /* data read register */
#define RTC_MR 0x04 /* match register */
#define RTC_LR 0x08 /* data load register */
#define RTC_CR 0x0c /* control register */
#define RTC_IMSC 0x10 /* interrupt mask and set register */
#define RTC_RIS 0x14 /* raw interrupt status register */
#define RTC_MIS 0x18 /* masked interrupt status register */
#define RTC_ICR 0x1c /* interrupt clear register */
#define RTC_CR_OPEN 1
#define RTC_CR_CLOSE 0
static struct hw_rtc_device rtc_device;
static rt_ubase_t pl031_rtc_base = PL031_RTC_BASE;
rt_inline rt_uint32_t pl031_read32(rt_ubase_t offset)
{
return (*((volatile unsigned int *)(pl031_rtc_base + offset)));
}
rt_inline void pl031_write32(rt_ubase_t offset, rt_uint32_t value)
{
(*((volatile unsigned int *)(pl031_rtc_base + offset))) = value;
}
static rt_err_t pl031_rtc_init(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t pl031_rtc_open(rt_device_t dev, rt_uint16_t oflag)
{
pl031_write32(RTC_CR, RTC_CR_OPEN);
return RT_EOK;
}
static rt_err_t pl031_rtc_close(rt_device_t dev)
{
pl031_write32(RTC_CR, RTC_CR_CLOSE);
return RT_EOK;
}
static rt_err_t pl031_rtc_control(rt_device_t dev, int cmd, void *args)
{
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
*(rt_uint32_t *)args = pl031_read32(RTC_DR);
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
pl031_write32(RTC_LR, *(time_t *)args);
break;
default:
return RT_EINVAL;
}
return RT_EOK;
}
static rt_size_t pl031_rtc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
pl031_rtc_control(dev, RT_DEVICE_CTRL_RTC_GET_TIME, buffer);
return size;
}
static rt_size_t pl031_rtc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
pl031_rtc_control(dev, RT_DEVICE_CTRL_RTC_SET_TIME, (void *)buffer);
return size;
}
const static struct rt_device_ops pl031_rtc_ops =
{
.init = pl031_rtc_init,
.open = pl031_rtc_open,
.close = pl031_rtc_close,
.read = pl031_rtc_read,
.write = pl031_rtc_write,
.control = pl031_rtc_control
};
int rt_hw_rtc_init(void)
{
#ifdef RT_USING_LWP
pl031_rtc_base = (rt_size_t)rt_ioremap((void *)pl031_rtc_base, PL031_RTC_SIZE);
#endif
rt_memset(&rtc_device, 0, sizeof(rtc_device));
rtc_device.device.type = RT_Device_Class_RTC;
rtc_device.device.rx_indicate = RT_NULL;
rtc_device.device.tx_complete = RT_NULL;
rtc_device.device.ops = &pl031_rtc_ops;
rtc_device.device.user_data = RT_NULL;
/* register a rtc device */
rt_device_register(&rtc_device.device, "rtc", RT_DEVICE_FLAG_RDWR);
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
#endif /* BSP_USING_RTC */
bsp/qemu-virt64-aarch64/driver/drv_rtc.h → bsp/qemu-virt64-aarch64/drivers/drv_rtc.h
View File
File renamed without changes.
bsp/qemu-virt64-aarch64/drivers/drv_timer.c
+46
View File
@@ -0,0 +1,46 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-22 Jesven first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <stdint.h>
#include "cp15.h"
#include "board.h"
#include "gtimer.h"
#define TIMER_IRQ 30
static rt_uint64_t timerStep = 0;
static void rt_hw_timer_isr(int vector, void *param)
{
rt_hw_set_gtimer_val(timerStep);
rt_tick_increase();
}
void rt_hw_timer_enable(void)
{
rt_hw_set_gtimer_val(timerStep);
rt_hw_interrupt_umask(TIMER_IRQ);
rt_hw_gtimer_enable();
}
int rt_hw_timer_init(void)
{
rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
__ISB();
timerStep = rt_hw_get_gtimer_frq();
__DSB();
timerStep /= RT_TICK_PER_SECOND;
rt_hw_timer_enable();
return 0;
}
INIT_BOARD_EXPORT(rt_hw_timer_init);
bsp/qemu-virt64-aarch64/drivers/drv_timer.h
+16
View File
@@ -0,0 +1,16 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-22 Jesven first version
*/
#ifndef DRV_TIMER_H__
#define DRV_TIMER_H__
void timer_init(int timer, unsigned int preload);
#endif
bsp/qemu-virt64-aarch64/driver/drv_uart.c → bsp/qemu-virt64-aarch64/drivers/drv_uart.c
+45 -49
View File
@@ -1,39 +1,46 @@
/*
* serial.c UART driver
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/5/5 Bernard The first version
* 2013-03-30 Bernard the first verion
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#define PL011_UARTDR 0x000
#define PL011_UARTFR 0x018
#define PL011_UARTFR_TXFF_BIT 5
unsigned int readl(volatile void *addr)
{
return *(volatile unsigned int *)addr;
}
void writel(unsigned int v, volatile void *addr)
{
*(volatile unsigned int *)addr = v;
}
#include "mmu.h"
struct hw_uart_device
{
rt_ubase_t hw_base;
rt_uint32_t irqno;
rt_size_t hw_base;
rt_size_t irqno;
};
#define UART_DR(base) __REG32(base + 0x00)
#define UART_FR(base) __REG32(base + 0x18)
#define UART_CR(base) __REG32(base + 0x30)
#define UART_IMSC(base) __REG32(base + 0x38)
#define UART_ICR(base) __REG32(base + 0x44)
#define UARTFR_RXFE 0x10
#define UARTFR_TXFF 0x20
#define UARTIMSC_RXIM 0x10
#define UARTIMSC_TXIM 0x20
#define UARTICR_RXIC 0x10
#define UARTICR_TXIC 0x20
static void rt_hw_uart_isr(int irqno, void *param)
{
struct rt_serial_device *serial = (struct rt_serial_device *)param;
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
return RT_EOK;
@@ -42,28 +49,22 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct hw_uart_device *uart;
uint32_t val;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
val = readl((volatile void *)(uart->hw_base + 0x38));
val &= ~0x10;
writel(val, (volatile void *)(uart->hw_base + 0x38));
rt_hw_interrupt_mask(uart->irqno);
break;
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
UART_IMSC(uart->hw_base) &= ~UARTIMSC_RXIM;
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
val = readl((volatile void *)(uart->hw_base + 0x38));
val |= 0x10;
writel(val, (volatile void *)(uart->hw_base + 0x38));
rt_hw_interrupt_umask(uart->irqno);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
UART_IMSC(uart->hw_base) |= UARTIMSC_RXIM;
rt_hw_interrupt_umask(uart->irqno);
break;
}
return RT_EOK;
@@ -76,26 +77,24 @@ static int uart_putc(struct rt_serial_device *serial, char c)
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
while (readl((volatile void *)(uart->hw_base + PL011_UARTFR)) & (1 << PL011_UARTFR_TXFF_BIT))
{
}
writel(c, (volatile void *)( uart->hw_base + PL011_UARTDR));
while (UART_FR(uart->hw_base) & UARTFR_TXFF);
UART_DR(uart->hw_base) = c;
return 1;
}
static int uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
int ch;
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
if (!(readl((volatile void *)(uart->hw_base + 0x18)) & (1 << 4)))
ch = -1;
if (!(UART_FR(uart->hw_base) & UARTFR_RXFE))
{
ch = readl((volatile void *)(uart->hw_base));
ch = UART_DR(uart->hw_base) & 0xff;
}
return ch;
@@ -109,12 +108,6 @@ static const struct rt_uart_ops _uart_ops =
uart_getc,
};
static void rt_hw_uart_isr(int irqno, void *param)
{
struct rt_serial_device *serial = (struct rt_serial_device*)param;
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
#ifdef RT_USING_UART0
/* UART device driver structure */
static struct hw_uart_device _uart0_device =
@@ -131,6 +124,7 @@ int rt_hw_uart_init(void)
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef RT_USING_UART0
_uart0_device.hw_base = (rt_size_t)rt_ioremap((void*)_uart0_device.hw_base, PL011_UART0_SIZE);
uart = &_uart0_device;
_serial0.ops = &_uart_ops;
@@ -138,9 +132,11 @@ int rt_hw_uart_init(void)
/* register UART1 device */
rt_hw_serial_register(&_serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
/* enable Rx and Tx of UART */
UART_CR(uart->hw_base) = (1 << 0) | (1 << 8) | (1 << 9);
#endif
return 0;
bsp/qemu-virt64-aarch64/driver/drv_uart.h → bsp/qemu-virt64-aarch64/drivers/drv_uart.h
+4 -4
View File
@@ -5,12 +5,12 @@
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
* 2013-03-30 Bernard the first verion
*/
#ifndef DRV_UART_H__
#define DRV_UART_H__
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
int rt_hw_uart_init(void);
#endif /* DRV_UART_H__ */
#endif /* __DRV_UART_H__ */
bsp/qemu-virt64-aarch64/driver/drv_virtio.c → bsp/qemu-virt64-aarch64/drivers/drv_virtio.c
+9
View File
@@ -62,6 +62,15 @@ int rt_virtio_devices_init(void)
return 0;
}
#ifdef RT_USING_LWP
mmio_base = (rt_ubase_t)rt_ioremap((void *)mmio_base, VIRTIO_MMIO_SIZE * VIRTIO_MAX_NR);
if (mmio_base == RT_NULL)
{
return -RT_ERROR;
}
#endif
for (i = 0; i < VIRTIO_MAX_NR; ++i, ++irq, mmio_base += VIRTIO_MMIO_SIZE)
{
mmio_config = (struct virtio_mmio_config *)mmio_base;
bsp/qemu-virt64-aarch64/driver/drv_virtio.h → bsp/qemu-virt64-aarch64/drivers/drv_virtio.h
View File
File renamed without changes.
bsp/qemu-virt64-aarch64/drivers/secondary_cpu.c
+36
View File
@@ -0,0 +1,36 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include <cpu.h>
#include "gic.h"
#include "interrupt.h"
#include "mmu.h"
#ifdef RT_USING_SMP
extern unsigned long MMUTable[];
void rt_hw_secondary_cpu_bsp_start(void)
{
rt_hw_spin_lock(&_cpus_lock);
rt_hw_mmu_ktbl_set((unsigned long)MMUTable);
// interrupt init
rt_hw_vector_init();
arm_gic_cpu_init(0, 0);
// local timer init
rt_system_scheduler_start();
}
#endif // SMP
bsp/qemu-virt64-aarch64/driver/virt.h → bsp/qemu-virt64-aarch64/drivers/virt.h
+18 -4
View File
@@ -13,6 +13,18 @@
#include <rtdef.h>
#ifdef RT_USING_SMART
#include <mmu.h>
#include <ioremap.h>
extern rt_mmu_info mmu_info;
#else
#define rt_ioremap(x, ...) (x)
#endif
#define __REG32(x) (*((volatile unsigned int *)(x)))
#define __REG16(x) (*((volatile unsigned short *)(x)))
/* UART */
#define PL011_UART0_BASE 0x09000000
#define PL011_UART0_SIZE 0x00001000
@@ -47,6 +59,8 @@
/* GICv2 */
#define GIC_PL390_DISTRIBUTOR_PPTR 0x08000000
#define GIC_PL390_CONTROLLER_PPTR 0x08010000
#define GIC_PL390_HYPERVISOR_BASE 0x08030000
#define GIC_PL390_VIRTUAL_CPU_BASE 0x08040000
/* GICv3 */
#define GIC_PL500_DISTRIBUTOR_PPTR GIC_PL390_DISTRIBUTOR_PPTR
@@ -55,7 +69,7 @@
#define GIC_PL500_ITS_PPTR 0x08080000
/* the basic constants and interfaces needed by gic */
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
rt_inline rt_ubase_t platform_get_gic_dist_base(void)
{
#ifdef BSP_USING_GICV2
return GIC_PL390_DISTRIBUTOR_PPTR;
@@ -64,12 +78,12 @@ rt_inline rt_uint32_t platform_get_gic_dist_base(void)
#endif
}
rt_inline rt_uint32_t platform_get_gic_redist_base(void)
rt_inline rt_ubase_t platform_get_gic_redist_base(void)
{
return GIC_PL500_REDISTRIBUTOR_PPTR;
}
rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
rt_inline rt_ubase_t platform_get_gic_cpu_base(void)
{
#ifdef BSP_USING_GICV2
return GIC_PL390_CONTROLLER_PPTR;
@@ -78,7 +92,7 @@ rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
#endif
}
rt_inline rt_uint32_t platform_get_gic_its_base(void)
rt_inline rt_ubase_t platform_get_gic_its_base(void)
{
return GIC_PL500_ITS_PPTR;
}
bsp/qemu-virt64-aarch64/link.lds
+69 -111
View File
File diff suppressed because it is too large. Load diff
bsp/qemu-virt64-aarch64/qemu-debug.bat
+9
View File
@@ -0,0 +1,9 @@
@echo off
if exist sd.bin goto run
qemu-img create -f raw sd.bin 64M
:run
qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.bin -nographic ^
-drive if=none,file=sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 ^
-netdev user,id=net0 -device virtio-net-device,netdev=net0,bus=virtio-mmio-bus.1 -s -S ^
-device virtio-serial-device -chardev socket,host=127.0.0.1,port=4321,server=on,wait=off,telnet=on,id=console0 -device virtserialport,chardev=console0
bsp/qemu-virt64-aarch64/qemu-debug.sh
+7
View File
@@ -0,0 +1,7 @@
if [ ! -f "sd.bin" ]; then
dd if=/dev/zero of=sd.bin bs=1024 count=65536
fi
qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.bin -nographic \
-drive if=none,file=sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 \
-netdev user,id=net0 -device virtio-net-device,netdev=net0,bus=virtio-mmio-bus.1 -s -S \
-device virtio-serial-device -chardev socket,host=127.0.0.1,port=4321,server=on,wait=off,telnet=on,id=console0 -device virtserialport,chardev=console0
bsp/qemu-virt64-aarch64/qemu-graphic.bat
+1 -1
View File
@@ -3,7 +3,7 @@ if exist sd.bin goto run
qemu-img create -f raw sd.bin 64M
:run
qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.elf -serial stdio ^
qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.bin -serial stdio ^
-drive if=none,file=sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 ^
-netdev user,id=net0 -device virtio-net-device,netdev=net0,bus=virtio-mmio-bus.1 ^
-device virtio-gpu-device,xres=800,yres=600,bus=virtio-mmio-bus.2 ^
bsp/qemu-virt64-aarch64/qemu-graphic.sh
+1 -1
View File
@@ -1,7 +1,7 @@
if [ ! -f "sd.bin" ]; then
dd if=/dev/zero of=sd.bin bs=1024 count=65536
fi
qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.elf -serial stdio \
qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.bin -serial stdio \
-drive if=none,file=sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 \
-netdev user,id=net0 -device virtio-net-device,netdev=net0,bus=virtio-mmio-bus.1 \
-device virtio-gpu-device,xres=800,yres=600,bus=virtio-mmio-bus.2 \
bsp/qemu-virt64-aarch64/qemu.sh
Regular → Executable
+1 -1
View File
@@ -1,7 +1,7 @@
if [ ! -f "sd.bin" ]; then
dd if=/dev/zero of=sd.bin bs=1024 count=65536
fi
qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.elf -nographic \
qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.bin -nographic \
-drive if=none,file=sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 \
-netdev user,id=net0 -device virtio-net-device,netdev=net0,bus=virtio-mmio-bus.1 \
-device virtio-serial-device -chardev socket,host=127.0.0.1,port=4321,server=on,wait=off,telnet=on,id=console0 -device virtserialport,chardev=console0
bsp/qemu-virt64-aarch64/rtconfig.h
+43 -88
View File
File diff suppressed because it is too large. Load diff
bsp/qemu-virt64-aarch64/rtconfig.py
+19 -31
View File
@@ -3,31 +3,14 @@ import os
# toolchains options
ARCH ='aarch64'
CPU ='cortex-a'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.join(os.getcwd(), '..', '..')
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery,
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:/Program Files/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
CROSS_TOOL = 'gcc'
PLATFORM = 'gcc'
EXEC_PATH = os.getenv('RTT_EXEC_PATH') or '/usr/bin'
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'aarch64-none-elf-'
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
@@ -37,21 +20,26 @@ if PLATFORM == 'gcc':
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
STRIP = PREFIX + 'strip'
CFPFLAGS = ' '
AFPFLAGS = ' '
DEVICE = ' -march=armv8-a -mtune=cortex-a53 -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
DEVICE = ' -g -march=armv8-a -mtune=cortex-a53'
CFLAGS = DEVICE + ' -Wall -fdiagnostics-color=always'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall'
CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99'
AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -O0 -gdwarf-2'
CXXFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
CFLAGS += ' -Os'
CXXFLAGS += ' -Os'
CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
bsp/raspberry-pi/raspi3-64/.config
+15 -176
View File
File diff suppressed because it is too large. Load diff
bsp/raspberry-pi/raspi3-64/Kconfig
+5
View File
@@ -25,6 +25,11 @@ config BCM2836_SOC
select RT_USING_USER_MAIN
select ARCH_CPU_64BIT
select RT_USING_CACHE
select SOC_BCM283x
default y
config SOC_BCM283x
bool
default y
source "driver/Kconfig"
bsp/raspberry-pi/raspi3-64/driver/board.c
+4 -2
View File
@@ -51,14 +51,16 @@ void rt_hw_timer_isr(int vector, void *parameter)
rt_tick_increase();
}
rt_uint8_t core_timer_flag;
void rt_hw_timer_init(void)
{
rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
rt_hw_interrupt_umask(IRQ_ARM_TIMER);
#ifdef BSP_USING_CORETIMER
__ISB();
rt_hw_isb();
timer_step = rt_hw_get_gtimer_frq();
__DSB();
rt_hw_dsb();
timer_step /= RT_TICK_PER_SECOND;
rt_hw_gtimer_enable();
bsp/raspberry-pi/raspi3-64/driver/board.h
+5
View File
@@ -20,6 +20,11 @@ extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
#ifndef RT_USING_SMART
#define PV_OFFSET 0
#define KERNEL_VADDR_START 0
#endif
void rt_hw_board_init(void);
#endif
bsp/raspberry-pi/raspi3-64/driver/drv_fb.c
+3 -2
View File
@@ -14,6 +14,7 @@
#include "mbox.h"
#include "drv_fb.h"
#include "mmu.h"
#include "cache.h"
#define LCD_WIDTH (800)
#define LCD_HEIGHT (480)
@@ -299,9 +300,9 @@ int hdmi_fb_init(void)
_hdmi.pitch = 0;
_hdmi.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB888;
rt_hw_mmu_map((unsigned long)_hdmi.fb, 0x200000, DEVICE_MEM);
// rt_hw_mmu_map(&mmu_info, (unsigned long)_hdmi.fb, (void *)0x200000, DEVICE_MEM);
rt_hw_dcache_invalidate_range((unsigned long)_hdmi.fb,LCD_WIDTH * LCD_HEIGHT * 3);
rt_hw_cpu_dcache_invalidate((unsigned long)_hdmi.fb,LCD_WIDTH * LCD_HEIGHT * 3);
//rt_kprintf("_hdmi.fb is %p\n", _hdmi.fb);
rt_hdmi_fb_device_init(&_hdmi, "lcd");
bsp/raspberry-pi/raspi3-64/rtconfig.h
+3 -16
View File
@@ -55,7 +55,9 @@
#define RT_VER_NUM 0x50000
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
@@ -204,11 +206,6 @@
/* peripheral libraries and drivers */
/* sensors drivers */
/* touch drivers */
/* Kendryte SDK */
@@ -216,9 +213,6 @@
/* AI packages */
/* Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
@@ -262,15 +256,8 @@
/* Uncategorized */
/* Privated Packages of RealThread */
/* Network Utilities */
/* RT-Thread Smart */
#define BCM2836_SOC
#define SOC_BCM283x
/* Hardware Drivers Config */
bsp/raspberry-pi/raspi3-64/rtconfig.py
+2 -2
View File
@@ -23,7 +23,7 @@ BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'aarch64-none-elf-'
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
@@ -35,7 +35,7 @@ if PLATFORM == 'gcc':
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -march=armv8-a -mtune=cortex-a53'
CFLAGS = DEVICE + ' -Wall'
CFLAGS = DEVICE + ' -Wall -Wno-cpp'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
bsp/raspberry-pi/raspi4-32/rtconfig.py
+2 -2
View File
@@ -24,7 +24,7 @@ if os.getenv('RTT_EXEC_PATH'):
if PLATFORM == 'gcc':
# toolchains
# PREFIX = 'arm-none-eabi-'
PREFIX = 'arm-none-eabi-'
PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
@@ -36,7 +36,7 @@ if PLATFORM == 'gcc':
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -march=armv8-a -mtune=cortex-a72'
CFLAGS = DEVICE + ' -Wall'
CFLAGS = DEVICE + ' -Wall -Wno-cpp'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
bsp/raspberry-pi/raspi4-64/driver/board.h
+5
View File
@@ -20,6 +20,11 @@ extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
#ifndef RT_USING_SMART
#define PV_OFFSET 0
#define KERNEL_VADDR_START 0
#endif
void rt_hw_board_init(void);
#endif
bsp/raspberry-pi/raspi4-64/rtconfig.py
+2 -2
View File
@@ -23,7 +23,7 @@ BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'aarch64-none-elf-'
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
@@ -35,7 +35,7 @@ if PLATFORM == 'gcc':
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -march=armv8-a -mtune=cortex-a72'
CFLAGS = DEVICE + ' -Wall'
CFLAGS = DEVICE + ' -Wall -Wno-cpp'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
bsp/rockchip/rk3568/driver/board.c
+2 -2
View File
@@ -51,7 +51,7 @@ void rt_hw_board_init(void)
rt_thread_idle_sethook(idle_wfi);
arm_psci_init(PSCI_METHOD_SMC, RT_NULL, RT_NULL);
// TODO porting to FDT-driven PSCI: arm_psci_init(PSCI_METHOD_SMC, RT_NULL, RT_NULL);
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
/* set console device */
@@ -77,7 +77,7 @@ void rt_hw_board_init(void)
void reboot(void)
{
arm_psci_system_reboot();
// TODO poring to FDT to use new PSCI: arm_psci_system_reboot();
}
MSH_CMD_EXPORT(reboot, reboot...);
bsp/rockchip/rk3568/driver/board.h
+5
View File
@@ -19,6 +19,11 @@ extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void *)&__bss_end
#define RT_HW_HEAP_END (void *)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
#ifndef RT_USING_SMART
#define PV_OFFSET 0
#define KERNEL_VADDR_START 0
#endif
void rt_hw_board_init(void);
#endif /* __BOARD_H__ */
bsp/rockchip/rk3568/driver/rk3568.h
+2
View File
@@ -11,6 +11,8 @@
#ifndef __RK3568_H__
#define __RK3568_H__
#include <rtthread.h>
/* UART */
#define UART_MMIO_BASE 0xfe650000
#define UART0_MMIO_BASE 0xfdd50000
bsp/rockchip/rk3568/rtconfig.py
+3 -3
View File
@@ -23,7 +23,7 @@ BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'aarch64-none-elf-'
PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
@@ -34,8 +34,8 @@ if PLATFORM == 'gcc':
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -g -march=armv8-a -mtune=cortex-a55'
CFLAGS = DEVICE + ' -Wall'
DEVICE = ' -g -march=armv8-a -mtune=cortex-a53'
CFLAGS = DEVICE + ' -Wall -Wno-cpp'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.c
+486 -486
View File
File diff suppressed because it is too large. Load diff
bsp/wch/risc-v/Libraries/ch32_drivers/drv_hwtimer.h
+148 -148
View File
File diff suppressed because it is too large. Load diff
bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.c
+963 -963
View File
File diff suppressed because it is too large. Load diff
bsp/wch/risc-v/Libraries/ch32_drivers/drv_pwm.h
+40 -40
View File
@@ -1,40 +1,40 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 MXH the first version
*/
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include <rtthread.h>
#ifdef BSP_USING_PWM
#include "ch32v30x_tim.h"
#include <drivers/rt_drv_pwm.h>
#include <drivers/hwtimer.h>
#include <board.h>
#ifndef ITEM_NUM
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
#endif
#define MAX_COUNTER 65535
#define MIN_COUNTER 2
#define MIN_PULSE 2
#define FLAG_NOT_INIT 0xFF
struct rtdevice_pwm_device
{
struct rt_device_pwm parent;
TIM_TypeDef* periph;
rt_uint8_t channel[4];
char* name;
};
#endif/* BSP_USING_PWM */
#endif/* __DRV_PWM_H__ */
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 MXH the first version
*/
#ifndef __DRV_PWM_H__
#define __DRV_PWM_H__
#include <rtthread.h>
#ifdef BSP_USING_PWM
#include "ch32v30x_tim.h"
#include <drivers/rt_drv_pwm.h>
#include <drivers/hwtimer.h>
#include <board.h>
#ifndef ITEM_NUM
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
#endif
#define MAX_COUNTER 65535
#define MIN_COUNTER 2
#define MIN_PULSE 2
#define FLAG_NOT_INIT 0xFF
struct rtdevice_pwm_device
{
struct rt_device_pwm parent;
TIM_TypeDef* periph;
rt_uint8_t channel[4];
char* name;
};
#endif/* BSP_USING_PWM */
#endif/* __DRV_PWM_H__ */
components/drivers/fdt/inc/dtb_node.h
+2 -1
View File
@@ -8,6 +8,7 @@
#include "libfdt_env.h"
#include <rtthread.h>
#include <stdint.h>
//#define RT_DTB_DEBUG
#ifdef RT_DTB_DEBUG
@@ -326,7 +327,7 @@ struct dtb_node *dtb_node_first_subnode(const struct dtb_node *node);
struct dtb_node *dtb_node_next_subnode(const struct dtb_node *node);
struct dtb_node *dtb_node_get_parent(const struct dtb_node *node);
const char *dtb_node_get_name(const struct dtb_node *node);
struct dtb_node *dtb_node_get_by_phandle(uint phandle);
struct dtb_node *dtb_node_get_by_phandle(uint32_t phandle);
int dtb_node_read_size(const struct dtb_node *node, const char *propname);
size_t dtb_node_get_addr_index(const struct dtb_node *node, int index);
size_t dtb_node_get_addr(const struct dtb_node *node);
components/drivers/fdt/libfdt/fdt.h
+49 -35
View File
@@ -1,3 +1,13 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-12-20 RT-Thread the first version
*/
#ifndef _FDT_H
#define _FDT_H
/*
@@ -54,58 +64,62 @@
#ifndef __ASSEMBLY__
#include <errno.h>
#include <unistd.h>
#include <fcntl.h>
struct fdt_header {
fdt32_t magic; /* magic word FDT_MAGIC */
fdt32_t totalsize; /* total size of DT block */
fdt32_t off_dt_struct; /* offset to structure */
fdt32_t off_dt_strings; /* offset to strings */
fdt32_t off_mem_rsvmap; /* offset to memory reserve map */
fdt32_t version; /* format version */
fdt32_t last_comp_version; /* last compatible version */
fdt32_t magic; /* magic word FDT_MAGIC */
fdt32_t totalsize; /* total size of DT block */
fdt32_t off_dt_struct; /* offset to structure */
fdt32_t off_dt_strings; /* offset to strings */
fdt32_t off_mem_rsvmap; /* offset to memory reserve map */
fdt32_t version; /* format version */
fdt32_t last_comp_version; /* last compatible version */
/* version 2 fields below */
fdt32_t boot_cpuid_phys; /* Which physical CPU id we're
booting on */
/* version 3 fields below */
fdt32_t size_dt_strings; /* size of the strings block */
/* version 2 fields below */
fdt32_t boot_cpuid_phys; /* Which physical CPU id we're
booting on */
/* version 3 fields below */
fdt32_t size_dt_strings; /* size of the strings block */
/* version 17 fields below */
fdt32_t size_dt_struct; /* size of the structure block */
/* version 17 fields below */
fdt32_t size_dt_struct; /* size of the structure block */
};
struct fdt_reserve_entry {
fdt64_t address;
fdt64_t size;
fdt64_t address;
fdt64_t size;
};
struct fdt_node_header {
fdt32_t tag;
char name[0];
fdt32_t tag;
char name[0];
};
struct fdt_property {
fdt32_t tag;
fdt32_t len;
fdt32_t nameoff;
char data[0];
fdt32_t tag;
fdt32_t len;
fdt32_t nameoff;
char data[0];
};
#endif /* !__ASSEMBLY */
#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
#define FDT_TAGSIZE sizeof(fdt32_t)
#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
#define FDT_TAGSIZE sizeof(fdt32_t)
#define FDT_BEGIN_NODE 0x1 /* Start node: full name */
#define FDT_END_NODE 0x2 /* End node */
#define FDT_PROP 0x3 /* Property: name off,
size, content */
#define FDT_NOP 0x4 /* nop */
#define FDT_END 0x9
#define FDT_BEGIN_NODE 0x1 /* Start node: full name */
#define FDT_END_NODE 0x2 /* End node */
#define FDT_PROP 0x3 /* Property: name off,
size, content */
#define FDT_NOP 0x4 /* nop */
#define FDT_END 0x9
#define FDT_V1_SIZE (7*sizeof(fdt32_t))
#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t))
#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t))
#define FDT_V16_SIZE FDT_V3_SIZE
#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t))
#define FDT_V1_SIZE (7*sizeof(fdt32_t))
#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t))
#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t))
#define FDT_V16_SIZE FDT_V3_SIZE
#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t))
#endif /* _FDT_H */
components/drivers/tty/pty.c
+1 -2
View File
@@ -308,7 +308,7 @@ static int ptmx_register(void)
level = rt_hw_interrupt_disable();
RT_ASSERT(ptm_drv->init_flag == TTY_INIT_FLAG_NONE);
device = &(ptm_drv->parent);
device->type = RT_Device_Class_Char;
@@ -348,7 +348,6 @@ static int ptmx_register(void)
}
tty_initstack(ptm_drv->head);
rt_spin_lock_init(&ptm_drv->spinlock);
ptm_drv->pgrp = -1;
ptm_drv->session = -1;
ptm_drv->foreground = RT_NULL;
libcpu/Kconfig
+2
View File
@@ -82,6 +82,7 @@ config ARCH_ARM_MMU
if RT_USING_SMART
config KERNEL_VADDR_START
hex "The virtural address of kernel start"
default 0xffff000000000000 if ARCH_ARMV8
default 0xc0000000 if ARCH_ARM
default 0x80000000 if ARCH_RISCV
depends on ARCH_MM_MMU
@@ -159,6 +160,7 @@ config RT_BACKTRACE_FUNCTION_NAME
config ARCH_ARMV8
bool
select ARCH_ARM
select ARCH_ARM_MMU
config ARCH_MIPS
bool
libcpu/aarch64/common/armv8.h
+42 -45
View File
@@ -1,67 +1,64 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
* 2021-12-28 GuEe-GUI add fpu support
*/
#ifndef __ARMV8_H__
#define __ARMV8_H__
#include <rtdef.h>
/* the exception stack without VFP registers */
struct rt_hw_exp_stack
{
unsigned long long pc;
unsigned long long spsr;
unsigned long long x30;
unsigned long long xzr;
unsigned long long fpcr;
unsigned long long fpsr;
unsigned long long x28;
unsigned long long x29;
unsigned long long x26;
unsigned long long x27;
unsigned long long x24;
unsigned long long x25;
unsigned long long x22;
unsigned long long x23;
unsigned long long x20;
unsigned long long x21;
unsigned long long x18;
unsigned long long x19;
unsigned long long x16;
unsigned long long x17;
unsigned long long x14;
unsigned long long x15;
unsigned long long x12;
unsigned long long x13;
unsigned long long x10;
unsigned long long x11;
unsigned long long x8;
unsigned long long x9;
unsigned long long x6;
unsigned long long x7;
unsigned long long x4;
unsigned long long x5;
unsigned long long x2;
unsigned long long x3;
unsigned long long x0;
unsigned long long x1;
unsigned long pc;
unsigned long cpsr;
unsigned long sp_el0;
unsigned long x30;
unsigned long fpcr;
unsigned long fpsr;
unsigned long x28;
unsigned long x29;
unsigned long x26;
unsigned long x27;
unsigned long x24;
unsigned long x25;
unsigned long x22;
unsigned long x23;
unsigned long x20;
unsigned long x21;
unsigned long x18;
unsigned long x19;
unsigned long x16;
unsigned long x17;
unsigned long x14;
unsigned long x15;
unsigned long x12;
unsigned long x13;
unsigned long x10;
unsigned long x11;
unsigned long x8;
unsigned long x9;
unsigned long x6;
unsigned long x7;
unsigned long x4;
unsigned long x5;
unsigned long x2;
unsigned long x3;
unsigned long x0;
unsigned long x1;
unsigned long long fpu[16];
};
#define SP_ELx ( ( unsigned long long ) 0x01 )
#define SP_EL0 ( ( unsigned long long ) 0x00 )
#define PSTATE_EL1 ( ( unsigned long long ) 0x04 )
#define PSTATE_EL2 ( ( unsigned long long ) 0x08 )
#define PSTATE_EL3 ( ( unsigned long long ) 0x0c )
#define SP_ELx ((unsigned long)0x01)
#define SP_EL0 ((unsigned long)0x00)
#define PSTATE_EL1 ((unsigned long)0x04)
#define PSTATE_EL2 ((unsigned long)0x08)
#define PSTATE_EL3 ((unsigned long)0x0c)
rt_ubase_t rt_hw_get_current_el(void);
void rt_hw_set_elx_env(void);
libcpu/aarch64/common/asm-fpu.h
+46
View File
@@ -0,0 +1,46 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-05-18 Jesven the first version
*/
.macro SAVE_FPU, reg
STR Q0, [\reg, #-0x10]!
STR Q1, [\reg, #-0x10]!
STR Q2, [\reg, #-0x10]!
STR Q3, [\reg, #-0x10]!
STR Q4, [\reg, #-0x10]!
STR Q5, [\reg, #-0x10]!
STR Q6, [\reg, #-0x10]!
STR Q7, [\reg, #-0x10]!
STR Q8, [\reg, #-0x10]!
STR Q9, [\reg, #-0x10]!
STR Q10, [\reg, #-0x10]!
STR Q11, [\reg, #-0x10]!
STR Q12, [\reg, #-0x10]!
STR Q13, [\reg, #-0x10]!
STR Q14, [\reg, #-0x10]!
STR Q15, [\reg, #-0x10]!
.endm
.macro RESTORE_FPU, reg
LDR Q15, [\reg], #0x10
LDR Q14, [\reg], #0x10
LDR Q13, [\reg], #0x10
LDR Q12, [\reg], #0x10
LDR Q11, [\reg], #0x10
LDR Q10, [\reg], #0x10
LDR Q9, [\reg], #0x10
LDR Q8, [\reg], #0x10
LDR Q7, [\reg], #0x10
LDR Q6, [\reg], #0x10
LDR Q5, [\reg], #0x10
LDR Q4, [\reg], #0x10
LDR Q3, [\reg], #0x10
LDR Q2, [\reg], #0x10
LDR Q1, [\reg], #0x10
LDR Q0, [\reg], #0x10
.endm
libcpu/aarch64/common/backtrace.c
+57
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@@ -0,0 +1,57 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-06-02 Jesven the first version
*/
#include <rtthread.h>
#include <backtrace.h>
#define BT_NESTING_MAX 100
static int unwind_frame(struct bt_frame *frame)
{
unsigned long fp = frame->fp;
if ((fp & 0x7)
#ifdef RT_USING_LWP
|| fp < KERNEL_VADDR_START
#endif
)
{
return 1;
}
frame->fp = *(unsigned long *)fp;
frame->pc = *(unsigned long *)(fp + 8);
return 0;
}
static void walk_unwind(unsigned long pc, unsigned long fp)
{
struct bt_frame frame;
unsigned long lr = pc;
int nesting = 0;
frame.fp = fp;
while (nesting < BT_NESTING_MAX)
{
rt_kprintf(" %p", (void *)lr);
if (unwind_frame(&frame))
{
break;
}
lr = frame.pc;
nesting++;
}
}
void backtrace(unsigned long pc, unsigned long lr, unsigned long fp)
{
rt_kprintf("please use: addr2line -e rtthread.elf -a -f %p", (void *)pc);
walk_unwind(lr, fp);
rt_kprintf("\n");
}
libcpu/aarch64/common/backtrace.h
+22
View File
@@ -0,0 +1,22 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-06-02 Jesven the first version
*/
#ifndef __BACKTRACE_H__
#define __BACKTRACE_H__
struct bt_frame
{
unsigned long fp;
unsigned long pc;
};
void backtrace(unsigned long pc, unsigned long lr, unsigned long fp);
#endif /*__BACKTRACE_H__*/
libcpu/aarch64/common/cache.S
+3 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -127,7 +127,8 @@ __asm_flush_dcache_range:
/* x2 <- minimal cache line size in cache system */
sub x3, x2, #1
bic x0, x0, x3
1: dc civac, x0 /* clean & invalidate data or unified cache */
1: dc civac, x0 /* clean & invalidate data or unified cache */
add x0, x0, x2
cmp x0, x1
b.lo 1b
libcpu/aarch64/common/cache.h
+23
View File
@@ -0,0 +1,23 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-12-18 RT-Thread the first version
*/
#ifndef __CACHE_H__
#define __CACHE_H__
void rt_hw_dcache_flush_all(void);
void rt_hw_dcache_invalidate_all(void);
void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
void rt_hw_cpu_dcache_clean(void *addr, int size);
void rt_hw_cpu_dcache_invalidate(unsigned long start_addr,unsigned long size);
void rt_hw_icache_invalidate_all();
void rt_hw_icache_invalidate_range(unsigned long start_addr, int size);
#endif /* __CACHE_H__ */
libcpu/aarch64/common/cache_ops.c
+53 -21
View File
@@ -1,59 +1,58 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-28 GuEe-GUI the first version
* 2019-03-29 quanzhao the first version
*/
#include <rthw.h>
#include <rtdef.h>
void __asm_invalidate_icache_all(void);
void __asm_flush_dcache_all(void);
void __asm_invalidate_dcache_all(void);
void __asm_flush_dcache_range(unsigned long start, unsigned long end);
void __asm_invalidate_dcache_range(unsigned long start, unsigned long end);
void __asm_invalidate_icache_all(void);
void __asm_invalidate_icache_range(unsigned long start, unsigned long end);
void __asm_invalidate_dcache_all(void);
void __asm_invalidate_icache_all(void);
void rt_hw_dcache_flush_all(void)
rt_inline rt_uint32_t rt_cpu_icache_line_size(void)
{
__asm_flush_dcache_all();
return 0;
}
void rt_hw_dcache_invalidate_all(void)
rt_inline rt_uint32_t rt_cpu_dcache_line_size(void)
{
__asm_invalidate_dcache_all();
return 0;
}
void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
void rt_hw_cpu_icache_invalidate(void *addr, int size)
{
__asm_flush_dcache_range(start_addr, start_addr + size);
__asm_invalidate_icache_range((unsigned long)addr, (unsigned long)addr + size);
}
void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
void rt_hw_cpu_dcache_invalidate(void *addr, int size)
{
__asm_invalidate_dcache_range(start_addr, start_addr + size);
__asm_invalidate_dcache_range((unsigned long)addr, (unsigned long)addr + size);
}
void rt_hw_icache_invalidate_all()
void rt_hw_cpu_dcache_clean(void *addr, int size)
{
__asm_invalidate_icache_all();
__asm_flush_dcache_range((unsigned long)addr, (unsigned long)addr + size);
}
void rt_hw_icache_invalidate_range(unsigned long start_addr, int size)
void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size)
{
__asm_invalidate_icache_range(start_addr, start_addr + size);
__asm_flush_dcache_range((unsigned long)addr, (unsigned long)addr + size);
}
void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
{
if (ops == RT_HW_CACHE_INVALIDATE)
{
rt_hw_icache_invalidate_range((unsigned long)addr, size);
rt_hw_cpu_icache_invalidate(addr, size);
}
}
@@ -61,10 +60,43 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
{
if (ops == RT_HW_CACHE_FLUSH)
{
rt_hw_dcache_flush_range((unsigned long)addr, size);
rt_hw_cpu_dcache_clean(addr, size);
}
else if (ops == RT_HW_CACHE_INVALIDATE)
{
rt_hw_dcache_invalidate_range((unsigned long)addr, size);
rt_hw_cpu_dcache_invalidate(addr, size);
}
}
rt_base_t rt_hw_cpu_icache_status(void)
{
return 0;
}
rt_base_t rt_hw_cpu_dcache_status(void)
{
return 0;
}
#ifdef RT_USING_LWP
#define ICACHE (1<<0)
#define DCACHE (1<<1)
#define BCACHE (ICACHE|DCACHE)
int sys_cacheflush(void *addr, int size, int cache)
{
if ((size_t)addr < KERNEL_VADDR_START && (size_t)addr + size <= KERNEL_VADDR_START)
{
if ((cache & DCACHE) != 0)
{
rt_hw_cpu_dcache_clean_and_invalidate(addr, size);
}
if ((cache & ICACHE) != 0)
{
rt_hw_cpu_icache_invalidate(addr, size);
}
return 0;
}
return -1;
}
#endif
libcpu/aarch64/common/context_gcc.S
+309 -184
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File diff suppressed because it is too large. Load diff
libcpu/aarch64/common/cp15.h
+65
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@@ -0,0 +1,65 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
*/
#ifndef __CP15_H__
#define __CP15_H__
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#define __WFI() __asm__ volatile ("wfi":::"memory")
#define __WFE() __asm__ volatile ("wfe":::"memory")
#define __SEV() __asm__ volatile ("sev")
__STATIC_FORCEINLINE void __ISB(void)
{
__asm__ volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__asm__ volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__asm__ volatile ("dmb 0xF":::"memory");
}
unsigned long rt_cpu_get_smp_id(void);
void rt_cpu_mmu_disable(void);
void rt_cpu_mmu_enable(void);
void rt_cpu_tlb_set(volatile unsigned long*);
void rt_cpu_dcache_clean_flush(void);
void rt_cpu_icache_flush(void);
void rt_cpu_vector_set_base(rt_ubase_t addr);
void rt_hw_mmu_init(void);
void rt_hw_vector_init(void);
void set_timer_counter(unsigned int counter);
void set_timer_control(unsigned int control);
#endif
libcpu/aarch64/common/cpu.c
+292 -34
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File diff suppressed because it is too large. Load diff
libcpu/aarch64/common/cpu.h
+63
View File
@@ -0,0 +1,63 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __RT_HW_CPU_H__
#define __RT_HW_CPU_H__
#include <rthw.h>
#include <rtthread.h>
#include <stdbool.h>
#ifndef RT_CPUS_NR
#define RT_CPUS_NR 1
#endif /* RT_CPUS_NR */
#ifdef RT_USING_SMP
struct cpu_ops_t
{
const char *method;
int (*cpu_init)(rt_uint32_t id);
int (*cpu_boot)(rt_uint32_t id);
void (*cpu_shutdown)(void);
};
/**
* Identifier to mark a wrong CPU MPID.
* All elements in rt_cpu_mpidr_early[] should be initialized with this value
*/
#define ID_ERROR __INT64_MAX__
extern rt_uint64_t rt_cpu_mpidr_early[];
extern struct dtb_node *_cpu_node[];
#define cpuid_to_hwid(cpuid) \
((((cpuid) >= 0) && ((cpuid) < RT_CPUS_NR)) ? rt_cpu_mpidr_early[cpuid] : ID_ERROR)
#define set_hwid(cpuid, hwid) \
((((cpuid) >= 0) && ((cpuid) < RT_CPUS_NR)) ? (rt_cpu_mpidr_early[cpuid] = (hwid)) : ID_ERROR)
#define get_cpu_node(cpuid) \
((((cpuid) >= 0) && ((cpuid) < RT_CPUS_NR)) ? _cpu_node[cpuid] : NULL)
#define set_cpu_node(cpuid, node) \
((((cpuid) >= 0) && ((cpuid) < RT_CPUS_NR)) ? (_cpu_node[cpuid] = node) : NULL)
extern int rt_hw_cpu_init();
extern int rt_hw_cpu_boot_secondary(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *cpu_ops[]);
extern void rt_hw_secondary_cpu_idle_exec(void);
extern struct cpu_ops_t cpu_ops_psci;
extern struct cpu_ops_t cpu_ops_spin_tbl;
#endif /* RT_USING_SMP */
extern void rt_hw_cpu_shutdown(void);
extern void (*system_off)(void);
#endif /* __RT_HW_CPU_H__ */
libcpu/aarch64/common/cpu_gcc.S
+73 -52
View File
@@ -1,82 +1,103 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2018-10-06 ZhaoXiaowei the first version
*/
.text
.globl rt_hw_get_current_el
rt_hw_get_current_el:
MRS X0, CurrentEL
CMP X0, 0xc
B.EQ 3f
CMP X0, 0x8
B.EQ 2f
CMP X0, 0x4
B.EQ 1f
LDR X0, =0
B 0f
MRS X0, CurrentEL
CMP X0, 0xc
B.EQ 3f
CMP X0, 0x8
B.EQ 2f
CMP X0, 0x4
B.EQ 1f
LDR X0, =0
B 0f
3:
LDR X0, =3
B 0f
LDR X0, =3
B 0f
2:
LDR X0, =2
B 0f
LDR X0, =2
B 0f
1:
LDR X0, =1
B 0f
LDR X0, =1
B 0f
0:
RET
RET
.globl rt_hw_set_current_vbar
rt_hw_set_current_vbar:
MRS X1, CurrentEL
CMP X1, 0xc
B.EQ 3f
CMP X1, 0x8
B.EQ 2f
CMP X1, 0x4
B.EQ 1f
B 0f
MRS X1, CurrentEL
CMP X1, 0xc
B.EQ 3f
CMP X1, 0x8
B.EQ 2f
CMP X1, 0x4
B.EQ 1f
B 0f
3:
MSR VBAR_EL3,X0
B 0f
MSR VBAR_EL3,X0
B 0f
2:
MSR VBAR_EL2,X0
B 0f
MSR VBAR_EL2,X0
B 0f
1:
MSR VBAR_EL1,X0
B 0f
MSR VBAR_EL1,X0
B 0f
0:
RET
RET
.globl rt_hw_set_elx_env
rt_hw_set_elx_env:
MRS X1, CurrentEL
CMP X1, 0xc
B.EQ 3f
CMP X1, 0x8
B.EQ 2f
CMP X1, 0x4
B.EQ 1f
B 0f
MRS X1, CurrentEL
CMP X1, 0xc
B.EQ 3f
CMP X1, 0x8
B.EQ 2f
CMP X1, 0x4
B.EQ 1f
B 0f
3:
MRS X0, SCR_EL3
ORR X0, X0, #0xF /* SCR_EL3.NS|IRQ|FIQ|EA */
MSR SCR_EL3, X0
B 0f
MRS X0, SCR_EL3
ORR X0, X0, #0xF /* SCR_EL3.NS|IRQ|FIQ|EA */
MSR SCR_EL3, X0
B 0f
2:
MRS X0, HCR_EL2
ORR X0, X0, #0x38
MSR HCR_EL2, X0
B 0f
MRS X0, HCR_EL2
ORR X0, X0, #0x38
MSR HCR_EL2, X0
B 0f
1:
B 0f
B 0f
0:
RET
.global rt_cpu_vector_set_base
rt_cpu_vector_set_base:
MSR VBAR_EL1,X0
RET
/**
* unsigned long rt_hw_ffz(unsigned long x)
*/
.global rt_hw_ffz
rt_hw_ffz:
mvn x1, x0
clz x0, x1
mov x1, #0x3f
sub x0, x1, x0
ret
.global rt_hw_clz
rt_hw_clz:
clz x0, x0
ret
libcpu/aarch64/common/cpu_ops_common.h
+21
View File
@@ -0,0 +1,21 @@
#ifndef __CPU_OPS_COMMON_H__
#define __CPU_OPS_COMMON_H__
#include <rthw.h>
#include <rtthread.h>
#include <mmu.h>
#include "entry_point.h"
static inline rt_uint64_t get_secondary_entry_pa(void)
{
rt_uint64_t secondary_entry_pa = (rt_uint64_t)rt_hw_mmu_v2p(&mmu_info, _secondary_cpu_entry);
if (!secondary_entry_pa)
{
LOG_E("Failed to translate 'secondary_entry_pa' to physical address");
return 0;
}
return secondary_entry_pa;
}
#endif /* __CPU_OPS_COMMON_H__ */
libcpu/aarch64/common/cpu_psci.c
+70
View File
@@ -0,0 +1,70 @@
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include <stdint.h>
#ifdef RT_USING_SMP
#define DBG_TAG "libcpu.aarch64.cpu_psci"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include "cpu_ops_common.h"
#include "cpu.h"
#include "errno.h"
#include "psci.h"
#include "psci_api.h"
static int (*_psci_init)(void) = psci_init;
static int __call_method_init()
{
int (*init)(void) = _psci_init;
_psci_init = RT_NULL;
return init();
}
/** return 0 on success, otherwise failed */
#define _call_method_init() ((_psci_init) ? __call_method_init() : 0);
static int cpu_psci_cpu_init(rt_uint32_t cpuid)
{
// init psci only once
return _call_method_init();
}
static int cpu_psci_cpu_boot(rt_uint32_t cpuid)
{
rt_uint64_t secondary_entry_pa = get_secondary_entry_pa();
if (!secondary_entry_pa)
return -1;
if (!psci_ops.cpu_on) {
LOG_E("Uninitialized psci operation");
return -1;
}
return psci_ops.cpu_on(cpuid_to_hwid(cpuid), secondary_entry_pa);
}
static void cpu_psci_cpu_shutdown()
{
psci_ops.cpu_off(cpuid_to_hwid(rt_hw_cpu_id()));
}
struct cpu_ops_t cpu_ops_psci = {
.method = "psci",
.cpu_boot = cpu_psci_cpu_boot,
.cpu_init = cpu_psci_cpu_init,
.cpu_shutdown = cpu_psci_cpu_shutdown,
};
#endif /* RT_USING_SMP */
libcpu/aarch64/common/cpu_spin_table.c
+80
View File
@@ -0,0 +1,80 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include "cpu.h"
#ifdef RT_USING_SMART
#include <ioremap.h>
#else
#define rt_ioremap(x, ...) (x)
#define rt_iounmap(x)
#endif
#define DBG_TAG "libcpu.aarch64.cpu_spin_table"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include "cpu_ops_common.h"
#ifdef RT_USING_SMP
#ifdef RT_USING_FDT
#include <dtb_node.h>
static rt_uint64_t cpu_release_addr[RT_CPUS_NR];
static int spin_table_cpu_init(rt_uint32_t cpuid)
{
struct dtb_node *cpu = get_cpu_node(cpuid);
if (!cpu)
return -1; /* uninitialized cpu node in fdt */
int size;
rt_uint64_t *phead = (rt_uint64_t*)dtb_node_get_dtb_node_property_value(cpu, "cpu-release-addr", &size);
cpu_release_addr[cpuid] = fdt64_to_cpu(*phead);
LOG_D("Using release address 0x%p for CPU %d", cpu_release_addr[cpuid], cpuid);
return 0;
}
static int spin_table_cpu_boot(rt_uint32_t cpuid)
{
rt_uint64_t secondary_entry_pa = get_secondary_entry_pa();
if (!secondary_entry_pa)
return -1;
// map release_addr to addressable place
void *rel_va = (void *)cpu_release_addr[cpuid];
#ifdef RT_USING_SMART
rel_va = rt_ioremap(rel_va, sizeof(cpu_release_addr[0]));
#endif
if (!rel_va)
{
LOG_E("IO remap failing");
return -1;
}
__asm__ volatile("str %0, [%1]" ::"rZ"(secondary_entry_pa), "r"(rel_va));
__asm__ volatile("dsb sy");
__asm__ volatile("sev");
rt_iounmap(rel_va);
return 0;
}
#endif /* RT_USING_FDT */
struct cpu_ops_t cpu_ops_spin_tbl = {
.method = "spin-table",
#ifdef RT_USING_FDT
.cpu_init = spin_table_cpu_init,
.cpu_boot = spin_table_cpu_boot,
#endif
};
#endif /* RT_USING_SMP */
libcpu/aarch64/common/cpuport.h
+7 -15
View File
@@ -5,20 +5,12 @@
*
* Change Logs:
* Date Author Notes
* 2021-09-10 GuEe-GUI first version
*/
#ifndef __CPUPORT_H__
#define __CPUPORT_H__
#ifndef CPUPORT_H__
#define CPUPORT_H__
#include <rtdef.h>
#define __WFI() __asm__ volatile ("wfi":::"memory")
#define __WFE() __asm__ volatile ("wfe":::"memory")
#define __SEV() __asm__ volatile ("sev")
#define __ISB() __asm__ volatile ("isb 0xf":::"memory")
#define __DSB() __asm__ volatile ("dsb 0xf":::"memory")
#define __DMB() __asm__ volatile ("dmb 0xf":::"memory")
#include <armv8.h>
#ifdef RT_USING_SMP
typedef union {
@@ -32,17 +24,17 @@ typedef union {
rt_inline void rt_hw_isb(void)
{
__asm__ volatile ("isb":::"memory");
asm volatile ("isb":::"memory");
}
rt_inline void rt_hw_dmb(void)
{
__asm__ volatile ("dmb sy":::"memory");
asm volatile ("dmb sy":::"memory");
}
rt_inline void rt_hw_dsb(void)
{
__asm__ volatile ("dsb sy":::"memory");
asm volatile ("dsb sy":::"memory");
}
#endif /* __CPUPORT_H__ */
#endif /*CPUPORT_H__*/
libcpu/aarch64/common/entry_point.h
+13
View File
@@ -0,0 +1,13 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __ENTRY_POINT_H__
#define __ENTRY_POINT_H__
extern void _secondary_cpu_entry(void);
#endif /* __ENTRY_POINT_H__ */
libcpu/aarch64/common/exception.c
+232
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File diff suppressed because it is too large. Load diff
libcpu/aarch64/common/gic.c
+45 -42
View File
@@ -9,7 +9,6 @@
* 2014-04-03 Grissiom many enhancements
* 2018-11-22 Jesven add rt_hw_ipi_send()
* add rt_hw_ipi_handler_install()
* 2022-03-08 GuEe-GUI add BSP bind SPI CPU self support
*/
#include <rthw.h>
@@ -17,17 +16,15 @@
#if defined(BSP_USING_GIC) && defined(BSP_USING_GICV2)
#include <gic.h>
#include <cpuport.h>
#include <board.h>
#include "gic.h"
#include "cp15.h"
struct arm_gic
{
rt_uint64_t offset; /* the first interrupt index in the vector table */
rt_uint64_t dist_hw_base; /* the base address of the gic distributor */
rt_uint64_t cpu_hw_base; /* the base address of the gic cpu interface */
rt_uint64_t cpu_hw_base; /* the base addrees of the gic cpu interface */
};
/* 'ARM_GIC_MAX_NR' is the number of cores */
@@ -35,33 +32,33 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
/** Macro to access the Generic Interrupt Controller Interface (GICC)
*/
#define GIC_CPU_CTRL(hw_base) HWREG32((hw_base) + 0x00U)
#define GIC_CPU_PRIMASK(hw_base) HWREG32((hw_base) + 0x04U)
#define GIC_CPU_BINPOINT(hw_base) HWREG32((hw_base) + 0x08U)
#define GIC_CPU_INTACK(hw_base) HWREG32((hw_base) + 0x0cU)
#define GIC_CPU_EOI(hw_base) HWREG32((hw_base) + 0x10U)
#define GIC_CPU_RUNNINGPRI(hw_base) HWREG32((hw_base) + 0x14U)
#define GIC_CPU_HIGHPRI(hw_base) HWREG32((hw_base) + 0x18U)
#define GIC_CPU_IIDR(hw_base) HWREG32((hw_base) + 0xFCU)
#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U)
#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U)
#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U)
#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU)
#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U)
#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U)
#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U)
#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU)
/** Macro to access the Generic Interrupt Controller Distributor (GICD)
*/
#define GIC_DIST_CTRL(hw_base) HWREG32((hw_base) + 0x000U)
#define GIC_DIST_TYPE(hw_base) HWREG32((hw_base) + 0x004U)
#define GIC_DIST_IGROUP(hw_base, n) HWREG32((hw_base) + 0x080U + ((n)/32U) * 4U)
#define GIC_DIST_ENABLE_SET(hw_base, n) HWREG32((hw_base) + 0x100U + ((n)/32U) * 4U)
#define GIC_DIST_ENABLE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x180U + ((n)/32U) * 4U)
#define GIC_DIST_PENDING_SET(hw_base, n) HWREG32((hw_base) + 0x200U + ((n)/32U) * 4U)
#define GIC_DIST_PENDING_CLEAR(hw_base, n) HWREG32((hw_base) + 0x280U + ((n)/32U) * 4U)
#define GIC_DIST_ACTIVE_SET(hw_base, n) HWREG32((hw_base) + 0x300U + ((n)/32U) * 4U)
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x380U + ((n)/32U) * 4U)
#define GIC_DIST_PRI(hw_base, n) HWREG32((hw_base) + 0x400U + ((n)/4U) * 4U)
#define GIC_DIST_TARGET(hw_base, n) HWREG32((hw_base) + 0x800U + ((n)/4U) * 4U)
#define GIC_DIST_CONFIG(hw_base, n) HWREG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
#define GIC_DIST_SOFTINT(hw_base) HWREG32((hw_base) + 0xf00U)
#define GIC_DIST_CPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
#define GIC_DIST_SPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
#define GIC_DIST_ICPIDR2(hw_base) HWREG32((hw_base) + 0xfe8U)
#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U)
#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U)
#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U)
#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U)
#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U)
static unsigned int _gic_max_irq;
@@ -184,7 +181,7 @@ void arm_gic_clear_pending_irq(rt_uint64_t index, int irq)
}
}
void arm_gic_set_configuration(rt_uint64_t index, int irq, rt_uint32_t config)
void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config)
{
rt_uint64_t icfgr;
rt_uint64_t shift;
@@ -328,8 +325,6 @@ void arm_gic_send_sgi(rt_uint64_t index, int irq, rt_uint64_t target_list, rt_ui
GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) =
((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL);
__DSB();
}
rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index)
@@ -348,8 +343,8 @@ rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index)
void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group)
{
rt_uint32_t igroupr;
rt_uint32_t shift;
uint32_t igroupr;
uint32_t shift;
RT_ASSERT(index < ARM_GIC_MAX_NR);
RT_ASSERT(group <= 1U);
@@ -380,10 +375,6 @@ int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start)
unsigned int gic_type, i;
rt_uint64_t cpumask = 1U << 0U;
#ifdef ARM_SPI_BIND_CPU_ID
cpumask = 1U << ARM_SPI_BIND_CPU_ID;
#endif
RT_ASSERT(index < ARM_GIC_MAX_NR);
_gic_table[index].dist_hw_base = dist_base;
@@ -438,6 +429,12 @@ int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start)
}
/* All interrupts defaults to IGROUP1(IRQ). */
/*
for (i = 0; i < _gic_max_irq; i += 32)
{
GIC_DIST_IGROUP(dist_base, i) = 0xffffffffU;
}
*/
for (i = 0U; i < _gic_max_irq; i += 32U)
{
GIC_DIST_IGROUP(dist_base, i) = 0U;
@@ -489,17 +486,23 @@ void arm_gic_dump(rt_uint64_t index)
rt_kprintf("--- hw mask ---\n");
for (i = 0U; i < _gic_max_irq / 32U; i++)
{
rt_kprintf("0x%08x, ", GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, i * 32U));
rt_kprintf("0x%08x, ",
GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
i * 32U));
}
rt_kprintf("\n--- hw pending ---\n");
for (i = 0U; i < _gic_max_irq / 32U; i++)
{
rt_kprintf("0x%08x, ", GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base, i * 32U));
rt_kprintf("0x%08x, ",
GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
i * 32U));
}
rt_kprintf("\n--- hw active ---\n");
for (i = 0U; i < _gic_max_irq / 32U; i++)
{
rt_kprintf("0x%08x, ", GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base, i * 32U));
rt_kprintf("0x%08x, ",
GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
i * 32U));
}
rt_kprintf("\n");
}
libcpu/aarch64/common/gic.h
+3 -6
View File
@@ -11,9 +11,8 @@
#ifndef __GIC_H__
#define __GIC_H__
#include <rtdef.h>
#if defined(BSP_USING_GIC) && defined(BSP_USING_GICV2)
#include <rthw.h>
#include <board.h>
int arm_gic_get_active_irq(rt_uint64_t index);
void arm_gic_ack(rt_uint64_t index, int irq);
@@ -25,7 +24,7 @@ rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq);
void arm_gic_set_pending_irq(rt_uint64_t index, int irq);
void arm_gic_clear_pending_irq(rt_uint64_t index, int irq);
void arm_gic_set_configuration(rt_uint64_t index, int irq, rt_uint32_t config);
void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config);
rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq);
void arm_gic_clear_active(rt_uint64_t index, int irq);
@@ -59,7 +58,5 @@ int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base);
void arm_gic_dump_type(rt_uint64_t index);
void arm_gic_dump(rt_uint64_t index);
#endif /* defined(BSP_USING_GIC) && defined(BSP_USING_GICV2) */
#endif
libcpu/aarch64/common/gicv3.c
+15 -2
View File
@@ -27,7 +27,7 @@
#if defined(BSP_USING_GIC) && defined(BSP_USING_GICV3)
#include <gicv3.h>
#include <cpuport.h>
#include <cp15.h>
#include <board.h>
@@ -479,7 +479,7 @@ rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq)
}
#ifdef RT_USING_SMP
void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint64_t cpu_masks[], rt_uint64_t routing_mode)
void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint32_t cpu_masks[], rt_uint64_t routing_mode)
{
const int cpu_mask_cpu_max_nr = sizeof(cpu_masks[0]) * 8;
rt_uint64_t int_id = (irq & 0xf) << 24;
@@ -731,9 +731,22 @@ int arm_gic_redist_init(rt_uint64_t index, rt_uint64_t redist_base)
{
int i;
int cpu_id = rt_hw_cpu_id();
static int master_cpu_id = -1;
RT_ASSERT(index < ARM_GIC_MAX_NR);
if (master_cpu_id < 0)
{
master_cpu_id = cpu_id;
rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, &master_cpu_id, sizeof(master_cpu_id));
}
if (!_gic_table[index].redist_hw_base[master_cpu_id])
{
_gic_table[index].redist_hw_base[master_cpu_id] = redist_base;
}
redist_base = _gic_table[index].redist_hw_base[master_cpu_id];
redist_base += cpu_id * (2 << 16);
_gic_table[index].redist_hw_base[cpu_id] = redist_base;
libcpu/aarch64/common/gicv3.h
+1 -1
View File
@@ -51,7 +51,7 @@ rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq);
#ifdef RT_USING_SMP
void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint64_t cpu_masks[], rt_uint64_t routing_mode);
void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint32_t cpu_masks[], rt_uint64_t routing_mode);
#endif
rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index);
libcpu/aarch64/common/gtimer.c
+2 -2
View File
@@ -26,9 +26,9 @@ static void rt_hw_timer_isr(int vector, void *parameter)
void rt_hw_gtimer_init(void)
{
rt_hw_interrupt_install(EL1_PHY_TIMER_IRQ_NUM, rt_hw_timer_isr, RT_NULL, "tick");
__ISB();
rt_hw_isb();
timer_step = rt_hw_get_gtimer_frq();
__DSB();
rt_hw_dsb();
timer_step /= RT_TICK_PER_SECOND;
rt_hw_gtimer_local_enable();
}
libcpu/aarch64/common/gtimer.h
+6 -1
View File
@@ -18,7 +18,12 @@ void rt_hw_gtimer_local_enable(void);
void rt_hw_gtimer_local_disable(void);
void rt_hw_gtimer_enable();
void rt_hw_gtimer_disable();
rt_inline void rt_hw_gtimer_disable(void)
{
__asm__ volatile ("msr CNTP_CTL_EL0, xzr":::"memory");
}
void rt_hw_set_gtimer_val(rt_uint64_t value);
rt_uint64_t rt_hw_get_gtimer_val();
rt_uint64_t rt_hw_get_cntpct_val();
libcpu/aarch64/common/hypercall.c
+16
View File
@@ -0,0 +1,16 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-02-24 GuEe-GUI first version
*/
#include <hypercall.h>
rt_err_t rt_hv_stage2_map(unsigned long paddr, unsigned long size)
{
return rt_hw_hypercall(120, paddr & (~4095), (paddr & (~4095)) + size, (1 << 0) | (1 << 1) | (1 << 4), 0, 0, 0, 0);
}
libcpu/aarch64/common/hypercall.h
+27
View File
@@ -0,0 +1,27 @@
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-02-24 GuEe-GUI first version
*/
#ifndef __HYPERCALL_H__
#define __HYPERCALL_H__
#include <rtdef.h>
rt_inline rt_uint32_t rt_hw_hypercall(rt_uint32_t w0, rt_uint64_t x1, rt_uint64_t x2,
rt_uint64_t x3, rt_uint64_t x4, rt_uint64_t x5, rt_uint64_t x6, rt_uint32_t w7)
{
register rt_uint64_t ret __asm__ ("x0");
__asm__ volatile ("hvc #0");
return (rt_uint32_t)ret;
}
rt_err_t rt_hv_stage2_map(unsigned long paddr, unsigned long size);
#endif
libcpu/aarch64/common/interrupt.c
+88 -75
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