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Merge pull request #5561 from iysheng/up_gd32

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同步更新 GD32 框架代码，移动 wdt 和 rtc 驱动
This commit is contained in:
guo
2022-01-26 10:46:01 +08:00
committed by GitHub
parent 9b44734643 e4892b95fd
commit e6cc9363c7
87 changed files with 192 additions and 41843 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/gd32/gd32103c-eval/board/Kconfig
+56 -2
View File
@@ -74,12 +74,66 @@ menu "On-chip Peripheral Drivers"
range 1 216
default 25
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_RTC
bool "Enable Internal RTC"
select RT_USING_RTC
default n
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
config BSP_USING_HWTIMER4
bool "using hwtimer4"
default n
config BSP_USING_HWTIMER5
bool "using hwtimer5"
default n
config BSP_USING_HWTIMER6
bool "using hwtimer6"
default n
config BSP_USING_HWTIMER7
bool "using hwtimer7"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
config BSP_USING_ADC1
bool "using adc1"
default n
endif
source "../libraries/gd32_drivers/Kconfig"
endmenu
menu "Board extended module Drivers"
endmenu
endmenu
bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript
+1
View File
@@ -40,6 +40,7 @@ if GetDepend(['RT_USING_HWTIMER']):
if GetDepend(['RT_USING_RTC']):
src += ['GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c']
src += ['GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c']
if GetDepend(['RT_USING_WDT']):
src += ['GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c']
bsp/gd32/libraries/gd32_drivers/SConscript
+14 -2
View File
@@ -27,9 +27,21 @@ if GetDepend('RT_USING_SPI'):
# add spi flash drivers.
if GetDepend('RT_USING_SFUD'):
src += ['drv_spi_flash.c', 'drv_spi.c']
src += ['drv_spi_flash.c', 'drv_spi.c']
path = [cwd]
if GetDepend('RT_USING_WDT'):
src += ['drv_wdt.c']
if GetDepend('RT_USING_RTC'):
src += ['drv_rtc.c']
if GetDepend('RT_USING_HWTIMER'):
src += ['drv_hwtimer.c']
if GetDepend('RT_USING_ADC'):
src += ['drv_adc.c']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
bsp/gd32103c-eval/drivers/drv_adc.c → bsp/gd32/libraries/gd32_drivers/drv_adc.c
+23 -35
View File
@@ -1,15 +1,14 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-03 iysheng first version
* 2021-02-25 iysheng first version
*/
#include <board.h>
#include <drivers/drv_comm.h>
#include <drivers/adc.h>
#define DBG_TAG "drv.adc"
@@ -39,7 +38,7 @@ static gd32_adc_device g_gd32_devs[] = {
GET_PIN(B, 0), GET_PIN(B, 1), GET_PIN(C, 0), GET_PIN(C, 1),
GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), GET_PIN(C, 5),
},
ADC0,
(void *)ADC0,
},
#endif
@@ -53,7 +52,7 @@ static gd32_adc_device g_gd32_devs[] = {
GET_PIN(B, 0), GET_PIN(B, 1), GET_PIN(C, 0), GET_PIN(C, 1),
GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), GET_PIN(C, 5),
},
ADC1,
(void *)ADC1,
},
#endif
};
@@ -61,53 +60,41 @@ static gd32_adc_device g_gd32_devs[] = {
/*
* static void init_pin4adc
*
* 初始化指定的管腳爲 analog 模式
* @ rt_uint32_t pin: pin information
* return: N/A
*/
static void init_pin4adc(rt_base_t pin)
{
GPIO_InitPara GPIO_InitStruct = {0};
GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin);
GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_50MHZ;
GPIO_InitStruct.GPIO_Mode = GPIO_MODE_AIN;
GPIO_Init(PIN_GDPORT(pin), &GPIO_InitStruct);
gpio_init(PIN_GDPORT(pin), GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, PIN_GDPIN(pin));
}
static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
ADC_TypeDef *ADCx;
ADC_InitPara ADC_InitParaStruct = {0};
uint32_t adc_periph;
gd32_adc_device * gd32_adc = (gd32_adc_device *)device;
if (channel >= MAX_EXTERN_ADC_CHANNEL)
{
LOG_E("invalid channel");
return -E2BIG;
return -RT_EINVAL;
}
ADCx = (ADC_TypeDef *)(device->parent.user_data);
adc_periph = (uint32_t )(device->parent.user_data);
if (enabled == ENABLE)
{
init_pin4adc(gd32_adc->adc_pins[channel]);
ADC_InitParaStruct.ADC_Trig_External = ADC_EXTERNAL_TRIGGER_MODE_NONE;
/* Fix the channel number to fit the firmware library */
ADC_InitParaStruct.ADC_Channel_Number = 1 + channel;
ADC_InitParaStruct.ADC_Data_Align = ADC_DATAALIGN_RIGHT;
ADC_InitParaStruct.ADC_Mode_Scan = DISABLE;
ADC_InitParaStruct.ADC_Mode = ADC_MODE_INDEPENDENT;
ADC_InitParaStruct.ADC_Mode_Continuous = ENABLE;
ADC_Init(ADCx, &ADC_InitParaStruct);
ADC_RegularChannel_Config(ADCx, channel, 1, ADC_SAMPLETIME_13POINT5);
ADC_Enable(ADCx, ENABLE);
ADC_SoftwareStartConv_Enable(ADCx, ENABLE);
adc_deinit(adc_periph);
adc_channel_length_config(adc_periph, ADC_REGULAR_CHANNEL, 1);
adc_data_alignment_config(adc_periph, ADC_DATAALIGN_RIGHT);
adc_external_trigger_source_config(adc_periph, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_INSERTED_NONE);
adc_external_trigger_config(adc_periph, ADC_REGULAR_CHANNEL, ENABLE);
adc_regular_channel_config(adc_periph, 0, channel, ADC_SAMPLETIME_13POINT5);
adc_enable(adc_periph);
}
else
{
ADC_Enable(ADCx, DISABLE);
adc_disable(adc_periph);
}
return 0;
@@ -115,16 +102,17 @@ static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
static rt_err_t gd32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
ADC_TypeDef *ADCx;
uint32_t adc_periph;
if (!value)
{
LOG_E("invalid param");
return -EINVAL;
return -RT_EINVAL;
}
ADCx = (ADC_TypeDef *)(device->parent.user_data);
*value = ADC_GetConversionValue(ADCx);
adc_periph = (uint32_t )(device->parent.user_data);
adc_software_trigger_enable(adc_periph, ADC_REGULAR_CHANNEL);
*value = adc_regular_data_read(adc_periph);
return 0;
}
@@ -148,11 +136,11 @@ static int rt_hw_adc_init(void)
rcu_periph_clock_enable(RCU_ADC1);
#endif
for (; i < ARRAY_SIZE(g_gd32_devs); i++)
for (; i < sizeof(g_gd32_devs) / sizeof(g_gd32_devs[0]); i++)
{
ret = rt_hw_adc_register(&g_gd32_devs[i].adc_dev, \
(const char *)g_gd32_devs[i].name, \
&g_gd32_adc_ops, g_gd32_devs[i].private_data);
&g_gd32_adc_ops, (void *)g_gd32_devs[i].private_data);
if (ret != RT_EOK)
{
/* TODO err handler */
bsp/gd32/libraries/gd32_drivers/drv_gpio.h
+7 -1
View File
@@ -38,7 +38,7 @@ extern "C" {
EXTI_SOURCE_PIN##pin}
#else
#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
GPIO##port, GPIO_PIN_##pin, \
GPIO##port, GPIO_PIN_##pin, \
GPIO_PORT_SOURCE_GPIO##port, \
GPIO_PIN_SOURCE_##pin}
@@ -48,6 +48,12 @@ extern "C" {
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN)
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_GDPORT(pin) (GPIO_BASE + (0x400u * PIN_PORT(pin)))
#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
struct pin_index
{
rt_int16_t index;
bsp/gd32103c-eval/drivers/drv_hwtimer.c → bsp/gd32/libraries/gd32_drivers/drv_hwtimer.c
+63 -51
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File diff suppressed because it is too large Load Diff
bsp/gd32103c-eval/drivers/drv_rtc.c → bsp/gd32/libraries/gd32_drivers/drv_rtc.c
+9 -10
View File
@@ -1,16 +1,15 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-20 iysheng first version
* 2022-01-25 iysheng first version
*/
#include <board.h>
#include <sys/time.h>
#include <drivers/drv_comm.h>
#define DBG_TAG "drv.rtc"
#define DBG_LVL DBG_INFO
@@ -29,7 +28,7 @@ static time_t get_rtc_timestamp(void)
{
time_t rtc_counter;
rtc_counter = (time_t)RTC_GetCounter();
rtc_counter = (time_t)rtc_counter_get();
return rtc_counter;
}
@@ -41,15 +40,15 @@ static rt_err_t set_rtc_timestamp(time_t time_stamp)
rtc_counter = (uint32_t)time_stamp;
/* wait until LWOFF bit in RTC_CTL to 1 */
RTC_WaitLWOFF();
rtc_lwoff_wait();
/* enter configure mode */
RTC_EnterConfigMode();
rtc_configuration_mode_enter();
/* write data to rtc register */
RTC_SetCounter(rtc_counter);
rtc_counter_set(rtc_counter);
/* exit configure mode */
RTC_ExitConfigMode();
rtc_configuration_mode_exit();
/* wait until LWOFF bit in RTC_CTL to 1 */
RTC_WaitLWOFF();
rtc_lwoff_wait();
return RT_EOK;
}
@@ -94,7 +93,7 @@ static int rt_hw_rtc_init(void)
time_t rtc_counter;
rcu_periph_clock_enable(RCU_PMU);
PWR_BackupAccess_Enable(ENABLE);
pmu_backup_write_enable();
rcu_periph_clock_enable(RCU_BKPI);
rtc_counter = get_rtc_timestamp();
bsp/gd32103c-eval/drivers/drv_iwdt.c → bsp/gd32/libraries/gd32_drivers/drv_wdt.c
+19 -20
View File
@@ -1,11 +1,11 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-03-03 iysheng first version
* 2022-01-25 iysheng first version
*/
#include <board.h>
@@ -25,13 +25,13 @@ typedef struct {
static gd32_wdt_device_t g_wdt_dev;
static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt)
static rt_err_t gd32_wdt_init(rt_watchdog_t *wdt)
{
rcu_osci_on(RCU_IRC40K);
if (ERROR == rcu_osci_stab_wait(RCU_IRC40K))
{
LOG_E("failed init IRC40K clock for free watchdog.");
return -EINVAL;
return -RT_EINVAL;
}
g_wdt_dev.min_threshold_s = 1;
@@ -39,22 +39,21 @@ static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt)
LOG_I("threshold section [%u, %d]", \
g_wdt_dev.min_threshold_s, g_wdt_dev.max_threshold_s);
IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE);
IWDG_SetPrescaler(IWDG_PRESCALER_256);
IWDG_SetReloadValue(0xfff);
IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE);
fwdgt_write_enable();
fwdgt_config(0xfff, FWDGT_PSC_DIV256);
fwdgt_enable();
return 0;
}
static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
static rt_err_t gd32_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
rt_uint32_t param;
switch (cmd)
{
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
IWDG_ReloadCounter();
fwdgt_counter_reload();
break;
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
param = *(rt_uint32_t *) arg;
@@ -62,21 +61,21 @@ static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
(param < g_wdt_dev.min_threshold_s))
{
LOG_E("invalid param@%u.", param);
return -E2BIG;
return -RT_EINVAL;
}
else
{
g_wdt_dev.current_threshold_s = param;
}
IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE);
IWDG_SetReloadValue(param * 40000 >> 8);
IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE);
fwdgt_write_enable();
fwdgt_config(param * 40000 >> 8, FWDGT_PSC_DIV256);
fwdgt_write_disable();
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
*(rt_uint32_t *)arg = g_wdt_dev.current_threshold_s;
break;
case RT_DEVICE_CTRL_WDT_START:
IWDG_Enable();
fwdgt_enable();
break;
default:
LOG_W("This command is not supported.");
@@ -87,17 +86,17 @@ static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
}
static struct rt_watchdog_ops g_wdt_ops = {
gd32_iwdt_init,
gd32_iwdt_control,
gd32_wdt_init,
gd32_wdt_control,
};
static int rt_hw_iwdt_init(void)
static int rt_hw_wdt_init(void)
{
rt_err_t ret;
g_wdt_dev.wdt.ops = &g_wdt_ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "iwdt", \
if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "wdt", \
RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
@@ -107,5 +106,5 @@ static int rt_hw_iwdt_init(void)
return ret;
}
INIT_BOARD_EXPORT(rt_hw_iwdt_init);
INIT_PREV_EXPORT(rt_hw_wdt_init);
#endif
bsp/gd32103c-eval/.config
-672
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File diff suppressed because it is too large Load Diff
bsp/gd32103c-eval/Kconfig
-109
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@@ -1,109 +0,0 @@
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default: "rt-thread"
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_SERIES_GD32F1
bool
default y
config SOC_GD32103C
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select SOC_SERIES_GD32F1
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "using uart0"
default n
config BSP_USING_UART1
bool "using uart1"
default n
config BSP_USING_UART2
bool "using uart2"
default y
config BSP_USING_UART3
bool "using uart3"
default n
config BSP_USING_UART4
bool "using uart4"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
config BSP_USING_ADC1
bool "using adc1"
default n
endif
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
config BSP_USING_HWTIMER4
bool "using hwtimer4"
default n
config BSP_USING_HWTIMER5
bool "using hwtimer5"
default n
config BSP_USING_HWTIMER6
bool "using hwtimer6"
default n
config BSP_USING_HWTIMER7
bool "using hwtimer7"
default n
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_RTC
bool "using internal rtc"
default n
select RT_USING_RTC
endmenu
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x.h
-8033
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bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x_conf.h
-39
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@@ -1,39 +0,0 @@
/**
******************************************************************************
* @brief Configuration file.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_CONF_H
#define __GD32F10X_CONF_H
/* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */
#include "gd32f10x_adc.h"
#include "gd32f10x_bkp.h"
#include "gd32f10x_can.h"
#include "gd32f10x_crc.h"
#include "gd32f10x_dac.h"
#include "gd32f10x_dma.h"
#include "gd32f10x_eth.h"
#include "gd32f10x_exmc.h"
#include "gd32f10x_exti.h"
#include "gd32f10x_fmc.h"
#include "gd32f10x_gpio.h"
#include "gd32f10x_i2c.h"
#include "gd32f10x_iwdg.h"
#include "gd32f10x_mcudbg.h"
#include "gd32f10x_misc.h"
#include "gd32f10x_pwr.h"
#include "gd32f10x_rcc.h"
#include "gd32f10x_rcu.h"
#include "gd32f10x_rtc.h"
#include "gd32f10x_sdio.h"
#include "gd32f10x_spi.h"
#include "gd32f10x_timer.h"
#include "gd32f10x_usart.h"
#include "gd32f10x_wwdg.h"
#endif /* __GD32F10X_CONF_H */
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/system_gd32f10x.h
-64
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@@ -1,64 +0,0 @@
/**
******************************************************************************
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup GD32F10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_GD32F10X_H
#define __SYSTEM_GD32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup GD32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup GD32F10x_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup GD32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_GD32F10X_H */
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s
-213
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bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s
-48
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@@ -1,48 +0,0 @@
/*
* File : startup_gd32f10x_hd.s
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2021, RT-Thread Development Team
*
* Change Logs:
* Date Author Notes
* 2021-01-02 iysheng first implementation
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global Reset_Handler
.section .text.Reset_Handler
.type Reset_Handler, STT_FUNC
Reset_Handler:
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
subs r3, r2
ble fill_bss_start
loop_copy_data:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt loop_copy_data
fill_bss_start:
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble startup_enter
loop_fill_bss:
subs r2, #4
str r0, [r1, r2]
bgt loop_fill_bss
startup_enter:
bl SystemInit
bl entry
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c
-1131
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bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c
-784
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bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.h
-1614
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bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h
-616
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bsp/gd32103c-eval/Libraries/CMSIS/core_cmInstr.h
-618
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File diff suppressed because it is too large Load Diff
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h
-278
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_bkp.h
-139
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/**
******************************************************************************
* @brief BKP header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_BKP_H
#define __GD32F10X_BKP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup BKP
* @{
*/
/** @defgroup BKP_Exported_Constants
* @{
*/
/** @defgroup TAMPER_pin_active_level
* @{
*/
#define BKP_TPAL_HIGH ((uint16_t)0x0000)
#define BKP_TPAL_LOW ((uint16_t)0x0002)
/**
* @}
*/
/** @defgroup RTC_output_on_the_TAMPER_pin
* @{
*/
#define BKP_RTCOUTPUT_NULL ((uint16_t)0x0000)
#define BKP_RTCOUTPUT_CLKCAL ((uint16_t)0x0080)
#define BKP_RTCOUTPUT_ALARM ((uint16_t)0x0100)
#define BKP_RTCOUTPUT_SECOND ((uint16_t)0x0300)
/**
* @}
*/
/** @defgroup Backup_Data_Register
* @{
*/
#define BKP_DR1 ((uint16_t)0x0004)
#define BKP_DR2 ((uint16_t)0x0008)
#define BKP_DR3 ((uint16_t)0x000C)
#define BKP_DR4 ((uint16_t)0x0010)
#define BKP_DR5 ((uint16_t)0x0014)
#define BKP_DR6 ((uint16_t)0x0018)
#define BKP_DR7 ((uint16_t)0x001C)
#define BKP_DR8 ((uint16_t)0x0020)
#define BKP_DR9 ((uint16_t)0x0024)
#define BKP_DR10 ((uint16_t)0x0028)
#define BKP_DR11 ((uint16_t)0x0040)
#define BKP_DR12 ((uint16_t)0x0044)
#define BKP_DR13 ((uint16_t)0x0048)
#define BKP_DR14 ((uint16_t)0x004C)
#define BKP_DR15 ((uint16_t)0x0050)
#define BKP_DR16 ((uint16_t)0x0054)
#define BKP_DR17 ((uint16_t)0x0058)
#define BKP_DR18 ((uint16_t)0x005C)
#define BKP_DR19 ((uint16_t)0x0060)
#define BKP_DR20 ((uint16_t)0x0064)
#define BKP_DR21 ((uint16_t)0x0068)
#define BKP_DR22 ((uint16_t)0x006C)
#define BKP_DR23 ((uint16_t)0x0070)
#define BKP_DR24 ((uint16_t)0x0074)
#define BKP_DR25 ((uint16_t)0x0078)
#define BKP_DR26 ((uint16_t)0x007C)
#define BKP_DR27 ((uint16_t)0x0080)
#define BKP_DR28 ((uint16_t)0x0084)
#define BKP_DR29 ((uint16_t)0x0088)
#define BKP_DR30 ((uint16_t)0x008C)
#define BKP_DR31 ((uint16_t)0x0090)
#define BKP_DR32 ((uint16_t)0x0094)
#define BKP_DR33 ((uint16_t)0x0098)
#define BKP_DR34 ((uint16_t)0x009C)
#define BKP_DR35 ((uint16_t)0x00A0)
#define BKP_DR36 ((uint16_t)0x00A4)
#define BKP_DR37 ((uint16_t)0x00A8)
#define BKP_DR38 ((uint16_t)0x00AC)
#define BKP_DR39 ((uint16_t)0x00B0)
#define BKP_DR40 ((uint16_t)0x00B4)
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
/**
* @}
*/
/**
* @}
*/
/** @defgroup BKP_Exported_Functions
* @{
*/
void BKP_DeInit(void);
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
void BKP_RTCOutputConfig(uint16_t BKP_RTCOUTPUT);
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
void BKP_TamperPinConfig(uint16_t BKP_TPAL, TypeState NewValue);
void BKP_TamperINT_Enable(TypeState NewValue);
TypeState BKP_GetBitState(void);
void BKP_ClearBitState(void);
TypeState BKP_GetIntBitState(void);
void BKP_ClearIntBitState(void);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_BKP_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_can.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h
-52
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/**
******************************************************************************
* @brief CRC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_CRC_H
#define __GD32F10X_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @defgroup CRC_Exported_Functions
* @{
*/
void CRC_ResetDTR(void);
uint32_t CRC_CalcSingleData(uint32_t CRC_data);
uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length);
uint32_t CRC_ReadDTR(void);
void CRC_WriteFDTR(uint8_t CRC_fdtr);
uint8_t CRC_ReadFDTR(void);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_CRC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dac.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_dma.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_eth.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exmc.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_exti.h
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/**
******************************************************************************
* @brief EXTI header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_EXTI_H
#define __GD32F10X_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** @defgroup EXTI_Exported_Types
* @{
*/
/**
* @brief EXTI Mode enumeration
*/
typedef enum {
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTI_ModePara;
/**
* @brief EXTI Trigger enumeration
*/
typedef enum {
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTI_TriggerPara;
/**
* @brief EXTI Initial Parameters
*/
typedef struct {
uint32_t EXTI_LINE; /*!< The selection of EXTI lines. */
EXTI_ModePara EXTI_Mode; /*!< The mode for the EXTI lines, detailed in @ref EXTIMode_Para. */
EXTI_TriggerPara EXTI_Trigger; /*!< The trigger edge for the EXTI lines, detailed in EXTI_TriggerPara. */
TypeState EXTI_LINEEnable; /*!< The new value of the selected EXTI lines. */
} EXTI_InitPara;
/**
* @}
*/
/** @defgroup EXTI_Exported_Constants
* @{
*/
/** @defgroup EXTI_lines
* @{
*/
#define EXTI_LINE0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
#define EXTI_LINE1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
#define EXTI_LINE2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
#define EXTI_LINE3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
#define EXTI_LINE4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
#define EXTI_LINE5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
#define EXTI_LINE6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
#define EXTI_LINE7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
#define EXTI_LINE8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
#define EXTI_LINE9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
#define EXTI_LINE10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
#define EXTI_LINE11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
#define EXTI_LINE12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
#define EXTI_LINE13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
#define EXTI_LINE14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
#define EXTI_LINE15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
#define EXTI_LINE16 ((uint32_t)0x00010000) /*!< External interrupt line 16
Connected to the LVD */
#define EXTI_LINE17 ((uint32_t)0x00020000) /*!< External interrupt line 17
Connected to the RTC Alarm */
#define EXTI_LINE18 ((uint32_t)0x00040000) /*!< External interrupt line 18
Connected to the USB Wakeup */
#define EXTI_LINE19 ((uint32_t)0x00080000) /*!< External interrupt line 19
Connected to the Ethernet Wakeup */
/**
* @}
*/
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions
* @{
*/
void EXTI_DeInit(EXTI_InitPara *EXTI_InitParaStruct);
void EXTI_Init(EXTI_InitPara *EXTI_InitParaStruct);
void EXTI_SWINT_Enable(uint32_t EXTI_LINE);
TypeState EXTI_GetBitState(uint32_t EXTI_LINE);
void EXTI_ClearBitState(uint32_t EXTI_LINE);
TypeState EXTI_GetIntBitState(uint32_t EXTI_LINE);
void EXTI_ClearIntBitState(uint32_t EXTI_LINE);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_EXTI_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_fmc.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_gpio.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_i2c.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_iwdg.h
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/**
******************************************************************************
* @brief IWDG header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_IWDG_H
#define __GD32F10X_IWDG_H
/* Exported macro ------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup IWDG
* @{
*/
/** @defgroup IWDG_Exported_Constants
* @{
*/
/** @defgroup IWDG_WriteAccess
* @{
*/
#define IWDG_WRITEACCESS_ENABLE ((uint16_t)0x5555)
#define IWDG_WRITEACCESS_DISABLE ((uint16_t)0x0000)
/**
* @}
*/
/** @defgroup IWDG_prescaler
* @{
*/
#define IWDG_PRESCALER_4 ((uint8_t)0x00)
#define IWDG_PRESCALER_8 ((uint8_t)0x01)
#define IWDG_PRESCALER_16 ((uint8_t)0x02)
#define IWDG_PRESCALER_32 ((uint8_t)0x03)
#define IWDG_PRESCALER_64 ((uint8_t)0x04)
#define IWDG_PRESCALER_128 ((uint8_t)0x05)
#define IWDG_PRESCALER_256 ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup IWDG_Flag
* @{
*/
#define IWDG_BIT_PUD IWDG_STR_PUD
#define IWDG_BIT_RUD IWDG_STR_RUD
#define IWDG_BIT_WUD IWDG_STR_WUD
/**
* @}
*/
/**
* @}
*/
/** @defgroup IWDG_Exported_functions
* @{
*/
/* Prescaler and Counter configuration functions ******************************/
void IWDG_Write_Enable(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t PrescalerValue);
void IWDG_SetReloadValue(uint16_t ReloadValue);
void IWDG_ReloadCounter(void);
/* IWDG activation function ***************************************************/
void IWDG_Enable(void);
/* Flag management function ***************************************************/
TypeState IWDG_GetBitState(uint16_t IWDG_FLAG);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __IWDG_GD32F10X_H */
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_mcudbg.h
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/**
******************************************************************************
* @brief MCUDBG header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_MCUDBG_H
#define __GD32F10X_MCUDBG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup MCUDBG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MCUDBG_Exported_Constants
* @{
*/
#define MCUDBG_SLEEP_HOLD ((uint32_t)0x00000001)
#define MCUDBG_DEEPSLEEP_HOLD ((uint32_t)0x00000002)
#define MCUDBG_STDBY_HOLD ((uint32_t)0x00000004)
#define MCUDBG_IWDG_HOLD ((uint32_t)0x00000100)
#define MCUDBG_WWDG_HOLD ((uint32_t)0x00000200)
#define MCUDBG_TIMER1_HOLD ((uint32_t)0x00000400)
#define MCUDBG_TIMER2_HOLD ((uint32_t)0x00000800)
#define MCUDBG_TIMER3_HOLD ((uint32_t)0x00001000)
#define MCUDBG_TIMER4_HOLD ((uint32_t)0x00002000)
#define MCUDBG_CAN1_HOLD ((uint32_t)0x00004000)
#define MCUDBG_I2C1_HOLD ((uint32_t)0x00008000)
#define MCUDBG_I2C2_HOLD ((uint32_t)0x00010000)
#define MCUDBG_TIMER5_HOLD ((uint32_t)0x00020000)
#define MCUDBG_TIMER6_HOLD ((uint32_t)0x00040000)
#define MCUDBG_TIMER7_HOLD ((uint32_t)0x00080000)
#define MCUDBG_TIMER8_HOLD ((uint32_t)0x00100000)
#define MCUDBG_CAN2_HOLD ((uint32_t)0x00200000)
#define MCUDBG_TIMER12_HOLD ((uint32_t)0x02000000)
#define MCUDBG_TIMER13_HOLD ((uint32_t)0x04000000)
#define MCUDBG_TIMER14_HOLD ((uint32_t)0x08000000)
#define MCUDBG_TIMER9_HOLD ((uint32_t)0x10000000)
#define MCUDBG_TIMER10_HOLD ((uint32_t)0x20000000)
#define MCUDBG_TIMER11_HOLD ((uint32_t)0x40000000)
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/** @defgroup MCUDBG_Exported_Functions
* @{
*/
uint32_t MCUDBG_GetREVID(void);
uint32_t MCUDBG_GetDEVID(void);
void MCUDBG_PeriphConfig(uint32_t MCUDBG_Periph, TypeState NewValue);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_MCUDBG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_misc.h
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/**
******************************************************************************
* @brief MISC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_MISC_H
#define __GD32F10X_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @defgroup MISC_Exported_Types
* @{
*/
/**
* @brief MISC Initial Parameters
*/
typedef struct {
uint8_t NVIC_IRQ; /*!< The IRQ type,detailed in @ref IRQn_Type */
uint8_t NVIC_IRQPreemptPriority; /*!< The pre-emption priority of NVIC_IRQ, detailed in @ref NVIC_Priority_Table */
uint8_t NVIC_IRQSubPriority; /*!< The SubPriority of NVIC_IRQ, detailed in @ref NVIC_Priority_Table */
TypeState NVIC_IRQEnable; /*!< Enable or disable the IRQ,this parameter can be ENABLE or DISABLE */
} NVIC_InitPara;
/**
* @}
*/
/** @defgroup MISC_Exported_Constants
* @{
*/
/** @defgroup MISC_System_Low_Power
* @{
*/
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000)
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000)
#define NVIC_LOWPOWER_SEVONPEND ((uint8_t)0x10)
#define NVIC_LOWPOWER_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LOWPOWER_SLEEPONEXIT ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup MISC_Preemption_Priority_Group
* @{
*/
/* Preemption Priority Group -------------------------------------------------*/
#define NVIC_PRIGROUP_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
#define NVIC_PRIGROUP_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
#define NVIC_PRIGROUP_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
#define NVIC_PRIGROUP_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
#define NVIC_PRIGROUP_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
/**
* @}
*/
/** @defgroup MISC_SysTick_clock_source
* @{
*/
#define SYSTICK_CKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFB)
#define SYSTICK_CKSOURCE_HCLK ((uint32_t)0x00000004)
/**
* @}
*/
/**
* @}
*/
/** @defgroup MISC_Exported_Functions
* @{
*/
void NVIC_Init(NVIC_InitPara *NVIC_InitStruct);
void NVIC_SystemLowPowerConfig(uint8_t LowPowerMode, TypeState NewValue);
void SysTick_CKSource_Enable(uint32_t SysTick_CKSource);
void NVIC_VectTableSet(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_PRIGroup_Enable(uint32_t NVIC_PRIGroup);
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_MISC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_pwr.h
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/**
******************************************************************************
* @brief PWR header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_PWR_H
#define __GD32F10X_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup PWR
* @{
*/
/** @defgroup PWR_Exported_Constants
* @{
*/
/** @defgroup PWR_Low_Voltage_Detector_Threshold
* @{
*/
#define PWR_LVDT_0 PWR_CTLR_LVDT_2V2
#define PWR_LVDT_1 PWR_CTLR_LVDT_2V3
#define PWR_LVDT_2 PWR_CTLR_LVDT_2V4
#define PWR_LVDT_3 PWR_CTLR_LVDT_2V5
#define PWR_LVDT_4 PWR_CTLR_LVDT_2V6
#define PWR_LVDT_5 PWR_CTLR_LVDT_2V7
#define PWR_LVDT_6 PWR_CTLR_LVDT_2V8
#define PWR_LVDT_7 PWR_CTLR_LVDT_2V9
/**
* @}
*/
/** @defgroup PWR_LDO_state_in_Deep-sleep_mode
* @{
*/
#define PWR_LDO_ON ((uint32_t)0x00000000)
#define PWR_LDO_LOWPOWER PWR_CTLR_LDOLP
/**
* @}
*/
/** @defgroup PWR_Sleep_mode_entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup PWR_Deep-sleep_mode_entry
* @{
*/
#define PWR_DEEPSLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_DEEPSLEEPENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup PWR_Standby_mode_entry
* @{
*/
#define PWR_STDBYENTRY_WFI ((uint8_t)0x01)
#define PWR_STDBYENTRY_WFE ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup PWR_Flag
* @{
*/
#define PWR_FLAG_WKUP PWR_STR_WUF
#define PWR_FLAG_STB PWR_STR_SBF
#define PWR_FLAG_LVDF PWR_STR_LVDF
/**
* @}
*/
/**
* @}
*/
/** @defgroup PWR_Exported_Functions
* @{
*/
void PWR_DeInit(void);
void PWR_BackupAccess_Enable(TypeState NewValue);
void PWR_LVDConfig(uint32_t PWR_LVDT, TypeState NewValue);
void PWR_WKUP_Pin_Enable(TypeState NewValue);
void PWR_SLEEPMode_Entry(uint8_t PWR_SLEEPENTRY);
void PWR_DEEPSLEEPMode_Entry(uint32_t PWR_LDO, uint8_t PWR_DEEPSLEEPENTRY);
void PWR_STDBYMode_Entry(uint8_t PWR_STDBYENTRY);
TypeState PWR_GetBitState(uint32_t PWR_FLAG);
void PWR_ClearBitState(uint32_t PWR_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_PWR_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rcc.h
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_rtc.h
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/**
******************************************************************************
* @brief RTC header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_RTC_H
#define __GD32F10X_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @addtogroup RTC
* @{
*/
/** @defgroup RTC_Exported_Defines
* @{
*/
/** @defgroup RTC_Interrupt_Def
* @{
*/
#define RTC_INT_OVF ((uint16_t)0x0004) /*!< Overflow interrupt */
#define RTC_INT_AF ((uint16_t)0x0002) /*!< Alarm interrupt */
#define RTC_INT_SF ((uint16_t)0x0001) /*!< Second interrupt */
/**
* @}
*/
/** @defgroup RTC_Interrupts_Flags
* @{
*/
#define RTC_FLAG_LWOFF ((uint16_t)0x0020) /*!< Last write operation finished flag */
#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */
#define RTC_FLAG_OVF ((uint16_t)0x0004) /*!< Overflow flag */
#define RTC_FLAG_AF ((uint16_t)0x0002) /*!< Alarm flag */
#define RTC_FLAG_SF ((uint16_t)0x0001) /*!< Second flag */
/**
* @}
*/
/**
* @}
*/
/** @defgroup RTC_Exported_Functions
* @{
*/
void RTC_INT_Enable(uint16_t RTC_int, TypeState NewValue);
void RTC_EnterConfigMode(void);
void RTC_ExitConfigMode(void);
uint32_t RTC_GetCounter(void);
void RTC_SetCounter(uint32_t CounterValue);
void RTC_SetPrescaler(uint32_t PrescalerValue);
void RTC_SetAlarm(uint32_t AlarmTime);
uint32_t RTC_GetDividerValue(void);
void RTC_WaitLWOFF(void);
void RTC_WaitRSF(void);
TypeState RTC_GetBitState(uint16_t RTC_flag);
void RTC_ClearBitState(uint16_t RTC_flag);
TypeState RTC_GetIntBitState(uint16_t RTC_INT);
void RTC_ClearIntBitState(uint16_t RTC_INT);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__GD32F10X_RTC_H */
/**
* @}
*/
/**
* @}
*/
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_wwdg.h
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/**
******************************************************************************
* @brief WWDG header file of the firmware library.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_WWDG_H
#define __GD32F10X_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup WWDG
* @{
*/
/** @defgroup WWDG_Exported_Constants
* @{
*/
/** @defgroup WWDG_PRESCALER
* @{
*/
#define WWDG_PRESCALER_1 ((uint32_t)0x00000000)
#define WWDG_PRESCALER_2 ((uint32_t)0x00000080)
#define WWDG_PRESCALER_4 ((uint32_t)0x00000100)
#define WWDG_PRESCALER_8 ((uint32_t)0x00000180)
/**
* @}
*/
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/** @defgroup WWDG_Exported_Functions
* @{
*/
void WWDG_DeInit(void);
void WWDG_SetPrescalerValue(uint32_t PrescalerValue);
void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableInt(void);
void WWDG_SetCounterValue(uint8_t CounterValue);
void WWDG_Enable(uint8_t CounterValue);
TypeState WWDG_GetBitState(void);
void WWDG_ClearBitState(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GD32F10X_WWDG_H */
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_adc.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_crc.c
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/**
******************************************************************************
* @brief CRC functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_crc.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup CRC
* @brief CRC driver modules
* @{
*/
/** @defgroup CRC_Private_Functions
* @{
*/
/**
* @brief Reset CRC DTR register to the value of 0xFFFFFFFF.
* @param None
* @retval None
*/
void CRC_ResetDTR(void)
{
CRC->CTLR = CRC_CTLR_RESET;
}
/**
* @brief Compute the 32-bit CRC value of a 32-bit data.
* @param CRC_data: data to compute its CRC value
* @retval 32-bit CRC value
*/
uint32_t CRC_CalcSingleData(uint32_t CRC_data)
{
CRC->DTR = CRC_data;
return (CRC->DTR);
}
/**
* @brief Compute the 32-bit CRC value of a 32-bit data array.
* @param pbuffer[]: pointer to the data array
* @param buffer_length: length of the data array
* @retval 32-bit CRC value
*/
uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length)
{
uint32_t index = 0;
for (index = 0; index < buffer_length; index++) {
CRC->DTR = pbuffer[index];
}
return (CRC->DTR);
}
/**
* @brief Read current CRC value.
* @param None
* @retval 32-bit CRC value
*/
uint32_t CRC_ReadDTR(void)
{
return (CRC->DTR);
}
/**
* @brief Write an 8-bit data in FDTR.
* @param CRC_fdtr: 8-bit data to write
* @retval None
*/
void CRC_WriteFDTR(uint8_t CRC_fdtr)
{
CRC->FDTR = CRC_fdtr;
}
/**
* @brief Read the 8-bit data stored in FDTR
* @param None
* @retval 8-bit data
*/
uint8_t CRC_ReadFDTR(void)
{
return (CRC->FDTR);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_exti.c
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/**
******************************************************************************
* @brief EXTI functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_exti.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup EXTI
* @brief EXTI driver modules
* @{
*/
/** @defgroup EXTI_Private_Defines
* @{
*/
/* No interrupt line is selected */
#define EXTI_LINE_NULL ((uint32_t)0x00000000)
/* ----------------- EXTI Reset Configuration Registers ------------------ */
/* The reset value of EXTI_IER */
#define EXTI_IER_RST ((uint32_t)0x00000000)
/* The reset value of EXTI_EER */
#define EXTI_EER_RST ((uint32_t)0x00000000)
/* The reset value of EXTI_RTE */
#define EXTI_RTE_RST ((uint32_t)0x00000000)
/* The reset value of EXTI_FTE */
#define EXTI_FTE_RST ((uint32_t)0x00000000)
/* The reset value of EXTI_PD */
#define EXTI_PD_RST ((uint32_t)0x000FFFFF)
/**
* @}
*/
/** @defgroup EXTI_Private_Functions
* @{
*/
/**
* @brief Reset the EXTI peripheral registers and the struct EXTI_InitPara.
* @param EXTI_InitParaStruct: the struct EXTI_InitPara pointer.
* @retval None
*/
void EXTI_DeInit(EXTI_InitPara *EXTI_InitParaStruct)
{
/* Reset the EXTI peripheral registers */
EXTI->IER = EXTI_IER_RST;
EXTI->EER = EXTI_EER_RST;
EXTI->RTE = EXTI_RTE_RST;
EXTI->FTE = EXTI_FTE_RST;
EXTI->PD = EXTI_PD_RST;
/* Reset the struct EXTI_InitPara */
EXTI_InitParaStruct->EXTI_LINE = EXTI_LINE_NULL;
EXTI_InitParaStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitParaStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitParaStruct->EXTI_LINEEnable = DISABLE;
}
/**
* @brief Initialize the EXTI peripheral registers.
* @param EXTI_InitParaStruct: the struct EXTI_InitPara pointer.
* @retval None
*/
void EXTI_Init(EXTI_InitPara *EXTI_InitParaStruct)
{
uint32_t temp = 0;
temp = (uint32_t)EXTI_BASE;
if (EXTI_InitParaStruct->EXTI_LINEEnable != DISABLE) {
/* Clear Interrupt and Event from EXTI Lines */
EXTI->IER &= ~EXTI_InitParaStruct->EXTI_LINE;
EXTI->EER &= ~EXTI_InitParaStruct->EXTI_LINE;
temp += EXTI_InitParaStruct->EXTI_Mode;
*(__IO uint32_t *) temp |= EXTI_InitParaStruct->EXTI_LINE;
/* Clear the Rising and Falling edge trigger enable registers */
EXTI->RTE &= ~EXTI_InitParaStruct->EXTI_LINE;
EXTI->FTE &= ~EXTI_InitParaStruct->EXTI_LINE;
/* Select the trigger type for the selected EXTI Lines */
if (EXTI_InitParaStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) {
/* Rising and Falling edge trigger are both selected */
EXTI->RTE |= EXTI_InitParaStruct->EXTI_LINE;
EXTI->FTE |= EXTI_InitParaStruct->EXTI_LINE;
} else {
temp = (uint32_t)EXTI_BASE;
temp += EXTI_InitParaStruct->EXTI_Trigger;
*(__IO uint32_t *) temp |= EXTI_InitParaStruct->EXTI_LINE;
}
} else {
temp += EXTI_InitParaStruct->EXTI_Mode;
/* Disable the selected EXTI lines */
*(__IO uint32_t *) temp &= ~EXTI_InitParaStruct->EXTI_LINE;
}
}
/**
* @brief Activate the software interrupt or event request of the selected EXTI Lines.
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval None
*/
void EXTI_SWINT_Enable(uint32_t EXTI_LINE)
{
/* Enable the software interrupt or event request of the selected EXTI Lines */
EXTI->SIE |= EXTI_LINE;
}
/**
* @brief Get the bit flag of the selected EXTI lines.
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval The new value of EXTI_LINE (SET or RESET).
*/
TypeState EXTI_GetBitState(uint32_t EXTI_LINE)
{
/* Check and get the selected EXTI lines flag */
if ((EXTI->PD & EXTI_LINE) != (uint32_t)RESET) {
/* EXTI_LINE bit is SET */
return SET;
} else {
/* EXTI_LINE bit is RESET */
return RESET;
}
}
/**
* @brief Clear the bit flag of the selected EXTI lines.
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval None
*/
void EXTI_ClearBitState(uint32_t EXTI_LINE)
{
/* Clear the bit flag of the selected EXTI lines */
EXTI->PD = EXTI_LINE;
}
/**
* @brief Get the interrupt bit flag of the selected EXTI lines..
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval The new value of EXTI_LINE (SET or RESET).
*/
TypeState EXTI_GetIntBitState(uint32_t EXTI_LINE)
{
/* Check and get the interrupt source is set or not */
if (((EXTI->PD & EXTI_LINE) != (uint32_t)RESET) && ((EXTI->IER & EXTI_LINE) != (uint32_t)RESET)) {
/* The interrupt bit of EXTI_LINE is SET */
return SET;
} else {
/* The interrupt bit of EXTI_LINE is RESET */
return RESET;
}
}
/**
* @brief Clear the interrupt bit flag of the selected EXTI lines.
* @param EXTI_LINE: the selected EXTI lines.
* This parameter can be any combination of EXTI_LINEx where x can be (0..19).
* @retval None
*/
void EXTI_ClearIntBitState(uint32_t EXTI_LINE)
{
/* Clear the interrupt bit flag of the selected EXTI lines */
EXTI->PD = EXTI_LINE;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_iwdg.c
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/**
******************************************************************************
* @brief IWDG functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_iwdg.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup IWDG
* @brief IWDG driver modules
* @{
*/
/** @defgroup IWDG_Private_Variables
* @{
*/
/* CTLR register bit mask */
#define CTLR_KEY_RELOAD ((uint16_t)0xAAAA)
#define CTLR_KEY_ENABLE ((uint16_t)0xCCCC)
/**
* @}
*/
/** @defgroup IWDG_Private_Functions
* @{
*/
/**
* @brief Enable or disable the IWDG_PSR, IWDG_RLDR and IWDG_WND write protection.
* @param IWDG_WriteAccess: value to enable or disable the write access to registers.
* This parameter can be one of the following values:
* @arg IWDG_WRITEACCESS_ENABLE: Enable write access to IWDG_PSR, IWDG_RLDR and IWDG_WND registers
* @arg IWDG_WRITEACCESS_DISABLE: Disable write access to IWDG_PSR, IWDG_RLDR and IWDG_WND registers
* @retval None
*/
void IWDG_Write_Enable(uint16_t IWDG_WriteAccess)
{
IWDG->CTLR = IWDG_WriteAccess;
}
/**
* @brief Set IWDG prescaler value.
* @param PrescalerValue: IWDG Prescaler value.
* This parameter can be one of the following values:
* @arg IWDG_PRESCALER_4: IWDG prescaler set to 4
* @arg IWDG_PRESCALER_8: IWDG prescaler set to 8
* @arg IWDG_PRESCALER_16: IWDG prescaler set to 16
* @arg IWDG_PRESCALER_32: IWDG prescaler set to 32
* @arg IWDG_PRESCALER_64: IWDG prescaler set to 64
* @arg IWDG_PRESCALER_128: IWDG prescaler set to 128
* @arg IWDG_PRESCALER_256: IWDG prescaler set to 256
* @retval None
*/
void IWDG_SetPrescaler(uint8_t PrescalerValue)
{
IWDG->PSR = PrescalerValue;
}
/**
* @brief Set independent watchdog counter reload value.
* @param ReloadValue: IWDG Reload value.
* This parameter must be between 0 and 0x0FFF.
* @retval None
*/
void IWDG_SetReloadValue(uint16_t ReloadValue)
{
IWDG->RLDR = ReloadValue;
}
/**
* @brief Reload the counter.
* @param None
* @retval None
*/
void IWDG_ReloadCounter(void)
{
IWDG->CTLR = CTLR_KEY_RELOAD;
}
/**
* @brief Start the independent watchdog counter.
* @param None
* @retval None
*/
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_ENABLE;
}
/**
* @brief Check registers' bit state.
* @param IWDG_FLAG: the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_BIT_PUD: A write operation to IWDG_PSR register on going
* @arg IWDG_BIT_RUD: A write operation to IWDG_RLDR register on going
* @arg IWDG_BIT_WUD: A write operation to IWDG_WND register on going
* @retval The new state of IWDG_FLAG (SET or RESET).
*/
TypeState IWDG_GetBitState(uint16_t IWDG_FLAG)
{
if ((IWDG->STR & IWDG_FLAG) != (uint32_t)RESET) {
return SET;
} else {
return RESET;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_mcudbg.c
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/**
******************************************************************************
* @brief MCUDBG functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_mcudbg.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup MCUDBG
* @brief MCUDBG driver modules
* @{
*/
/** @defgroup MCUDBG_Private_Defines
* @{
*/
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/**
* @}
*/
/** @defgroup MCUDBG_Private_Functions
* @{
*/
/**
* @brief Returns the device revision identifier.
* @param None
* @retval Device revision identifier
*/
uint32_t MCUDBG_GetREVID(void)
{
return (MCUDBG->IDR >> 16);
}
/**
* @brief Returns the device identifier.
* @param None
* @retval Device identifier
*/
uint32_t MCUDBG_GetDEVID(void)
{
return (MCUDBG->IDR & IDCODE_DEVID_MASK);
}
/**
* @brief Configure the specified peripheral and low power mode behavior
* when the MCU under Debug mode.
* @param MCUDBG_Periph: specifies the peripheral and low power mode.
* This parameter can be any combination of the following values:
* @arg MCUDBG_SLEEP_HOLD: Keep debugger connection during SLEEP mode
* @arg MCUDBG_DEEPSLEEP_HOLD: Keep debugger connection during DEEPSLEEP mode
* @arg MCUDBG_STDBY_HOLD: Keep debugger connection during STANDBY mode
* @arg MCUDBG_IWDG_HOLD: Debug IWDG hold when Core is halted
* @arg MCUDBG_WWDG_HOLD: Debug WWDG hold when Core is halted
* @arg MCUDBG_TIMER1_HOLD: TIMER1 counter hold when Core is halted
* @arg MCUDBG_TIMER2_HOLD: TIMER2 counter hold when Core is halted
* @arg MCUDBG_TIMER3_HOLD: TIMER3 counter hold when Core is halted
* @arg MCUDBG_TIMER4_HOLD: TIMER4 counter hold when Core is halted
* @arg MCUDBG_CAN1_HOLD: Debug CAN1 hold when Core is halted
* @arg MCUDBG_I2C1_HOLD: I2C1 SMBUS timeout mode hold when Core is halted
* @arg MCUDBG_I2C2_HOLD: I2C2 SMBUS timeout mode hold when Core is halted
* @arg MCUDBG_TIMER5_HOLD: TIMER5 counter hold when Core is halted
* @arg MCUDBG_TIMER6_HOLD: TIMER6 counter hold when Core is halted
* @arg MCUDBG_TIMER7_HOLD: TIMER7 counter hold when Core is halted
* @arg MCUDBG_TIMER8_HOLD: TIMER8 counter hold when Core is halted
* @arg MCUDBG_CAN2_HOLD: Debug CAN2 hold when Core is halted
* @arg MCUDBG_TIMER12_HOLD: TIMER12 counter hold when Core is halted
* @arg MCUDBG_TIMER13_HOLD: TIMER13 counter hold when Core is halted
* @arg MCUDBG_TIMER14_HOLD: TIMER14 counter hold when Core is halted
* @arg MCUDBG_TIMER9_HOLD: TIMER9 counter hold when Core is halted
* @arg MCUDBG_TIMER10_HOLD: TIMER10 counter hold when Core is halted
* @arg MCUDBG_TIMER11_HOLD: TIMER11 counter hold when Core is halted
* @param NewState: new state of the specified peripheral in Debug mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void MCUDBG_PeriphConfig(uint32_t MCUDBG_Periph, TypeState NewValue)
{
if (NewValue != DISABLE) {
MCUDBG->CTLR |= MCUDBG_Periph;
} else {
MCUDBG->CTLR &= ~MCUDBG_Periph;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_misc.c
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/**
******************************************************************************
* @brief MISC functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_misc.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup MISC
* @brief MISC driver modules
* @{
*/
/** @defgroup MISC_Private_Defines
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @}
*/
/** @defgroup MISC_Private_Functions
* @{
*/
/**
* @brief By the PRIGROUP[10:8] bits of the AIRCR register, Setting the priority grouping:
* pre-emption priority and subpriority.
* @param NVIC_PriGroup: NVIC_PRIGROUP_0, NVIC_PRIGROUP_1,...NVIC_PRIGROUP_4.
* @retval None
*/
void NVIC_PRIGroup_Enable(uint32_t NVIC_PRIGroup)
{
/* Set the priority grouping value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PRIGroup;
}
/**
* @brief The NVIC peripheral Initialization.
* @param NVIC_InitStruct: a NVIC_InitPara structure pointer.
* @retval None
*/
void NVIC_Init(NVIC_InitPara *NVIC_InitStruct)
{
uint32_t temppriority = 0x00, temppreempt = 0x00, tempsub = 0x00;
if (NVIC_InitStruct->NVIC_IRQEnable != DISABLE) {
if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_0) {
temppreempt = 0;
tempsub = 0x4;
} else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_1) {
temppreempt = 1;
tempsub = 0x3;
} else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_2) {
temppreempt = 2;
tempsub = 0x2;
} else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_3) {
temppreempt = 3;
tempsub = 0x1;
} else if (((SCB->AIRCR) & (uint32_t)0x700) == NVIC_PRIGROUP_4) {
temppreempt = 4;
tempsub = 0x0;
}
temppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQPreemptPriority << (0x4 - temppreempt);
temppriority |= NVIC_InitStruct->NVIC_IRQSubPriority & (0x0F >> (0x4 - tempsub));
temppriority = temppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQ] = temppriority;
/* Enable the Selected IRQ Channels */
NVIC->ISER[NVIC_InitStruct->NVIC_IRQ >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQ & (uint8_t)0x1F);
} else {
/* Disable the Selected IRQ Channels */
NVIC->ICER[NVIC_InitStruct->NVIC_IRQ >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQ & (uint8_t)0x1F);
}
}
/**
* @brief Specify the vector table in RAM or FLASH memory and its Offset.
* @param NVIC_VectTab: NVIC_VECTTAB_RAM,NVIC_VECTTAB_FLASH
* @param Offset: Vector Table start address.
* @retval None
*/
void NVIC_VectTableSet(uint32_t NVIC_VectTab, uint32_t Offset)
{
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Specify the state of the system to enter low power mode.
* @param LowPowerMode: NVIC_LOWPOWER_SEVONPEND,NVIC_LOWPOWER_SLEEPDEEP,NVIC_LOWPOWER_SLEEPONEXIT.
* @param NewValue: new value of Low Power state. This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void NVIC_SystemLowPowerConfig(uint8_t LowPowerMode, TypeState NewValue)
{
if (NewValue != DISABLE) {
SCB->SCR |= LowPowerMode;
} else {
SCB->SCR &= (~(uint32_t)LowPowerMode);
}
}
/**
* @brief Specify the SysTick clock source.
* @param SysTick_CKSource: SYSTICK_CKSOURCE_HCLK_DIV8,SYSTICK_CKSOURCE_HCLK.
* @retval None
*/
void SysTick_CKSource_Enable(uint32_t SysTick_CKSource)
{
if (SysTick_CKSource == SYSTICK_CKSOURCE_HCLK) {
SysTick->CTRL |= SYSTICK_CKSOURCE_HCLK;
} else {
SysTick->CTRL &= SYSTICK_CKSOURCE_HCLK_DIV8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_pwr.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcc.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rcu.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_rtc.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_sdio.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_spi.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_timer.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_usart.c
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bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Source/gd32f10x_wwdg.c
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@@ -1,155 +0,0 @@
/**
******************************************************************************
* @brief WWDG functions of the firmware library.
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "gd32f10x_wwdg.h"
#include "gd32f10x_rcc.h"
/** @addtogroup GD32F10x_Firmware
* @{
*/
/** @defgroup WWDG
* @brief WWDG driver modules
* @{
*/
/** @defgroup WWDG_Private_Variables
* @{
*/
/* CFR register bit mask */
#define CFR_PS_MASK ((uint32_t)0xFFFFFE7F)
#define CFR_WIN_MASK ((uint32_t)0xFFFFFF80)
#define BIT_MASK ((uint8_t)0x7F)
/**
* @}
*/
/** @defgroup WWDG_Private_Functions
* @{
*/
/**
* @brief Reset the WWDG configuration.
* @param None
* @retval None
*/
void WWDG_DeInit(void)
{
RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_WWDG, ENABLE);
RCC_APB1PeriphReset_Enable(RCC_APB1PERIPH_WWDG, DISABLE);
}
/**
* @brief Set WWDG prescaler value.
* @param PrescalerValue: WWDG Prescaler value.
* This parameter can be one of the following values:
* @arg WWDG_PRESCALER_1: the time base of watchdog counter = (PCLK1/4096)/1
* @arg WWDG_PRESCALER_2: the time base of watchdog counter = (PCLK1/4096)/2
* @arg WWDG_PRESCALER_4: the time base of watchdog counter = (PCLK1/4096)/4
* @arg WWDG_PRESCALER_8: the time base of watchdog counter = (PCLK1/4096)/8
* @retval None
*/
void WWDG_SetPrescalerValue(uint32_t PrescalerValue)
{
uint32_t temp = 0;
/* Clear PS[1:0] bits */
temp = WWDG->CFR & CFR_PS_MASK;
/* Set PS[1:0] bits */
temp |= PrescalerValue;
WWDG->CFR = temp;
}
/**
* @brief Set watchdog window value.
* @param WindowValue: the window value to be compared to the downcounter.
* @retval None
*/
void WWDG_SetWindowValue(uint8_t WindowValue)
{
__IO uint32_t temp = 0;
/* Clear WIN[6:0] bits */
temp = WWDG->CFR & CFR_WIN_MASK;
/* Set WIN[6:0] bits */
temp |= WindowValue & (uint32_t) BIT_MASK;
WWDG->CFR = temp;
}
/**
* @brief Enable the WWDG Early wakeup interrupt(EWI).
* @note An interrupt occurs when the counter reaches 0x40 if the bit is set.
* It's cleared by a hardware reset. A write of 0 has no effect.
* @param None
* @retval None
*/
void WWDG_EnableInt(void)
{
WWDG->CFR |= WWDG_CFR_EWI;
}
/**
* @brief Set the value of the watchdog counter.
* @param CounterValue: the watchdog counter value.
* @retval None
*/
void WWDG_SetCounterValue(uint8_t CounterValue)
{
/* Write to CNT[6:0] bits */
WWDG->CTLR = CounterValue & BIT_MASK;
}
/**
* @brief Start the window watchdog counter.
* @param CounterValue: The value of the watchdog counter.
* @retval None
*/
void WWDG_Enable(uint8_t CounterValue)
{
WWDG->CTLR = WWDG_CTLR_WDGEN | CounterValue;
}
/**
* @brief Check the Early Wakeup interrupt bit state.
* @param None
* @retval The new state of the Early Wakeup interrupt (SET or RESET).
*/
TypeState WWDG_GetBitState(void)
{
if ((WWDG->STR) != (uint32_t)RESET) {
return SET;
} else {
return RESET;
}
}
/**
* @brief Clear Early Wakeup interrupt flag.
* @param None
* @retval None
*/
void WWDG_ClearBitState(void)
{
WWDG->STR = (uint32_t)RESET;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/SConscript
-26
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@@ -1,26 +0,0 @@
import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('GD32F1xx_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s']
src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s']
path = [
cwd + '/CMSIS/GD/GD32F1xx/Include',
cwd + '/CMSIS',
cwd + '/GD32F1xx_standard_peripheral/Include',]
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F1XX']
group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/gd32103c-eval/README.md
-74
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@@ -1,74 +0,0 @@
# GD32103C-EVAL
## 简介
GD32103C-EVAL是-兆易创新推出的一款GD32F103VCT6系列的评估板，板载资源主要如下：
| 硬件 | 描述 |
| --------- | ------------- |
| 芯片型号 | GD32F103VCT6 |
| CPU | ARM Cortex M3 |
| 主频 | 108M |
| 片内SRAM | 48K |
| 片内FLASH | 256K |
| 片外FLASH | 1Gb |
## 编译说明
GD32103C-EVAL板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以下是具体版本信息：
| IDE/编译器 | 已测试版本 |
| ---------- | ---------------------------- |
| GCC |gcc version 6.2.1 20161205 (release) |
## 烧写及执行
供电方式：开发板使用 Mini USB 接口或者 DC-005 连接器提供 5V 电源。
下载程序：下载程序到开发板需要一套 JLink 或者使用 GD-Link 工具。
串口连接：使用串口线连接到COM1(UART0)，或者使用USB转TTL模块连接PA9(MCU TX)和PA10(MCU RX)。
### 运行结果
如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build Jan 4 2021
2006 - 2021 Copyright by rt-thread team
msh />
```
## 驱动支持情况及计划
| 驱动 | 支持情况 | 备注 |
| --------- | -------- | :------------------------: |
| UART | 支持 | UART0~4 |
| GPIO | 支持 | GPIOA~G |
| ADC | 支持 | ADC0~1 |
| HWTIMER | 支持 | TIMER0~7 |
| RTC | 支持 | RTC |
| WDT | 支持 | Free watchdog timer |
| IIC | 未支持 | I2C0~1 |
| SPI | 未支持 | SPI0~2 |
| ETH | 未支持 | |
| LCD | 未支持 | |
| SDRAM | 未支持 | |
| SPI FLASH | 未支持 | |
### IO在板级支持包中的映射情况
| IO号 | 板级包中的定义 |
| ---- | -------------- |
| PC0 | LED1 |
| PC2 | LED2 |
| PE0 | LED3 |
| PE1 | LED4 |
| PA0 | KEY1 |
| PC13 | KEY2 |
| PB14 | KEY3 |
## 联系人信息
维护人：[iysheng](https://github.com/iysheng)
bsp/gd32103c-eval/SConscript
-14
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@@ -1,14 +0,0 @@
# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/gd32103c-eval/SConstruct
-40
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@@ -1,40 +0,0 @@
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread-gd32f4xx.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)
bsp/gd32103c-eval/applications/SConscript
-11
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@@ -1,11 +0,0 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/gd32103c-eval/applications/main.c
-33
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@@ -1,33 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
*/
#include <board.h>
#include <drivers/adc.h>
#include <rtdbg.h>
#include <stdio.h>
#include <rtthread.h>
#include "board.h"
#define LED1 GET_PIN(C, 0)
int main(void)
{
rt_pin_mode(LED1, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED1, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED1, PIN_LOW);
rt_thread_mdelay(500);
}
return 0;
}
bsp/gd32103c-eval/drivers/SConscript
-35
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@@ -1,35 +0,0 @@
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
# add the general drivers.
src = Split("""
board.c
""")
CPPPATH = [cwd]
# add uart drivers.
if GetDepend('RT_USING_SERIAL'):
src += ['drv_usart.c']
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
if GetDepend('RT_USING_ADC'):
src += ['drv_adc.c']
if GetDepend('RT_USING_HWTIMER'):
src += ['drv_hwtimer.c']
if GetDepend('RT_USING_RTC'):
src += ['drv_rtc.c']
if GetDepend('RT_USING_WDT'):
src += ['drv_iwdt.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/gd32103c-eval/drivers/board.c
-74
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@@ -1,74 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
*/
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include <gd32f10x.h>
#include <board.h>
#include <drv_usart.h>
/*
* System Clock Configuration
*/
void SystemClock_Config(void)
{
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
NVIC_SetPriority(SysTick_IRQn, 0);
}
/*
* This is the timer interrupt service routine.
*/
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
/**
* This function will initial GD32 board.
*/
void rt_hw_board_init()
{
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK);
#else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x08000000 */
SCB->VTOR = (0x08000000 & NVIC_VTOR_MASK);
#endif
SystemClock_Config();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef BSP_USING_SDRAM
rt_system_heap_init((void *)EXT_SDRAM_BEGIN, (void *)EXT_SDRAM_END);
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}
/*@}*/
bsp/gd32103c-eval/drivers/board.h
-26
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@@ -1,26 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <gd32f10x.h>
#include "drv_gpio.h"
#define GD32_SRAM_SIZE 48
#define GD32_SRAM_END (0x20000000 + GD32_SRAM_SIZE * 1024)
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#define HEAP_END GD32_SRAM_END
#endif
bsp/gd32103c-eval/drivers/drv_adc.h
-23
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@@ -1,23 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-03 iysheng first release
*/
#ifndef __DRV_ADC_H__
#define __DRV_ADC_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_ADC_H__ */
bsp/gd32103c-eval/drivers/drv_comm.h
-27
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@@ -1,27 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 iysheng first version
*/
#ifndef __DRV_COMM_H__
#define __DRV_COMM_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DRV_HWTIMER_H__ */
bsp/gd32103c-eval/drivers/drv_gpio.c
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bsp/gd32103c-eval/drivers/drv_gpio.h
-45
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@@ -1,45 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-12-27 iysheng first release
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __GD32_PORT(port) GPIO##port##_BASE
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_GDPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin))))
#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
struct pin_irq_map
{
rt_uint16_t pinbit;
IRQn_Type irqno;
};
#ifdef __cplusplus
}
#endif
#endif /* __DRV_GPIO_H__ */
bsp/gd32103c-eval/drivers/drv_hwtimer.h
-38
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@@ -1,38 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-15 iysheng first release
*/
#ifndef __DRV_HWTIMER_H__
#define __DRV_HWTIMER_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <drivers/hwtimer.h>
typedef struct {
TIMER_TypeDef *reg_base;
IRQn_Type irqn;
rcu_periph_enum rcu;
} gd32_hwtimer_data;
typedef struct {
char dev_name[RT_NAME_MAX];
const gd32_hwtimer_data hw_data;
rt_hwtimer_t hwtimer_dev;
const struct rt_hwtimer_info hwtimer_info;
} gd32_hwtimer_device;
#ifdef __cplusplus
}
#endif
#endif /* __DRV_HWTIMER_H__ */
bsp/gd32103c-eval/drivers/drv_usart.c
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bsp/gd32103c-eval/drivers/drv_usart.h
-33
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@@ -1,33 +0,0 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-04 iysheng first version
*/
#ifndef __USART_H__
#define __USART_H__
#include <rthw.h>
#include <rtthread.h>
/* GD32 uart driver */
struct gd32_uart {
USART_TypeDef * uart_periph;
IRQn_Type irqn;
rcu_periph_enum per_clk;
rcu_periph_enum tx_gpio_clk;
rcu_periph_enum rx_gpio_clk;
GPIO_TypeDef * tx_port;
GPIO_TypeDef * rx_port;
uint16_t tx_pin;
uint16_t rx_pin;
struct rt_serial_device *serial;
char *device_name;
};
#endif
bsp/gd32103c-eval/gd32_rom.ld
-146
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@@ -1,146 +0,0 @@
/*
* linker script for GD32F1xx with GNU ld
*
* Change Logs:
* Date Author Notes
* 2009-10-14 bernard.xiong first implementation
* 2021-01-02 iysheng modify to suite gd32f103c
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x08000000, LENGTH = 256k /* 256KB flash */
DATA (rw) : ORIGIN = 0x20000000, LENGTH = 48k /* 48KB sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
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bsp/gd32103c-eval/rtconfig.h
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bsp/gd32103c-eval/rtconfig.py
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import os
# toolchains options
ARCH='arm'
CPU='cortex-m3'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'D:/toolchain/gnu_tools_arm_embedded/5.4_2016q3/bin'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
PLATFORM = 'iar'
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# tool-chains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Dgcc' # -D' + PART_TYPE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-gd32.map,-cref,-u,Reset_Handler -T gd32_rom.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2 -g'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
AS = 'armasm'
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
DEVICE = ' --cpu Cortex-M4'
CFLAGS = DEVICE + ' --apcs=interwork'
AFLAGS = DEVICE
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-gd32.map --scatter gd32_rom.sct'
LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
EXEC_PATH += '/ARM/ARMCC/bin'
print(EXEC_PATH)
CFLAGS += ' --c99'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
AFLAGS += ' -g'
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = ' -D USE_STDPERIPH_DRIVER' + ' -D GD32F30X_HD'
CFLAGS = DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --debug'
CFLAGS += ' --endian=little'
CFLAGS += ' --cpu=Cortex-M4'
CFLAGS += ' -e'
CFLAGS += ' --fpu=None'
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' -Ol'
CFLAGS += ' --use_c++_inline'
AFLAGS = ''
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --cpu Cortex-M4'
AFLAGS += ' --fpu None'
LFLAGS = ' --config gd32_rom.icf'
LFLAGS += ' --redirect _Printf=_PrintfTiny'
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
LFLAGS += ' --entry __iar_program_start'
EXEC_PATH += '/arm/bin/'
POST_ACTION = ''