Add mb9bf568r to bsp

bsp/mb9bf568r/CMSIS/DeviceSupport/base_types.h

@@ -0,0 +1,160 @@
+/*******************************************************************************
+* Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
+*
+* This software is owned and published by: 
+* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with Spansion 
+* components. This software is licensed by Spansion to be adapted only 
+* for use in systems utilizing Spansion components. Spansion shall not be 
+* responsible for misuse or illegal use of this software for devices not 
+* supported herein.  Spansion is providing this software "AS IS" and will 
+* not be responsible for issues arising from incorrect user implementation 
+* of the software.  
+*
+* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
+* WARRANTY OF NONINFRINGEMENT.  
+* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 
+* SAVINGS OR PROFITS, 
+* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
+* FROM, THE SOFTWARE.  
+*
+* This software may be replicated in part or whole for the licensed use, 
+* with the restriction that this Disclaimer and Copyright notice must be 
+* included with each copy of this software, whether used in part or whole, 
+* at all times.  
+*/
+
+/*****************************************************************************/
+/** \file base_types.h
+ **
+ ** Additional base type definitions to stddef.h and stdint.h
+ **
+ ** History:
+ **   - 2013-03-21  1.0  MWi  First version.
+ **
+ *****************************************************************************/
+
+#ifndef __BASE_TYPES_H__
+#define __BASE_TYPES_H__
+
+/*****************************************************************************/
+/* Include files                                                             */
+/*****************************************************************************/
+#include <stddef.h>
+#include "stdint.h"
+  
+/*****************************************************************************/
+/* Global pre-processor symbols/macros ('#define')                           */
+/*****************************************************************************/
+#ifndef TRUE
+  /** Value is true (boolean_t type) */
+  #define TRUE        ((boolean_t) 1)
+#endif
+
+#ifndef FALSE
+  /** Value is false (boolean_t type) */
+  #define FALSE       ((boolean_t) 0)
+#endif  
+
+/** Returns the minimum value out of two values */
+#define MIN( X, Y )  ((X) < (Y) ? (X) : (Y))
+
+/** Returns the maximum value out of two values */
+#define MAX( X, Y )  ((X) > (Y) ? (X) : (Y))
+
+/** Returns the dimension of an array */
+#define DIM( X )  (sizeof(X) / sizeof(X[0]))
+
+/******************************************************************************
+ * Global type definitions
+ ******************************************************************************/
+
+/** logical datatype (only values are TRUE and FALSE) */
+typedef uint8_t      boolean_t;
+  
+/** single precision floating point number (4 byte) */
+typedef float        float32_t;
+
+/** double precision floating point number (8 byte) */
+typedef double       float64_t;
+
+/** ASCCI character for string generation (8 bit) */
+typedef char         char_t;
+
+/** function pointer type to void/void function */
+typedef void         (*func_ptr_t)(void);
+
+/** function pointer type to void/uint8_t function */
+typedef void         (*func_ptr_arg1_t)(uint8_t);
+
+/** generic error codes */
+typedef enum en_result
+{
+    Ok                          = 0,  ///< No error
+    Error                       = 1,  ///< Non-specific error code
+    ErrorAddressAlignment       = 2,  ///< Address alignment does not match
+    ErrorAccessRights           = 3,  ///< Wrong mode (e.g. user/system) mode is set
+    ErrorInvalidParameter       = 4,  ///< Provided parameter is not valid
+    ErrorOperationInProgress    = 5,  ///< A conflicting or requested operation is still in progress
+    ErrorInvalidMode            = 6,  ///< Operation not allowed in current mode
+    ErrorUninitialized          = 7,  ///< Module (or part of it) was not initialized properly
+    ErrorBufferFull             = 8,  ///< Circular buffer can not be written because the buffer is full
+    ErrorTimeout                = 9,  ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.)
+    ErrorNotReady               = 10, ///< A requested final state is not reached
+    OperationInProgress         = 11  ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.)
+} en_result_t;
+
+/**
+ ******************************************************************************
+ ** \brief Level
+ ** 
+ ** Specifies levels.
+ **
+ ******************************************************************************/
+typedef enum en_level
+{
+    PDLLow      = 0,  ///< Low level '0'
+    PDLHigh     = 1   ///< High level '1'
+} en_level_t;
+
+/**
+ ******************************************************************************
+ ** \brief Generic Flag Code
+ ** 
+ ** Specifies flags.
+ **
+ ******************************************************************************/
+typedef enum en_flag
+{
+    PdlClr = 0,       ///< Flag clr '0'
+    PdlSet = 1        ///< Flag set '1' 
+} en_stat_flag_t, en_int_flag_t;      
+
+/*****************************************************************************/
+/* Global variable declarations ('extern', definition in C source)           */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* Global function prototypes ('extern', definition in C source)             */
+/*****************************************************************************/
+
+#endif /* __BASE_TYPES_H__ */
+
+/******************************************************************************/
+/* EOF (not truncated)                                                        */
+/******************************************************************************/

bsp/mb9bf568r/CMSIS/DeviceSupport/system_mb9abxxx.c

@@ -0,0 +1,240 @@
+/*******************************************************************************
+* Copyright (C) 2013 Spansion LLC. All Rights Reserved. 
+*
+* This software is owned and published by: 
+* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA  94088-3453 ("Spansion").
+*
+* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND 
+* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT.
+*
+* This software contains source code for use with Spansion 
+* components. This software is licensed by Spansion to be adapted only 
+* for use in systems utilizing Spansion components. Spansion shall not be 
+* responsible for misuse or illegal use of this software for devices not 
+* supported herein.  Spansion is providing this software "AS IS" and will 
+* not be responsible for issues arising from incorrect user implementation 
+* of the software.  
+*
+* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE,
+* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), 
+* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, 
+* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED 
+* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED 
+* WARRANTY OF NONINFRINGEMENT.  
+* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, 
+* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT 
+* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, 
+* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR 
+* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, 
+* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, 
+* SAVINGS OR PROFITS, 
+* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
+* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR
+* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED 
+* FROM, THE SOFTWARE.  
+*
+* This software may be replicated in part or whole for the licensed use, 
+* with the restriction that this Disclaimer and Copyright notice must be 
+* included with each copy of this software, whether used in part or whole, 
+* at all times.  
+*/
+/**
+ ******************************************************************************
+ ** \file system_mb9abxxx.c
+ **
+ ** FM3 system initialization functions
+ ** All adjustments can be done in belonging header file.
+ **
+ ** History:
+ ** 2013-01-21  0.1  MWi  AI: Unification to be done
+ ** 2013-01-23  0.2  MWi  mcu.h inclusion changed to pdl.h
+ ** 2013-06-28  0.3  EH   Added Trace Buffer enable
+ ******************************************************************************/
+
+#include "mcu.h"
+
+/**
+ ******************************************************************************
+ ** System Clock Frequency (Core Clock) Variable according CMSIS
+ ******************************************************************************/
+uint32_t SystemCoreClock = __HCLK;
+
+/**
+ ******************************************************************************
+ ** \brief  Update the System Core Clock with current core Clock retrieved from
+ ** cpu registers.
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemCoreClockUpdate (void) {
+  uint32_t masterClk;
+  uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
+
+  switch ((FM4_CRG->SCM_CTL >> 5U) & 0x07U) {
+    case 0u:                                 /* internal High-speed Cr osc.    */
+      masterClk = __CLKHC;
+      break;
+
+    case 1u:                                 /* external main osc.             */
+      masterClk = __CLKMO;
+      break;
+
+    case 2u:                                 /* PLL clock                      */
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violation:
+  //   "Unordered accesses to a volatile location"
+      u32RegisterRead = (__CLKMO  * (((uint32_t)(FM4_CRG->PLL_CTL2) & 0x3Fu) + 1u));
+      masterClk = (u32RegisterRead / ((((uint32_t)(FM4_CRG->PLL_CTL1) >> 4ul) & 0x0Fu) + 1u));
+      break;
+
+    case 4u:                                 /* internal Low-speed CR osc.     */
+      masterClk = __CLKLC;
+      break;
+
+    case 5u:                                 /* external Sub osc.              */
+      masterClk = __CLKSO;
+      break;
+
+    default:
+      masterClk = 0ul;
+      break;
+  }
+
+  switch (FM4_CRG->BSC_PSR & 0x07u) {
+    case 0u:
+      SystemCoreClock = masterClk;
+      break;
+
+    case 1u:
+      SystemCoreClock = masterClk / 2u;
+      break;
+
+    case 2u:
+      SystemCoreClock = masterClk / 3u;
+      break;
+
+    case 3u:
+      SystemCoreClock = masterClk / 4u;
+      break;
+
+    case 4u:
+      SystemCoreClock = masterClk / 6u;
+      break;
+
+    case 5u:
+      SystemCoreClock = masterClk /8u;
+      break;
+
+    case 6u:
+      SystemCoreClock = masterClk /16u;
+      break;
+
+    default:
+      SystemCoreClock = 0ul;
+      break;
+  }
+
+}
+
+/**
+ ******************************************************************************
+ ** \brief  Setup the microcontroller system. Initialize the System and update
+ ** the SystemCoreClock variable.
+ **
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemInit (void) {
+
+  static uint8_t u8IoRegisterRead;  // Workaround variable for MISRA C rule conformance
+  
+#if (HWWD_DISABLE)                                 /* HW Watchdog Disable */
+  FM4_HWWDT->WDG_LCK = 0x1ACCE551u;                /* HW Watchdog Unlock */
+  FM4_HWWDT->WDG_LCK = 0xE5331AAEu;
+  FM4_HWWDT->WDG_CTL = 0u;                         /* HW Watchdog stop */
+#endif
+
+#if (TRACE_BUFFER_ENABLE)
+  FM4_FLASH_IF->FBFCR = 0x01;                      /* Trace Buffer enable */
+#endif
+
+#if (CLOCK_SETUP)                                  /* Clock Setup */
+  FM4_CRG->BSC_PSR   = (uint8_t)BSC_PSR_Val;                 /* set System Clock presacaler */
+  FM4_CRG->APBC0_PSR = (uint8_t)APBC0_PSR_Val;               /* set APB0 presacaler */
+  FM4_CRG->APBC1_PSR = (uint8_t)APBC1_PSR_Val;               /* set APB1 presacaler */
+  FM4_CRG->APBC2_PSR = (uint8_t)APBC2_PSR_Val;               /* set APB2 presacaler */
+  FM4_CRG->SWC_PSR   = (uint8_t)(SWC_PSR_Val | (1ul << 7u)); /* set SW Watchdog presacaler */
+  FM4_CRG->TTC_PSR   = (uint8_t)TTC_PSR_Val;                 /* set Trace Clock presacaler */
+
+  FM4_CRG->CSW_TMR   = (uint8_t)CSW_TMR_Val;                 /* set oscillation stabilization wait time */
+  
+  if (SCM_CTL_Val & (1ul << 1u)) {                 /* Main clock oscillator enabled ? */
+    FM4_CRG->SCM_CTL |= (uint8_t)(1ul << 1u);            /* enable main oscillator */ 
+    
+    while (!((FM4_CRG->SCM_STR) & (uint8_t)(1ul << 1u))) /* wait for Main clock oscillation stable */ 
+    {}
+  }
+  
+  if (SCM_CTL_Val & (1UL << 3)) {                    /* Sub clock oscillator enabled ? */
+    // Initialize VBAT (Temporary process)
+    FM4_RTC->VDET = 0x00;
+    FM4_RTC->VBPFR = 0x1C;
+    FM4_RTC->CCB = 0x10;
+    FM4_RTC->CCS = 0x08;
+
+    // VB_CLK is less or equal to 1MHz (Temporary process)
+    FM4_RTC->VB_CLKDIV = 0x4E;
+    FM4_RTC->BOOST = 0x03;
+
+    // Enable SUB CLK oscilation (Temporary process)
+    FM4_RTC->WTOSCCNT_f.SOSCEX  = 0;
+    FM4_RTC->WTOSCCNT_f.SOSCNTL = 1;
+
+    // Transmit to VBAT domain (Temporary process)
+    FM4_RTC->WTCR20_f.PWRITE = 1;
+
+    // Wait to complete transmission
+    while(0 != FM4_RTC->WTCR10_f.TRANS)
+
+    FM4_CRG->SCM_CTL |= (1UL << 3);                /* enable sub oscillator */ 
+    while (!(FM4_CRG->SCM_STR & (1UL << 3)));      /* wait for Sub clock oscillation stable */
+  }
+
+  FM4_CRG->PSW_TMR   =  (uint8_t)PSW_TMR_Val;                /* set PLL stabilization wait time */
+  FM4_CRG->PLL_CTL1  = (uint8_t) PLL_CTL1_Val;               /* set PLLM and PLLK */
+  FM4_CRG->PLL_CTL2  =  (uint8_t)PLL_CTL2_Val;               /* set PLLN          */
+  
+  if (SCM_CTL_Val &  (uint8_t)(1ul << 4u)) {                    /* PLL enabled ? */
+    FM4_CRG->SCM_CTL  |=  (uint8_t)(1ul << 4u);               /* enable PLL */ 
+    while (!(FM4_CRG->SCM_STR &  (uint8_t)(1ul << 4u)))      /* wait for PLL stable */
+    {}
+  }
+
+  FM4_CRG->SCM_CTL  |=  (uint8_t)(SCM_CTL_Val & 0xE0u);       /* Set Master Clock switch */ 
+  
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violations:
+  //   "Unordered reads and writes to or from same location" and
+  //   "Unordered accesses to a volatile location"
+  do                                              
+  {                                               
+    u8IoRegisterRead = (FM4_CRG->SCM_CTL & 0xE0u); 
+  }while ((FM4_CRG->SCM_STR & 0xE0u) != u8IoRegisterRead);
+#endif // (CLOCK_SETUP)
+  
+#if (CR_TRIM_SETUP)
+  /* CR Trimming Data  */
+  if( 0x000003FFu != (FM4_FLASH_IF->CRTRMM & 0x000003FFu) )
+  {
+    /* UnLock (MCR_FTRM) */
+    FM4_CRTRIM->MCR_RLR =  (uint32_t)0x1ACCE554u;
+    /* Set MCR_FTRM */
+    FM4_CRTRIM->MCR_FTRM = (uint16_t)FM4_FLASH_IF->CRTRMM;
+    /* Lock (MCR_FTRM) */
+    FM4_CRTRIM->MCR_RLR =  (uint32_t)0x00000000u;
+  }
+#endif // (CR_TRIM_SETUP)
+}
+
+
+

bsp/mb9bf568r/CMSIS/Include/arm_common_tables.h

@@ -0,0 +1,35 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved. 
+* 
+* $Date:        11. November 2010  
+* $Revision: 	V1.0.2  
+* 
+* Project: 	    CMSIS DSP Library 
+* Title:	    arm_common_tables.h 
+* 
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.2 2010/11/11 
+*    Documentation updated.  
+* 
+* Version 1.0.1 2010/10/05  
+*    Production release and review comments incorporated. 
+* 
+* Version 1.0.0 2010/09/20  
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */ 
+ 
+#ifndef _ARM_COMMON_TABLES_H 
+#define _ARM_COMMON_TABLES_H 
+ 
+#include "arm_math.h" 
+ 
+extern uint16_t armBitRevTable[256]; 
+extern q15_t armRecipTableQ15[64]; 
+extern q31_t armRecipTableQ31[64]; 
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+ 
+#endif /*  ARM_COMMON_TABLES_H */ 

bsp/mb9bf568r/CMSIS/SConscript

@@ -0,0 +1,18 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('DeviceSupport/*.c')
+
+CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport']
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'keil':
+	src += ['DeviceSupport/startup_mb9bf56xr.s']
+
+
+
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf568r/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/mb9bf568r/SConstruct

@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-stm32f4xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/mb9bf568r/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf568r/applications/application.c

@@ -0,0 +1,63 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-24     Bernard      the first version
+ */
+
+/**
+ * @addtogroup FM4
+ */
+/*@{*/
+
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+void rt_init_thread_entry(void *parameter)
+{
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization RT-Thread Components */
+    rt_components_init();
+#endif
+
+
+		//finsh_system_init();
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+
+
+    /**< init led device */
+    {
+        extern void rt_led_hw_init(void);
+        rt_led_hw_init();
+    }
+		{
+        extern int demo_init(void);
+        demo_init();
+    }
+
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry, RT_NULL,
+                           2048, 8, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}
+
+/*@}*/

bsp/mb9bf568r/applications/demo.c

@@ -0,0 +1,69 @@
+/*
+	此demo用于演示动态线程创建
+ */
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+#include <shell.h>
+#endif
+
+
+static	rt_thread_t tid1 = RT_NULL;
+static	rt_thread_t tid2 = RT_NULL;
+
+
+static void thread1_entry(void* parameter)
+{
+    rt_uint32_t count = 0;
+
+    rt_kprintf("thread1 dynamicly created ok\n");
+    while (1)
+    {
+        rt_kprintf("thread1 count: %d\n",count++);
+        rt_thread_delay(RT_TICK_PER_SECOND); 
+    }
+}
+						
+static void thread2_entry(void* parameter)
+{		
+		rt_uint32_t count = 0;
+    rt_kprintf("thread2 dynamicly created ok\n");
+	  
+		while(1)
+    {
+				if(count == 3)
+					break;
+        rt_kprintf("thread2 count: %d\n",count++);
+        rt_thread_delay(RT_TICK_PER_SECOND);   
+			
+    }
+    rt_thread_delay(RT_TICK_PER_SECOND * 4);  
+    
+    rt_thread_delete(tid1);							
+    rt_kprintf("thread1 deleted ok\n");
+}
+
+
+int demo_init(void)
+{
+				
+    tid1 = rt_thread_create("thread1",
+				thread1_entry,
+				RT_NULL,
+				512, 6, 10);
+	
+    if (tid1 != RT_NULL)
+        rt_thread_startup(tid1);        
+
+    tid2 = rt_thread_create("thread2",
+        thread2_entry, 
+				RT_NULL,
+        512, 6, 10);
+		
+    if (tid2 != RT_NULL)
+        rt_thread_startup(tid2);
+
+    return 0;
+}

bsp/mb9bf568r/applications/startup.c

@@ -0,0 +1,91 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-24     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+/**
+ * @addtogroup FM4
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+	
+    /* init timer system */
+    rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM4_SRAM_END);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void*)FM4_SRAM_END);
+#else
+    /* init memory system */
+    rt_system_heap_init((void*)&__bss_end, (void*)FM4_SRAM_END);
+#endif
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/

bsp/mb9bf568r/drivers/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf568r/drivers/board.c

@@ -0,0 +1,100 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-24     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#include "serial.h"
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+/**
+ * @addtogroup FM4
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This fucntion returns milliseconds since system passed
+ */
+rt_uint32_t rt_hw_tick_get_millisecond(void)
+{
+    rt_tick_t tick;
+    rt_uint32_t value;
+
+#define TICK_MS (1000/RT_TICK_PER_SECOND)
+
+    tick = rt_tick_get();
+    value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD;
+
+    return value;
+}
+
+/**
+ * This fucntion returns microseconds since system passed
+ */
+rt_uint32_t rt_hw_tick_get_microsecond(void)
+{
+    rt_tick_t tick;
+    rt_uint32_t value;
+
+#define TICK_US	(1000000/RT_TICK_PER_SECOND)
+
+    tick = rt_tick_get();
+    value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD;
+
+    return value;
+}
+
+/**
+* This function will initial FM3 Easy Kit board.
+ */
+void rt_hw_board_init(void)
+{
+    /* disable all analog input. */
+    FM4_GPIO->ADE = 0x00u;
+
+    /* init systick */
+    SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND);
+
+    /* initialize UART device */
+    rt_hw_serial_init();
+    /* set console as UART device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/

bsp/mb9bf568r/drivers/board.h

@@ -0,0 +1,39 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2011-03-04     lgnq         add board.h to FM3 bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+
+#include <system_mb9bf56xr.h>
+#include <mb9b560r.h>
+#include <base_types.h>
+
+#include "serial.h"
+
+
+#define FM4_SRAM_SIZE         128
+#define FM4_SRAM_END          (0x1FFF0000 + FM4_SRAM_SIZE * 1024)
+
+/* RT_USING_UART */
+#define RT_USING_UART0
+
+#define RT_UART_RX_BUFFER_SIZE        128
+
+void rt_hw_board_init(void);
+rt_uint32_t rt_hw_tick_get_millisecond(void);
+rt_uint32_t rt_hw_tick_get_microsecond(void);
+
+#endif

bsp/mb9bf568r/drivers/led.c

@@ -0,0 +1,155 @@
+#include <rtthread.h>
+#include "board.h"
+
+#define RT_DEVICE_CTRL_RTC_GET_COUNT        0x81        /**< get count                                   */
+
+#define LED_NUM                             3
+struct fm4_gpio_ctrl
+{
+    uint32_t led_num;
+    volatile uint32_t * PDOR;
+    volatile uint32_t * PDIR;
+};
+
+struct fm4_led
+{
+    /* inherit from rt_device */
+    struct rt_device parent;
+
+    struct fm4_gpio_ctrl fm4_gpio_ctrl[LED_NUM];
+};
+
+static struct fm4_led fm4_led;
+
+static rt_err_t rt_led_init (rt_device_t dev)
+{
+    uint32_t i;
+
+    /* led0-1-2 : P27-P38-PE0 */
+    FM4_GPIO->PFR2 &= ~((1<<7) );  /* set P27 fuction is GPIO. */
+    FM4_GPIO->DDR2 |=  (1<<7) ;    /* set P27 output. */
+		FM4_GPIO->PFR3 &= ~((1<<8) );  /* set P38 fuction is GPIO. */
+    FM4_GPIO->DDR3 |=  (1<<8) ;    /* set P38 output. */
+		FM4_GPIO->PFRE &= ~((1<<0) );  /* set PE0 fuction is GPIO. */
+    FM4_GPIO->DDRE |=  (1<<0) ;    /* set PE0 output. */
+
+    /* LED0 */
+    i = 0;
+    fm4_led.fm4_gpio_ctrl[i].led_num = 7;
+    fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDOR2;
+    fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIR2;
+
+    /* LED1 */
+    i++;
+    fm4_led.fm4_gpio_ctrl[i].led_num = 8;
+    fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDOR3;
+    fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIR3;
+
+    /* LED2 */
+    i++;
+    fm4_led.fm4_gpio_ctrl[i].led_num = 0;
+    fm4_led.fm4_gpio_ctrl[i].PDOR = &FM4_GPIO->PDORE;
+    fm4_led.fm4_gpio_ctrl[i].PDIR = &FM4_GPIO->PDIRE;
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer,
+                              rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nr = size;
+    rt_uint8_t * value = buffer;
+
+    RT_ASSERT(dev == &fm4_led.parent);
+    RT_ASSERT((pos+size) <= LED_NUM );
+
+    for(index=0; index<nr; index++)
+    {
+        if(*fm4_led.fm4_gpio_ctrl[pos+index].PDIR & 1<<fm4_led.fm4_gpio_ctrl[pos+index].led_num)
+        {
+            *value = 0;
+        }
+        else
+        {
+            *value = 1;
+        }
+        value++;
+    }
+    return index;
+}
+
+static rt_size_t rt_led_write (rt_device_t dev, rt_off_t pos,
+                               const void* buffer, rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nw = size;
+    const rt_uint8_t * value = buffer;
+
+    RT_ASSERT(dev == &fm4_led.parent);
+    RT_ASSERT((pos+size) <= LED_NUM );
+
+    for(index=0; index<nw; index++)
+    {
+        if(*value++)
+        {
+            *fm4_led.fm4_gpio_ctrl[pos+index].PDOR &= ~(1<<fm4_led.fm4_gpio_ctrl[pos+index].led_num);
+        }
+        else
+        {
+            *fm4_led.fm4_gpio_ctrl[pos+index].PDOR |= (1<<fm4_led.fm4_gpio_ctrl[pos+index].led_num);
+        }
+    }
+    return index;
+}
+
+static rt_err_t rt_led_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev == &fm4_led.parent);
+
+    if(cmd == RT_DEVICE_CTRL_RTC_GET_COUNT)
+    {
+        rt_uint32_t * led_num = args;
+        *led_num = LED_NUM;
+    }
+    return RT_EOK;
+}
+
+void rt_led_hw_init(void)
+{
+    fm4_led.parent.type 		= RT_Device_Class_Char;
+    fm4_led.parent.rx_indicate  = RT_NULL;
+    fm4_led.parent.tx_complete  = RT_NULL;
+    fm4_led.parent.init 		= rt_led_init;
+    fm4_led.parent.open		    = rt_led_open;
+    fm4_led.parent.close		= rt_led_close;
+    fm4_led.parent.read         = rt_led_read;
+    fm4_led.parent.write 		= rt_led_write;
+    fm4_led.parent.control 	    = rt_led_control;
+    fm4_led.parent.user_data	= RT_NULL;
+
+    /* register a character device */
+    rt_device_register(&fm4_led.parent, "led", RT_DEVICE_FLAG_RDWR);
+    /* init led device */
+    rt_led_init(&fm4_led.parent);
+}
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+void led(rt_uint32_t led, rt_uint32_t value)
+{
+    rt_uint8_t led_value = value;
+    rt_led_write(&fm4_led.parent, led, &led_value, 1);
+}
+FINSH_FUNCTION_EXPORT(led, e.g:led(0,0)/led(0,1).)
+#endif

bsp/mb9bf568r/drivers/mcu.h

@@ -0,0 +1,65 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+/**
+ ******************************************************************************
+ ** \file   mcu.h
+ **
+ ** Header File for device dependent includes
+ **
+ ** History:
+ ** 2011-05-19 V1.00 MWi first version
+ **
+ ******************************************************************************/
+
+#define  PDL_INT_TYPE_C		1
+#define  PDL_INT_TYPE_A		2
+
+#define PDL_MCU_INT_TYPE  PDL_INT_TYPE_A
+
+/**
+ ******************************************************************************
+ ** \brief MCU header file include
+ **
+ ******************************************************************************/ 
+#ifndef _MB9B560R_H_
+  #include "mb9b560r.h"
+#endif
+
+/**
+ ******************************************************************************
+ ** \brief MCU system start-up header file include
+ **
+ ******************************************************************************/ 
+#ifndef _SYSTEM_MB9ABXXX_H_
+  #include "system_mb9bf56xr.h"
+#endif

bsp/mb9bf568r/drivers/serial.c

@@ -0,0 +1,359 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
+ */
+
+#include <rtthread.h>
+
+#include "serial.h"
+
+/**
+ * @addtogroup FM4 MB9BF568R
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+/**
+ * This function initializes serial
+ */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+    struct serial_device* uart = (struct serial_device*) dev->user_data;
+
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            rt_memset(uart->int_rx->rx_buffer, 0,
+                      sizeof(uart->int_rx->rx_buffer));
+            uart->int_rx->read_index = uart->int_rx->save_index = 0;
+        }
+
+        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_memset(uart->int_tx->tx_buffer, 0,
+                      sizeof(uart->int_tx->tx_buffer));
+            uart->int_tx->write_index = uart->int_tx->save_index = 0;
+        }
+
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
+
+    return RT_EOK;
+}
+
+/* save a char to serial buffer */
+static void rt_serial_savechar(struct serial_device* uart, char ch)
+{
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+    uart->int_rx->save_index ++;
+    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+        uart->int_rx->save_index = 0;
+
+    /* if the next position is read index, discard this 'read char' */
+    if (uart->int_rx->save_index == uart->int_rx->read_index)
+    {
+        uart->int_rx->read_index ++;
+        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+            uart->int_rx->read_index = 0;
+    }
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    struct serial_device* uart;
+
+    RT_ASSERT(dev != RT_NULL);
+    uart = (struct serial_device*) dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* enable interrupt */
+        UART_ENABLE_IRQ(uart->rx_irq);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+    struct serial_device* uart;
+
+    RT_ASSERT(dev != RT_NULL);
+    uart = (struct serial_device*) dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable interrupt */
+        UART_DISABLE_IRQ(uart->rx_irq);
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer,
+                                 rt_size_t size)
+{
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
+
+    ptr = buffer;
+    err_code = RT_EOK;
+    uart = (struct serial_device*)dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        rt_base_t level;
+
+        /* interrupt mode Rx */
+        while (size)
+        {
+            if (uart->int_rx->read_index != uart->int_rx->save_index)
+            {
+                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+                size --;
+
+                /* disable interrupt */
+                level = rt_hw_interrupt_disable();
+
+                uart->int_rx->read_index ++;
+                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+                    uart->int_rx->read_index = 0;
+
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+            }
+            else
+            {
+                /* set error code */
+                err_code = -RT_EEMPTY;
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* polling mode */
+        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+        {
+            while (uart->uart_device->SSR & SSR_RDRF)
+            {
+                *ptr = uart->uart_device->RDR & 0xff;
+                ptr ++;
+            }
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos,
+                                  const void* buffer, rt_size_t size)
+{
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
+
+    err_code = RT_EOK;
+    ptr = (rt_uint8_t*)buffer;
+    uart = (struct serial_device*)dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* interrupt mode Tx */
+        while (uart->int_tx->save_index != uart->int_tx->write_index)
+        {
+            /* save on tx buffer */
+            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+
+            -- size;
+
+            /* move to next position */
+            uart->int_tx->save_index ++;
+
+            /* wrap save index */
+            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+                uart->int_tx->save_index = 0;
+        }
+
+        /* set error code */
+        if (size > 0)
+            err_code = -RT_EFULL;
+    }
+    else
+    {
+        /* polling mode */
+        while (size)
+        {
+            /*
+             * to be polite with serial console add a line feed
+             * to the carriage return character
+             */
+            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
+            {
+                while (!(uart->uart_device->SSR & SSR_TDRE));
+                uart->uart_device->TDR = '\r';
+            }
+
+            while (!(uart->uart_device->SSR & SSR_TDRE));
+            uart->uart_device->TDR = (*ptr & 0x1FF);
+
+            ++ptr;
+            --size;
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        break;
+
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/*
+ * serial register
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name,
+                               rt_uint32_t flag, struct serial_device *serial)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    device->type 		= RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init 		= rt_serial_init;
+    device->open		= rt_serial_open;
+    device->close		= rt_serial_close;
+    device->read 		= rt_serial_read;
+    device->write 		= rt_serial_write;
+    device->control 	= rt_serial_control;
+    device->user_data	= serial;
+
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+    struct serial_device* uart = (struct serial_device*) device->user_data;
+
+    /* interrupt mode receive */
+    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+    /* save on rx buffer */
+    while (uart->uart_device->SSR & SSR_RDRF)
+    {
+        rt_serial_savechar(uart, uart->uart_device->RDR & 0xff);
+    }
+
+    /* invoke callback */
+    if (device->rx_indicate != RT_NULL)
+    {
+        rt_size_t rx_length;
+
+        /* get rx length */
+        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+                    UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+                    uart->int_rx->save_index - uart->int_rx->read_index;
+
+        device->rx_indicate(device, rx_length);
+    }
+}
+
+#ifdef RT_USING_UART0
+/* UART0 device driver structure */
+#define UART0	FM4_MFS0
+struct serial_int_rx uart0_int_rx;
+struct serial_device uart0 =
+{
+    UART0,
+    MFS0_RX_IRQn,
+    MFS0_TX_IRQn,
+    &uart0_int_rx,
+    RT_NULL
+};
+struct rt_device uart0_device;
+
+void MFS0_RX_IRQHandler(void)
+{	 
+		/* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&uart0_device);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+#endif /**< #ifdef RT_USING_UART0 */
+
+
+void rt_hw_serial_init(void)
+{
+		uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03));
+	
+#ifdef RT_USING_UART0
+     // Initialize ports for MFS0
+		FM4_GPIO->PFR2   = 0x06u;   // P21>SIN0_0, P22>SOT0_0
+		FM4_GPIO->EPFR07 &= 0xFFFFFF0Ful;
+		FM4_GPIO->EPFR07 |= 0x00000040ul;
+		
+		// Initialize MFS to UART asynchronous mode
+		
+		uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+    uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
+    uart0.uart_device->ESCR = ESCR_DATABITS_8;
+    uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+		
+    /* register UART0 device */
+    rt_hw_serial_register(&uart0_device,
+                          "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart0);
+													
+		
+#endif /**< #ifdef RT_USING_UART0 */
+
+}
+
+/*@}*/

bsp/mb9bf568r/drivers/serial.h

@@ -0,0 +1,100 @@
+/*
+ * File      : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2011-05-15     lgnq         modified according bernard's implementaion.      	  	
+ */
+
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#define SMR_SOE          0x01U
+#define SMR_BDS          0x04U
+#define SMR_SBL          0x08U
+#define SMR_WUCR         0x10U
+#define SMR_MD_UART      0x00U
+#define SMR_MD_UART_MP   0x20U
+#define SMR_MD_SIO       0x40U
+#define SMR_MD_LIN       0x60U
+#define SMR_MD_I2C       0x80U
+
+#define SCR_TXE          0x01U
+#define SCR_RXE          0x02U
+#define SCR_TBIE         0x04U
+#define SCR_TIE          0x08U
+#define SCR_RIE          0x10U
+#define SCR_UPGL         0x80U
+
+#define SSR_TBI          0x01U
+#define SSR_TDRE         0x02U
+#define SSR_RDRF         0x04U
+#define SSR_ORE          0x08U
+#define SSR_FRE          0x10U
+#define SSR_PE           0x20U
+#define SSR_REC          0x80U
+
+#define ESCR_P           0x08U
+#define ESCR_PEN         0x10U
+#define ESCR_INV         0x20U
+#define ESCR_ESBL        0x40U
+#define ESCR_FLWEN       0x80U
+#define ESCR_DATABITS_8  0x00U
+#define ESCR_DATABITS_5  0x01U
+#define ESCR_DATABITS_6  0x02U
+#define ESCR_DATABITS_7  0x03U
+#define ESCR_DATABITS_9  0x04U
+
+#define BPS					115200	/* serial baudrate */
+
+#define UART_RX_BUFFER_SIZE		128
+#define UART_TX_BUFFER_SIZE		128
+
+struct serial_int_rx
+{
+	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+	rt_uint32_t read_index, save_index;
+};
+
+struct serial_int_tx
+{
+	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+	rt_uint32_t write_index, save_index;
+};
+
+/*
+ *  Enable/DISABLE Interrupt Controller
+ */
+/* deviation from MISRA-C:2004 Rule 19.7 */
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+struct serial_device
+{
+	FM4_MFS_TypeDef* uart_device;
+	/* irq number */
+	IRQn_Type rx_irq;
+	IRQn_Type tx_irq;
+
+	/* rx structure */
+	struct serial_int_rx* int_rx;
+	/* tx structure */
+	struct serial_int_tx* int_tx;
+};
+
+void rt_hw_serial_isr(rt_device_t device);
+void rt_hw_serial_init(void);
+
+#endif

bsp/mb9bf568r/rtconfig.h

@@ -0,0 +1,74 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX				        8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE			        4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	        64
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND		        100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore */
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+
+/* SECTION: Console options */
+/* #define RT_TINY_SIZE */
+#define RT_USING_CONSOLE
+/* the buffer size of console */
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	        "uart0"
+
+/* SECTION: finsh, a C-Express shell */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_STACK_SIZE         1024
+
+#endif

bsp/mb9bf568r/rtconfig.py

@@ -0,0 +1,82 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+BOARD_NAME = 'lpc408x'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= r'D:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'D:/Keil'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-' + BOARD_NAME + '.map,-cref,-u,Reset_Handler -T rtthread-' + BOARD_NAME + '.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread_' + \
+        BOARD_NAME + '.map --scatter rtthread-' + BOARD_NAME + '.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'

bsp/mb9bf568r/template.uvopt

@@ -0,0 +1,172 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rtthread-fm4</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>4000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>14</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"CMSIS-DAP" -U	 -O175 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(0) -FO15 -FD20000000 -FC8000 -FN2 -FF0MB9B560_1024 -FS00 -FL0100000 -FF1MB9B560_WORK32 -FS1200C0000 -FL18000</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Source Group 1</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+  </Group>
+
+</ProjectOpt>

bsp/mb9bf568r/template.uvproj

@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread-fm4</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>Cortex-M4 FPU</Device>
+          <Vendor>ARM</Vendor>
+          <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId>5237</DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>template_mb9b56xx</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>1</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>14</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>BIN\CMSIS_AGDI.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4105</DriverSelection>
+          </Flash1>
+          <Flash2>BIN\CMSIS_AGDI.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>0</AdsALst>
+            <AdsACrf>0</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>0</AdsLcgr>
+            <AdsLsym>0</AdsLsym>
+            <AdsLszi>0</AdsLszi>
+            <AdsLtoi>0</AdsLtoi>
+            <AdsLsun>0</AdsLsun>
+            <AdsLven>0</AdsLven>
+            <AdsLsxf>0</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>0</hadIROM>
+            <hadIRAM>0</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>0</RoSelD>
+            <RwSelD>5</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>1</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IRAM>
+              <IROM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x200c0000</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20038000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x00000000</DataAddressRange>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Group 1</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>