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[bsp/stm32] add sdram for openmv

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This commit is contained in:
supperthomas
2022-01-04 19:23:26 +08:00
parent 09c089d511
commit e56221c7b1
10 changed files with 826 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/stm32/stm32h743-openmv-h7plus/README.md
+2 -1
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@@ -38,7 +38,8 @@ OPENMV4-H7-PLUS 是 OPENMV公司推出的一款针对 STM32H7系列设计的 Cor
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------: | :------------------------------------- |
| GPIO | 支持 | |
| UART | 支持 | UART1 （console） |
| UART | 支持 | UART1(PB14 TX)(PB15 RX) |
| SDRAM | 支持 | IS42S32800 BANK1 |
## 使用说明
bsp/stm32/stm32h743-openmv-h7plus/applications/main.c
-1
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@@ -12,7 +12,6 @@
#include <rtdevice.h>
#include <board.h>
/* defined the LED2 pin: PB7 */
#define LED1_PIN GET_PIN(C, 0)
int main(void)
bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h
+2 -2
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@@ -50,7 +50,7 @@
/* #define HAL_NOR_MODULE_ENABLED */
/* #define HAL_OTFDEC_MODULE_ENABLED */
/* #define HAL_SRAM_MODULE_ENABLED */
/* #define HAL_SDRAM_MODULE_ENABLED */
#define HAL_SDRAM_MODULE_ENABLED
/* #define HAL_HASH_MODULE_ENABLED */
/* #define HAL_HRTIM_MODULE_ENABLED */
/* #define HAL_HSEM_MODULE_ENABLED */
@@ -168,7 +168,7 @@
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
#define USE_RTOS 0
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Src/main.c
+61 -5
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@@ -42,6 +42,8 @@
UART_HandleTypeDef huart1;
SDRAM_HandleTypeDef hsdram1;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
@@ -50,6 +52,7 @@ UART_HandleTypeDef huart1;
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_USART1_UART_Init(void);
static void MX_FMC_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
@@ -88,6 +91,7 @@ int main(void)
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_USART1_UART_Init();
MX_FMC_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
@@ -117,7 +121,7 @@ void SystemClock_Config(void)
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters
@@ -127,12 +131,12 @@ void SystemClock_Config(void)
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLN = 80;
RCC_OscInitStruct.PLL.PLLM = 3;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
@@ -152,7 +156,7 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
@@ -206,6 +210,53 @@ static void MX_USART1_UART_Init(void)
}
/* FMC initialization function */
static void MX_FMC_Init(void)
{
/* USER CODE BEGIN FMC_Init 0 */
/* USER CODE END FMC_Init 0 */
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
/* USER CODE BEGIN FMC_Init 1 */
/* USER CODE END FMC_Init 1 */
/** Perform the SDRAM1 memory initialization sequence
*/
hsdram1.Instance = FMC_SDRAM_DEVICE;
/* hsdram1.Init */
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
/* SdramTiming */
SdramTiming.LoadToActiveDelay = 2;
SdramTiming.ExitSelfRefreshDelay = 7;
SdramTiming.SelfRefreshTime = 5;
SdramTiming.RowCycleDelay = 6;
SdramTiming.WriteRecoveryTime = 3;
SdramTiming.RPDelay = 2;
SdramTiming.RCDDelay = 2;
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
{
Error_Handler( );
}
/* USER CODE BEGIN FMC_Init 2 */
/* USER CODE END FMC_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
@@ -216,7 +267,12 @@ static void MX_GPIO_Init(void)
GPIO_InitTypeDef GPIO_InitStruct = {0};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
+269
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@@ -21,7 +21,9 @@
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
#ifdef __RTTHREAD__
#include "drv_common.h"
#endif
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@@ -150,6 +152,273 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
}
static uint32_t FMC_Initialized = 0;
static void HAL_FMC_MspInit(void){
/* USER CODE BEGIN FMC_MspInit 0 */
/* USER CODE END FMC_MspInit 0 */
GPIO_InitTypeDef GPIO_InitStruct ={0};
if (FMC_Initialized) {
return;
}
FMC_Initialized = 1;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC;
PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_ENABLE();
/** FMC GPIO Configuration
PE1 ------> FMC_NBL1
PE0 ------> FMC_NBL0
PG15 ------> FMC_SDNCAS
PD0 ------> FMC_D2
PI7 ------> FMC_D29
PI6 ------> FMC_D28
PI5 ------> FMC_NBL3
PD1 ------> FMC_D3
PI3 ------> FMC_D27
PI2 ------> FMC_D26
PI9 ------> FMC_D30
PI4 ------> FMC_NBL2
PH15 ------> FMC_D23
PI1 ------> FMC_D25
PF0 ------> FMC_A0
PI10 ------> FMC_D31
PH13 ------> FMC_D21
PH14 ------> FMC_D22
PI0 ------> FMC_D24
PF2 ------> FMC_A2
PF1 ------> FMC_A1
PG8 ------> FMC_SDCLK
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PH5 ------> FMC_SDNWE
PF5 ------> FMC_A5
PH12 ------> FMC_D20
PG5 ------> FMC_BA1
PG4 ------> FMC_BA0
PH11 ------> FMC_D19
PH10 ------> FMC_D18
PD15 ------> FMC_D1
PG1 ------> FMC_A11
PH8 ------> FMC_D16
PH9 ------> FMC_D17
PD14 ------> FMC_D0
PC4 ------> FMC_SDNE0
PF13 ------> FMC_A7
PG0 ------> FMC_A10
PE13 ------> FMC_D10
PD10 ------> FMC_D15
PC5 ------> FMC_SDCKE0
PF12 ------> FMC_A6
PF15 ------> FMC_A9
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE11 ------> FMC_D8
PE14 ------> FMC_D11
PD9 ------> FMC_D14
PD8 ------> FMC_D13
PF11 ------> FMC_SDNRAS
PF14 ------> FMC_A8
PE7 ------> FMC_D4
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_13|GPIO_PIN_8
|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7
|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
|GPIO_PIN_1|GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_3
|GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_4|GPIO_PIN_1
|GPIO_PIN_10|GPIO_PIN_0;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_5
|GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8
|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_12
|GPIO_PIN_15|GPIO_PIN_11|GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* USER CODE BEGIN FMC_MspInit 1 */
/* USER CODE END FMC_MspInit 1 */
}
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN SDRAM_MspInit 0 */
/* USER CODE END SDRAM_MspInit 0 */
HAL_FMC_MspInit();
/* USER CODE BEGIN SDRAM_MspInit 1 */
/* USER CODE END SDRAM_MspInit 1 */
}
static uint32_t FMC_DeInitialized = 0;
static void HAL_FMC_MspDeInit(void){
/* USER CODE BEGIN FMC_MspDeInit 0 */
/* USER CODE END FMC_MspDeInit 0 */
if (FMC_DeInitialized) {
return;
}
FMC_DeInitialized = 1;
/* Peripheral clock enable */
__HAL_RCC_FMC_CLK_DISABLE();
/** FMC GPIO Configuration
PE1 ------> FMC_NBL1
PE0 ------> FMC_NBL0
PG15 ------> FMC_SDNCAS
PD0 ------> FMC_D2
PI7 ------> FMC_D29
PI6 ------> FMC_D28
PI5 ------> FMC_NBL3
PD1 ------> FMC_D3
PI3 ------> FMC_D27
PI2 ------> FMC_D26
PI9 ------> FMC_D30
PI4 ------> FMC_NBL2
PH15 ------> FMC_D23
PI1 ------> FMC_D25
PF0 ------> FMC_A0
PI10 ------> FMC_D31
PH13 ------> FMC_D21
PH14 ------> FMC_D22
PI0 ------> FMC_D24
PF2 ------> FMC_A2
PF1 ------> FMC_A1
PG8 ------> FMC_SDCLK
PF3 ------> FMC_A3
PF4 ------> FMC_A4
PH5 ------> FMC_SDNWE
PF5 ------> FMC_A5
PH12 ------> FMC_D20
PG5 ------> FMC_BA1
PG4 ------> FMC_BA0
PH11 ------> FMC_D19
PH10 ------> FMC_D18
PD15 ------> FMC_D1
PG1 ------> FMC_A11
PH8 ------> FMC_D16
PH9 ------> FMC_D17
PD14 ------> FMC_D0
PC4 ------> FMC_SDNE0
PF13 ------> FMC_A7
PG0 ------> FMC_A10
PE13 ------> FMC_D10
PD10 ------> FMC_D15
PC5 ------> FMC_SDCKE0
PF12 ------> FMC_A6
PF15 ------> FMC_A9
PE8 ------> FMC_D5
PE9 ------> FMC_D6
PE11 ------> FMC_D8
PE14 ------> FMC_D11
PD9 ------> FMC_D14
PD8 ------> FMC_D13
PF11 ------> FMC_SDNRAS
PF14 ------> FMC_A8
PE7 ------> FMC_D4
PE10 ------> FMC_D7
PE12 ------> FMC_D9
PE15 ------> FMC_D12
*/
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_13|GPIO_PIN_8
|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7
|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
|GPIO_PIN_1|GPIO_PIN_0);
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8);
HAL_GPIO_DeInit(GPIOI, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_3
|GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_4|GPIO_PIN_1
|GPIO_PIN_10|GPIO_PIN_0);
HAL_GPIO_DeInit(GPIOH, GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_5
|GPIO_PIN_12|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8
|GPIO_PIN_9);
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_3
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_12
|GPIO_PIN_15|GPIO_PIN_11|GPIO_PIN_14);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5);
/* USER CODE BEGIN FMC_MspDeInit 1 */
/* USER CODE END FMC_MspDeInit 1 */
}
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
/* USER CODE BEGIN SDRAM_MspDeInit 0 */
/* USER CODE END SDRAM_MspDeInit 0 */
HAL_FMC_MspDeInit();
/* USER CODE BEGIN SDRAM_MspDeInit 1 */
/* USER CODE END SDRAM_MspDeInit 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
bsp/stm32/stm32h743-openmv-h7plus/board/CubeMX_Config/CubeMX_Config.ioc
+413 -63
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File diff suppressed because it is too large Load Diff
bsp/stm32/stm32h743-openmv-h7plus/board/Kconfig
+4 -1
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@@ -45,7 +45,10 @@ menu "On-chip Peripheral Drivers"
depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
default n
endif
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
source "../libraries/HAL_Drivers/Kconfig"
endmenu
bsp/stm32/stm32h743-openmv-h7plus/board/SConscript
+1
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@@ -14,6 +14,7 @@ CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
path = [cwd]
path += [cwd + '/CubeMX_Config/Core/Inc']
path += [cwd + '/ports']
startup_path_prefix = SDK_LIB
bsp/stm32/stm32h743-openmv-h7plus/board/board.c
+6 -6
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@@ -14,7 +14,7 @@
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
/** Supply configuration update enable
@@ -22,7 +22,7 @@ void SystemClock_Config(void)
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters
@@ -32,12 +32,12 @@ void SystemClock_Config(void)
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLN = 80;
RCC_OscInitStruct.PLL.PLLM = 3;
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
@@ -57,7 +57,7 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{
Error_Handler();
}
bsp/stm32/stm32h743-openmv-h7plus/board/ports/sdram_port.h
+68
View File
@@ -0,0 +1,68 @@
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-12-14 supperthomas The first version for STM32H7xx
*/
#ifndef __SDRAM_PORT_H__
#define __SDRAM_PORT_H__
/* parameters for sdram peripheral */
/* Bank1 or Bank2 */
#define SDRAM_TARGET_BANK 1
/* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
/* data width: 8, 16, 32 */
#define SDRAM_DATA_WIDTH 32
/* column bit numbers: 8, 9, 10, 11 */
#define SDRAM_COLUMN_BITS 9
/* row bit numbers: 11, 12, 13 */
#define SDRAM_ROW_BITS 12
/* cas latency clock number: 1, 2, 3 */
#define SDRAM_CAS_LATENCY 2
/* read pipe delay: 0, 1, 2 */
#define SDRAM_RPIPE_DELAY 0
/* clock divid: 2, 3 */
#define SDCLOCK_PERIOD 2
/* refresh rate counter */
#define SDRAM_REFRESH_RATE (64) // ms
#define SDRAM_FREQUENCY (100000) // 100 MHz
#define SDRAM_REFRESH_CYCLES 4096
#define SDRAM_REFRESH_COUNT (SDRAM_REFRESH_RATE * SDRAM_FREQUENCY / SDRAM_REFRESH_CYCLES - 20) //((uint32_t)0x02A5)
#define SDRAM_SIZE (32 * 1024 * 1024)
/* Timing configuration for W9825G6KH-6 */
/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
/* TMRD: 2 Clock cycles */
#define LOADTOACTIVEDELAY 2
/* TXSR: 8x10ns */
#define EXITSELFREFRESHDELAY 7
/* TRAS: 5x10ns */
#define SELFREFRESHTIME 5
/* TRC: 7x10ns */
#define ROWCYCLEDELAY 6
/* TWR: 2 Clock cycles */
#define WRITERECOVERYTIME 3
/* TRP: 2x10ns */
#define RPDELAY 2
/* TRCD: 2x10ns */
#define RCDDELAY 2
/* memory mode register */
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
#endif