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add bsp lpc54102
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
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*
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* $Date: 17. January 2013
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* $Revision: V1.4.1
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*
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* Project: CMSIS DSP Library
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* Title: arm_common_tables.h
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*
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* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
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*
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* Target Processor: Cortex-M4/Cortex-M3
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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||||
* - Neither the name of ARM LIMITED nor the names of its contributors
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||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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||||
* -------------------------------------------------------------------- */
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#ifndef _ARM_COMMON_TABLES_H
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#define _ARM_COMMON_TABLES_H
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#include "arm_math.h"
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extern const uint16_t armBitRevTable[1024];
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extern const q15_t armRecipTableQ15[64];
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extern const q31_t armRecipTableQ31[64];
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extern const q31_t realCoefAQ31[1024];
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extern const q31_t realCoefBQ31[1024];
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extern const float32_t twiddleCoef_16[32];
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extern const float32_t twiddleCoef_32[64];
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extern const float32_t twiddleCoef_64[128];
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extern const float32_t twiddleCoef_128[256];
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extern const float32_t twiddleCoef_256[512];
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extern const float32_t twiddleCoef_512[1024];
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extern const float32_t twiddleCoef_1024[2048];
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extern const float32_t twiddleCoef_2048[4096];
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extern const float32_t twiddleCoef_4096[8192];
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#define twiddleCoef twiddleCoef_4096
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extern const q31_t twiddleCoefQ31[6144];
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extern const q15_t twiddleCoefQ15[6144];
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extern const float32_t twiddleCoef_rfft_32[32];
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extern const float32_t twiddleCoef_rfft_64[64];
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extern const float32_t twiddleCoef_rfft_128[128];
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extern const float32_t twiddleCoef_rfft_256[256];
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extern const float32_t twiddleCoef_rfft_512[512];
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extern const float32_t twiddleCoef_rfft_1024[1024];
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extern const float32_t twiddleCoef_rfft_2048[2048];
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extern const float32_t twiddleCoef_rfft_4096[4096];
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#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
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#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
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#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
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#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
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#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
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#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
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#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
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#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
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#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
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extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
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#endif /* ARM_COMMON_TABLES_H */
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@@ -0,0 +1,22 @@
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# RT-Thread building script for component
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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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src = Split('''
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startup/sysinit.c
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''')
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CPPPATH = [cwd + '/../CMSIS/Include']
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CPPDEFINES = ['CORE_M4']
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# add for startup script
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if rtconfig.CROSS_TOOL == 'gcc':
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src += ['startup/gcc_startup_lpc5410x.c']
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elif rtconfig.CROSS_TOOL == 'keil':
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src += ['startup/keil_startup_lpc5410x.s']
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group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
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Return('group')
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//*****************************************************************************
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// crp.c
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//
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// Source file to create CRP word expected by LPCXpresso IDE linker
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//*****************************************************************************
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//
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// Copyright(C) NXP Semiconductors, 2013
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// All rights reserved.
|
||||
//
|
||||
// Software that is described herein is for illustrative purposes only
|
||||
// which provides customers with programming information regarding the
|
||||
// LPC products. This software is supplied "AS IS" without any warranties of
|
||||
// any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
// all warranties, express or implied, including all implied warranties of
|
||||
// merchantability, fitness for a particular purpose and non-infringement of
|
||||
// intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
// or liability for the use of the software, conveys no license or rights under any
|
||||
// patent, copyright, mask work right, or any other intellectual property rights in
|
||||
// or to any products. NXP Semiconductors reserves the right to make changes
|
||||
// in the software without notification. NXP Semiconductors also makes no
|
||||
// representation or warranty that such application will be suitable for the
|
||||
// specified use without further testing or modification.
|
||||
//
|
||||
// Permission to use, copy, modify, and distribute this software and its
|
||||
// documentation is hereby granted, under NXP Semiconductors' and its
|
||||
// licensor's relevant copyrights in the software, without fee, provided that it
|
||||
// is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
// copyright, permission, and disclaimer notice must appear in all copies of
|
||||
// this code.
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||||
//*****************************************************************************
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#if defined (__CODE_RED)
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#include <NXP/crp.h>
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// Variable to store CRP value in. Will be placed automatically
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// by the linker when "Enable Code Read Protect" selected.
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// See crp.h header for more information
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__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
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#endif
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//*****************************************************************************
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// +--+
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// | ++----+
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// +-++ |
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// | |
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// +-+--+ |
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// | +--+--+
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// +----+ Copyright (c) 2013 Code Red Technologies Ltd.
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//
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// mtb.c
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//
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// Optionally defines an array to be used as a buffer for Micro Trace
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// Buffer (MTB) instruction trace on Cortex-M0+ parts
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//
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// Version : 130502
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//
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// Software License Agreement
|
||||
//
|
||||
// The software is owned by Code Red Technologies and/or its suppliers, and is
|
||||
// protected under applicable copyright laws. All rights are reserved. Any
|
||||
// use in violation of the foregoing restrictions may subject the user to criminal
|
||||
// sanctions under applicable laws, as well as to civil liability for the breach
|
||||
// of the terms and conditions of this license.
|
||||
//
|
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
|
||||
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
|
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// CODE RED TECHNOLOGIES LTD.
|
||||
//
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||||
//*****************************************************************************
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||||
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||||
/*******************************************************************
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||||
* Symbols controlling behavior of this code...
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*
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* __MTB_DISABLE
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* If this symbol is defined, then the buffer array for the MTB
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* will not be created.
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*
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* __MTB_BUFFER_SIZE
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* Symbol specifying the sizer of the buffer array for the MTB.
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* This must be a power of 2 in size, and fit into the available
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* RAM. The MTB buffer will also be aligned to its 'size'
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* boundary and be placed at the start of a RAM bank (which
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* should ensure minimal or zero padding due to alignment).
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||||
*
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||||
* __MTB_RAM_BANK
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* Allows MTB Buffer to be placed into specific RAM bank. When
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* this is not defined, the "default" (first if there are
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* several) RAM bank is used.
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*******************************************************************/
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// Ignore with none Code Red tools
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#if defined (__CODE_RED)
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// Allow MTB to be removed by setting a define (via command line)
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#if !defined (__MTB_DISABLE)
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// Allow for MTB buffer size being set by define set via command line
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// Otherwise provide small default buffer
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#if !defined (__MTB_BUFFER_SIZE)
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#define __MTB_BUFFER_SIZE 128
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#endif
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// Check that buffer size requested is >0 bytes in size
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#if (__MTB_BUFFER_SIZE > 0)
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// Pull in MTB related macros
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#include <cr_mtb_buffer.h>
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// Check if MYTB buffer is to be placed in specific RAM bank
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#if defined(__MTB_RAM_BANK)
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// Place MTB buffer into explicit bank of RAM
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__CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK);
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#else
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// Place MTB buffer into 'default' bank of RAM
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__CR_MTB_BUFFER(__MTB_BUFFER_SIZE);
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#endif // defined(__MTB_RAM_BANK)
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#endif // (__MTB_BUFFER_SIZE > 0)
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#endif // !defined (__MTB_DISABLE)
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#endif // defined (__CODE_RED)
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@@ -0,0 +1,78 @@
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/*
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* @brief Common SystemInit function for LPC54xxx chips
|
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*
|
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* @note
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||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
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****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
/* Clock rate on the CLKIN pin */
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const uint32_t ExtClockIn = 0;
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
/* Set up and initialize hardware prior to call to main */
|
||||
void SystemInit(void)
|
||||
{
|
||||
#if defined(__CODE_RED)
|
||||
extern void(*const g_pfnVectors[]) (void);
|
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SCB->VTOR = (uint32_t) &g_pfnVectors;
|
||||
#else
|
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//extern void *__Vectors;
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//SCB->VTOR = (uint32_t) &isr_vector;
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SCB->VTOR = 0x00000000 & 0x3FFFFF80;
|
||||
#endif
|
||||
|
||||
#if defined(CORE_M4)
|
||||
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
|
||||
fpuInit();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(__MULTICORE_M0SLAVE) && !defined(__MULTICORE_M4SLAVE)
|
||||
/* Chip specific SystemInit */
|
||||
Chip_SystemInit();
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,15 @@
|
||||
# RT-Thread building script for bridge
|
||||
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
@@ -0,0 +1,75 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
|
||||
|
||||
src = Split('''
|
||||
chip_common/fpu_init.c
|
||||
chip_common/iap.c
|
||||
chip_common/ring_buffer.c
|
||||
chip_common/rtc_ut.c
|
||||
|
||||
chip_5410x/chip_5410x.c
|
||||
chip_5410x/clock_5410x.c
|
||||
chip_5410x/crc_5410x.c
|
||||
chip_5410x/fifo_5410x.c
|
||||
chip_5410x/gpiogroup_5410x.c
|
||||
chip_5410x/gpio_5410x.c
|
||||
chip_5410x/hw_adc.c
|
||||
chip_5410x/hw_dmaaltd.c
|
||||
chip_5410x/hw_dmaaltd_rom_api.c
|
||||
chip_5410x/hw_i2cmd.c
|
||||
chip_5410x/hw_i2cmd_rom_api.c
|
||||
chip_5410x/hw_i2cmond.c
|
||||
chip_5410x/hw_i2cmond_rom_api.c
|
||||
chip_5410x/hw_i2csd.c
|
||||
chip_5410x/hw_i2csd_rom_api.c
|
||||
chip_5410x/hw_spimd.c
|
||||
chip_5410x/hw_spimd_rom_api.c
|
||||
chip_5410x/hw_spisd.c
|
||||
chip_5410x/hw_spisd_rom_api.c
|
||||
chip_5410x/hw_uart.c
|
||||
chip_5410x/iocon_5410x.c
|
||||
chip_5410x/pinint_5410x.c
|
||||
chip_5410x/pll_5410x.c
|
||||
chip_5410x/ritimer_5410x.c
|
||||
chip_5410x/romapi_adc.c
|
||||
chip_5410x/romapi_dma.c
|
||||
chip_5410x/romapi_i2cm.c
|
||||
chip_5410x/romapi_i2cmon.c
|
||||
chip_5410x/romapi_i2cs.c
|
||||
chip_5410x/romapi_spim.c
|
||||
chip_5410x/romapi_spis.c
|
||||
chip_5410x/romapi_uart.c
|
||||
chip_5410x/rtc_5410x.c
|
||||
chip_5410x/sct_5410x.c
|
||||
chip_5410x/sct_pwm_5410x.c
|
||||
chip_5410x/stopwatch_5410x.c
|
||||
chip_5410x/syscon_5410x.c
|
||||
chip_5410x/sysinit_5410x.c
|
||||
chip_5410x/timer_5410x.c
|
||||
chip_5410x/utick_5410x.c
|
||||
chip_5410x/wwdt_5410x.c
|
||||
''')
|
||||
|
||||
|
||||
#LIBS = [cwd + '/chip_5410x/power_lib/keil/lib_power']
|
||||
|
||||
#lpc_chip\chip_5410x\power_lib\lpcxpresso
|
||||
# add for startup script
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
LIBPATH = [cwd + '/chip_5410x/power_lib/lpcxpresso']
|
||||
LIBS = ['libpower']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
LIBPATH = [cwd + '/chip_5410x/power_lib/keil']
|
||||
LIBS = ['lib_power']
|
||||
|
||||
CPPPATH = [cwd + '/chip_common',cwd + '/chip_5410x',cwd + '/chip_5410x/config']
|
||||
|
||||
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH,LIBS = LIBS,LIBPATH=LIBPATH)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large.
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@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* @brief LPC5410X Miscellaneous chip specific functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/* System Clock Frequency (Core Clock) */
|
||||
uint32_t SystemCoreClock;
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Update system core clock rate, should be called if the system has
|
||||
a clock rate change */
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
/* CPU core speed (main clock speed adjusted by system clock divider) */
|
||||
SystemCoreClock = Chip_Clock_GetSystemClockRate();
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1 @@
|
||||
dir *.c >C:\Users\Administrator\Desktop\c.txt
|
||||
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* @brief LPC5410x selective CMSIS inclusion file
|
||||
*
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_H_
|
||||
#define __CMSIS_H_
|
||||
|
||||
#include "lpc_types.h"
|
||||
#include "sys_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Select correct CMSIS include file based on CORE_* definition */
|
||||
#if defined(CORE_M4)
|
||||
#include "cmsis_5410x.h"
|
||||
typedef LPC5410X_IRQn_Type IRQn_Type;
|
||||
#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
|
||||
#elif defined(CORE_M0PLUS)
|
||||
#include "cmsis_5410x_m0.h"
|
||||
typedef LPC5410X_M0_IRQn_Type IRQn_Type;
|
||||
#include "core_cm0plus.h" /*!< Cortex-M0 Plus processor and core peripherals */
|
||||
#else
|
||||
#error "No CORE_* definition is defined"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CMSIS_H_ */
|
||||
@@ -0,0 +1,48 @@
|
||||
<LPCOpenCfg>
|
||||
<symbol options="default" name="varChipConfigDir" value="${varChipLibSrcDir}/config"/>
|
||||
<symbol options="default" name="varCPUCore" value="m4"/>
|
||||
<symbol options="default" name="varPMULibName_m4" value="power"/>
|
||||
<symbol options="default" name="varPMULibName_m0plus" value="power_m0"/>
|
||||
<symbol name="varExampleName" value="${prjCurrClassName}_${prjCurrExampleName}"/> <!-- FIXME: Need to append class name -->
|
||||
<symbol name="varSysinitDir" value="${prjDestToRoot}/${prjExampleBaseDir}/startup"/>
|
||||
|
||||
<module name="core_${varCPUCore}"/>
|
||||
<template section="filelist" name="${varChipLibName}" tool="xpresso">
|
||||
<import src="${varChipConfigDir}" dest="inc">
|
||||
<include>*.h</include>
|
||||
</import>
|
||||
</template>
|
||||
<template section="import" name="${varChipLibName}_inc1" tool="xpresso">
|
||||
<copy>../chip_common/error.h</copy>
|
||||
<copy>../chip_common/iap.h</copy>
|
||||
<copy>../chip_common/packing.h</copy>
|
||||
<copy>../chip_common/rtc_ut.h</copy>
|
||||
<copy>../chip_common/stopwatch.h</copy>
|
||||
</template>
|
||||
<template section="import" name="${varChipLibName}_src1" tool="xpresso">
|
||||
<copy>../chip_common/iap.c</copy>
|
||||
<copy>../chip_common/rtc_ut.c</copy>
|
||||
</template>
|
||||
<template section="filelist" name="${varChipLibName}" tool="xpresso">
|
||||
<import src="${varChipLibSrcDir}/power_lib/lpcxpresso" dest="libs">
|
||||
<copy>lib${varPMULibName_${varCPUCore}}.a</copy>
|
||||
</import>
|
||||
</template>
|
||||
<template section="import" name="${varExampleEnable}_startup" tool="xpresso">
|
||||
<copy>crp.c</copy>
|
||||
</template>
|
||||
<template section="cfglist" tool="xpresso" name="${varExampleEnable}">
|
||||
<setting id="linker.crp">
|
||||
<value>true</value>
|
||||
</setting>
|
||||
</template>
|
||||
<template tool="xpresso" section="cfglist" name="${varExampleEnable}">
|
||||
<setting id="linker.paths">
|
||||
<value>${workspace_loc:/${varChipLibName}/libs}</value>
|
||||
</setting>
|
||||
<!-- FIXME: These must be single -->
|
||||
<setting id="linker.libs">
|
||||
<value>${varPMULibName_${varCPUCore}}</value>
|
||||
</setting>
|
||||
</template>
|
||||
</LPCOpenCfg>
|
||||
@@ -0,0 +1,172 @@
|
||||
/*
|
||||
* @brief Basic CMSIS include file for LPC5410x M4 core
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_5410X_H_
|
||||
#define __CMSIS_5410X_H_
|
||||
|
||||
#include "lpc_types.h"
|
||||
#include "sys_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup CMSIS_5410X_M4 CHIP: LPC5410X M4 core CMSIS include file
|
||||
* @ingroup CHIP_5410X_CMSIS_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
// Kill warning "#pragma push with no matching #pragma pop"
|
||||
#pragma diag_suppress 2525
|
||||
#pragma push
|
||||
#pragma anon_unions
|
||||
#elif defined(__CWCC__)
|
||||
#pragma push
|
||||
#pragma cpp_extensions on
|
||||
#elif defined(__GNUC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined(__IAR_SYSTEMS_ICC__)
|
||||
// #pragma push // FIXME not usable for IAR
|
||||
#pragma language=extended
|
||||
#else
|
||||
#error Not supported compiler type
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ---------- Interrupt Number Definition -----------------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
#if !defined(CORE_M4)
|
||||
#error "CORE_M4 is not defined"
|
||||
#endif
|
||||
|
||||
/** @defgroup CMSIS_5410X_M4_IRQ CHIP_5410X: LPC5410X M4 core peripheral interrupt numbers
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
|
||||
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
|
||||
|
||||
/****** LPC5410X Specific Interrupt Numbers ********************************************************/
|
||||
WDT_IRQn = 0, /*!< WWDT */
|
||||
BOD_IRQn = 1, /*!< BOD */
|
||||
Reserved2_IRQn = 2, /*!< Reserved Interrupt */
|
||||
DMA_IRQn = 3, /*!< DMA */
|
||||
GINT0_IRQn = 4, /*!< GINT0 */
|
||||
PIN_INT0_IRQn = 5, /*!< PININT0 */
|
||||
PIN_INT1_IRQn = 6, /*!< PININT1 */
|
||||
PIN_INT2_IRQn = 7, /*!< PININT2 */
|
||||
PIN_INT3_IRQn = 8, /*!< PININT3 */
|
||||
UTICK_IRQn = 9, /*!< Micro-tick Timer interrupt */
|
||||
MRT_IRQn = 10, /*!< Multi-rate timer interrupt */
|
||||
CT32B0_IRQn = 11, /*!< CTMR0 */
|
||||
CT32B1_IRQn = 12, /*!< CTMR1 */
|
||||
CT32B2_IRQn = 13, /*!< CTMR2 */
|
||||
CT32B3_IRQn = 14, /*!< CTMR3 */
|
||||
CT32B4_IRQn = 15, /*!< CTMR4 */
|
||||
SCT0_IRQn = 16, /*!< SCT */
|
||||
UART0_IRQn = 17, /*!< UART0 */
|
||||
UART1_IRQn = 18, /*!< UART1 */
|
||||
UART2_IRQn = 19, /*!< UART2 */
|
||||
UART3_IRQn = 20, /*!< UART3 */
|
||||
I2C0_IRQn = 21, /*!< I2C0 */
|
||||
I2C1_IRQn = 22, /*!< I2C1 */
|
||||
I2C2_IRQn = 23, /*!< I2C2 */
|
||||
SPI0_IRQn = 24, /*!< SPI0 */
|
||||
SPI1_IRQn = 25, /*!< SPI1 */
|
||||
ADC_SEQA_IRQn = 26, /*!< ADC0 sequence A completion */
|
||||
ADC_SEQB_IRQn = 27, /*!< ADC0 sequence B completion */
|
||||
ADC_THCMP_IRQn = 28, /*!< ADC0 threshold compare and error */
|
||||
RTC_IRQn = 29, /*!< RTC alarm and wake-up interrupts */
|
||||
Reserved30_IRQn = 30, /*!< Reserved Interrupt */
|
||||
MAILBOX_IRQn = 31, /*!< Mailbox */
|
||||
GINT1_IRQn = 32, /*!< GINT1 */
|
||||
PIN_INT4_IRQn = 33, /*!< External Interrupt 4 */
|
||||
PIN_INT5_IRQn = 34, /*!< External Interrupt 5 */
|
||||
PIN_INT6_IRQn = 35, /*!< External Interrupt 6 */
|
||||
PIN_INT7_IRQn = 36, /*!< External Interrupt 7 */
|
||||
Reserved37_IRQn = 37, /*!< Reserved Interrupt */
|
||||
Reserved38_IRQn = 38, /*!< Reserved Interrupt */
|
||||
Reserved39_IRQn = 39, /*!< Reserved Interrupt */
|
||||
RIT_IRQn = 40, /*!< Repetitive Interrupt Timer */
|
||||
Reserved41_IRQn = 41, /*!< Reserved Interrupt */
|
||||
Reserved42_IRQn = 42, /*!< Reserved Interrupt */
|
||||
Reserved43_IRQn = 43, /*!< Reserved Interrupt */
|
||||
Reserved44_IRQn = 44, /*!< Reserved Interrupt */
|
||||
} LPC5410X_IRQn_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ----------- Processor and Core Peripheral Section ------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
/** @defgroup CMSIS_5410X_M4_COMMON CHIP: LPC5410X M4 core Cortex CMSIS definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Configuration of the Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __FPU_PRESENT 1
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CMSIS_5410X_H_ */
|
||||
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* @brief Basic CMSIS include file for LPC5410x M0+ core
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_5410X_M0_H_
|
||||
#define __CMSIS_5410X_M0_H_
|
||||
|
||||
#include "lpc_types.h"
|
||||
#include "sys_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup CMSIS_5410X_M0 CHIP: LPC5410X M0 core CMSIS include file
|
||||
* @ingroup CHIP_5410X_CMSIS_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
// Kill warning "#pragma push with no matching #pragma pop"
|
||||
#pragma diag_suppress 2525
|
||||
#pragma push
|
||||
#pragma anon_unions
|
||||
#elif defined(__CWCC__)
|
||||
#pragma push
|
||||
#pragma cpp_extensions on
|
||||
#elif defined(__GNUC__)
|
||||
/* anonymous unions are enabled by default */
|
||||
#elif defined(__IAR_SYSTEMS_ICC__)
|
||||
// #pragma push // FIXME not usable for IAR
|
||||
#pragma language=extended
|
||||
#else
|
||||
#error Not supported compiler type
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ---------- Interrupt Number Definition -----------------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
#if !defined(CORE_M0PLUS)
|
||||
#error "CORE_M0PLUS is not defined"
|
||||
#endif
|
||||
|
||||
/** @defgroup CMSIS_5410X_M0_IRQ CHIP_5410X: LPC5410X M0 core peripheral interrupt numbers
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
|
||||
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
|
||||
|
||||
/****** LPC5410X Specific Interrupt Numbers ********************************************************/
|
||||
WDT_IRQn = 0, /*!< WWDT */
|
||||
BOD_IRQn = 1, /*!< BOD */
|
||||
Reserved2_IRQn = 2, /*!< Reserved Interrupt */
|
||||
DMA_IRQn = 3, /*!< DMA */
|
||||
GINT0_IRQn = 4, /*!< GINT0 */
|
||||
PIN_INT0_IRQn = 5, /*!< PININT0 */
|
||||
PIN_INT1_IRQn = 6, /*!< PININT1 */
|
||||
PIN_INT2_IRQn = 7, /*!< PININT2 */
|
||||
PIN_INT3_IRQn = 8, /*!< PININT3 */
|
||||
UTICK_IRQn = 9, /*!< Micro-tick Timer interrupt */
|
||||
MRT_IRQn = 10, /*!< Multi-rate timer interrupt */
|
||||
CT32B0_IRQn = 11, /*!< CTMR0 */
|
||||
CT32B1_IRQn = 12, /*!< CTMR1 */
|
||||
CT32B2_IRQn = 13, /*!< CTMR2 */
|
||||
CT32B3_IRQn = 14, /*!< CTMR3 */
|
||||
CT32B4_IRQn = 15, /*!< CTMR4 */
|
||||
SCT0_IRQn = 16, /*!< SCT */
|
||||
UART0_IRQn = 17, /*!< UART0 */
|
||||
UART1_IRQn = 18, /*!< UART1 */
|
||||
UART2_IRQn = 19, /*!< UART2 */
|
||||
UART3_IRQn = 20, /*!< UART3 */
|
||||
I2C0_IRQn = 21, /*!< I2C0 */
|
||||
I2C1_IRQn = 22, /*!< I2C1 */
|
||||
I2C2_IRQn = 23, /*!< I2C2 */
|
||||
SPI0_IRQn = 24, /*!< SPI0 */
|
||||
SPI1_IRQn = 25, /*!< SPI1 */
|
||||
ADC_SEQA_IRQn = 26, /*!< ADC0 sequence A completion */
|
||||
ADC_SEQB_IRQn = 27, /*!< ADC0 sequence B completion */
|
||||
ADC_THCMP_IRQn = 28, /*!< ADC0 threshold compare and error */
|
||||
RTC_IRQn = 29, /*!< RTC alarm and wake-up interrupts */
|
||||
Reserved30_IRQn = 30, /*!< Reserved Interrupt */
|
||||
MAILBOX_IRQn = 31, /*!< Mailbox */
|
||||
} LPC5410X_M0_IRQn_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ----------- Processor and Core Peripheral Section ------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
/** @defgroup CMSIS_5410X_M0_COMMON CHIP: LPC5410X M0 core Cortex CMSIS definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
|
||||
#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CMSIS_5410X_M0_H_ */
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __SYS_CONFIG_H_
|
||||
#define __SYS_CONFIG_H_
|
||||
|
||||
/* Build for LPC5410X chip family */
|
||||
#define CHIP_LPC5410X
|
||||
|
||||
/* Define ROMDRIVERSV2_PRESENT to enable v2 driver support in ROM. For LPC54xxx
|
||||
devices with boot ROM version 17.2 and later, this should be defined.
|
||||
For earlier versions, this should not be defined. If the definitions is
|
||||
not defined, the same v2 drivers will be used, but will use a version that
|
||||
is located in FLASH instead. */
|
||||
// #define ROMDRIVERSV2_PRESENT
|
||||
|
||||
#endif /* __SYS_CONFIG_H_ */
|
||||
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* @brief LPC5410X CPU multi-core support driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __CPUCTRL_5410X_H_
|
||||
#define __CPUCTRL_5410X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup CPUCTRL_5410X CHIP: LPC5410X CPU multi-core support driver
|
||||
* @ingroup CHIP_5410X_DRIVERS
|
||||
* This driver helps with determine which MCU core the software is running,
|
||||
* whether the MCU core is in master or slave mode, and provides functions
|
||||
* for master and slave core control.<br>
|
||||
*
|
||||
* The functions for the driver are provided as part of the
|
||||
* @ref POWER_LIBRARY_5410X library. For more information on using the
|
||||
* LPC5410x LPCopen package with multi-core, see @ref CHIP_5410X_MULTICORE<br>.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Determine which MCU this code is running on
|
||||
* @return true if executing on the CM4, or false if executing on the CM0+
|
||||
*/
|
||||
STATIC INLINE bool Chip_CPU_IsM4Core(void) {
|
||||
/* M4 core is designated by values 0xC24 on bits 15..4 */
|
||||
if (((SCB->CPUID >> 4) & 0xFFF) == 0xC24) {
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Determine if this core is a slave or master
|
||||
* @return true if this MCU is operating as the master, or false if operating as a slave
|
||||
*/
|
||||
bool Chip_CPU_IsMasterCore(void);
|
||||
|
||||
/**
|
||||
* @brief Setup M0+ boot and reset M0+ core
|
||||
* @param coentry : Pointer to boot entry point for M0+ core
|
||||
* @param costackptr : Pointer to where stack should be located for M0+ core
|
||||
* @return Nothing
|
||||
* @note Will setup boot stack and entry point, enable M0+ clock and then
|
||||
* reset M0+ core.
|
||||
*/
|
||||
void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr);
|
||||
|
||||
/**
|
||||
* @brief Setup M4 boot and reset M4 core
|
||||
* @param coentry : Pointer to boot entry point for M4 core
|
||||
* @param costackptr : Pointer to where stack should be located for M4 core
|
||||
* @return Nothing
|
||||
* @note Will setup boot stack and entry point, enable M4 clock and then
|
||||
* reset M0+ core.
|
||||
*/
|
||||
void Chip_CPU_CM4Boot(uint32_t *coentry, uint32_t *costackptr);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CPUCTRL_5410X_H_ */
|
||||
@@ -0,0 +1,118 @@
|
||||
/*
|
||||
* @brief LPC5410X Cyclic Redundancy Check (CRC) Engine driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Initialize CRC engine */
|
||||
void Chip_CRC_Init(void)
|
||||
{
|
||||
Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_CRC);
|
||||
Chip_SYSCON_PeriphReset(RESET_CRC);
|
||||
}
|
||||
|
||||
/* De-initialize CRC engine */
|
||||
void Chip_CRC_Deinit(void)
|
||||
{
|
||||
Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_CRC);
|
||||
}
|
||||
|
||||
/* Sets up the CRC engine with defaults based on the polynomial to be used */
|
||||
void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly)
|
||||
{
|
||||
switch (poly) {
|
||||
case CRC_POLY_CRC16:
|
||||
Chip_CRC_UseCRC16();
|
||||
break;
|
||||
|
||||
case CRC_POLY_CRC32:
|
||||
Chip_CRC_UseCRC32();
|
||||
break;
|
||||
|
||||
case CRC_POLY_CCITT:
|
||||
default:
|
||||
Chip_CRC_UseCCITT();
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* configure CRC engine and compute CCITT checksum from 8-bit data */
|
||||
uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes)
|
||||
{
|
||||
Chip_CRC_UseCCITT();
|
||||
while (bytes > 0) {
|
||||
Chip_CRC_Write8(*data);
|
||||
data++;
|
||||
bytes--;
|
||||
}
|
||||
|
||||
return Chip_CRC_Sum();
|
||||
}
|
||||
|
||||
/* Convenience function for computing a standard CRC16 checksum from 16-bit data block */
|
||||
uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords)
|
||||
{
|
||||
Chip_CRC_UseCRC16();
|
||||
while (hwords > 0) {
|
||||
Chip_CRC_Write16(*data);
|
||||
data++;
|
||||
hwords--;
|
||||
}
|
||||
|
||||
return Chip_CRC_Sum();
|
||||
}
|
||||
|
||||
/* Convenience function for computing a standard CRC32 checksum from 32-bit data block */
|
||||
uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words)
|
||||
{
|
||||
Chip_CRC_UseCRC32();
|
||||
while (words > 0) {
|
||||
Chip_CRC_Write32(*data);
|
||||
data++;
|
||||
words--;
|
||||
}
|
||||
|
||||
return Chip_CRC_Sum();
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* @brief LPC5410X GPIO driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* GPIO initilisation function */
|
||||
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
|
||||
{
|
||||
Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO0);
|
||||
Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO1);
|
||||
Chip_SYSCON_PeriphReset(RESET_GPIO0);
|
||||
Chip_SYSCON_PeriphReset(RESET_GPIO1);
|
||||
}
|
||||
|
||||
/* GPIO deinitialisation function */
|
||||
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
|
||||
{
|
||||
Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GPIO0);
|
||||
Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GPIO1);
|
||||
}
|
||||
|
||||
/* Set GPIO direction for a single GPIO pin */
|
||||
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting)
|
||||
{
|
||||
if (setting) {
|
||||
pGPIO->DIR[port] |= 1UL << pin;
|
||||
}
|
||||
else {
|
||||
pGPIO->DIR[port] &= ~(1UL << pin);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set GPIO direction for a single GPIO pin */
|
||||
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
|
||||
{
|
||||
if (output) {
|
||||
Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
|
||||
}
|
||||
else {
|
||||
Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Direction for a GPIO port */
|
||||
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
|
||||
{
|
||||
if (out) {
|
||||
pGPIO->DIR[portNum] |= bitValue;
|
||||
}
|
||||
else {
|
||||
pGPIO->DIR[portNum] &= ~bitValue;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set GPIO direction for a all selected GPIO pins to an input or output */
|
||||
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet)
|
||||
{
|
||||
if (outSet) {
|
||||
Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
|
||||
}
|
||||
else {
|
||||
Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* @brief LPC5410x GPIO group driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* @brief DMA master ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_DMAALTD_H
|
||||
#define __HW_DMAALTD_H
|
||||
|
||||
#include "error.h"
|
||||
#include "hw_dmaaltd_rom_api.h"
|
||||
|
||||
// *** DMA controller functions called by Application Program ***
|
||||
uint32_t dmaalt_get_mem_size(void);
|
||||
|
||||
ROM_DMA_HANDLE_T dmaalt_init(void *mem, const ROM_DMA_INIT_T *pInit);
|
||||
|
||||
ErrorCode_t dmaalt_setup_channel(ROM_DMA_HANDLE_T pHandle, ROM_DMA_CHAN_CFG_T *pCfg, uint8_t dmaCh);
|
||||
|
||||
ErrorCode_t dmaalt_init_queue(ROM_DMA_HANDLE_T pHandle, uint8_t dmaCh, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
void dmaalt_register_queue_callback(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, uint32_t cbIndex, void *pCB);
|
||||
|
||||
ErrorCode_t dmaalt_build_descriptor_chain(ROM_DMA_HANDLE_T pHandle,
|
||||
ROM_DMA_XFERDESC_CFG_T *pXferCfg,
|
||||
ROM_DMA_DESC_T *pDesc,
|
||||
ROM_DMA_DESC_T *pDescPrev);
|
||||
|
||||
uint32_t dmaalt_get_transfer_count(ROM_DMA_HANDLE_T pHandle, ROM_DMA_DESC_T *pDesc);
|
||||
|
||||
void dmaalt_unstall_descriptor_chain(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
void dmaalt_queue_descriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, ROM_DMA_DESC_T *pDescChainHead);
|
||||
|
||||
ROM_DMA_DESC_STS_T dmaalt_get_queue_pop_descriptor_status(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
ROM_DMA_DESC_T *dmaalt_unqueue_descriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
ErrorCode_t dmaalt_start_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
ErrorCode_t dmaalt_stop_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
void dmaalt_flush_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
uint8_t dmaalt_get_queue_state(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
void dmaalt_force_trigger(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
|
||||
|
||||
void dmaalt_handler(ROM_DMA_HANDLE_T pHandle);
|
||||
|
||||
uint32_t dmaalt_get_driver_version(void);
|
||||
|
||||
// ***
|
||||
|
||||
#endif /* __HW_DMAALTD_H */
|
||||
@@ -0,0 +1,147 @@
|
||||
/*
|
||||
* @brief DMA master ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_DMA_REGS_H_
|
||||
#define __HW_DMA_REGS_H_
|
||||
|
||||
/**
|
||||
* @brief DMA Controller shared registers structure
|
||||
*/
|
||||
typedef struct { /*!< DMA shared registers structure */
|
||||
volatile uint32_t ENABLESET; /*!< DMA Channel Enable read and Set for all DMA channels */
|
||||
volatile uint32_t RESERVED0;
|
||||
volatile uint32_t ENABLECLR; /*!< DMA Channel Enable Clear for all DMA channels */
|
||||
volatile uint32_t RESERVED1;
|
||||
volatile uint32_t ACTIVE; /*!< DMA Channel Active status for all DMA channels */
|
||||
volatile uint32_t RESERVED2;
|
||||
volatile uint32_t BUSY; /*!< DMA Channel Busy status for all DMA channels */
|
||||
volatile uint32_t RESERVED3;
|
||||
volatile uint32_t ERRINT; /*!< DMA Error Interrupt status for all DMA channels */
|
||||
volatile uint32_t RESERVED4;
|
||||
volatile uint32_t INTENSET; /*!< DMA Interrupt Enable read and Set for all DMA channels */
|
||||
volatile uint32_t RESERVED5;
|
||||
volatile uint32_t INTENCLR; /*!< DMA Interrupt Enable Clear for all DMA channels */
|
||||
volatile uint32_t RESERVED6;
|
||||
volatile uint32_t INTA; /*!< DMA Interrupt A status for all DMA channels */
|
||||
volatile uint32_t RESERVED7;
|
||||
volatile uint32_t INTB; /*!< DMA Interrupt B status for all DMA channels */
|
||||
volatile uint32_t RESERVED8;
|
||||
volatile uint32_t SETVALID; /*!< DMA Set ValidPending control bits for all DMA channels */
|
||||
volatile uint32_t RESERVED9;
|
||||
volatile uint32_t SETTRIG; /*!< DMA Set Trigger control bits for all DMA channels */
|
||||
volatile uint32_t RESERVED10;
|
||||
volatile uint32_t ABORT; /*!< DMA Channel Abort control for all DMA channels */
|
||||
} LPC_DMA_COMMON_T;
|
||||
|
||||
/**
|
||||
* @brief DMA Controller shared registers structure
|
||||
*/
|
||||
typedef struct { /*!< DMA channel register structure */
|
||||
volatile uint32_t CFG; /*!< DMA Configuration register */
|
||||
volatile uint32_t CTLSTAT; /*!< DMA Control and status register */
|
||||
volatile uint32_t XFERCFG; /*!< DMA Transfer configuration register */
|
||||
volatile uint32_t RESERVED;
|
||||
} LPC_DMA_CHANNEL_T;
|
||||
|
||||
/* On LPC540XX, Max DMA channel is 22 */
|
||||
#define MAX_DMA_CHANNEL (22)
|
||||
|
||||
/**
|
||||
* @brief DMA Controller register block structure
|
||||
*/
|
||||
typedef struct { /*!< DMA Structure */
|
||||
volatile uint32_t CTRL; /*!< DMA control register */
|
||||
volatile uint32_t INTSTAT; /*!< DMA Interrupt status register */
|
||||
volatile uint32_t SRAMBASE; /*!< DMA SRAM address of the channel configuration table */
|
||||
volatile uint32_t RESERVED2[5];
|
||||
LPC_DMA_COMMON_T DMACOMMON[1]; /*!< DMA shared channel (common) registers */
|
||||
volatile uint32_t RESERVED0[225];
|
||||
LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL]; /*!< DMA channel registers */
|
||||
} LPC_DMA_T;
|
||||
|
||||
/* DMA interrupt status bits (common) */
|
||||
#define DMA_INTSTAT_ACTIVEINT 0x2 /*!< Summarizes whether any enabled interrupts are pending */
|
||||
#define DMA_INTSTAT_ACTIVEERRINT 0x4 /*!< Summarizes whether any error interrupts are pending */
|
||||
|
||||
/* Support macro for DMA_CHDESC_T */
|
||||
#define DMA_ADDR(addr) ((uint32_t) (addr))
|
||||
|
||||
/* Support definitions for setting the configuration of a DMA channel. You
|
||||
will need to get more information on these options from the User manual. */
|
||||
#define DMA_CFG_PERIPHREQEN (1 << 0) /*!< Enables Peripheral DMA requests */
|
||||
#define DMA_CFG_HWTRIGEN (1 << 1) /*!< Use hardware triggering via imput mux */
|
||||
#define DMA_CFG_TRIGPOL_LOW (0 << 4) /*!< Hardware trigger is active low or falling edge */
|
||||
#define DMA_CFG_TRIGPOL_HIGH (1 << 4) /*!< Hardware trigger is active high or rising edge */
|
||||
#define DMA_CFG_TRIGTYPE_EDGE (0 << 5) /*!< Hardware trigger is edge triggered */
|
||||
#define DMA_CFG_TRIGTYPE_LEVEL (1 << 5) /*!< Hardware trigger is level triggered */
|
||||
#define DMA_CFG_TRIGBURST_SNGL (0 << 6) /*!< Single transfer. Hardware trigger causes a single transfer */
|
||||
#define DMA_CFG_TRIGBURST_BURST (1 << 6) /*!< Burst transfer (see UM) */
|
||||
#define DMA_CFG_BURSTPOWER_1 (0 << 8) /*!< Set DMA burst size to 1 transfer */
|
||||
#define DMA_CFG_BURSTPOWER_2 (1 << 8) /*!< Set DMA burst size to 2 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_4 (2 << 8) /*!< Set DMA burst size to 4 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_8 (3 << 8) /*!< Set DMA burst size to 8 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_16 (4 << 8) /*!< Set DMA burst size to 16 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_32 (5 << 8) /*!< Set DMA burst size to 32 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_64 (6 << 8) /*!< Set DMA burst size to 64 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_128 (7 << 8) /*!< Set DMA burst size to 128 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_256 (8 << 8) /*!< Set DMA burst size to 256 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_512 (9 << 8) /*!< Set DMA burst size to 512 transfers */
|
||||
#define DMA_CFG_BURSTPOWER_1024 (10 << 8) /*!< Set DMA burst size to 1024 transfers */
|
||||
#define DMA_CFG_BURSTPOWER(n) ((n) << 8) /*!< Set DMA burst size to 2^n transfers, max n=10 */
|
||||
#define DMA_CFG_SRCBURSTWRAP (1 << 14) /*!< Source burst wrapping is enabled for this DMA channel */
|
||||
#define DMA_CFG_DSTBURSTWRAP (1 << 15) /*!< Destination burst wrapping is enabled for this DMA channel */
|
||||
#define DMA_CFG_CHPRIORITY(p) ((p) << 16) /*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */
|
||||
|
||||
/* DMA channel control and status register definitions */
|
||||
#define DMA_CTLSTAT_VALIDPENDING (1 << 0) /*!< Valid pending flag for this channel */
|
||||
#define DMA_CTLSTAT_TRIG (1 << 2) /*!< Trigger flag. Indicates that the trigger for this channel is currently set */
|
||||
|
||||
/* DMA channel transfer configuration registers definitions */
|
||||
#define DMA_XFERCFG_CFGVALID (1 << 0) /*!< Configuration Valid flag */
|
||||
#define DMA_XFERCFG_RELOAD (1 << 1) /*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */
|
||||
#define DMA_XFERCFG_SWTRIG (1 << 2) /*!< Software Trigger */
|
||||
#define DMA_XFERCFG_CLRTRIG (1 << 3) /*!< Clear Trigger */
|
||||
#define DMA_XFERCFG_SETINTA (1 << 4) /*!< Set Interrupt flag A for this channel to fire when descriptor is complete */
|
||||
#define DMA_XFERCFG_SETINTB (1 << 5) /*!< Set Interrupt flag B for this channel to fire when descriptor is complete */
|
||||
#define DMA_XFERCFG_WIDTH_8 (0 << 8) /*!< 8-bit transfers are performed */
|
||||
#define DMA_XFERCFG_WIDTH_16 (1 << 8) /*!< 16-bit transfers are performed */
|
||||
#define DMA_XFERCFG_WIDTH_32 (2 << 8) /*!< 32-bit transfers are performed */
|
||||
#define DMA_XFERCFG_SRCINC_0 (0 << 12) /*!< DMA source address is not incremented after a transfer */
|
||||
#define DMA_XFERCFG_SRCINC_1 (1 << 12) /*!< DMA source address is incremented by 1 (width) after a transfer */
|
||||
#define DMA_XFERCFG_SRCINC_2 (2 << 12) /*!< DMA source address is incremented by 2 (width) after a transfer */
|
||||
#define DMA_XFERCFG_SRCINC_4 (3 << 12) /*!< DMA source address is incremented by 4 (width) after a transfer */
|
||||
#define DMA_XFERCFG_DSTINC_0 (0 << 14) /*!< DMA destination address is not incremented after a transfer */
|
||||
#define DMA_XFERCFG_DSTINC_1 (1 << 14) /*!< DMA destination address is incremented by 1 (width) after a transfer */
|
||||
#define DMA_XFERCFG_DSTINC_2 (2 << 14) /*!< DMA destination address is incremented by 2 (width) after a transfer */
|
||||
#define DMA_XFERCFG_DSTINC_4 (3 << 14) /*!< DMA destination address is incremented by 4 (width) after a transfer */
|
||||
#define DMA_XFERCFG_XFERCOUNT(n) ((n - 1) << 16) /*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */
|
||||
|
||||
#endif /* __HW_DMA_REGS_H_ */
|
||||
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* @brief DMA controller ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "hw_dmaaltd.h"
|
||||
|
||||
const ROM_DMAALTD_API_T dmaalt_api = {
|
||||
&dmaalt_get_mem_size,
|
||||
&dmaalt_init,
|
||||
&dmaalt_setup_channel,
|
||||
&dmaalt_init_queue,
|
||||
&dmaalt_register_queue_callback,
|
||||
&dmaalt_build_descriptor_chain,
|
||||
&dmaalt_get_transfer_count,
|
||||
&dmaalt_unstall_descriptor_chain,
|
||||
&dmaalt_queue_descriptor,
|
||||
&dmaalt_get_queue_pop_descriptor_status,
|
||||
&dmaalt_unqueue_descriptor,
|
||||
&dmaalt_start_queue,
|
||||
&dmaalt_stop_queue,
|
||||
&dmaalt_flush_queue,
|
||||
&dmaalt_get_queue_state,
|
||||
&dmaalt_force_trigger,
|
||||
&dmaalt_handler,
|
||||
&dmaalt_get_driver_version
|
||||
}; // end of table ************************************
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* @brief I2C master ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_I2CMD_H
|
||||
#define __HW_I2CMD_H
|
||||
|
||||
#include "error.h"
|
||||
#include "hw_i2cmd_rom_api.h"
|
||||
|
||||
// *** I2C functions called by Application Program ***
|
||||
uint32_t i2cm_get_mem_size(void);
|
||||
|
||||
ROM_I2CM_HANDLE_T i2cm_init(void *mem, const ROM_I2CM_INIT_T *pInit);
|
||||
|
||||
uint32_t i2cm_set_clock_rate(ROM_I2CM_HANDLE_T pHandle, uint32_t inRate, uint32_t i2cRate);
|
||||
|
||||
void i2cm_register_callback(ROM_I2CM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB);
|
||||
|
||||
ErrorCode_t i2cm_transfer(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_XFER_T *pXfer);
|
||||
|
||||
void i2cm_transfer_handler(ROM_I2CM_HANDLE_T pHandle);
|
||||
|
||||
uint32_t i2cm_get_driver_version(void);
|
||||
|
||||
// ***
|
||||
|
||||
#endif /* __HW_I2CMD_H */
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* @brief I2C master ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "hw_i2cmd.h"
|
||||
|
||||
// This creates a table with the addresses of all the I2C functions
|
||||
// This table of function pointers is the API interface.
|
||||
const ROM_I2CMD_API_T i2cm_api = {
|
||||
&i2cm_get_mem_size,
|
||||
&i2cm_init,
|
||||
&i2cm_set_clock_rate,
|
||||
&i2cm_register_callback,
|
||||
&i2cm_transfer,
|
||||
&i2cm_transfer_handler,
|
||||
&i2cm_get_driver_version,
|
||||
}; // end of table ************************************
|
||||
@@ -0,0 +1,127 @@
|
||||
/*
|
||||
* @brief I2C master ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_I2CMD_ROM_API_H
|
||||
#define __HW_I2CMD_ROM_API_H
|
||||
|
||||
#include "stdint.h" // added to define uint32_t, etc.
|
||||
#include "error.h"
|
||||
#include "packing.h"
|
||||
#include "hw_i2c_common.h"
|
||||
|
||||
/** @defgroup ROMAPI_I2CM I2C master ROM driver functions and definitions
|
||||
* @ingroup ROMAPI_I2CM_WRAPPER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief I2C master handle type */
|
||||
typedef void *ROM_I2CM_HANDLE_T;
|
||||
|
||||
/** @brief User context conversion macro
|
||||
* Macro used to extract the user defined data pointer from a I2C master
|
||||
* handle context.<br>
|
||||
* To get a user context, simple use the macro on the drivers handle:
|
||||
* void *pUserData = (void *) ROM_I2CM_HANDLE_TOUDATA(driverHandle);
|
||||
*/
|
||||
#define ROM_I2CM_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p)
|
||||
|
||||
/** @brief I2C master optional transfer flags */
|
||||
#define ROM_I2CM_FLAG_BLOCKING (1UL << 31) /*!< Transfer function will block until complete */
|
||||
#define ROM_I2CM_FLAG_DMATX (1UL << 30) /*!< DMA will be used for TX, requires DMA setup outside of the driver */
|
||||
#define ROM_I2CM_FLAG_DMARX (1UL << 29) /*!< DMA will be used for RX, requires DMA setup outside of the driver */
|
||||
#define ROM_I2CM_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */
|
||||
|
||||
/** @brief Master transfer descriptor */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
const void *txBuff; /*!< Pointer to array of bytes to be transmitted */
|
||||
void *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */
|
||||
volatile ErrorCode_t status; /*!< Packed status of the current I2C transfer (ErrorCode_t), must be 32-bits */
|
||||
uint32_t flags; /*!< Optional transfer flags */
|
||||
uint16_t txSz; /*!< Number of bytes in transmit array, if 0 only receive transfer will be performed */
|
||||
uint16_t rxSz; /*!< Number of bytes to receive, if 0 only transmission we be performed */
|
||||
uint16_t slaveAddr; /*!< 7-bit I2C Slave address */
|
||||
uint16_t reserved; /*!< Reserved for alignment */
|
||||
} ROM_I2CM_XFER_T;
|
||||
|
||||
/** I2C master callback IDs */
|
||||
typedef enum {
|
||||
ROM_I2CM_DATACOMPLETE_CB = 0, /*!< Callback ID for I2C master data transfer complete */
|
||||
ROM_I2CM_DATATRANSMITSTART_CB, /*!< Callback ID for I2C master transmit start */
|
||||
ROM_I2CM_DATATRECEIVESTART_CB /*!< Callback ID for I2C master receive start */
|
||||
} ROM_I2CM_CALLBACK_T;
|
||||
|
||||
/** @brief I2C master transfer complete callback prototype
|
||||
* The I2C master state machine will call this function when the transfer completes normally
|
||||
* or due to an error (NAK, arbitration, etc.).
|
||||
*/
|
||||
typedef void (*i2cMasterCompleteCB)(ROM_I2CM_HANDLE_T i2cmHandle, ROM_I2CM_XFER_T *pXfer);
|
||||
|
||||
/** @brief I2C master data receive start callback
|
||||
* The I2C master state machine will call this optional function prior to data transfer.
|
||||
* The callback can be used to setup DMA or alter the receive buffer size. The callback is
|
||||
* only called if it has been registered and the receive size (rxSz) in the transfer descriptor
|
||||
* is 0.
|
||||
*/
|
||||
typedef void (*i2cMasterReceiveStartCB)(ROM_I2CM_HANDLE_T i2cmHandle, ROM_I2CM_XFER_T *pXfer);
|
||||
|
||||
/** @brief I2C master data transmit start callback
|
||||
* The I2C master state machine will call this optional function prior to data transfer.
|
||||
* The callback can be used to setup DMA or alter the transmit buffer size. The callback is
|
||||
* only called if it has been registered and the transmit size (txSz) in the transfer descriptor
|
||||
* is 0.
|
||||
*/
|
||||
typedef void (*i2cMasterTransmitStartCB)(ROM_I2CM_HANDLE_T i2cmHandle, ROM_I2CM_XFER_T *pXfer);
|
||||
|
||||
/** @brief I2C master initialization structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
|
||||
uint32_t base; /*!< Base address of I2C peripheral to use */
|
||||
} ROM_I2CM_INIT_T;
|
||||
|
||||
/** @brief I2C master ROM indirect function structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of I2C master driver */
|
||||
ROM_I2CM_HANDLE_T (*Init)(void *mem, const ROM_I2CM_INIT_T *pInit); /*!< Initializes the I2C master driver and peripheral */
|
||||
uint32_t (*SetClockRate)(ROM_I2CM_HANDLE_T pHandle, uint32_t inRate, uint32_t i2cRate); /*!< Sets the I2C master clock rate */
|
||||
void (*RegisterCallback)(ROM_I2CM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an I2C master callback */
|
||||
ErrorCode_t (*Transfer)(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_XFER_T *pXfer); /*!< Perform or start and I2C master transfer */
|
||||
void (*TransferHandler)(ROM_I2CM_HANDLE_T pHandle); /*!< I2C master transfer (interrupt) handler */
|
||||
uint32_t (*GetDriverVersion)(void);
|
||||
} ROM_I2CMD_API_T;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
extern const ROM_I2CMD_API_T i2cm_api; // so application program can access pointer to
|
||||
// function table
|
||||
|
||||
#endif /* __HW_I2CMD_ROM_API_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,53 @@
|
||||
/*
|
||||
* @brief I2C monitor ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_I2CMOND_H
|
||||
#define __HW_I2CMOND_H
|
||||
|
||||
#include "error.h"
|
||||
#include "hw_i2cmond_rom_api.h"
|
||||
|
||||
// *** I2C functions called by Application Program ***
|
||||
uint32_t i2cmon_get_mem_size(void);
|
||||
|
||||
ROM_I2CMON_HANDLE_T i2cmon_init(void *mem, const ROM_I2CMON_INIT_T *pInit);
|
||||
|
||||
void i2cmom_register_callback(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, void *pCB);
|
||||
|
||||
ErrorCode_t i2cmom_start_log(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap);
|
||||
|
||||
void i2cmon_transfer_handler(ROM_I2CMON_HANDLE_T pHandle);
|
||||
|
||||
uint32_t i2cmon_get_driver_version(void);
|
||||
|
||||
// ***
|
||||
|
||||
#endif /* __HW_I2CMOND_H */
|
||||
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* @brief I2C monitor ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "hw_i2cmond.h"
|
||||
|
||||
// This creates a table with the addresses of all the I2C functions
|
||||
// This table of function pointers is the API interface.
|
||||
const ROM_I2CMOND_API_T i2cmon_api = {
|
||||
&i2cmon_get_mem_size,
|
||||
&i2cmon_init,
|
||||
&i2cmom_register_callback,
|
||||
&i2cmom_start_log,
|
||||
&i2cmon_transfer_handler,
|
||||
&i2cmon_get_driver_version,
|
||||
}; // end of table ************************************
|
||||
@@ -0,0 +1,112 @@
|
||||
/*
|
||||
* @brief I2C monitor ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_I2CMOND_ROM_API_H
|
||||
#define __HW_I2CMOND_ROM_API_H
|
||||
|
||||
#include "stdint.h" // added to define uint32_t, etc.
|
||||
#include "error.h"
|
||||
#include "packing.h"
|
||||
#include "hw_i2c_common.h"
|
||||
|
||||
/** @defgroup ROMAPI_I2CMON I2C monitor ROM driver functions and definitions
|
||||
* @ingroup ROMAPI_I2CMON_WRAPPER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief I2C monitor handle type */
|
||||
typedef void *ROM_I2CMON_HANDLE_T;
|
||||
|
||||
/** @brief User context conversion macro
|
||||
* Macro used to extract the user defined data pointer from a I2C monitor
|
||||
* handle context.<br>
|
||||
* To get a user context, simple use the macro on the drivers handle:
|
||||
* void *pUserData = (void *) ROM_I2CMON_HANDLE_TOUDATA(driverHandle);
|
||||
*/
|
||||
#define ROM_I2CMON_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p)
|
||||
|
||||
/** @brief I2C monitor optional transfer flags */
|
||||
#define ROM_I2CMON_FLAG_BLOCKING (1UL << 31) /*!< Capture function will block until complete */
|
||||
#define ROM_I2CMON_FLAG_DMARX (1UL << 29) /*!< DMA will be used for RX, requires DMA setup outside of the driver */
|
||||
#define ROM_I2CMON_FLAG_FLUSH (1UL << 25) /*!< Force monitor FIFO flush */
|
||||
#define ROM_I2CMON_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */
|
||||
|
||||
/** @brief Monitor transfer descriptor */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
const void *startBuff; /*!< Pointer to a buffer for capturing data after start, msy be 16-bit aligned */
|
||||
uint16_t startBuffSz; /*!< Number of bytes in startBuff buffer, data will be tossed if not big enough */
|
||||
uint16_t capStartBuffSz; /*!< Number of bytes captured in startBuff buffer */
|
||||
uint32_t flags; /*!< Optional transfer flags of type ROM_I2CMON_FLAG_* */
|
||||
volatile ErrorCode_t status; /*!< LPC_OK, busy status, or error code */
|
||||
} ROM_I2CMON_CAP_T;
|
||||
|
||||
/** I2C monitor callback IDs */
|
||||
typedef enum {
|
||||
ROM_I2CMON_CAPTUREREADY_CB = 0, /*!< Callback ID for I2C monitor capture ready */
|
||||
ROM_I2CMON_DMASETUP_CB /*!< Callback for DMA setup */
|
||||
} ROM_I2CMON_CALLBACK_T;
|
||||
|
||||
/** @brief I2C monitor capture complete callback prototype
|
||||
* The I2C monitor state machine will call this function when it captures an I2C transfer.
|
||||
*/
|
||||
typedef void (*i2cMonCapReadyCB)(ROM_I2CMON_HANDLE_T i2cmonHandle, ROM_I2CMON_CAP_T *pCap);
|
||||
|
||||
/** @brief I2C monitor capture DMA setup callback prototype
|
||||
* The I2C monitor state machine will call this function when DMA needs to be setup for
|
||||
* the capture oeprations.
|
||||
*/
|
||||
typedef void (*i2cMonSetupDMACB)(ROM_I2CMON_HANDLE_T i2cmonHandle, ROM_I2CMON_CAP_T *pCap);
|
||||
|
||||
/** @brief I2C monitor initialization structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
|
||||
uint32_t base; /*!< Base address of I2C peripheral to use */
|
||||
uint8_t stretch; /*!< 0 = disable monitor clock stretching, !0 = enable */
|
||||
} ROM_I2CMON_INIT_T;
|
||||
|
||||
/** @brief I2C monitor ROM indirect function structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of I2C monitor driver */
|
||||
ROM_I2CMON_HANDLE_T (*Init)(void *mem, const ROM_I2CMON_INIT_T *pInit); /*!< Initializes the I2C monitor driver and peripheral */
|
||||
void (*RegisterCallback)(ROM_I2CMON_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an I2C monitor callback */
|
||||
ErrorCode_t (*StartLog)(ROM_I2CMON_HANDLE_T pHandle, ROM_I2CMON_CAP_T *pCap); /*!< Start/queue a log descriptor */
|
||||
void (*TransferHandler)(ROM_I2CMON_HANDLE_T pHandle); /*!< I2C monitor transfer (interrupt) handler */
|
||||
uint32_t (*GetDriverVersion)(void);
|
||||
} ROM_I2CMOND_API_T;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
extern const ROM_I2CMOND_API_T i2cmon_api; // so application program can access pointer to
|
||||
// function table
|
||||
|
||||
#endif /* __HW_I2CMOND_ROM_API_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* @brief I2C slave ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_I2CSD_H
|
||||
#define __HW_I2CSD_H
|
||||
|
||||
#include "error.h"
|
||||
#include "hw_i2csd_rom_api.h"
|
||||
|
||||
// *** I2C functions called by Application Program ***
|
||||
uint32_t i2cs_get_mem_size(void);
|
||||
|
||||
ROM_I2CS_HANDLE_T i2cs_init(void *mem, const ROM_I2CS_INIT_T *pInit);
|
||||
|
||||
void i2cs_setup_slave(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_SLAVE_T *pSlaveSetup);
|
||||
|
||||
void i2cs_register_callback(ROM_I2CS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB);
|
||||
|
||||
ErrorCode_t i2cs_transfer(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_XFER_T *pXfer);
|
||||
|
||||
void i2cs_transfer_handler(ROM_I2CS_HANDLE_T pHandle);
|
||||
|
||||
uint32_t i2cs_get_driver_version(void);
|
||||
|
||||
// ***
|
||||
|
||||
#endif /* __HW_I2CSD_H */
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* @brief I2C slave ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "hw_i2csd.h"
|
||||
|
||||
// This creates a table with the addresses of all the I2C functions
|
||||
// This table of function pointers is the API interface.
|
||||
const ROM_I2CSD_API_T i2cs_api = {
|
||||
&i2cs_get_mem_size,
|
||||
&i2cs_init,
|
||||
&i2cs_setup_slave,
|
||||
&i2cs_register_callback,
|
||||
&i2cs_transfer,
|
||||
&i2cs_transfer_handler,
|
||||
&i2cs_get_driver_version,
|
||||
}; // end of table ************************************
|
||||
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* @brief I2C slave ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_I2CSD_ROM_API_H
|
||||
#define __HW_I2CSD_ROM_API_H
|
||||
|
||||
#include "stdint.h" // added to define uint32_t, etc.
|
||||
#include "error.h"
|
||||
#include "packing.h"
|
||||
#include "hw_i2c_common.h"
|
||||
|
||||
/** @defgroup ROMAPI_I2CS I2C slave ROM driver functions and definitions
|
||||
* @ingroup ROMAPI_I2CS_WRAPPER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief I2C slave handle type */
|
||||
typedef void *ROM_I2CS_HANDLE_T;
|
||||
|
||||
/** @brief Maximum number of slave addresses supported by this driver */
|
||||
#define ROM_I2CS_MAX_SLAVES 4
|
||||
|
||||
/** @brief User context conversion macro
|
||||
* Macro used to extract the user defined data pointer from a I2C master
|
||||
* handle context.<br>
|
||||
* To get a user context, simple use the macro on the drivers handle:
|
||||
* void *pUserData = (void *) ROM_I2CS_HANDLE_TOUDATA(driverHandle);
|
||||
*/
|
||||
#define ROM_I2CS_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p)
|
||||
|
||||
/** @brief I2C master optional transfer flags */
|
||||
#define ROM_I2CS_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */
|
||||
|
||||
/** @brief slave transfer descriptor */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
const void *txBuff; /*!< Pointer to array of bytes to be transmitted */
|
||||
void *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */
|
||||
volatile ErrorCode_t status; /*!< Packed status of the current I2C transfer (ErrorCode_t), must be 32-bits */
|
||||
uint32_t flags; /*!< Reserved, set to 0 */
|
||||
uint16_t txSz; /*!< Number of bytes in transmit array, if 0 only receive transfer will be performed */
|
||||
uint16_t rxSz; /*!< Number of bytes to receive, if 0 only transmission will be performed */
|
||||
uint16_t bytesSent; /*!< Number of bytes sent */
|
||||
uint16_t bytesRecv; /*!< Number of bytes recevied */
|
||||
} ROM_I2CS_XFER_T;
|
||||
|
||||
/** I2C slave callback IDs */
|
||||
typedef enum {
|
||||
ROM_I2CS_START_CB = 0, /*!< Callback ID for I2C slave service start callback */
|
||||
ROM_I2CS_XFERSEND_CB, /*!< Callback ID for I2C slave send data callback */
|
||||
ROM_I2CS_XFERRECV_CB, /*!< Callback ID for I2C slave receive data callback */
|
||||
ROM_I2CS_DONE_CB, /*!< Callback ID for I2C slave service done callback */
|
||||
} ROM_I2CS_CALLBACK_T;
|
||||
|
||||
/** @brief I2C slave state machine transfer control */
|
||||
typedef enum {
|
||||
ROM_I2CS_CONTINUE = 0, /*!< Continue transfer */
|
||||
ROM_I2CS_NAK, /*!< Will NAK master at next opportunity */
|
||||
ROM_I2CS_DMA /*!< Tell I2C handler DMA is handling the data */
|
||||
} ROM_I2CS_TRANCTRL_T;
|
||||
|
||||
/** @brief I2C slave transfer start callback
|
||||
* This callback is called from the I2C slave handler when an I2C slave address supported
|
||||
* by the controller is addressed.
|
||||
*/
|
||||
typedef void (*i2cSlaveStartCB)(ROM_I2CS_HANDLE_T i2csHandle, uint16_t addr);
|
||||
|
||||
/** @brief I2C slave send data callback
|
||||
* This callback is called from the I2C slave handler when an I2C slave address needs
|
||||
* data to send in the transfer descriptor. It is called on demand only when transmit
|
||||
* data is needed for the transmit FIFO and the descriptor buffer is empty.<br>
|
||||
* If you want to NAK the master, return ROM_I2CS_NAK to the caller.
|
||||
* Return ROM_I2CS_CONTINUE or 0 to the caller for normal non-DMA data transfer.
|
||||
* If you've setup a DMA descriptor for the transfer, return ROM_I2CS_DMA to the caller.<br>
|
||||
*/
|
||||
typedef ROM_I2CS_TRANCTRL_T (*i2cSlaveTransmitCB)(ROM_I2CS_HANDLE_T i2csHandle, ROM_I2CS_XFER_T *pXfer);
|
||||
|
||||
/** @brief I2C slave receive data callback
|
||||
* This callback is called from the I2C slave handler when an I2C slave address has
|
||||
* receive data and the receive buffer is full.<br>
|
||||
* If you want to NAK the master, return ROM_I2CS_NAK to the caller.
|
||||
* Return ROM_I2CS_CONTINUE or 0 to the caller for normal non-DMA data transfer.
|
||||
* If you've setup a DMA descriptor for the transfer, return ROM_I2CS_DMA to the caller.<br>
|
||||
*/
|
||||
typedef ROM_I2CS_TRANCTRL_T (*i2cSlaveReceiveCB)(ROM_I2CS_HANDLE_T i2csHandle, ROM_I2CS_XFER_T *pXfer);
|
||||
|
||||
/** @brief I2C slave service done callback
|
||||
* This callback is called from the I2C slave handler when an I2C slave transfer is
|
||||
* completed. It's used to indicate the end of a slave transfer.
|
||||
*/
|
||||
typedef void (*i2cSlaveCompleteCB)(ROM_I2CS_HANDLE_T i2csHandle, ROM_I2CS_XFER_T *pXfer);
|
||||
|
||||
/** @brief I2C slave initialization structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
|
||||
uint32_t base; /*!< Base address of I2C peripheral to use */
|
||||
} ROM_I2CS_INIT_T;
|
||||
|
||||
/** @brief I2C slave address setup structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
uint16_t slaveAddr; /*!< Slave address used for this index in the controller */
|
||||
uint8_t SlaveIndex; /*!< Slave index to use, 0 is first index */
|
||||
uint8_t EnableSlave; /*!< Set to 0 to disable this slave index, or non-0 to enable */
|
||||
} ROM_I2CS_SLAVE_T;
|
||||
|
||||
/** @brief I2C slave ROM indirect function structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of I2C slave driver */
|
||||
ROM_I2CS_HANDLE_T (*Init)(void *mem, const ROM_I2CS_INIT_T *pInit); /*!< Initializes the I2C slave driver and peripheral */
|
||||
void (*SetupSlave)(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_SLAVE_T *pSlaveSetup); /*!< Sets up a slave address to use with the I2C controller */
|
||||
void (*RegisterCallback)(ROM_I2CS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an I2C slave callback */
|
||||
ErrorCode_t (*Transfer)(ROM_I2CS_HANDLE_T pHandle, ROM_I2CS_XFER_T *pXfer); /*!< Queues an I2C slave transfer */
|
||||
void (*TransferHandler)(ROM_I2CS_HANDLE_T pHandle); /*!< I2C slave transfer (interrupt) handler */
|
||||
uint32_t (*GetDriverVersion)(void);
|
||||
} ROM_I2CSD_API_T;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
extern const ROM_I2CSD_API_T i2cs_api; // so application program can access pointer to
|
||||
// function table
|
||||
|
||||
#endif /* __HW_I2CSD_ROM_API_H */
|
||||
@@ -0,0 +1,187 @@
|
||||
/*
|
||||
* @brief SPI ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_SPI_COMMON_H_
|
||||
#define __HW_SPI_COMMON_H_
|
||||
|
||||
/**
|
||||
* @brief SPI register block structure
|
||||
*/
|
||||
typedef struct { /*!< SPI Structure */
|
||||
volatile uint32_t CFG; /*!< SPI Configuration register */
|
||||
volatile uint32_t DLY; /*!< SPI Delay register */
|
||||
volatile uint32_t STAT; /*!< SPI Status register */
|
||||
volatile uint32_t INTENSET; /*!< SPI Interrupt Enable Set register */
|
||||
volatile uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear register */
|
||||
volatile uint32_t RXDAT; /*!< SPI Receive Data register */
|
||||
volatile uint32_t TXDATCTL; /*!< SPI Transmit Data with Control register */
|
||||
volatile uint32_t TXDAT; /*!< SPI Transmit Data register */
|
||||
volatile uint32_t TXCTRL; /*!< SPI Transmit Control register */
|
||||
volatile uint32_t DIV; /*!< SPI clock Divider register */
|
||||
volatile uint32_t INTSTAT; /*!< SPI Interrupt Status register */
|
||||
} LPC_SPI_T;
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Configuration register
|
||||
*/
|
||||
#define SPI_CFG_BITMASK (0xFBD) /** SPI register bit mask */
|
||||
#define SPI_CFG_SPI_EN (1 << 0) /** SPI Slave Mode Select */
|
||||
#define SPI_CFG_SLAVE_EN (0 << 0) /** SPI Master Mode Select */
|
||||
#define SPI_CFG_MASTER_EN (1 << 2) /** SPI MSB First mode enable */
|
||||
#define SPI_CFG_MSB_FIRST_EN (0 << 3) /** SPI LSB First mode enable */
|
||||
#define SPI_CFG_LSB_FIRST_EN (1 << 3) /** SPI Clock Phase Select */
|
||||
#define SPI_CFG_CPHA_FIRST (0 << 4) /** Capture data on the first edge, Change data on the following edge */
|
||||
#define SPI_CFG_CPHA_SECOND (1 << 4) /** SPI Clock Polarity Select */
|
||||
#define SPI_CFG_CPOL_LO (0 << 5) /** The rest state of the clock (between frames) is low. */
|
||||
#define SPI_CFG_CPOL_HI (1 << 5) /** The rest state of the clock (between frames) is high. */
|
||||
#define SPI_CFG_LBM_EN (1 << 7) /** SPI control 1 loopback mode enable */
|
||||
#define SPI_CFG_SPOL_LO (0 << 8) /** SPI SSEL0 Polarity Select */
|
||||
#define SPI_CFG_SPOL_HI (1 << 8) /** SSEL0 is active High */
|
||||
#define SPI_CFG_SPOLNUM_HI(n) (1 << ((n) + 8)) /** SSELN is active High, selects 0 - 3 */
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Delay register
|
||||
*/
|
||||
#define SPI_DLY_BITMASK (0xFFFF) /** SPI DLY Register Mask */
|
||||
#define SPI_DLY_PRE_DELAY(n) (((n) & 0x0F) << 0) /** Time in SPI clocks between SSEL assertion and the beginning of a data frame */
|
||||
#define SPI_DLY_POST_DELAY(n) (((n) & 0x0F) << 4) /** Time in SPI clocks between the end of a data frame and SSEL deassertion. */
|
||||
#define SPI_DLY_FRAME_DELAY(n) (((n) & 0x0F) << 8) /** Minimum time in SPI clocks between adjacent data frames. */
|
||||
#define SPI_DLY_TRANSFER_DELAY(n) (((n) & 0x0F) << 12) /** Minimum time in SPI clocks that the SSEL is deasserted between transfers. */
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Status register
|
||||
*/
|
||||
#define SPI_STAT_BITMASK (0x1FF) /** SPI STAT Register BitMask */
|
||||
#define SPI_STAT_RXRDY (1 << 0) /** Receiver Ready Flag */
|
||||
#define SPI_STAT_TXRDY (1 << 1) /** Transmitter Ready Flag */
|
||||
#define SPI_STAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */
|
||||
#define SPI_STAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */
|
||||
#define SPI_STAT_SSA (1 << 4) /** Slave Select Assert */
|
||||
#define SPI_STAT_SSD (1 << 5) /** Slave Select Deassert */
|
||||
#define SPI_STAT_STALLED (1 << 6) /** Stalled status flag */
|
||||
#define SPI_STAT_EOT (1 << 7) /** End Transfer flag */
|
||||
#define SPI_STAT_MSTIDLE (1 << 8) /** Idle status flag */
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Interrupt Enable read and Set register
|
||||
*/
|
||||
#define SPI_INTENSET_BITMASK (0x3F) /** SPI INTENSET Register BitMask */
|
||||
#define SPI_INTENSET_RXDYEN (1 << 0) /** Enable Interrupt when receiver data is available */
|
||||
#define SPI_INTENSET_TXDYEN (1 << 1) /** Enable Interrupt when the transmitter holding register is available. */
|
||||
#define SPI_INTENSET_RXOVEN (1 << 2) /** Enable Interrupt when a receiver overrun occurs */
|
||||
#define SPI_INTENSET_TXUREN (1 << 3) /** Enable Interrupt when a transmitter underrun occurs (In Slave Mode Only)*/
|
||||
#define SPI_INTENSET_SSAEN (1 << 4) /** Enable Interrupt when the Slave Select is asserted.*/
|
||||
#define SPI_INTENSET_SSDEN (1 << 5) /** Enable Interrupt when the Slave Select is deasserted..*/
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Interrupt Enable Clear register
|
||||
*/
|
||||
#define SPI_INTENCLR_BITMASK (0x3F) /** SPI INTENCLR Register BitMask */
|
||||
#define SPI_INTENCLR_RXDYEN (1 << 0) /** Disable Interrupt when receiver data is available */
|
||||
#define SPI_INTENCLR_TXDYEN (1 << 1) /** Disable Interrupt when the transmitter holding register is available. */
|
||||
#define SPI_INTENCLR_RXOVEN (1 << 2) /** Disable Interrupt when a receiver overrun occurs */
|
||||
#define SPI_INTENCLR_TXUREN (1 << 3) /** Disable Interrupt when a transmitter underrun occurs (In Slave Mode Only) */
|
||||
#define SPI_INTENCLR_SSAEN (1 << 4) /** Disable Interrupt when the Slave Select is asserted. */
|
||||
#define SPI_INTENCLR_SSDEN (1 << 5) /** Disable Interrupt when the Slave Select is deasserted.. */
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Receiver Data register
|
||||
*/
|
||||
#define SPI_RXDAT_BITMASK (0x1FFFFF) /** SPI RXDAT Register BitMask */
|
||||
#define SPI_RXDAT_DATA(n) ((n) & 0xFFFF) /** Receiver Data */
|
||||
#define SPI_RXDAT_RXSSELN_ACTIVE (0 << 16) /** The state of SSEL pin is active */
|
||||
#define SPI_RXDAT_RXSSELN_INACTIVE ((1 << 16) /** The state of SSEL pin is inactive */
|
||||
#define SPI_RXDAT_RXSSELNUM_INACTIVE(n) (1 << ((n) + 16)) /** The state of SSELN pin is inactive */
|
||||
#define SPI_RXDAT_SOT (1 << 20) /** Start of Transfer flag */
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Transmitter Data and Control register
|
||||
*/
|
||||
#define SPI_TXDATCTL_BITMASK (0xF7FFFFF) /** SPI TXDATCTL Register BitMask */
|
||||
#define SPI_TXDATCTL_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */
|
||||
#define SPI_TXDATCTL_CTRLMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask for control bits only */
|
||||
#define SPI_TXDATCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */
|
||||
#define SPI_TXDATCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */
|
||||
#define SPI_TXDATCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */
|
||||
#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */
|
||||
#define SPI_TXDATCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */
|
||||
#define SPI_TXDATCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */
|
||||
#define SPI_TXDATCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */
|
||||
#define SPI_TXDATCTL_FLEN(n) (((n) & 0x0F) << 24) /** Frame length - 1 */
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Transmitter Data Register
|
||||
*/
|
||||
#define SPI_TXDAT_DATA(n) ((n) & 0xFFFF) /** SPI Transmit Data */
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Transmitter Control register
|
||||
*/
|
||||
#define SPI_TXCTL_BITMASK (0xF7F0000) /** SPI TXDATCTL Register BitMask */
|
||||
#define SPI_TXCTL_ASSERT_SSEL (0 << 16) /** Assert SSEL0 pin */
|
||||
#define SPI_TXCTL_DEASSERT_SSEL (1 << 16) /** Deassert SSEL0 pin */
|
||||
#define SPI_TXCTL_DEASSERTNUM_SSEL(n) (1 << ((n) + 16)) /** Deassert SSELN pin */
|
||||
#define SPI_TXDATCTL_DEASSERT_ALL (0xF << 16) /** Deassert all SSEL pins */
|
||||
#define SPI_TXCTL_EOT (1 << 20) /** End of Transfer flag (TRANSFER_DELAY is applied after sending the current frame) */
|
||||
#define SPI_TXCTL_EOF (1 << 21) /** End of Frame flag (FRAME_DELAY is applied after sending the current part) */
|
||||
#define SPI_TXCTL_RXIGNORE (1 << 22) /** Receive Ignore Flag */
|
||||
#define SPI_TXCTL_FLEN(n) ((((n) - 1) & 0x0F) << 24) /** Frame length, 0 - 16 */
|
||||
#define SPI_TXCTL_FLENMASK (0xF << 24) /** Frame length mask */
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Divider register
|
||||
*/
|
||||
#define SPI_DIV_VAL(n) ((n) & 0xFFFF) /** Rate divider value mask (In Master Mode only)*/
|
||||
|
||||
/**
|
||||
* Macro defines for SPI Interrupt Status register
|
||||
*/
|
||||
#define SPI_INTSTAT_BITMASK (0x3F) /** SPI INTSTAT Register Bitmask */
|
||||
#define SPI_INTSTAT_RXRDY (1 << 0) /** Receiver Ready Flag */
|
||||
#define SPI_INTSTAT_TXRDY (1 << 1) /** Transmitter Ready Flag */
|
||||
#define SPI_INTSTAT_RXOV (1 << 2) /** Receiver Overrun interrupt flag */
|
||||
#define SPI_INTSTAT_TXUR (1 << 3) /** Transmitter Underrun interrupt flag (In Slave Mode only) */
|
||||
#define SPI_INTSTAT_SSA (1 << 4) /** Slave Select Assert */
|
||||
#define SPI_INTSTAT_SSD (1 << 5) /** Slave Select Deassert */
|
||||
|
||||
/** @brief SPI Clock Mode*/
|
||||
typedef enum {
|
||||
ROM_SPI_CLOCK_CPHA0_CPOL0 = 0, /**< CPHA = 0, CPOL = 0 */
|
||||
ROM_SPI_CLOCK_MODE0 = ROM_SPI_CLOCK_CPHA0_CPOL0, /**< Alias for CPHA = 0, CPOL = 0 */
|
||||
ROM_SPI_CLOCK_CPHA1_CPOL0 = 1, /**< CPHA = 0, CPOL = 1 */
|
||||
ROM_SPI_CLOCK_MODE1 = ROM_SPI_CLOCK_CPHA1_CPOL0, /**< Alias for CPHA = 0, CPOL = 1 */
|
||||
ROM_SPI_CLOCK_CPHA0_CPOL1 = 2, /**< CPHA = 1, CPOL = 0 */
|
||||
ROM_SPI_CLOCK_MODE2 = ROM_SPI_CLOCK_CPHA0_CPOL1, /**< Alias for CPHA = 1, CPOL = 0 */
|
||||
ROM_SPI_CLOCK_CPHA1_CPOL1 = 3, /**< CPHA = 1, CPOL = 1 */
|
||||
ROM_SPI_CLOCK_MODE3 = ROM_SPI_CLOCK_CPHA1_CPOL1, /**< Alias for CPHA = 1, CPOL = 1 */
|
||||
} ROM_SPI_CLOCK_MODE_T;
|
||||
|
||||
#endif /* __HW_SPI_COMMON_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* @brief SPI master ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_SPIMD_H
|
||||
#define __HW_SPIMD_H
|
||||
|
||||
#include "error.h"
|
||||
#include "hw_spimd_rom_api.h"
|
||||
|
||||
// *** SPI functions called by Application Program ***
|
||||
uint32_t spim_get_mem_size(void);
|
||||
|
||||
ROM_SPIM_HANDLE_T spim_init(void *mem, const ROM_SPIM_INIT_T *pInit);
|
||||
|
||||
void spim_register_callback(ROM_SPIM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB);
|
||||
|
||||
ErrorCode_t spim_setup_transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_CONFIG_T *pCfg);
|
||||
|
||||
ErrorCode_t spim_transfer(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer);
|
||||
|
||||
void spim_transfer_handler(ROM_SPIM_HANDLE_T pHandle);
|
||||
|
||||
void spim_close_pending_transfer(ROM_SPIM_HANDLE_T pHandle);
|
||||
|
||||
uint32_t spim_get_driver_version(void);
|
||||
|
||||
// ***
|
||||
|
||||
#endif /* __HW_SPIMD_H */
|
||||
@@ -0,0 +1,45 @@
|
||||
/*
|
||||
* @brief SPI master ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "hw_spimd.h"
|
||||
|
||||
// This creates a table with the addresses of all the SPI functions
|
||||
// This table of function pointers is the API interface.
|
||||
const ROM_SPIMD_API_T spim_api = {
|
||||
&spim_get_mem_size,
|
||||
&spim_init,
|
||||
&spim_register_callback,
|
||||
&spim_setup_transfer,
|
||||
&spim_transfer,
|
||||
&spim_transfer_handler,
|
||||
&spim_close_pending_transfer,
|
||||
&spim_get_driver_version,
|
||||
}; // end of table ************************************
|
||||
@@ -0,0 +1,167 @@
|
||||
/*
|
||||
* @brief SPI master ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_SPIMD_ROM_API_H
|
||||
#define __HW_SPIMD_ROM_API_H
|
||||
|
||||
#include "stdint.h" // added to define uint32_t, etc.
|
||||
#include "error.h"
|
||||
#include "packing.h"
|
||||
#include "hw_spi_common.h"
|
||||
|
||||
/** @defgroup ROMAPI_SPIM SPI master ROM driver functions and definitions
|
||||
* @ingroup ROMAPI_SPIM_WRAPPER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief SPI master handle type */
|
||||
typedef void *ROM_SPIM_HANDLE_T;
|
||||
|
||||
/* Number of selects the SPI driver supports */
|
||||
#define ROM_SPIM_MAXSELECTS (4)
|
||||
|
||||
/** @brief User context conversion macro
|
||||
* Macro used to extract the user defined data pointer from a SPI master
|
||||
* handle context.<br>
|
||||
* To get a user context, simple use the macro on the drivers handle:
|
||||
* void *pUserData = (void *) ROM_SPIM_HANDLE_TOUDATA(driverHandle);
|
||||
*/
|
||||
#define ROM_SPIM_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p)
|
||||
|
||||
/** @brief SPI master optional transfer flags */
|
||||
#define ROM_SPIM_FLAG_BLOCKING (1UL << 31) /*!< Transfer function will block until complete */
|
||||
#define ROM_SPIM_FLAG_DMATX (1UL << 30) /*!< DMA will be used for TX, requires DMA setup outside of the driver */
|
||||
#define ROM_SPIM_FLAG_DMARX (1UL << 29) /*!< DMA will be used for RX, requires DMA setup outside of the driver */
|
||||
#define ROM_SPIM_FLAG_LOOPBACK (1UL << 28) /*!< Enables loopback mode for the transfer, useful for testing only */
|
||||
#define ROM_SPIM_FLAG_TXIGNORE (1UL << 27) /*!< Ignores receive data regardless of txBuff, transmit data callback will not be called, stops when txSz = 0 */
|
||||
#define ROM_SPIM_FLAG_RXIGNORE (1UL << 26) /*!< Ignores receive data regardless of rxBuff/rxSz, receive data callback will not be called */
|
||||
#define ROM_SPIM_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */
|
||||
|
||||
/** @brief SPI transfer configuration structure - once of these needs to be setup for
|
||||
* each SPI select (SSEL) used on the master. If only SSEL0 is used, it only needs to be setup
|
||||
* for that one slave select. This structure must be statically allocated for use with the
|
||||
* driver and should not be created on the program stack. If anything in this structure
|
||||
* changes, SetupSSEL() must be called again with the structure reference. */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
uint32_t dXferBitRate; /*!< Desired bit transfer rate (SPI clock) in Hz */
|
||||
uint32_t rXferBitRate; /*!< Real bit transfer rate (SPI clock) in Hz, modified by driver to actual rate */
|
||||
uint8_t mode; /*!< Mode selection for this transfer (ROM_SPI_CLOCK_MODE_T) */
|
||||
uint8_t lsbFirst; /*!< 0 for msb sent/recv first, !0 = for lsb send/recv first */
|
||||
uint8_t dataBits; /*!< Data transfer size in bits, between 1 and 16, txBuff and rxBuff must be 16-bit aligned if >8 */
|
||||
/* The time delays are based in SPI clocks (rXferBitRate). These values are used to configure the
|
||||
SPI delays when a transfer is started, so these values do not need to be populated for the
|
||||
SetupSSEL() function. The actual (rXferBitRate) and desired (dXferBitRate) SPI clocks may differ,
|
||||
and the actual clock won't be known until after SetupSSEL() is called, so it's best to setup
|
||||
these values after the call to SetupSSEL(). */
|
||||
uint8_t PreDelay; /*!< Pre-delay value in (rXferBitRate) SPI clocks, 0 - 15 */
|
||||
uint8_t PostDelay; /*!< Post-delay value in (rXferBitRate) SPI clocks, 0 - 15 */
|
||||
uint8_t FrameDelay; /*!< Delay value between frames of a transfer in (rXferBitRate) SPI clocks, 0 - 15 */
|
||||
uint8_t TransferDelay; /*!< Delay value between transfers in (rXferBitRate) SPI clocks, 1 - 16 */
|
||||
uint8_t reserved;
|
||||
} ROM_SPIM_XFER_CONFIG_T;
|
||||
|
||||
/** @brief SPI Master transfer descriptor */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
const void *txBuff; /*!< Pointer to array of datum to be transmitted, use NULL for receive only, must be 16-bit aligned if datum bits >8 */
|
||||
uint32_t txSz; /*!< Size of the transmit buffer (txBuff) in items (not bytes) before transmit callback is called */
|
||||
void *rxBuff; /*!< Pointer memory where datum received from SPI be stored, use NULL for transmit only, must be 16-bit aligned if datum bits >8 */
|
||||
uint32_t rxSz; /*!< Size of the receive buffer (rxBuff) in items (not bytes) before receive callback is called */
|
||||
uint32_t flags; /*!< Optional transfer flags, may be modified by driver */
|
||||
volatile ErrorCode_t status; /*!< Status of the current SPI transfer (ErrorCode_t), must be 32-bits */
|
||||
uint8_t sselNum; /*!< SPI master SSEL number for this transfer, 0 - 3 */
|
||||
uint8_t reserved1[3];
|
||||
} ROM_SPIM_XFER_T;
|
||||
|
||||
/** @brief SPI master callback IDs */
|
||||
typedef enum {
|
||||
ROM_SPIM_ASSERTSSEL_CB = 0, /*!< Callback ID for SPI master SSEL assertion */
|
||||
ROM_SPIM_DATATRANSMIT_CB, /*!< Callback ID for SPI master transmit start */
|
||||
ROM_SPIM_DATATRECEIVE_CB, /*!< Callback ID for SPI master receive start */
|
||||
ROM_SPIM_DEASSERTSSEL_CB /*!< Callback ID for SPI master SSEL de-assertion */
|
||||
} ROM_SPIM_CALLBACK_T;
|
||||
|
||||
/** @brief SPI master select assert callback
|
||||
* This callback is called from the SPI master handler when the SPI master
|
||||
* selects the slave (asserts SSEL). The callback is only called if it has been registered.<br>
|
||||
*/
|
||||
typedef void (*spiMasterXferCSAssertCB)(ROM_SPIM_HANDLE_T spimHandle, ROM_SPIM_XFER_T *pXfer);
|
||||
|
||||
/** @brief SPI master data receive start callback
|
||||
* The SPI master state machine will call this optional function when it needs a buffer to
|
||||
* receive data. The callback can be used to setup DMA or alter the receive buffer size. The
|
||||
* callback is only called if it has been registered, the buffer has been fully used, and
|
||||
* data is needed to populate the transmit FIFO. When using DMA, this callback must be enabled
|
||||
* and used for DMA setup.
|
||||
*/
|
||||
typedef void (*spiMasterReceiveCB)(ROM_SPIM_HANDLE_T spimHandle, ROM_SPIM_XFER_T *pXfer);
|
||||
|
||||
/** @brief SPI master data transmit start callback
|
||||
* The SPI master state machine will call this optional function for data transfer.
|
||||
* The callback can be used to setup DMA or alter the receive buffer size. The callback is
|
||||
* only called if it has been registered, the buffer has been fully used, and data is pending
|
||||
* is the receive FIFO. When using DMA, this callback must be enabled and used for DMA setup.
|
||||
*/
|
||||
typedef void (*spiMasterTransmitCB)(ROM_SPIM_HANDLE_T spimHandle, ROM_SPIM_XFER_T *pXfer);
|
||||
|
||||
/** @brief SPI master transfer select deassert data callback
|
||||
* This callback is called from the SPI master handler when the SPI master
|
||||
* deasserts the slave select. The callback is only called if it has been registered.<br>
|
||||
*/
|
||||
typedef void (*spiMMasterXferCSDeAssertCB)(ROM_SPIM_HANDLE_T spimHandle, ROM_SPIM_XFER_T *pXfer);
|
||||
|
||||
/** @brief SPI master initialization structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
|
||||
uint32_t base; /*!< Base address of SPI peripheral to use */
|
||||
uint32_t baseClockRate; /*!< SPI base clock rate in Hz, call Init() again if this rate changes */
|
||||
uint8_t spiPol[4]; /*!< SPI SSEL pollarity for each slave select, 0 = active low, !0 = active high */
|
||||
} ROM_SPIM_INIT_T;
|
||||
|
||||
/** @brief SPI master ROM indirect function structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of SPI master driver */
|
||||
ROM_SPIM_HANDLE_T (*Init)(void *mem, const ROM_SPIM_INIT_T *pInit); /*!< Initializes the SPI master driver and peripheral */
|
||||
void (*RegisterCallback)(ROM_SPIM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an SPI master callback */
|
||||
ErrorCode_t (*SetupTransfer)(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_CONFIG_T *pCfg); /*!< Sets up a master select's transfer configuration, should be called when the transfer configuration changes */
|
||||
ErrorCode_t (*Transfer)(ROM_SPIM_HANDLE_T pHandle, ROM_SPIM_XFER_T *pXfer); /*!< Perform or start and SPI master transfer */
|
||||
void (*TransferHandler)(ROM_SPIM_HANDLE_T pHandle); /*!< SPI master transfer (interrupt) handler */
|
||||
void (*ClosePendingTransfer)(ROM_SPIM_HANDLE_T pHandle); /*!< Immediately terminates the current transfer */
|
||||
uint32_t (*GetDriverVersion)(void);
|
||||
} ROM_SPIMD_API_T;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
extern const ROM_SPIMD_API_T spim_api; // so application program can access pointer to
|
||||
// function table
|
||||
|
||||
#endif /* __HW_SPIMD_ROM_API_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* @brief SPI slave ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_SPISD_H
|
||||
#define __HW_SPISD_H
|
||||
|
||||
#include "error.h"
|
||||
#include "hw_spisd_rom_api.h"
|
||||
|
||||
// *** SPI functions called by Application Program ***
|
||||
uint32_t spis_get_mem_size(void);
|
||||
|
||||
ROM_SPIS_HANDLE_T spis_init(void *mem, const ROM_SPIS_INIT_T *pInit);
|
||||
|
||||
void spis_register_callback(ROM_SPIS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB);
|
||||
|
||||
ErrorCode_t spis_setup_slave(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_SLAVE_T *pCfg);
|
||||
|
||||
void spis_transfer_handler(ROM_SPIS_HANDLE_T pHandle);
|
||||
|
||||
ErrorCode_t spis_transfer(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer);
|
||||
|
||||
uint32_t spis_get_driver_version(void);
|
||||
|
||||
// ***
|
||||
|
||||
#endif /* __HW_SPISD_H */
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* @brief SPI slave ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "hw_spisd.h"
|
||||
|
||||
// This creates a table with the addresses of all the SPI functions
|
||||
// This table of function pointers is the API interface.
|
||||
const ROM_SPISD_API_T spis_api = {
|
||||
&spis_get_mem_size,
|
||||
&spis_init,
|
||||
&spis_register_callback,
|
||||
&spis_setup_slave,
|
||||
&spis_transfer,
|
||||
&spis_transfer_handler,
|
||||
&spis_get_driver_version,
|
||||
}; // end of table ************************************
|
||||
@@ -0,0 +1,151 @@
|
||||
/*
|
||||
* @brief SPI slave ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __HW_SPISD_ROM_API_H
|
||||
#define __HW_SPISD_ROM_API_H
|
||||
|
||||
#include "stdint.h" // added to define uint32_t, etc.
|
||||
#include "error.h"
|
||||
#include "packing.h"
|
||||
#include "hw_spi_common.h"
|
||||
|
||||
/** @defgroup ROMAPI_SPIS SPI slave ROM driver functions and definitions
|
||||
* @ingroup ROMAPI_SPIS_WRAPPER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief SPI slave handle type */
|
||||
typedef void *ROM_SPIS_HANDLE_T;
|
||||
|
||||
/** @brief Number of selects the SPI driver supports */
|
||||
#define ROM_SPIS_MAXSELECTS (4)
|
||||
|
||||
/** @brief User context conversion macro
|
||||
* Macro used to extract the user defined data pointer from a SPI slave
|
||||
* handle context.<br>
|
||||
* To get a user context, simple use the macro on the drivers handle:
|
||||
* void *pUserData = (void *) ROM_SPIS_HANDLE_TOUDATA(driverHandle);
|
||||
*/
|
||||
#define ROM_SPIS_HANDLE_TOUDATA(p) (void *) (*(uint32_t *) p)
|
||||
|
||||
/** @brief SPI slave optional transfer flags */
|
||||
#define ROM_SPIS_FLAG_DMATX (1UL << 30) /*!< DMA will be used for TX, requires DMA setup outside of the driver */
|
||||
#define ROM_SPIS_FLAG_DMARX (1UL << 29) /*!< DMA will be used for RX, requires DMA setup outside of the driver */
|
||||
#define ROM_SPIS_FLAG_TXIGNORE (1UL << 27) /*!< Ignores transmit data regardless of txBuff, transmit data callback will not be called, stops when txSz = 0 */
|
||||
#define ROM_SPIS_FLAG_RXIGNORE (1UL << 26) /*!< Ignores receive data regardless of rxBuff/rxSz, receive data callback will not be called */
|
||||
#define ROM_SPIS_FLAG_USERBITS (0xFFFF) /*!< Application can safely use the flag bits designated by this mask */
|
||||
|
||||
/** @brief SPI transfer configuration structure - once of these needs to be setup for
|
||||
* each SPI select (SSEL) used on the slave. If only SSEL0 is used, it only needs to be setup
|
||||
* for that one slave select. */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
uint8_t mode; /*!< Mode selection for this transfer (ROM_SPI_CLOCK_MODE_T) */
|
||||
uint8_t lsbFirst; /*!< 0 for msb sent/recv first, !0 = for lsb send/recv first */
|
||||
uint8_t dataBits; /*!< Data transfer size in bits, between 1 and 16, txBuff and rxBuff must be 16-bit aligned if >8 */
|
||||
uint8_t reserved;
|
||||
} ROM_SPIS_SLAVE_T;
|
||||
|
||||
/** @brief SPI slave transfer descriptor */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
const void *txBuff; /*!< Pointer to array of datum to be transmitted, must be 16-bit aligned if datum bits >8 */
|
||||
uint32_t txSz; /*!< Size of the transmit buffer (txBuff) in items (not bytes) before transmit callback is called */
|
||||
uint32_t txSent; /*!< Number of items (not bytes) sent between SSEL assertion and deassertion */
|
||||
void *rxBuff; /*!< Pointer memory where datum received from SPI be stored, must be 16-bit aligned if datum bits >8 */
|
||||
uint32_t rxSz; /*!< Size of the receive buffer (rxBuff) in items (not bytes) before receive callback is called */
|
||||
uint32_t rxRecv; /*!< Number of items (not bytes) received between SSEL assertion and deassertion */
|
||||
uint32_t flags; /*!< Optional transfer flags, may be modified by driver */
|
||||
volatile ErrorCode_t status; /*!< Status of the current SPI transfer (ErrorCode_t), must be 32-bits */
|
||||
} ROM_SPIS_XFER_T;
|
||||
|
||||
/** @brief SPI slave callback IDs */
|
||||
typedef enum {
|
||||
ROM_SPIS_ASSERTSSEL_CB = 0, /*!< Callback ID for SPI slave select (SSEL) assertion */
|
||||
ROM_SPIS_DATATRANSMIT_CB, /*!< Callback ID for SPI slave transmit start */
|
||||
ROM_SPIS_DATATRECEIVE_CB, /*!< Callback ID for SPI slave receive start */
|
||||
ROM_SPIS_DEASSERTSSEL_CB /*!< Callback ID for SPI slave select (SSEL) de-assertion (completion callback) */
|
||||
} ROM_SPIS_CALLBACK_T;
|
||||
|
||||
/** @brief SPI slave select assert callback
|
||||
* This callback is called from the SPI slave handler when the SPI slave
|
||||
* selects the slave (asserts SSEL). The callback is only called if it has been registered.
|
||||
*/
|
||||
typedef void (*spisSlaveXferCSAssertCB)(ROM_SPIS_HANDLE_T spisHandle, uint8_t slaveNum);
|
||||
|
||||
/** @brief SPI slave data receive start callback
|
||||
* The SPI slave state machine will call this optional function when it needs a buffer to
|
||||
* receive data. The callback can be used to setup DMA or alter the receive buffer size. The
|
||||
* callback is only called if it has been registered, the buffer has been fully used, and
|
||||
* data is pending is the receive FIFO. When using DMA, this callback must be enabled and
|
||||
* used for DMA setup.
|
||||
*/
|
||||
typedef void (*spisSlaveReceiveCB)(ROM_SPIS_HANDLE_T spisHandle, ROM_SPIS_XFER_T *pXfer);
|
||||
|
||||
/** @brief SPI slave data transmit start callback
|
||||
* The SPI slave state machine will call this optional function prior to data transfer.
|
||||
* The callback can be used to setup DMA or alter the receive buffer size. The callback
|
||||
* is only called if it has been registered, the buffer has been fully used, and data is
|
||||
* needed to populate the transmit FIFO. When using DMA, this callback must be enabled and
|
||||
* used for DMA setup.
|
||||
*/
|
||||
typedef void (*spisSlaveTransmitCB)(ROM_SPIS_HANDLE_T spisHandle, ROM_SPIS_XFER_T *pXfer);
|
||||
|
||||
/** @brief SPI slave transfer select deassert data callback
|
||||
* This callback is called from the SPI slave handler when the SPI slave
|
||||
* deasserts the slave select. The callback is only called if it has been registered.
|
||||
*/
|
||||
typedef void (*spisSlaveXferCSDeAssertCB)(ROM_SPIS_HANDLE_T spisHandle, ROM_SPIS_XFER_T *pXfer);
|
||||
|
||||
/** @brief SPI slave initialization structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
|
||||
uint32_t base; /*!< Base address of SPI peripheral to use */
|
||||
uint8_t spiPol[4]; /*!< SPI SSEL pollarity for each slave select, 0 = active low, !0 = active high */
|
||||
} ROM_SPIS_INIT_T;
|
||||
|
||||
/** @brief SPI slave ROM indirect function structure */
|
||||
typedef PRE_PACK struct POST_PACK {
|
||||
uint32_t (*GetMemSize)(void); /*!< Returns needed memory size required for run-time context of SPI slave driver */
|
||||
ROM_SPIS_HANDLE_T (*Init)(void *mem, const ROM_SPIS_INIT_T *pInit); /*!< Initializes the SPI slave driver and peripheral */
|
||||
void (*RegisterCallback)(ROM_SPIS_HANDLE_T pHandle, uint32_t cbIndex, void *pCB); /*!< Registers an SPI slave callback */
|
||||
ErrorCode_t (*SetupSlave)(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_SLAVE_T *pSlaveSetup); /*!< Setup SPI slave transfer configuration */
|
||||
ErrorCode_t (*Transfer)(ROM_SPIS_HANDLE_T pHandle, ROM_SPIS_XFER_T *pXfer); /*!< Prepare a SPI slave transfer */
|
||||
void (*TransferHandler)(ROM_SPIS_HANDLE_T pHandle); /*!< SPI slave transfer (interrupt) handler */
|
||||
uint32_t (*GetDriverVersion)(void);
|
||||
} ROM_SPISD_API_T;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
extern const ROM_SPISD_API_T spis_api; // so application program can access pointer to
|
||||
// function table
|
||||
|
||||
#endif /* __HW_SPISD_ROM_API_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,107 @@
|
||||
/*
|
||||
* @brief UART ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef _HW_UART_H
|
||||
#define _HW_UART_H
|
||||
|
||||
#define UART_DRIVER_VERSION 0x0100
|
||||
|
||||
/*******************
|
||||
* INCLUDE FILES *
|
||||
********************/
|
||||
#include <stdint.h>
|
||||
|
||||
/* UART Status Register bits */
|
||||
#define UART_RXRDY (1 << 0) /* Receive data ready */
|
||||
#define UART_RXIDLE (1 << 1) /* Receiver Idle */
|
||||
#define UART_TXRDY (1 << 2) /* Transmitter ready */
|
||||
#define UART_TXIDLE (1 << 3) /* Transmitter Idle */
|
||||
#define UART_RXDERR (0xF100) /* overrun err, frame err, parity err, RxNoise err */
|
||||
#define UART_TXDERR (0x0200) /* underrun err */
|
||||
#define UART_START (0x1000)
|
||||
|
||||
/* UART Interrupt register bits */
|
||||
#define UART_INT_RXRDY (1 << 0)
|
||||
#define UART_INT_TXRDY (1 << 2)
|
||||
#define UART_INT_TXIDLE (1 << 3)
|
||||
#define UART_INT_CTS (1 << 5)
|
||||
#define UART_INT_TXDIS (1 << 6)
|
||||
#define UART_INT_OVR (1 << 8)
|
||||
#define UART_INT_BREAK (1 << 11)
|
||||
#define UART_INT_START (1 << 12)
|
||||
#define UART_INT_FRMERR (1 << 13)
|
||||
#define UART_INT_PARERR (1 << 14)
|
||||
#define UART_INT_RXNOISE (1 << 15)
|
||||
#define UART_INT_ABAUDERR (1 << 16)
|
||||
|
||||
/* Configuration register bits */
|
||||
#define UARTEN 1
|
||||
|
||||
#define UART_CTL_TXDIS (1UL << 6)
|
||||
#define UART_CTL_TXBRKEN (1UL << 1)
|
||||
#define UART_CTL_AUTOBAUD (1UL << 16)
|
||||
#define UART_CFG_RES (2UL | (1UL << 10) | (1UL << 13) | (1UL << 17) | (0xFFUL << 24))
|
||||
#define UART_CFG_ENABLE 1
|
||||
#define UART_PAR_MASK (3 << 4)
|
||||
#define UART_DATA_MASK (3 << 2)
|
||||
#define UART_CTL_RES (1UL | (7UL << 3) | (1UL << 7) | (0x3FUL << 10) | (0x7FFFUL << 17))
|
||||
#define UART_IDLE_MASK (1 << 3)
|
||||
#define UART_STAT_CTS (1 << 4)
|
||||
#define UART_STAT_BREAK (1 << 10)
|
||||
#define UART_STAT_RXIDLE (1 << 1)
|
||||
|
||||
/*******************
|
||||
* EXPORTED MACROS *
|
||||
********************/
|
||||
#define ECHO_EN 1
|
||||
#define ECHO_DIS 0
|
||||
|
||||
/*********************
|
||||
* EXPORTED TYPEDEFS *
|
||||
**********************/
|
||||
|
||||
typedef struct { /* UART registers Structure */
|
||||
volatile uint32_t CFG; /*!< Offset: 0x000 Configuration register */
|
||||
volatile uint32_t CTL; /*!< Offset: 0x004 Control register */
|
||||
volatile uint32_t STAT; /*!< Offset: 0x008 Status register */
|
||||
volatile uint32_t INTENSET; /*!< Offset: 0x00C Interrupt Enable Read and Set register */
|
||||
volatile uint32_t INTENCLR; /*!< Offset: 0x010 Interrupt Enable Clear register */
|
||||
const volatile uint32_t RXDAT; /*!< Offset: 0x014 Receiver Data register */
|
||||
const volatile uint32_t RXDATSTAT; /*!< Offset: 0x018 Rx Data with status */
|
||||
volatile uint32_t TXDAT; /*!< Offset: 0x01C Transmitter Data Register */
|
||||
volatile uint32_t BRG; /*!< Offset: 0x020 Baud Rate Generator register */
|
||||
const volatile uint32_t INTSTAT; /*!< Offset: 0x024 Interrupt Status register */
|
||||
volatile uint32_t OSR; /*!< Offset: 0x028 Oversampling register */
|
||||
volatile uint32_t ADR; /*!< Offset: 0x02C Address register (for automatic address matching) */
|
||||
} UART_REGS_T;
|
||||
typedef UART_REGS_T LPC_USART_T;
|
||||
|
||||
#endif /* _HW_UART_H */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,162 @@
|
||||
/*
|
||||
* @brief LPC5410X Input Mux Registers and Driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __INMUX_5410X_H_
|
||||
#define __INMUX_5410X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup INMUX_5410X CHIP: LPC5410X Input Mux Registers and Driver
|
||||
* @ingroup CHIP_5410X_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LPC5410X Input Mux Register Block Structure
|
||||
*/
|
||||
typedef struct { /*!< INMUX Structure */
|
||||
__IO uint32_t RESERVED0[6];
|
||||
__I uint32_t RESERVED1[42];
|
||||
__IO uint32_t PINTSEL[8]; /*!< Pin interrupt select registers */
|
||||
__IO uint32_t DMA_ITRIG_INMUX[22]; /*!< Input mux register for DMA trigger inputs */
|
||||
__I uint32_t RESERVED2[2];
|
||||
__IO uint32_t DMA_OTRIG_INMUX[4]; /*!< Input mux register for DMA trigger inputs */
|
||||
__I uint32_t RESERVED3[4];
|
||||
__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement ref clock */
|
||||
__IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement target clock */
|
||||
} LPC_INMUX_T;
|
||||
|
||||
/**
|
||||
* @brief GPIO Pin Interrupt Pin Select (sets PINTSEL register)
|
||||
* @param pintSel : GPIO PINTSEL interrupt, should be: 0 to 7
|
||||
* @param portNum : GPIO port number interrupt, should be: 0 to 1
|
||||
* @param pinNum : GPIO pin number Interrupt, should be: 0 to 31
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_INMUX_PinIntSel(uint8_t pintSel, uint8_t portNum, uint8_t pinNum)
|
||||
{
|
||||
LPC_INMUX->PINTSEL[pintSel] = (portNum * 32) + pinNum;
|
||||
}
|
||||
|
||||
/* DMA triggers that can mapped to DMA channels */
|
||||
typedef enum {
|
||||
DMATRIG_ADC0_SEQA_IRQ = 0, /*!< ADC0 sequencer A interrupt as trigger */
|
||||
DMATRIG_ADC0_SEQB_IRQ, /*!< ADC0 sequencer B interrupt as trigger */
|
||||
DMATRIG_SCT0_DMA0, /*!< SCT 0, DMA 0 as trigger */
|
||||
DMATRIG_SCT0_DMA1, /*!< SCT 1, DMA 1 as trigger */
|
||||
DMATRIG_TIMER0_MATCH0, /*!< Timer 0, match 0 trigger */
|
||||
DMATRIG_TIMER0_MATCH1, /*!< Timer 0, match 1 trigger */
|
||||
DMATRIG_TIMER1_MATCH0, /*!< Timer 1, match 0 trigger */
|
||||
DMATRIG_TIMER1_MATCH1, /*!< Timer 1, match 1 trigger */
|
||||
DMATRIG_TIMER2_MATCH0, /*!< Timer 2, match 0 trigger */
|
||||
DMATRIG_TIMER2_MATCH1, /*!< Timer 2, match 1 trigger */
|
||||
DMATRIG_TIMER3_MATCH0, /*!< Timer 3, match 0 trigger */
|
||||
DMATRIG_TIMER3_MATCH1, /*!< Timer 3, match 1 trigger */
|
||||
DMATRIG_TIMER4_MATCH0, /*!< Timer 4, match 0 trigger */
|
||||
DMATRIG_TIMER4_MATCH1, /*!< Timer 4, match 1 trigger */
|
||||
DMATRIG_PININT0, /*!< Pin interrupt 0 trigger */
|
||||
DMATRIG_PININT1, /*!< Pin interrupt 1 trigger */
|
||||
DMATRIG_PININT2, /*!< Pin interrupt 2 trigger */
|
||||
DMATRIG_PININT3, /*!< Pin interrupt 3 trigger */
|
||||
DMATRIG_OUTMUX0, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
|
||||
DMATRIG_OUTMUX1, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
|
||||
DMATRIG_OUTMUX2, /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
|
||||
DMATRIG_OUTMUX3 /*!< DMA trigger tied to this source, Select with Chip_INMUX_SetDMAOutMux */
|
||||
} DMA_TRIGSRC_T;
|
||||
|
||||
/**
|
||||
* @brief Select a trigger source for a DMA channel
|
||||
* @param ch : DMA channel number
|
||||
* @param trig : Trigger source for the DMA channel
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_INMUX_SetDMATrigger(uint8_t ch, DMA_TRIGSRC_T trig)
|
||||
{
|
||||
LPC_INMUX->DMA_ITRIG_INMUX[ch] = (uint32_t) trig;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects a DMA trigger source for the DMATRIG_OUTMUXn IDs
|
||||
* @param index : Select 0 to 3 to sets the source for DMATRIG_OUTMUX0 to DMATRIG_OUTMUX3
|
||||
* @param dmaCh : DMA channel to select for DMATRIG_OUTMUXn source
|
||||
* @return Nothing
|
||||
* @note This function sets the DMA trigger (out) source used with the DMATRIG_OUTMUXn
|
||||
* trigger source.
|
||||
*/
|
||||
STATIC INLINE void Chip_INMUX_SetDMAOutMux(uint8_t index, uint8_t dmaCh)
|
||||
{
|
||||
LPC_INMUX->DMA_OTRIG_INMUX[index] = (uint32_t) dmaCh;
|
||||
}
|
||||
|
||||
/* Freqeuency measure reference and target clock sources */
|
||||
typedef enum {
|
||||
FREQMSR_CLKIN = 0, /*!< CLKIN pin */
|
||||
FREQMSR_IRC, /*!< Internal RC (IRC) oscillator */
|
||||
FREQMSR_WDOSC, /*!< Watchdog oscillator */
|
||||
FREQMSR_32KHZOSC, /*!< 32KHz (RTC) oscillator rate */
|
||||
FREQ_MEAS_MAIN_CLK, /*!< main system clock */
|
||||
FREQMSR_PIO0_4, /*!< External pin PIO0_4 as input rate */
|
||||
FREQMSR_PIO0_20, /*!< External pin PIO0_20 as input rate */
|
||||
FREQMSR_PIO0_24, /*!< External pin PIO0_24 as input rate */
|
||||
FREQMSR_PIO1_4 /*!< External pin PIO1_4 as input rate */
|
||||
} FREQMSR_SRC_T;
|
||||
|
||||
/**
|
||||
* @brief Selects a reference clock used with the frequency measure function
|
||||
* @param ref : Frequency measure function reference clock
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_INMUX_SetFreqMeasRefClock(FREQMSR_SRC_T ref)
|
||||
{
|
||||
LPC_INMUX->FREQMEAS_REF = (uint32_t) ref;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects a target clock used with the frequency measure function
|
||||
* @param targ : Frequency measure function reference clock
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_INMUX_SetFreqMeasTargClock(FREQMSR_SRC_T targ)
|
||||
{
|
||||
LPC_INMUX->FREQMEAS_TARGET = (uint32_t) targ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __INMUX_5410X_H_ */
|
||||
@@ -0,0 +1,58 @@
|
||||
/*
|
||||
* @brief LPC5410X IOCON driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Set all I/O Control pin muxing */
|
||||
void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T *pinArray, uint32_t arrayLength)
|
||||
{
|
||||
uint32_t ix;
|
||||
|
||||
for (ix = 0; ix < arrayLength; ix++ ) {
|
||||
Chip_IOCON_PinMuxSet(pIOCON, pinArray[ix].port, pinArray[ix].pin, pinArray[ix].modefunc);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,139 @@
|
||||
/*
|
||||
* @brief LPC5410X IOCON register block and driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __IOCON_5410X_H_
|
||||
#define __IOCON_5410X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup IOCON_5410X CHIP: LPC5410X IOCON register block and driver
|
||||
* @ingroup CHIP_5410X_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LPC5410X IO Configuration Unit register block structure
|
||||
*/
|
||||
typedef struct { /*!< LPC5410X IOCON Structure */
|
||||
__IO uint32_t PIO[2][32];
|
||||
} LPC_IOCON_T;
|
||||
|
||||
/**
|
||||
* @brief Array of IOCON pin definitions passed to Chip_IOCON_SetPinMuxing() must be in this format
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t port : 8; /* Pin port */
|
||||
uint32_t pin : 8; /* Pin number */
|
||||
uint32_t modefunc : 16; /* Function and mode */
|
||||
} PINMUX_GRP_T;
|
||||
|
||||
/**
|
||||
* IOCON function and mode selection definitions
|
||||
* See the User Manual for specific modes and functions supported by the
|
||||
* various LPC15XX pins.
|
||||
*/
|
||||
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
|
||||
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
|
||||
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
|
||||
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
|
||||
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
|
||||
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
|
||||
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
|
||||
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
|
||||
#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */
|
||||
#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */
|
||||
#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */
|
||||
#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */
|
||||
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */
|
||||
#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */
|
||||
#define IOCON_I2C_SLEW (0x1 << 5) /*!< I2C Slew Rate Control */
|
||||
#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */
|
||||
#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */
|
||||
#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */
|
||||
#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */
|
||||
#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */
|
||||
#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */
|
||||
#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */
|
||||
#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */
|
||||
#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */
|
||||
#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */
|
||||
#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */
|
||||
#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */
|
||||
#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */
|
||||
#define IOCON_CLKDIV(div) ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
|
||||
|
||||
/**
|
||||
* @brief Sets I/O Control pin mux
|
||||
* @param pIOCON : The base of IOCON peripheral on the chip
|
||||
* @param port : GPIO port to mux
|
||||
* @param pin : GPIO pin to mux
|
||||
* @param modefunc : OR'ed values or type IOCON_*
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
|
||||
{
|
||||
pIOCON->PIO[port][pin] = modefunc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief I/O Control pin mux
|
||||
* @param pIOCON : The base of IOCON peripheral on the chip
|
||||
* @param port : GPIO port to mux
|
||||
* @param pin : GPIO pin to mux
|
||||
* @param mode : OR'ed values or type IOCON_*
|
||||
* @param func : Pin function, value of type IOCON_FUNC?
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
|
||||
{
|
||||
Chip_IOCON_PinMuxSet(pIOCON, port, pin, (uint32_t) (mode | func));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set all I/O Control pin muxing
|
||||
* @param pIOCON : The base of IOCON peripheral on the chip
|
||||
* @param pinArray : Pointer to array of pin mux selections
|
||||
* @param arrayLength : Number of entries in pinArray
|
||||
* @return Nothing
|
||||
*/
|
||||
void Chip_IOCON_SetPinMuxing(LPC_IOCON_T *pIOCON, const PINMUX_GRP_T *pinArray, uint32_t arrayLength);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IOCON_5410X_H_ */
|
||||
@@ -0,0 +1,47 @@
|
||||
--create .\keil_output\core_m4\lib_chip_5410x.lib
|
||||
.\keil_output\core_m4\ring_buffer.o
|
||||
.\keil_output\core_m4\chip_5410x.o
|
||||
.\keil_output\core_m4\clock_5410x.o
|
||||
.\keil_output\core_m4\crc_5410x.o
|
||||
.\keil_output\core_m4\gpio_5410x.o
|
||||
.\keil_output\core_m4\iocon_5410x.o
|
||||
.\keil_output\core_m4\pinint_5410x.o
|
||||
.\keil_output\core_m4\sct_5410x.o
|
||||
.\keil_output\core_m4\sct_pwm_5410x.o
|
||||
.\keil_output\core_m4\syscon_5410x.o
|
||||
.\keil_output\core_m4\sysinit_5410x.o
|
||||
.\keil_output\core_m4\timer_5410x.o
|
||||
.\keil_output\core_m4\utick_5410x.o
|
||||
.\keil_output\core_m4\wwdt_5410x.o
|
||||
.\keil_output\core_m4\rtc_5410x.o
|
||||
.\keil_output\core_m4\fpu_init.o
|
||||
.\keil_output\core_m4\iap.o
|
||||
.\keil_output\core_m4\gpiogroup_5410x.o
|
||||
.\keil_output\core_m4\stopwatch_5410x.o
|
||||
.\keil_output\core_m4\ritimer_5410x.o
|
||||
.\keil_output\core_m4\romapi_adc.o
|
||||
.\keil_output\core_m4\romapi_dma.o
|
||||
.\keil_output\core_m4\romapi_i2cm.o
|
||||
.\keil_output\core_m4\romapi_i2cmon.o
|
||||
.\keil_output\core_m4\romapi_i2cs.o
|
||||
.\keil_output\core_m4\romapi_spim.o
|
||||
.\keil_output\core_m4\romapi_spis.o
|
||||
.\keil_output\core_m4\romapi_uart.o
|
||||
.\keil_output\core_m4\rtc_ut.o
|
||||
.\keil_output\core_m4\pll_5410x.o
|
||||
.\keil_output\core_m4\hw_adc.o
|
||||
.\keil_output\core_m4\hw_dmaaltd.o
|
||||
.\keil_output\core_m4\hw_dmaaltd_rom_api.o
|
||||
.\keil_output\core_m4\hw_i2cmd.o
|
||||
.\keil_output\core_m4\hw_i2cmd_rom_api.o
|
||||
.\keil_output\core_m4\hw_i2cmond.o
|
||||
.\keil_output\core_m4\hw_i2cmond_rom_api.o
|
||||
.\keil_output\core_m4\hw_i2csd.o
|
||||
.\keil_output\core_m4\hw_i2csd_rom_api.o
|
||||
.\keil_output\core_m4\hw_spimd_rom_api.o
|
||||
.\keil_output\core_m4\hw_spisd.o
|
||||
.\keil_output\core_m4\hw_spisd_rom_api.o
|
||||
.\keil_output\core_m4\hw_spimd.o
|
||||
.\keil_output\core_m4\hw_uart.o
|
||||
.\keil_output\core_m4\fifo_5410x.o
|
||||
.\power_lib\keil\lib_power.lib
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,173 @@
|
||||
/*
|
||||
* @brief LPC5410X Mailbox M4/M0+ driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __MAILBOX_5410X_H_
|
||||
#define __MAILBOX_5410X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup MAILBOX_5410X CHIP: LPC5410X Mailbox M4/M0+ driver
|
||||
* @ingroup CHIP_5410X_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Mailbox indexes */
|
||||
typedef enum {
|
||||
MAILBOX_CM0PLUS = 0,
|
||||
MAILBOX_CM4
|
||||
} MBOX_IDX_T;
|
||||
#define MAILBOX_AVAIL (MAILBOX_CM4 + 1) /* Number of available mailboxes */
|
||||
|
||||
/** Individual mailbox IRQ structure */
|
||||
typedef struct {
|
||||
__IO uint32_t IRQ; /*!< Mailbox data */
|
||||
__O uint32_t IRQSET; /*!< Mailbox data set bits only */
|
||||
__O uint32_t IRQCLR; /*!< Mailbox dataclearset bits only */
|
||||
__I uint32_t RESERVED;
|
||||
} LPC_MBOXIRQ_T;
|
||||
|
||||
/** Mailbox register structure */
|
||||
typedef struct { /*!< Mailbox register structure */
|
||||
LPC_MBOXIRQ_T BOX[MAILBOX_AVAIL]; /*!< Mailbox, offset 0 = M0+, offset 1 = M4 */
|
||||
LPC_MBOXIRQ_T RESERVED1[15 - MAILBOX_AVAIL];
|
||||
__I uint32_t RESERVED2[2];
|
||||
__IO uint32_t MUTEX; /*!< Mutex */
|
||||
} LPC_MBOX_T;
|
||||
|
||||
/**
|
||||
* @brief Initialize mailbox
|
||||
* @param pMBOX : Pointer to the mailbox register structure
|
||||
* @return Nothing
|
||||
* @note Even if both cores use the amilbox, only 1 core should initialize it.
|
||||
*/
|
||||
STATIC INLINE void Chip_MBOX_Init(LPC_MBOX_T *pMBOX)
|
||||
{
|
||||
Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_MAILBOX);
|
||||
Chip_SYSCON_PeriphReset(RESET_MAILBOX);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Shutdown mailbox
|
||||
* @param pMBOX : Pointer to the mailbox register structure
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_MBOX_DeInit(LPC_MBOX_T *pMBOX)
|
||||
{
|
||||
Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_MAILBOX);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set data value in the mailbox based on the CPU ID
|
||||
* @param pMBOX : Pointer to the mailbox register structure
|
||||
* @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4
|
||||
* @param mboxData : data to send in the mailbox
|
||||
* @return Nothing
|
||||
* @note Sets a data value to send via the MBOX to the other core.
|
||||
*/
|
||||
STATIC INLINE void Chip_MBOX_SetValue(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxData)
|
||||
{
|
||||
pMBOX->BOX[cpu_id].IRQ = mboxData;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set data bits in the mailbox based on the CPU ID
|
||||
* @param pMBOX : Pointer to the mailbox register structure
|
||||
* @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4
|
||||
* @param mboxSetBits : data bits to set in the mailbox
|
||||
* @return Nothing
|
||||
* @note Sets data bits to send via the MBOX to the other core, A value of 0 will
|
||||
* do nothing. Only sets bits selected with a 1 in it's bit position.
|
||||
*/
|
||||
STATIC INLINE void Chip_MBOX_SetValueBits(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxSetBits)
|
||||
{
|
||||
pMBOX->BOX[cpu_id].IRQSET = mboxSetBits;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear data bits in the mailbox based on the CPU ID
|
||||
* @param pMBOX : Pointer to the mailbox register structure
|
||||
* @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4
|
||||
* @param mboxClrBits : data bits to clear in the mailbox
|
||||
* @return Nothing
|
||||
* @note Clear data bits to send via the MBOX to the other core. A value of 0 will
|
||||
* do nothing. Only clears bits selected with a 1 in it's bit position.
|
||||
*/
|
||||
STATIC INLINE void Chip_MBOX_ClearValueBits(LPC_MBOX_T *pMBOX, uint32_t cpu_id, uint32_t mboxClrBits)
|
||||
{
|
||||
pMBOX->BOX[cpu_id].IRQCLR = mboxClrBits;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get data in the mailbox based on the cpu_id
|
||||
* @param pMBOX : Pointer to the mailbox register structure
|
||||
* @param cpu_id : MAILBOX_CM0PLUS is M0+ or MAILBOX_CM4 is M4
|
||||
* @return Current mailbox data
|
||||
*/
|
||||
STATIC INLINE uint32_t Chip_MBOX_GetValue(LPC_MBOX_T *pMBOX, uint32_t cpu_id)
|
||||
{
|
||||
return pMBOX->BOX[cpu_id].IRQ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get MUTEX state and lock mutex
|
||||
* @param pMBOX : Pointer to the mailbox register structure
|
||||
* @return See note
|
||||
* @note Returns '1' if the mutex was taken or '0' if another resources has the
|
||||
* mutex locked. Once a mutex is taken, it can be returned with the Chip_MBOX_SetMutex()
|
||||
* function.
|
||||
*/
|
||||
STATIC INLINE uint32_t Chip_MBOX_GetMutex(LPC_MBOX_T *pMBOX)
|
||||
{
|
||||
return pMBOX->MUTEX;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set MUTEX state
|
||||
* @param pMBOX : Pointer to the mailbox register structure
|
||||
* @return Nothing
|
||||
* @note Sets mutex state to '1' and allows other resources to get the mutex
|
||||
*/
|
||||
STATIC INLINE void Chip_MBOX_SetMutex(LPC_MBOX_T *pMBOX)
|
||||
{
|
||||
pMBOX->MUTEX = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MAILBOX_5410X_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* @brief LPC5410X Pin Interrupt and Pattern Match Registers and driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Set source for pattern match engine */
|
||||
void Chip_PININT_SetPatternMatchSrc(LPC_PIN_INT_T *pPININT,
|
||||
Chip_PININT_SELECT_T channelNum,
|
||||
Chip_PININT_BITSLICE_T sliceNum)
|
||||
{
|
||||
uint32_t pmsrc_reg;
|
||||
|
||||
/* Source source for pattern matching */
|
||||
pmsrc_reg = pPININT->PMSRC & ~(PININT_SRC_BITSOURCE_MASK << (PININT_SRC_BITSOURCE_START + (sliceNum * 3)));
|
||||
pPININT->PMSRC = pmsrc_reg | (channelNum << (PININT_SRC_BITSOURCE_START + (sliceNum * 3)));
|
||||
}
|
||||
|
||||
/* Configure Pattern match engine */
|
||||
void Chip_PININT_SetPatternMatchConfig(LPC_PIN_INT_T *pPININT, Chip_PININT_BITSLICE_T sliceNum,
|
||||
Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point)
|
||||
{
|
||||
uint32_t pmcfg_reg;
|
||||
|
||||
/* Configure bit slice configuration */
|
||||
pmcfg_reg = pPININT->PMCFG & ~(PININT_SRC_BITCFG_MASK << (PININT_SRC_BITCFG_START + (sliceNum * 3)));
|
||||
pPININT->PMCFG = pmcfg_reg | (slice_cfg << (PININT_SRC_BITCFG_START + (sliceNum * 3)));
|
||||
|
||||
/* If end point is true, enable the bits */
|
||||
if (end_point == true) {
|
||||
/* By default slice 7 is final component */
|
||||
if (sliceNum != PININTBITSLICE7) {
|
||||
pPININT->PMCFG |= (0x1 << sliceNum);
|
||||
}
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* @brief LPC5410x enhanced boot block
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __PINTABLE_5410X_H_
|
||||
#define __PINTABLE_5410X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup PINTAB_5410X CHIP: LPC5410X Enhanced boot block support
|
||||
* @ingroup CHIP_5410X_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LPC5410X Pin table structure used for enhanced boot block support
|
||||
*/
|
||||
struct PINTABLE {
|
||||
/* pin table marker: Should be 0xFEEDA5A5 */
|
||||
uint32_t marker;
|
||||
/* img_type:
|
||||
0 = Normal image check IRQ line to halt boot
|
||||
1 = Wait for AP to send SH_CMD_BOOT command
|
||||
2 = Boot image with no AP checks
|
||||
3 = No CRC or AP checks needed. Used during development */
|
||||
uint8_t img_type;
|
||||
/* ifSel: Interface selection for host
|
||||
(0,=AUTODETECT, 1=I2C0, 2=I2C1, 3=I2C2, 4=SPI0, 5=SPI1) */
|
||||
uint8_t ifSel;
|
||||
/* hostIrqPortPin: Host IRQ port (bits 7:5) and pins (bits 4:0) */
|
||||
uint8_t hostIrqPortPin;
|
||||
/* hostMisoPortPin: SPI MISO port (bits 7:5) and pins (bits 4:0) */
|
||||
uint8_t hostMisoPortPin;
|
||||
/* hostMosiPortPin: SPI MOSI port (bits 7:5) and pins (bits 4:0) */
|
||||
uint8_t hostMosiPortPin;
|
||||
/* hostSselPortPin: SPI SEL port (bits 7:5) and pins (bits 4:0) */
|
||||
uint8_t hostSselPortPin;
|
||||
/* hostSckPortPin: SPI SCK port (bits 7:5) and pins (bits 4:0) */
|
||||
uint8_t hostSckPortPin;
|
||||
/* xorVal: XOR value of the 7 bytes above */
|
||||
uint8_t xorVal;
|
||||
/* CRC32 length and value fields */
|
||||
uint32_t crc32_len;
|
||||
uint32_t crc32_val;
|
||||
/* Application image version number */
|
||||
uint32_t version;
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PINTAB_5410X_H_ */
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,184 @@
|
||||
/*
|
||||
* @brief LPC5410X Power Management declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __PMU_5410X_H_
|
||||
#define __PMU_5410X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup PMU_5410X CHIP: LPC5410X Power Management declarations and functions
|
||||
* @ingroup CHIP_5410X_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PMU register block structure
|
||||
* @note Most of the PMU support is handled by the PMU library.
|
||||
*/
|
||||
typedef struct {
|
||||
__I uint32_t RESERVED0[4];
|
||||
__I uint32_t RESERVED1[4];
|
||||
__I uint32_t RESERVED2[4];
|
||||
__I uint32_t RESERVED3[4];
|
||||
__I uint32_t RESERVED4;
|
||||
__IO uint32_t BODCTRL;
|
||||
__I uint32_t RESERVED5;
|
||||
__I uint32_t RESERVED6;
|
||||
__IO uint32_t DPDWAKESRC;
|
||||
} LPC_PMU_T;
|
||||
|
||||
/**
|
||||
* Brown-out detector reset level
|
||||
*/
|
||||
typedef enum {
|
||||
PMU_BODRSTLVL_0, /*!< Brown-out reset at ~1.5v */
|
||||
PMU_BODRSTLVL_1_50V = PMU_BODRSTLVL_0,
|
||||
PMU_BODRSTLVL_1, /*!< Brown-out reset at ~1.85v */
|
||||
PMU_BODRSTLVL_1_85V = PMU_BODRSTLVL_1,
|
||||
PMU_BODRSTLVL_2, /*!< Brown-out reset at ~2.0v */
|
||||
PMU_BODRSTLVL_2_00V = PMU_BODRSTLVL_2,
|
||||
PMU_BODRSTLVL_3, /*!< Brown-out reset at ~2.3v */
|
||||
PMU_BODRSTLVL_2_30V = PMU_BODRSTLVL_3
|
||||
} CHIP_PMU_BODRSTLVL_T;
|
||||
|
||||
/**
|
||||
* Brown-out detector interrupt level
|
||||
*/
|
||||
typedef enum CHIP_PMU_BODRINTVAL {
|
||||
PMU_BODINTVAL_LVL0, /*!< Brown-out interrupt at ~2.05v */
|
||||
PMU_BODINTVAL_2_05v = PMU_BODINTVAL_LVL0,
|
||||
PMU_BODINTVAL_LVL1, /*!< Brown-out interrupt at ~2.45v */
|
||||
PMU_BODINTVAL_2_45v = PMU_BODINTVAL_LVL1,
|
||||
PMU_BODINTVAL_LVL2, /*!< Brown-out interrupt at ~2.75v */
|
||||
PMU_BODINTVAL_2_75v = PMU_BODINTVAL_LVL2,
|
||||
PMU_BODINTVAL_LVL3, /*!< Brown-out interrupt at ~3.05v */
|
||||
PMU_BODINTVAL_3_05v = PMU_BODINTVAL_LVL3
|
||||
} CHIP_PMU_BODRINTVAL_T;
|
||||
|
||||
/**
|
||||
* brown-out detection reset status (in BODCTRL register)
|
||||
*/
|
||||
#define PMU_BOD_RST (1 << 6)
|
||||
/**
|
||||
* brown-out detection interrupt status (in BODCTRL register)
|
||||
*/
|
||||
#define PMU_BOD_INT (1 << 7)
|
||||
|
||||
/**
|
||||
* @brief Set brown-out detection interrupt and reset levels
|
||||
* @param rstlvl : Brown-out detector reset level
|
||||
* @param intlvl : Brown-out interrupt level
|
||||
* @return Nothing
|
||||
* @note Brown-out detection reset will be disabled upon exiting this function.
|
||||
* Use Chip_PMU_EnableBODReset() to re-enable.
|
||||
*/
|
||||
STATIC INLINE void Chip_PMU_SetBODLevels(CHIP_PMU_BODRSTLVL_T rstlvl,
|
||||
CHIP_PMU_BODRINTVAL_T intlvl)
|
||||
{
|
||||
LPC_PMU->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable brown-out detection reset
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_PMU_EnableBODReset(void)
|
||||
{
|
||||
LPC_PMU->BODCTRL |= (1 << 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable brown-out detection reset
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_PMU_DisableBODReset(void)
|
||||
{
|
||||
LPC_PMU->BODCTRL &= ~(1 << 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable brown-out detection interrupt
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_PMU_EnableBODInt(void)
|
||||
{
|
||||
LPC_PMU->BODCTRL |= (1 << 5);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable brown-out detection interrupt
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_PMU_DisableBODInt(void)
|
||||
{
|
||||
LPC_PMU->BODCTRL &= ~(1 << 5);
|
||||
}
|
||||
|
||||
/**
|
||||
* Deep power down reset sources
|
||||
*/
|
||||
#define PMU_DPDWU_RESET (1 << 0) /*!< Deep powerdown wakeup by reset pin */
|
||||
#define PMU_DPDWU_RTC (1 << 1) /*!< Deep powerdown wakeup by RTC */
|
||||
#define PMU_DPDWU_BODRESET (1 << 2) /*!< Deep powerdown wakeup by brown out reset*/
|
||||
#define PMU_DPDWU_BODINTR (1 << 3) /*!< Deep powerdown wakeup by brown out interrupt */
|
||||
|
||||
/**
|
||||
* @brief Return wakeup sources from deep power down mode
|
||||
* @return Deep power down mode wakeup sources
|
||||
* @note Mask the return value with a PMU_DPDWU_* value to determine
|
||||
* the wakeup source from deep power down.
|
||||
*/
|
||||
STATIC INLINE uint32_t Chip_PMU_GetDPDWUSource(void)
|
||||
{
|
||||
return LPC_PMU->DPDWAKESRC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear a deep power down mode wakeup source
|
||||
* @param mask : Or'ed PMU_DPDWU_* values to clear
|
||||
* @return Nothing
|
||||
*/
|
||||
STATIC INLINE void Chip_PMU_ClearDPDWUSource(uint32_t mask)
|
||||
{
|
||||
LPC_PMU->DPDWAKESRC = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PMU_5410X_H_ */
|
||||
@@ -0,0 +1,167 @@
|
||||
/*
|
||||
* @brief LPC5410x Power library functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __POWER_LIB_5410X_H_
|
||||
#define __POWER_LIB_5410X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup POWER_LIBRARY_5410X CHIP: LPC5410X Power LIBRARY functions
|
||||
* The power library provides functions to control system power usage and
|
||||
* place the device into low power modes.<br>
|
||||
*
|
||||
* <b>Clock shutdown in sleep and power down modes</b><br>
|
||||
* When using the Chip_POWER_EnterPowerMode() function, system clocks are
|
||||
* shutdown based on the selected sleep or power down mode and the device
|
||||
* version being used. The following list details which clocks are shut down
|
||||
* in which modes for which device versions. You can keep a clock enabled
|
||||
* for a sleep or power down mode by enabling it in the 'peripheral_ctrl'
|
||||
* field in the Chip_POWER_EnterPowerMode() function.<br>
|
||||
*
|
||||
* Mode: Sleep<br>
|
||||
* No clocks are disabled for any chip version.<br>
|
||||
*
|
||||
* Mode: Deep sleep<br>
|
||||
* SYSCON_PDRUNCFG_PD_IRC_OSC<br>
|
||||
* SYSCON_PDRUNCFG_PD_IRC<br>
|
||||
* SYSCON_PDRUNCFG_PD_FLASH (v17.1 and later only)<br>
|
||||
* SYSCON_PDRUNCFG_PD_BOD_INTR<br>
|
||||
* SYSCON_PDRUNCFG_PD_ADC0<br>
|
||||
* SYSCON_PDRUNCFG_PD_ROM<br>
|
||||
* SYSCON_PDRUNCFG_PD_VDDA_ENA<br>
|
||||
* SYSCON_PDRUNCFG_PD_SYS_PLL<br>
|
||||
* SYSCON_PDRUNCFG_PD_VREFP<br>
|
||||
*
|
||||
* Mode: Power down<br>
|
||||
* SYSCON_PDRUNCFG_PD_IRC_OSC<br>
|
||||
* SYSCON_PDRUNCFG_PD_IRC<br>
|
||||
* SYSCON_PDRUNCFG_PD_FLASH (v17.1 and later only)<br>
|
||||
* SYSCON_PDRUNCFG_PD_BOD_RST<br>
|
||||
* SYSCON_PDRUNCFG_PD_BOD_INTR<br>
|
||||
* SYSCON_PDRUNCFG_PD_ADC0<br>
|
||||
* SYSCON_PDRUNCFG_PD_SRAM0B<br>
|
||||
* SYSCON_PDRUNCFG_PD_SRAM1<br>
|
||||
* SYSCON_PDRUNCFG_PD_SRAM2<br>
|
||||
* SYSCON_PDRUNCFG_PD_ROM<br>
|
||||
* SYSCON_PDRUNCFG_PD_VDDA_ENA<br>
|
||||
* SYSCON_PDRUNCFG_PD_WDT_OSC<br>
|
||||
* SYSCON_PDRUNCFG_PD_SYS_PLL<br>
|
||||
* SYSCON_PDRUNCFG_PD_VREFP<br>
|
||||
* SYSCON_PDRUNCFG_PD_32K_OSC<br>
|
||||
*
|
||||
* Mode: Deep power down<br>
|
||||
* All clocks are disabled for all chip versions.<br>
|
||||
*
|
||||
* If you are using a peripheral was a wakeup source for a power down mode,
|
||||
* it needs to be kept active with the call to Chip_POWER_EnterPowerMode(). For
|
||||
* example, if you are using the RTC to wake the system up from power down mode,
|
||||
* the 32KHz RTC oscillator needs to remain active, so the power down call would
|
||||
* look like this:<br>
|
||||
* Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, SYSCON_PDRUNCFG_PD_32K_OSC);<br>
|
||||
* If your application uses internal RAM beyond the first 8K, you will also need
|
||||
* to prevent power down of the IRAM like this:<br>
|
||||
* Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, (SYSCON_PDRUNCFG_PD_32K_OSC | SYSCON_PDRUNCFG_PD_SRAM0A));<br>
|
||||
* @ingroup CHIP_5410X_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets up the System PLL given the PLL input frequency and feedback multiplier
|
||||
* @param multiply_by : PLL multiplier, minimum of 1, maximum of 16
|
||||
* @param input_freq : Input frequency into the PLL
|
||||
* @return LPC_OK on success, or an error code (see error.h)
|
||||
*/
|
||||
uint32_t Chip_POWER_SetPLL(uint32_t multiply_by, uint32_t input_freq);
|
||||
|
||||
/**
|
||||
* @brief Set optimal system voltage based on passed system frequency
|
||||
* @param mode : Power mode
|
||||
* @param desired_freq : System (CPU) frequency
|
||||
* @return LPC_OK on success, or an error code (see error.h)
|
||||
* @note This function will adjust the system voltages to the lowest
|
||||
* levels that will support the passed mode and CPU frequency.
|
||||
*/
|
||||
uint32_t Chip_POWER_SetVoltage(PERF_MODE_T mode, uint32_t desired_freq);
|
||||
|
||||
/**
|
||||
* @brief Enters the selected power state
|
||||
* @param mode : Power mode
|
||||
* @param peripheral_ctrl : Peripherals that will remain powered up in the power state
|
||||
* @return Nothing
|
||||
* @note The 'peripheral_ctrl' field is a bitmask of bits from the
|
||||
* PDRUNCFG register (SYSCON_PDRUNCFG_PD_*) that describe which
|
||||
* peripherals can wake up the chip from the power state. These
|
||||
* peripherals are not powered down during the power state.<br>
|
||||
*/
|
||||
void Chip_POWER_EnterPowerMode(POWER_MODE_T mode, uint32_t peripheral_ctrl);
|
||||
|
||||
/* ROM versions */
|
||||
#define LPC5410X_ROMVER_0 (0x1100)
|
||||
#define LPC5410X_ROMVER_1 (0x1101)
|
||||
#define LPC5410X_ROMVER_2 (0x1102)
|
||||
|
||||
/**
|
||||
* @brief Fast powerdown for IRAM based applications
|
||||
* @param peripheral_ctrl : Peripherals that will remain powered up in the power down state
|
||||
* @return Nothing
|
||||
* @note The 'peripheral_ctrl' field is a bitmask of bits from the
|
||||
* PDRUNCFG register (SYSCON_PDRUNCFG_PD_*) that describe which
|
||||
* peripherals can wake up the chip from the power state. These
|
||||
* peripherals are not powered down during the power state.<br>
|
||||
* This function should only be used when not executing code in FLASH.
|
||||
* It will power down FLASH and leave it powered down on exit, so all
|
||||
* code should be placed in IRAM prior to calling. It provides a quicker
|
||||
* wakeup response than the default powerdown function
|
||||
* (Chip_POWER_EnterPowerMode(POWER_POWER_DOWN, ...)).
|
||||
*/
|
||||
void Chip_POWER_EnterPowerModeIramOnly(uint32_t peripheral_ctrl);
|
||||
|
||||
/**
|
||||
* @brief Return ROM version
|
||||
* @return ROM version
|
||||
* @note Will return one of the following version numbers:<br>
|
||||
* (0x1100) for v17.0 ROMs.<br>
|
||||
* (0x1101) for v17.1 ROMs.<br>
|
||||
* (0x1102) for v17.2 ROMs.<br>
|
||||
*/
|
||||
uint32_t Chip_POWER_GetROMVersion(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __POWER_LIB_5410X_H_ */
|
||||
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
* @brief LPC5410X RITimer chip driver
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*****************************************************************************
|
||||
* Private types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public types/enumerations/variables
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Private functions
|
||||
****************************************************************************/
|
||||
|
||||
/*****************************************************************************
|
||||
* Public functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Initialize the RIT */
|
||||
void Chip_RIT_Init(LPC_RITIMER_T *pRITimer)
|
||||
{
|
||||
Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_RIT);
|
||||
Chip_SYSCON_PeriphReset(RESET_RIT);
|
||||
|
||||
/* Default is timer disabled */
|
||||
pRITimer->CTRL = 0x0;
|
||||
}
|
||||
|
||||
/* DeInitialize the RIT */
|
||||
void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer)
|
||||
{
|
||||
pRITimer->CTRL = 0x0;
|
||||
Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_RIT);
|
||||
}
|
||||
|
||||
/* Set timer interval value */
|
||||
void Chip_RIT_SetTimerInterval(LPC_RITIMER_T *pRITimer, uint32_t time_interval)
|
||||
{
|
||||
uint32_t cmp_value;
|
||||
|
||||
/* Determine aapproximate compare value based on clock rate and passed interval */
|
||||
cmp_value = (Chip_Clock_GetMainClockRate() / 1000) * time_interval;
|
||||
|
||||
/* Set timer compare value */
|
||||
Chip_RIT_SetCOMPVAL(pRITimer, cmp_value);
|
||||
}
|
||||
|
||||
/* Set timer interval value (48-bit) */
|
||||
void Chip_RIT_SetTimerInterval64(LPC_RITIMER_T *pRITimer, uint64_t time_interval)
|
||||
{
|
||||
uint64_t cmp_value;
|
||||
|
||||
/* Determine aapproximate compare value based on clock rate and passed interval */
|
||||
cmp_value = (uint64_t) Chip_Clock_GetMainClockRate() / 1000;
|
||||
cmp_value = cmp_value * time_interval;
|
||||
|
||||
/* Set timer compare value */
|
||||
Chip_RIT_SetCOMPVAL64(pRITimer, cmp_value);
|
||||
}
|
||||
|
||||
/* Check whether interrupt is pending */
|
||||
IntStatus Chip_RIT_GetIntStatus(LPC_RITIMER_T *pRITimer)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
if ((pRITimer->CTRL & RIT_CTRL_INT) == 1) {
|
||||
result = SET;
|
||||
}
|
||||
else {
|
||||
return RESET;
|
||||
}
|
||||
|
||||
return (IntStatus) result;
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* @brief LPC5410X Power ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __ROM_PWR_5410X_H_
|
||||
#define __ROM_PWR_5410X_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup PWRD_5410X CHIP: LPC5410X Power ROM API declarations and functions
|
||||
* @ingroup ROMAPI_5410X
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* 'mode' input values to set_voltage ROM function */
|
||||
typedef enum {
|
||||
POWER_LOW_POWER_MODE = 0,
|
||||
POWER_BALANCED_MODE,
|
||||
POWER_HIGH_PERFORMANCE
|
||||
} PERF_MODE_T;
|
||||
|
||||
/* 'mode' input values to power_mode_configure ROM function */
|
||||
typedef enum {
|
||||
POWER_SLEEP = 0,
|
||||
POWER_DEEP_SLEEP,
|
||||
POWER_POWER_DOWN,
|
||||
POWER_DEEP_POWER_DOWN
|
||||
} POWER_MODE_T;
|
||||
|
||||
/** @brief Power ROM indirect function structure
|
||||
* Do not use these functions as direct calls to ROM. Instead, use the
|
||||
* wrapper functions provided by the Power library (power_lib_5410x.h)
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t (*set_pll)(uint32_t multiply_by, uint32_t input_freq);
|
||||
uint32_t (*set_voltage)(uint32_t mode, uint32_t desired_freq);
|
||||
void (*power_mode_configure)(uint32_t mode, uint32_t peripheral_ctrl);
|
||||
} PWRD_API_T;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ROM_PWR_5410X_H_ */
|
||||
@@ -0,0 +1,139 @@
|
||||
/*
|
||||
* @brief LPC5410X ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __ROMAPI_5410X_H_
|
||||
#define __ROMAPI_5410X_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "iap.h"
|
||||
#include "error.h"
|
||||
#include "cmsis.h"
|
||||
|
||||
/* v1 ROM driver APIs */
|
||||
#include "rom_pwr_5410x.h"
|
||||
|
||||
/* v2 ROM driver APIs */
|
||||
#include "romapi_adc.h"
|
||||
#include "romapi_dma.h"
|
||||
#include "romapi_i2cm.h"
|
||||
#include "romapi_i2cmon.h"
|
||||
#include "romapi_i2cs.h"
|
||||
#include "romapi_spim.h"
|
||||
#include "romapi_spis.h"
|
||||
#include "romapi_uart.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup ROMAPI_5410X CHIP: LPC5410X ROM API declarations and functions
|
||||
* @ingroup CHIP_5410X_DRIVERS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief High level ROM API structure
|
||||
*/
|
||||
typedef struct {
|
||||
const uint32_t reserved_usb; /*!< Reserved */
|
||||
const uint32_t reserved_clib; /*!< Reserved */
|
||||
const uint32_t reserved_can; /*!< Reserved */
|
||||
const PWRD_API_T *pPWRD; /*!< Power API function table base address */
|
||||
const uint32_t reserved_div; /*!< Reserved */
|
||||
const uint32_t reserved_i2cd; /*!< Reserved */
|
||||
const uint32_t reserved_dmad; /*!< Reserved */
|
||||
const uint32_t reserved_spid; /*!< Reserved */
|
||||
const uint32_t reserved_adcd; /*!< Reserved */
|
||||
const uint32_t reserved_uartd; /*!< Reserved */
|
||||
const uint32_t reserved_vfifo; /*!< Reserved */
|
||||
const uint32_t reserved_usart; /*!< Reserved */
|
||||
/* v2 drivers - only present in some LPC5410x devices */
|
||||
const ROM_I2CMD_API_T *pI2CMD; /*!< v2 I2C master only driver API function table base address */
|
||||
const ROM_I2CSD_API_T *pI2CSD; /*!< v2 I2C slave only driver API function table base address */
|
||||
const ROM_I2CMOND_API_T *pI2CMOND; /*!< v2 I2C bus monitor driver API function table base address */
|
||||
const ROM_SPIMD_API_T *pSPIMD; /*!< v2 SPI master only driver API function table base address */
|
||||
const ROM_SPISD_API_T *pSPISD; /*!< v2 SPI slave only driver API function table base address */
|
||||
const ROM_DMAALTD_API_T *pDMAALT; /*!< v2 abstract DMA driver API function table base address */
|
||||
const ROM_ADC_API_T *pADCALT; /*!< v2 ADC driver API function table base address */
|
||||
const ROM_UART_API_T *pUARTALT; /*!< v2 UART driver API function table base address */
|
||||
} LPC_ROM_API_T;
|
||||
|
||||
/* Pointer to ROM API function address */
|
||||
#define LPC_ROM_API_BASE_LOC 0x03000200UL
|
||||
#define LPC_ROM_API (*(LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC)
|
||||
|
||||
/* Pointer to @ref PWRD_API_T functions in ROM */
|
||||
#define LPC_PWRD_API ((LPC_ROM_API)->pPWRD)
|
||||
|
||||
/* Pointer to v2 I2C master peripheral driver functions in ROM */
|
||||
#define ROMAPI_I2CM_API ((LPC_ROM_API)->pI2CMD)
|
||||
|
||||
/* Pointer to v2 I2C master peripheral driver functions in ROM */
|
||||
#define ROMAPI_I2CMON_API ((LPC_ROM_API)->pI2CMOND)
|
||||
|
||||
/* Pointer to v2 I2C slave peripheral driver functions in ROM */
|
||||
#define ROMAPI_I2CS_API ((LPC_ROM_API)->pI2CSD)
|
||||
|
||||
/* Pointer to v2 SPI master peripheral driver functions in ROM */
|
||||
#define ROMAPI_SPIM_API ((LPC_ROM_API)->pSPIMD)
|
||||
|
||||
/* Pointer to v2 SPI slave peripheral driver functions in ROM */
|
||||
#define ROMAPI_SPIS_API ((LPC_ROM_API)->pSPISD)
|
||||
|
||||
/* Pointer to v2 DMA controller driver functions in ROM */
|
||||
#define ROMAPI_DMAALT_API ((LPC_ROM_API)->pDMAALT)
|
||||
|
||||
/* Pointer to v2 ADC driver functions in ROM */
|
||||
#define ROMAPI_ADC_API ((LPC_ROM_API)->pADCALT)
|
||||
|
||||
/* Pointer to v2 UART controller driver functions in ROM */
|
||||
#define ROMAPI_UART_API ((LPC_ROM_API)->pUARTALT)
|
||||
|
||||
/* Pointer to ROM IAP entry functions */
|
||||
#define IAP_ENTRY_LOCATION 0x03000205
|
||||
|
||||
/**
|
||||
* @brief LPC5410x IAP_ENTRY API function type
|
||||
*/
|
||||
static INLINE void iap_entry(unsigned int cmd_param[5], unsigned int status_result[4])
|
||||
{
|
||||
((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ROMAPI_5410X_H_ */
|
||||
@@ -0,0 +1,160 @@
|
||||
/*
|
||||
* @brief ADC ROM API declarations and functions
|
||||
* These are the public ROM APIs and functions of the ADC ROM
|
||||
* driver.
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#include "romapi_5410x.h"
|
||||
|
||||
/* Get memory size in bytes needed for ADC driver context */
|
||||
uint32_t ROM_ADC_GetMemSize(void)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->GetMemSize();
|
||||
#else
|
||||
return adcrom_api.GetMemSize();
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Initialize the ADC ROM driver */
|
||||
ADC_HANDLE_T ROM_ADC_Init(void *pMem, uint32_t baseAddr, void *pUserData)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->Init(pMem, baseAddr, pUserData);
|
||||
#else
|
||||
return adcrom_api.Init(pMem, baseAddr, pUserData);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Configure the ADC peripheral */
|
||||
ErrorCode_t ROM_ADC_Configure(ADC_HANDLE_T hADC, const ADC_CFG_T *pCfg)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->Configure(hADC, pCfg);
|
||||
#else
|
||||
return adcrom_api.Configure(hADC, pCfg);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Calibrate the ADC */
|
||||
ErrorCode_t ROM_ADC_Calibrate(ADC_HANDLE_T hADC, uint32_t sysclk_freq)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->Calibrate(hADC, sysclk_freq);
|
||||
#else
|
||||
return adcrom_api.Calibrate(hADC, sysclk_freq);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Start the conversion on given SEQ */
|
||||
ErrorCode_t ROM_ADC_StartConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex, void *pBuf, size_t bufCount)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
/* Correct index adjust bug */
|
||||
uint32_t *ptr = &((uint32_t *)hADC)[9 + seqIndex * 6];
|
||||
if (*ptr != 2) *(ptr - 1) = 0;
|
||||
|
||||
return ROMAPI_ADC_API->StartConversion(hADC, seqIndex, pBuf, bufCount);
|
||||
#else
|
||||
return adcrom_api.StartConversion(hADC, seqIndex, pBuf, bufCount);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ADC Event handler */
|
||||
ErrorCode_t ROM_ADC_Handler(ADC_HANDLE_T hADC, ADC_HEVENT_T hEvent)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->Handler(hADC, hEvent);
|
||||
#else
|
||||
return adcrom_api.Handler(hADC, hEvent);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* ADC Callback register */
|
||||
ErrorCode_t ROM_ADC_RegisterCB(ADC_HANDLE_T hADC, ADC_CBINDEX_T cbIndex, void (*pCbFunc)(ADC_HANDLE_T,
|
||||
ADC_CBINDEX_T,
|
||||
void *))
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->RegisterCB(hADC, cbIndex, pCbFunc);
|
||||
#else
|
||||
return adcrom_api.RegisterCB(hADC, cbIndex, pCbFunc);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Set Threshold register values */
|
||||
void ROM_ADC_SetThreshold(ADC_HANDLE_T hADC, uint32_t valThr0, uint32_t valThr1)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
ROMAPI_ADC_API->SetThreshold(hADC, valThr0, valThr1);
|
||||
#else
|
||||
adcrom_api.SetThreshold(hADC, valThr0, valThr1);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Configure ADC channel */
|
||||
ErrorCode_t ROM_ADC_ConfigureCh(ADC_HANDLE_T hADC, uint32_t chanNum, uint32_t chanOpts)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->ConfigureCh(hADC, chanNum, chanOpts);
|
||||
#else
|
||||
return adcrom_api.ConfigureCh(hADC, chanNum, chanOpts);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Stop conversion of Analog samples */
|
||||
ErrorCode_t ROM_ADC_StopConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->StopConversion(hADC, seqIndex);
|
||||
#else
|
||||
return adcrom_api.StopConversion(hADC, seqIndex);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Generate a software trigger */
|
||||
ErrorCode_t ROM_ADC_SwTrigger(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->SwTrigger(hADC, seqIndex);
|
||||
#else
|
||||
return adcrom_api.SwTrigger(hADC, seqIndex);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Get Current verion of the driver */
|
||||
uint16_t ROM_ADC_GetDriverVersion(void)
|
||||
{
|
||||
#if defined(ROMDRIVERSV2_PRESENT)
|
||||
return ROMAPI_ADC_API->GetDriverVersion();
|
||||
#else
|
||||
return adcrom_api.GetDriverVersion();
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,184 @@
|
||||
/*
|
||||
* @brief ADC ROM API declarations and functions
|
||||
*
|
||||
* @note
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* LPC products. This software is supplied "AS IS" without any warranties of
|
||||
* any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
* all warranties, express or implied, including all implied warranties of
|
||||
* merchantability, fitness for a particular purpose and non-infringement of
|
||||
* intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
* or liability for the use of the software, conveys no license or rights under any
|
||||
* patent, copyright, mask work right, or any other intellectual property rights in
|
||||
* or to any products. NXP Semiconductors reserves the right to make changes
|
||||
* in the software without notification. NXP Semiconductors also makes no
|
||||
* representation or warranty that such application will be suitable for the
|
||||
* specified use without further testing or modification.
|
||||
*
|
||||
* @par
|
||||
* Permission to use, copy, modify, and distribute this software and its
|
||||
* documentation is hereby granted, under NXP Semiconductors' and its
|
||||
* licensor's relevant copyrights in the software, without fee, provided that it
|
||||
* is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
* copyright, permission, and disclaimer notice must appear in all copies of
|
||||
* this code.
|
||||
*/
|
||||
|
||||
#ifndef __ROMAPI_ADC_H_
|
||||
#define __ROMAPI_ADC_H_
|
||||
|
||||
#include "hw_adc_rom_api.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @defgroup ROMAPI_ADC_WRAPPER CHIP: ADC ROM Driver wrapper functions
|
||||
* @ingroup ROMAPI_5410X
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get memory size in bytes needed for ADC driver context
|
||||
* @return Size in bytes needed for the ROM driver
|
||||
*/
|
||||
uint32_t ROM_ADC_GetMemSize(void);
|
||||
|
||||
/**
|
||||
* @brief Initialize ADC ROM Driver
|
||||
* @param pMem : Pointer to memory area for driver context
|
||||
* @param baseAddr : Base address of the ADC peripheral
|
||||
* @param pUserData : Pointer to User Data
|
||||
* @return Pointer to the device context handle or NULL on alignment failure
|
||||
* @note Parameter @a pMem must be a pointer to word aligned memory
|
||||
* if the pointer is not word aligned (4-Byte) the function returns
|
||||
* NULL.
|
||||
*/
|
||||
ADC_HANDLE_T ROM_ADC_Init(void *pMem, uint32_t baseAddr, void *pUserData);
|
||||
|
||||
/**
|
||||
* @brief Configure the ADC peripheral
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param pCfg : Pointer to configuration structure #ADC_CFG_T
|
||||
* @return Always returns LPC_OK
|
||||
*/
|
||||
ErrorCode_t ROM_ADC_Configure(ADC_HANDLE_T hADC, const ADC_CFG_T *pCfg);
|
||||
|
||||
/**
|
||||
* @brief Calibrate ADC upon startup or wakeup after powerdown
|
||||
* @pre ADC must be Initialized and Configured
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param sysclk_freq : Frequency of the system
|
||||
* @return Result of calibrarion operation
|
||||
* @retval LPC_OK Calibration is successful
|
||||
* @retval ERR_ADC_NO_POWER Unable to powerup ADC
|
||||
* @retval ERR_TIME_OUT Calibration operation timed-out
|
||||
*/
|
||||
ErrorCode_t ROM_ADC_Calibrate(ADC_HANDLE_T hADC, uint32_t sysclk_freq);
|
||||
|
||||
/**
|
||||
* @brief Start the ADC peripheral
|
||||
* @pre ADC must be properly initialized, Configured and Calibrated
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param seqIndex : Index of the sequence to start must be one of #ADC_SEQ_A or #ADC_SEQ_B
|
||||
* @param pBuf : Pointer to buffer (see note below)
|
||||
* @param szBuf : Size of buffer (see note below)
|
||||
* @return Result of the start operation
|
||||
* @retval LPC_OK Successfully started ADC sampling on given sequence or
|
||||
* given buffer is queued successfully (when called from #ADC_BUFFER_DONE
|
||||
* callback handler)
|
||||
* @retval ERR_ADC_INVALID_SEQUENCE Parameter @a seqIndex is not one of #ADC_SEQ_A or #ADC_SEQ_B
|
||||
* @retval ERR_BUSY Already a buffer is active and swap buffer is also configured
|
||||
* @note The size of the buffer must be M x N where M is the number of channels enabled in
|
||||
* sequence @a seqIndex, and N is the number of samples to be converted.
|
||||
* The buffer provided by @a pBuf must be of size M x N x sizeof(uint16_t) bytes(for non-DMA).
|
||||
* Assume that channels 1, 3, 4, 8 are enabled in sequence @a seqIndex and number of
|
||||
* samples to be collected is N, the buffer will be filled with DATA_1[0], DATA_3[0],
|
||||
* DATA_4[0], DATA_8[0], ... , DATA_1[N], DATA_3[N], DATA_4[N], DATA_8[N], note
|
||||
* that the order in which the channels are enabled does not matter they will always be
|
||||
* filled up in ascending order.
|
||||
*/
|
||||
ErrorCode_t ROM_ADC_StartConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex, void *pBuf, size_t szBuf);
|
||||
|
||||
/**
|
||||
* @brief Handler to handle ADC events
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param hEvent : Type of the event
|
||||
* @return Event handling results
|
||||
* @retval LPC_OK Event successfully handled
|
||||
* @retval ERR_ADC_INVALID_SEQUENCE Event is not for the given sequence
|
||||
* @retval ERR_FAILED Internal ADC error (Channel enabled but no data available)
|
||||
* @retval ERR_ADC_PARAM Invaild event parameter for @a hEvent
|
||||
*/
|
||||
ErrorCode_t ROM_ADC_Handler(ADC_HANDLE_T hADC, ADC_HEVENT_T hEvent);
|
||||
|
||||
/**
|
||||
* @brief Registers a callback function associated with an event
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param cbIndex : Index of the call-back function (Associated with an event)
|
||||
* @param pCbFunc : Pointer to callback function
|
||||
* @return Success or failure
|
||||
* @retval LPC_OK Callback successfully registered
|
||||
* @retval ERR_ADC_PARAM Invaild event parameter for @a cbIndex
|
||||
*/
|
||||
ErrorCode_t ROM_ADC_RegisterCB(ADC_HANDLE_T hADC, ADC_CBINDEX_T cbIndex, void (*pCbFunc)(ADC_HANDLE_T,
|
||||
ADC_CBINDEX_T,
|
||||
void *));
|
||||
|
||||
/**
|
||||
* @brief Setup high and low threshold values for threshold 0, 1
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param valThr0 : Threshold 0 value (bits 31-16 has high value, bits 15-0 has low value)
|
||||
* @param valThr1 : Threshold 1 value (bits 31-16 has high value, bits 15-0 has low value)
|
||||
* @return Nothing
|
||||
*/
|
||||
void ROM_ADC_SetThreshold(ADC_HANDLE_T hADC, uint32_t valThr0, uint32_t valThr1);
|
||||
|
||||
/**
|
||||
* @brief Configure a single channel
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param chanNum : Channel number
|
||||
* @param chanOpts : Options for the channel
|
||||
* @return LPC_OK on success, ERR_ADC_PARAM if @a chanNum is invalid
|
||||
*/
|
||||
ErrorCode_t ROM_ADC_ConfigureCh(ADC_HANDLE_T hADC, uint32_t chanNum, uint32_t chanOpts);
|
||||
|
||||
/**
|
||||
* @brief Stop the conversion in progress
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param seqIndex : Sequence that needs to be stopped
|
||||
* @return LPC_OK on success, ERR_ADC_INVALID_SEQUENCE if @a seqIndex is invalid
|
||||
*/
|
||||
ErrorCode_t ROM_ADC_StopConversion(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex);
|
||||
|
||||
/**
|
||||
* @brief Generate software trigger for given sequence
|
||||
* @param hADC : Handle to ADC obtained using ROM_ADC_Init()
|
||||
* @param seqIndex : Sequence that needs to be triggered
|
||||
* @return LPC_OK on success, ERR_ADC_INVALID_SEQUENCE if @a seqIndex is invalid
|
||||
*/
|
||||
ErrorCode_t ROM_ADC_SwTrigger(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex);
|
||||
|
||||
/**
|
||||
* @brief Return the ADC ROM driver version
|
||||
* @return Driver version number
|
||||
* @note The returned driver version number consists of a major and minor
|
||||
* number, with the minor number in the lower 8 bits and the major number in
|
||||
* the upper 8 bits.
|
||||
*/
|
||||
uint16_t ROM_ADC_GetDriverVersion(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ROMAPI_ADC_H_ */
|
||||
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