add bsp lpc54102

bsp/lpc5410x/Libraries/CMSIS/Include/arm_common_tables.h

@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/lpc5410x/Libraries/Device/SConscript

@@ -0,0 +1,22 @@
+# RT-Thread building script for component
+
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Split('''
+startup/sysinit.c
+''')
+CPPPATH = [cwd + '/../CMSIS/Include']
+CPPDEFINES = ['CORE_M4']
+
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += ['startup/gcc_startup_lpc5410x.c'] 
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += ['startup/keil_startup_lpc5410x.s']
+	
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/lpc5410x/Libraries/Device/startup/cr_startup_lpc5410x-m0.c

@@ -0,0 +1,452 @@
+//*****************************************************************************
+// LPC5410x M0 Microcontroller Startup code for use with LPCXpresso IDE
+//
+// Version : 141022
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2014
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products.  This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights.  NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers.  This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+    extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+// Declaration of external SystemInit function
+extern void SystemInit(void);
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+void ResetISR(void);
+#if defined (__MULTICORE_MASTER)
+void ResetISR2(void);
+#endif
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+//WEAK void MemManage_Handler(void);
+//WEAK void BusFault_Handler(void);
+//WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+//WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+// External Interrupts - Available on M0/M4
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UTICK_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MAILBOX_IRQHandler(void) ALIAS(IntDefaultHandler);
+// External Interrupts - For M4 only
+//void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void SPI2_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void SPI3_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void Reserved41_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void Reserved42_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void Reserved43_IRQHandler(void) ALIAS(IntDefaultHandler);
+//void Reserved44_IRQHandler(void) ALIAS(IntDefaultHandler);
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    // Core Level -  CM0plus
+        &_vStackTop, // The initial stack pointer
+        ResetISR,                               // The reset handler
+        NMI_Handler,                            // The NMI handler
+        HardFault_Handler,                      // The hard fault handler
+        0,                                      // Reserved
+        0,                                      // Reserved
+        0,                                      // Reserved
+        0,                                      // Reserved
+        0,                                      // Reserved
+        0,                                      // Reserved
+        0,                                      // Reserved
+        SVC_Handler,                            // SVCall handler
+        0,                                      // Reserved
+        0,                                      // Reserved
+        PendSV_Handler,                         // The PendSV handler
+        SysTick_Handler,                        // The SysTick handler
+
+        // External Interrupts - Available on M0/M4
+        WDT_IRQHandler,         // Watchdog
+        BOD_IRQHandler,         // Brown Out Detect
+        Reserved_IRQHandler,    // Reserved
+        DMA_IRQHandler,         // DMA Controller
+        GINT0_IRQHandler,       // GPIO Group0 Interrupt
+        PIN_INT0_IRQHandler,    // PIO INT0
+        PIN_INT1_IRQHandler,    // PIO INT1
+        PIN_INT2_IRQHandler,    // PIO INT2
+        PIN_INT3_IRQHandler,    // PIO INT3
+        UTICK_IRQHandler,       // UTICK timer
+        MRT_IRQHandler,         // Multi-Rate Timer
+        CT32B0_IRQHandler,      // Counter Timer 0
+        CT32B1_IRQHandler,      // Counter Timer 1
+        CT32B2_IRQHandler,      // Counter Timer 2
+        CT32B3_IRQHandler,      // Counter Timer 3
+        CT32B4_IRQHandler,      // Counter Timer 4
+        SCT0_IRQHandler,        // Smart Counter Timer
+        UART0_IRQHandler,       // UART0
+        UART1_IRQHandler,       // UART1
+        UART2_IRQHandler,       // UART2
+        UART3_IRQHandler,       // UART3
+        I2C0_IRQHandler,        // I2C0 controller
+        I2C1_IRQHandler,        // I2C1 controller
+        I2C2_IRQHandler,        // I2C2 controller
+        SPI0_IRQHandler,        // SPI0 controller
+        SPI1_IRQHandler,        // SPI1 controller
+        ADC_SEQA_IRQHandler,    // ADC SEQA
+        ADC_SEQB_IRQHandler,    // ADC SEQB
+        ADC_THCMP_IRQHandler,   // ADC THCMP and OVERRUN ORed
+        RTC_IRQHandler,         // RTC Timer
+        Reserved_IRQHandler,    // Reserved
+        MAILBOX_IRQHandler,     // Mailbox
+
+        // External Interrupts - For M4 only
+//        GINT1_IRQHandler,       // GPIO Group1 Interrupt
+//        PIN_INT4_IRQHandler,    // PIO INT4
+//        PIN_INT5_IRQHandler,    // PIO INT5
+//        PIN_INT6_IRQHandler,    // PIO INT6
+//        PIN_INT7_IRQHandler,    // PIO INT7
+//        SPI2_IRQHandler,        // SPI2 controller
+//        SPI3_IRQHandler,        // SPI3 controller
+//        0,                      // Reserved
+//        RIT_IRQHandler,         // RIT Timer
+//        Reserved41_IRQHandler,  // Reserved
+//        Reserved42_IRQHandler,  // Reserved
+//        Reserved43_IRQHandler,  // Reserved
+//        Reserved44_IRQHandler,  // Reserved
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+
+#if defined (__MULTICORE_MASTER)
+//#define  cpu_ctrl 0x40000300
+//#define coproc_boot	0x40000304
+//#define set coproc_stack	0x40000308
+__attribute__ ((naked, section(".after_vectors.reset")))
+void ResetISR(void) {
+    asm volatile(
+        ".syntax unified\t\n"
+        ".set   cpu_ctrl,       0x40000300\t\n"
+        ".set   coproc_boot,    0x40000304\t\n"
+        ".set   coproc_stack,   0x40000308\t\n"
+        "MOVS   R5, #1\t\n"
+        "LDR    R0, =0xE000ED00\t\n"
+        "LDR    R1, [R0]\t\n"           // READ CPUID register
+        "LDR    R2,=0x410CC601\t\n"     // CM0 R0p1 identifier
+        "EORS   R1,R1,R2\t\n"           // XOR to see if we are C0
+        "LDR    R3, =cpu_ctrl\t\n"      // get address of CPU_CTRL
+        "LDR    R1,[R3]\t\n"            // read cpu_ctrl reg into R1
+        "BEQ.N  cm0_boot\t\n"
+    "cm4_boot:\t\n"
+        "LDR    R0,=coproc_boot\t\n"    // coproc boot address
+        "LDR    R0,[R0]\t\n"            // get address to branch to
+        "MOVS   R0,R0\t\n"              // Check if 0
+        "BEQ.N  check_master_m4\t\n"    // if zero in boot reg, we just branch to  real reset
+        "BX     R0\t\n"                 // otherwise, we branch to boot address
+    "commonboot:\t\n"
+        "LDR    R0, =ResetISR2\t\n"     // Jump to 'real' reset handler
+        "BX     R0\t\n"
+    "cm0_boot:\t\n"
+        "LDR    R0,=coproc_boot\t\n"    // coproc boot address
+        "LDR    R0,[R0]\t\n"            // get address to branch to
+        "MOVS   R0,R0\t\n"              // Check if 0
+        "BEQ.N  check_master_m0\t\n"    // if zero in boot reg, we just branch to  real reset
+        "LDR    R1,=coproc_stack\t\n"   // pickup coprocesor stackpointer (from syscon CPSTACK)
+        "LDR    R1,[R1]\t\n"
+        "MOV    SP,R1\t\n"
+        "BX     R0\t\n"                 // goto boot address
+    "check_master_m0:\t\n"
+        "ANDS   R1,R1,R5\t\n"           // bit test bit0
+        "BEQ.N  commonboot\t\n"         // if we get 0, that means we are masters
+        "B.N    goto_sleep_pending_reset\t\n"   // Otherwise, there is no startup vector for slave, so we go to sleep
+    "check_master_m4:\t\n"
+        "ANDS   R1,R1,R5\t\n"           // bit test bit0
+        "BNE.N  commonboot\t\n"         // if we get 1, that means we are masters
+    "goto_sleep_pending_reset:\t\n"
+        "MOV     SP,R5\t\n"             // load 0x1 into SP so that any stacking (eg on NMI) will not cause us to wakeup
+            // and write to uninitialised Stack area (instead it will LOCK us up before we cause damage)
+            // this code should only be reached if debugger bypassed ROM or we changed master without giving
+            // correct start address, the only way out of this is through a debugger change of SP and PC
+    "sleepo:\t\n"
+        "WFI\t\n"                       // go to sleep
+        "B.N    sleepo\t\n"
+        ".syntax divided\t\n"
+    );
+}
+
+
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR2(void) {
+
+#else
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR(void) {
+#endif
+
+    // If this is not the CM0+ core...
+#if !defined (CORE_M0PLUS)
+    // If this is not a slave project...
+#if !defined (__MULTICORE_M0SLAVE) && \
+    !defined (__MULTICORE_M4SLAVE)
+    // Optionally enable RAM banks that may be off by default at reset
+#if !defined (DONT_ENABLE_DISABLED_RAMBANKS)
+    volatile unsigned int *SYSCON_SYSAHBCLKCTRL0 = (unsigned int *) 0x400000c0;
+    // Ensure that SRAM2(4) bit in SYSAHBCLKCTRL0 are set
+    *SYSCON_SYSAHBCLKCTRL0 |= (1 << 4);
+#endif
+#endif
+#endif
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if !defined (__USE_LPCOPEN)
+// LPCOpen init code deals with VTOR initialisation
+    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+    if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
+        // CMSIS : SCB->VTOR = <address of vector table>
+        *pSCB_VTOR = (unsigned int) g_pfnVectors;
+    }
+#endif
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+    SystemInit();
+#endif
+
+#if defined (__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+    while (1) {
+        ;
+    }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void)
+{ while(1) {}
+}
+
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void)
+{ while(1) {}
+}

bsp/lpc5410x/Libraries/Device/startup/cr_startup_lpc5410x.c

@@ -0,0 +1,482 @@
+//*****************************************************************************
+// LPC5410x Microcontroller Startup code for use with LPCXpresso IDE
+//
+// Version : 141022
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2014
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products.  This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights.  NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers.  This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+    extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+// Declaration of external SystemInit function
+extern void SystemInit(void);
+#endif
+
+//*****************************************************************************
+//
+// Forward declaration of the default handlers. These are aliased.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions
+//
+//*****************************************************************************
+void ResetISR(void);
+#if defined (__MULTICORE_MASTER)
+void ResetISR2(void);
+#endif
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+//
+// Forward declaration of the specific IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//
+//*****************************************************************************
+// External Interrupts - Available on M0/M4
+void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved_IRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UTICK_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void CT32B4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
+void MAILBOX_IRQHandler(void) ALIAS(IntDefaultHandler);
+// External Interrupts - For M4 only
+void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI2_IRQHandler(void) ALIAS(IntDefaultHandler);
+void SPI3_IRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved41_IRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved42_IRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved43_IRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved44_IRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+//
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+//*****************************************************************************
+//
+// External declaration for the pointer to the stack top from the Linker Script
+//
+//*****************************************************************************
+extern void _vStackTop(void);
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+//
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    // Core Level - CM3
+        &_vStackTop,            // The initial stack pointer
+        ResetISR,               // The reset handler
+        NMI_Handler,            // The NMI handler
+        HardFault_Handler,      // The hard fault handler
+        MemManage_Handler,      // The MPU fault handler
+        BusFault_Handler,       // The bus fault handler
+        UsageFault_Handler,     // The usage fault handler
+        0,                      // Reserved
+        0,                      // Reserved
+        0,                      // Reserved
+        0,                      // Reserved
+        SVC_Handler,            // SVCall handler
+        DebugMon_Handler,       // Debug monitor handler
+        0,                      // Reserved
+        PendSV_Handler,         // The PendSV handler
+        SysTick_Handler,        // The SysTick handler
+
+        // External Interrupts - Available on M0/M4
+        WDT_IRQHandler,         // Watchdog
+        BOD_IRQHandler,         // Brown Out Detect
+        Reserved_IRQHandler,    // Reserved
+        DMA_IRQHandler,         // DMA Controller
+        GINT0_IRQHandler,       // GPIO Group0 Interrupt
+        PIN_INT0_IRQHandler,    // PIO INT0
+        PIN_INT1_IRQHandler,    // PIO INT1
+        PIN_INT2_IRQHandler,    // PIO INT2
+        PIN_INT3_IRQHandler,    // PIO INT3
+        UTICK_IRQHandler,       // UTICK timer
+        MRT_IRQHandler,         // Multi-Rate Timer
+        CT32B0_IRQHandler,      // Counter Timer 0
+        CT32B1_IRQHandler,      // Counter Timer 1
+        CT32B2_IRQHandler,      // Counter Timer 2
+        CT32B3_IRQHandler,      // Counter Timer 3
+        CT32B4_IRQHandler,      // Counter Timer 4
+        SCT0_IRQHandler,        // Smart Counter Timer
+        UART0_IRQHandler,       // UART0
+        UART1_IRQHandler,       // UART1
+        UART2_IRQHandler,       // UART2
+        UART3_IRQHandler,       // UART3
+        I2C0_IRQHandler,        // I2C0 controller
+        I2C1_IRQHandler,        // I2C1 controller
+        I2C2_IRQHandler,        // I2C2 controller
+        SPI0_IRQHandler,        // SPI0 controller
+        SPI1_IRQHandler,        // SPI1 controller
+        ADC_SEQA_IRQHandler,    // ADC SEQA
+        ADC_SEQB_IRQHandler,    // ADC SEQB
+        ADC_THCMP_IRQHandler,   // ADC THCMP and OVERRUN ORed
+        RTC_IRQHandler,         // RTC Timer
+        Reserved_IRQHandler,    // Reserved
+        MAILBOX_IRQHandler,     // Mailbox
+
+        // External Interrupts - For M4 only
+        GINT1_IRQHandler,       // GPIO Group1 Interrupt
+        PIN_INT4_IRQHandler,    // PIO INT4
+        PIN_INT5_IRQHandler,    // PIO INT5
+        PIN_INT6_IRQHandler,    // PIO INT6
+        PIN_INT7_IRQHandler,    // PIO INT7
+        SPI2_IRQHandler,        // SPI2 controller
+        SPI3_IRQHandler,        // SPI3 controller
+        0,                      // Reserved
+        RIT_IRQHandler,         // RIT Timer
+        Reserved41_IRQHandler,  // Reserved
+        Reserved42_IRQHandler,  // Reserved
+        Reserved43_IRQHandler,  // Reserved
+        Reserved44_IRQHandler,  // Reserved
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors")))
+void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+
+#if defined (__MULTICORE_MASTER)
+//#define  cpu_ctrl 0x40000300
+//#define coproc_boot	0x40000304
+//#define set coproc_stack	0x40000308
+__attribute__ ((naked, section(".after_vectors.reset")))
+void ResetISR(void) {
+    asm volatile(
+        ".set   cpu_ctrl,       0x40000300\t\n"
+        ".set   coproc_boot,    0x40000304\t\n"
+        ".set   coproc_stack,   0x40000308\t\n"
+        "MOVS   R5, #1\t\n"
+        "LDR    R0, =0xE000ED00\t\n"
+        "LDR    R1, [R0]\t\n"           // READ CPUID register
+        "LDR    R2,=0x410CC601\t\n"     // CM0 R0p1 identifier
+        "EORS   R1,R1,R2\t\n"           // XOR to see if we are C0
+        "LDR    R3, =cpu_ctrl\t\n"      // get address of CPU_CTRL
+        "LDR    R1,[R3]\t\n"            // read cpu_ctrl reg into R1
+        "BEQ.N  cm0_boot\t\n"
+    "cm4_boot:\t\n"
+        "LDR    R0,=coproc_boot\t\n"    // coproc boot address
+        "LDR    R0,[R0]\t\n"            // get address to branch to
+        "MOVS   R0,R0\t\n"              // Check if 0
+        "BEQ.N  check_master_m4\t\n"    // if zero in boot reg, we just branch to  real reset
+        "BX     R0\t\n"                 // otherwise, we branch to boot address
+    "commonboot:\t\n"
+        "LDR    R0, =ResetISR2\t\n"     // Jump to 'real' reset handler
+        "BX     R0\t\n"
+    "cm0_boot:\t\n"
+        "LDR    R0,=coproc_boot\t\n"    // coproc boot address
+        "LDR    R0,[R0]\t\n"            // get address to branch to
+        "MOVS   R0,R0\t\n"              // Check if 0
+        "BEQ.N  check_master_m0\t\n"    // if zero in boot reg, we just branch to  real reset
+        "LDR    R1,=coproc_stack\t\n"   // pickup coprocesor stackpointer (from syscon CPSTACK)
+        "LDR    R1,[R1]\t\n"
+        "MOV    SP,R1\t\n"
+        "BX     R0\t\n"                 // goto boot address
+    "check_master_m0:\t\n"
+        "ANDS   R1,R1,R5\t\n"           // bit test bit0
+        "BEQ.N  commonboot\t\n"         // if we get 0, that means we are masters
+        "B.N    goto_sleep_pending_reset\t\n"   // Otherwise, there is no startup vector for slave, so we go to sleep
+    "check_master_m4:\t\n"
+        "ANDS   R1,R1,R5\t\n"           // bit test bit0
+        "BNE.N  commonboot\t\n"         // if we get 1, that means we are masters
+    "goto_sleep_pending_reset:\t\n"
+        "MOV     SP,R5\t\n"             // load 0x1 into SP so that any stacking (eg on NMI) will not cause us to wakeup
+            // and write to uninitialised Stack area (instead it will LOCK us up before we cause damage)
+            // this code should only be reached if debugger bypassed ROM or we changed master without giving
+            // correct start address, the only way out of this is through a debugger change of SP and PC
+    "sleepo:\t\n"
+        "WFI\t\n"                       // go to sleep
+        "B.N    sleepo\t\n"
+    );
+}
+
+
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR2(void) {
+
+#else
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR(void) {
+#endif
+
+    // If this is not the CM0+ core...
+#if !defined (CORE_M0PLUS)
+    // If this is not a slave project...
+#if !defined (__MULTICORE_M0SLAVE) && \
+    !defined (__MULTICORE_M4SLAVE)
+    // Optionally enable RAM banks that may be off by default at reset
+#if !defined (DONT_ENABLE_DISABLED_RAMBANKS)
+    volatile unsigned int *SYSCON_SYSAHBCLKCTRL0 = (unsigned int *) 0x400000c0;
+    // Ensure that SRAM2(4) bit in SYSAHBCLKCTRL0 are set
+    *SYSCON_SYSAHBCLKCTRL0 |= (1 << 4);
+#endif
+#endif
+#endif
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if !defined (__USE_LPCOPEN)
+// LPCOpen init code deals with FP and VTOR initialisation
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+    /*
+     * Code to enable the Cortex-M4 FPU only included
+     * if appropriate build options have been selected.
+     * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+     */
+    // CPACR is located at address 0xE000ED88
+    asm("LDR.W R0, =0xE000ED88");
+    // Read CPACR
+    asm("LDR R1, [R0]");
+    // Set bits 20-23 to enable CP10 and CP11 coprocessors
+    asm(" ORR R1, R1, #(0xF << 20)");
+    // Write back the modified value to the CPACR
+    asm("STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+    // ******************************
+    // Check to see if we are running the code from a non-zero
+    // address (eg RAM, external flash), in which case we need
+    // to modify the VTOR register to tell the CPU that the
+    // vector table is located at a non-0x0 address.
+
+    // Note that we do not use the CMSIS register access mechanism,
+    // as there is no guarantee that the project has been configured
+    // to use CMSIS.
+    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+    if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
+        // CMSIS : SCB->VTOR = <address of vector table>
+        *pSCB_VTOR = (unsigned int) g_pfnVectors;
+    }
+#endif
+#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
+    SystemInit();
+#endif
+
+#if defined (__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif
+
+#if defined (__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+    while (1) {
+        ;
+    }
+}
+
+//*****************************************************************************
+// Default exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void NMI_Handler(void) {
+    while (1) {
+    }
+}
+
+__attribute__ ((section(".after_vectors")))
+void HardFault_Handler(void) {
+    while (1) {
+    }
+}
+
+__attribute__ ((section(".after_vectors")))
+void SVC_Handler(void) {
+    while (1) {
+    }
+}
+
+__attribute__ ((section(".after_vectors")))
+void PendSV_Handler(void) {
+    while (1) {
+    }
+}
+
+__attribute__ ((section(".after_vectors")))
+void SysTick_Handler(void) {
+    while (1) {
+    }
+}
+
+//*****************************************************************************
+//
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//
+//*****************************************************************************
+__attribute__ ((section(".after_vectors")))
+void IntDefaultHandler(void) {
+    while (1) {
+    }
+}
+

bsp/lpc5410x/Libraries/Device/startup/crp.c

@@ -0,0 +1,38 @@
+//*****************************************************************************
+// crp.c
+//
+// Source file to create CRP word expected by LPCXpresso IDE linker
+//*****************************************************************************
+//
+// Copyright(C) NXP Semiconductors, 2013
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// LPC products.  This software is supplied "AS IS" without any warranties of
+// any kind, and NXP Semiconductors and its licensor disclaim any and
+// all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights.  NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under any
+// patent, copyright, mask work right, or any other intellectual property rights in
+// or to any products. NXP Semiconductors reserves the right to make changes
+// in the software without notification. NXP Semiconductors also makes no
+// representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers.  This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+//*****************************************************************************
+
+#if defined (__CODE_RED)
+#include <NXP/crp.h>
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+#endif

bsp/lpc5410x/Libraries/Device/startup/gcc_startup_lpc5410x.c

@@ -0,0 +1,272 @@
+//*****************************************************************************
+//
+// Startup code for use with GNU tools.
+//
+//*****************************************************************************
+
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+static void Reset_Handler(void);
+static void Default_Handler(void);
+
+//*****************************************************************************
+//
+// External declaration for the interrupt handler used by the application.
+//
+//*****************************************************************************
+void NMI_Handler(void)          __attribute__((weak, alias("Default_Handler")));
+void HardFault_Handler(void)    __attribute__((weak, alias("Default_Handler")));
+void MemManage_Handler(void)    __attribute__((weak, alias("Default_Handler")));
+void BusFault_Handler(void)     __attribute__((weak, alias("Default_Handler")));
+void UsageFault_Handler(void)   __attribute__((weak, alias("Default_Handler")));
+void SVC_Handler(void)          __attribute__((weak, alias("Default_Handler")));
+void DebugMon_Handler(void)     __attribute__((weak, alias("Default_Handler")));
+void PendSV_Handler(void)       __attribute__((weak, alias("Default_Handler")));
+void SysTick_Handler(void)      __attribute__((weak, alias("Default_Handler")));
+
+void WDT_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void BOD_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void Reserved_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void DMA_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void GINT0_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+
+void PIN_INT0_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void PIN_INT1_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void PIN_INT2_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void PIN_INT3_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void UTICK_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void MRT_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void CT32B0_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void CT32B1_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void CT32B2_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void CT32B3_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void CT32B4_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void SCT0_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void UART0_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void UART1_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void UART2_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void UART3_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void I2C0_IRQHandler(void)     __attribute__((weak, alias("Default_Handler")));
+void I2C1_IRQHandler(void)     __attribute__((weak, alias("Default_Handler")));
+void I2C2_IRQHandler(void)     __attribute__((weak, alias("Default_Handler")));
+void SPI0_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void SPI1_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void ADC_SEQA_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void ADC_SEQB_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void ADC_THCMP_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+void RTC_IRQHandler(void)      __attribute__((weak, alias("Default_Handler")));
+//void Reserved_IRQHandler(void)    __attribute__((weak, alias("Default_Handler")));
+void MAILBOX_IRQHandler(void)   __attribute__((weak, alias("Default_Handler")));
+void GINT1_IRQHandler(void)       __attribute__((weak, alias("Default_Handler")));
+void PIN_INT4_IRQHandler(void)          __attribute__((weak, alias("Default_Handler")));
+void PIN_INT5_IRQHandler(void)   __attribute__((weak, alias("Default_Handler")));
+void PIN_INT6_IRQHandler(void)        __attribute__((weak, alias("Default_Handler")));
+void PIN_INT7_IRQHandler(void)            __attribute__((weak, alias("Default_Handler")));
+//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
+//void Reserved_IRQHandler(void)          __attribute__((weak, alias("Default_Handler")));
+//void Reserved_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
+void RIT_IRQHandler(void)          __attribute__((weak, alias("Default_Handler")));
+void Reserved41_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
+void Reserved42_IRQHandler(void)          __attribute__((weak, alias("Default_Handler")));
+void Reserved43_IRQHandler(void) __attribute__((weak, alias("Default_Handler")));
+void Reserved44_IRQHandler(void)          __attribute__((weak, alias("Default_Handler")));
+//*****************************************************************************
+//
+// The entry point for the application.
+//
+//*****************************************************************************
+extern int main(void);
+
+//*****************************************************************************
+//
+// Reserve space for the system stack.
+//
+//*****************************************************************************
+static unsigned long pulStack[512];
+
+//*****************************************************************************
+//
+// The vector table.  Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+//*****************************************************************************
+__attribute__ ((section(".isr_vector")))
+void (* const g_pfnVectors[])(void) =
+{
+    (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
+    // The initial stack pointer
+    Reset_Handler,              // Reset Handler
+    NMI_Handler,                // NMI Handler
+    HardFault_Handler,          // Hard Fault Handler
+    MemManage_Handler,          // MPU Fault Handler
+    BusFault_Handler,           // Bus Fault Handler
+    UsageFault_Handler,         // Usage Fault Handler
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    SVC_Handler,                // SVCall Handler
+    DebugMon_Handler,           // Debug Monitor Handler
+    0,                          // Reserved
+    PendSV_Handler,             // PendSV Handler
+    SysTick_Handler,            // SysTick Handler
+
+    // External Interrupts
+    WDT_IRQHandler,        
+    BOD_IRQHandler, 
+	Reserved_IRQHandler,	
+    DMA_IRQHandler,        
+    GINT0_IRQHandler,      
+    PIN_INT0_IRQHandler,   
+    PIN_INT1_IRQHandler,   
+    PIN_INT2_IRQHandler,   
+    PIN_INT3_IRQHandler,   
+    UTICK_IRQHandler,      
+    MRT_IRQHandler,        
+    CT32B0_IRQHandler,     
+    CT32B1_IRQHandler,     
+    CT32B2_IRQHandler,     
+    CT32B3_IRQHandler,     
+    CT32B4_IRQHandler,     
+    SCT0_IRQHandler,       
+    UART0_IRQHandler,      
+    UART1_IRQHandler,      
+    UART2_IRQHandler,      
+    UART3_IRQHandler,      
+    I2C0_IRQHandler,      
+    I2C1_IRQHandler,       
+    I2C2_IRQHandler,       
+    SPI0_IRQHandler,       
+    SPI1_IRQHandler,       
+    ADC_SEQA_IRQHandler,   
+    ADC_SEQB_IRQHandler,   
+    ADC_THCMP_IRQHandler,  
+    RTC_IRQHandler,    
+	Reserved_IRQHandler,    
+    MAILBOX_IRQHandler,   
+    GINT1_IRQHandler,      
+    PIN_INT4_IRQHandler,   
+    PIN_INT5_IRQHandler,   
+    PIN_INT6_IRQHandler,   
+    PIN_INT7_IRQHandler, 
+	Reserved_IRQHandler,
+	Reserved_IRQHandler,
+	Reserved_IRQHandler,
+	RIT_IRQHandler,       
+	Reserved41_IRQHandler,	
+	Reserved42_IRQHandler,
+	Reserved43_IRQHandler,
+	Reserved44_IRQHandler,	    
+};
+//**RIT_IRQHandler        ***************************************************************************
+//  Reserved41_IRQHandler 
+// TReserved42_IRQHandler he following are constructs created by the linker, indicating where the
+// tReserved43_IRQHandler he "data" and "bss" segments reside in memory.  The initializers for the
+// fReserved44_IRQHandler or the "data" segment resides immediately following the "text" segment.
+//
+//*****************************************************************************
+extern unsigned long _etext;
+extern unsigned long _data;
+extern unsigned long _edata;
+extern unsigned long _bss;
+extern unsigned long _ebss;
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event.  Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called.  Any fancy
+// actions (such as making decisions based on the reset cause register, and
+// resetting the bits in that register) are left solely in the hands of the
+// application.
+//
+//*****************************************************************************
+static void Reset_Handler(void)
+{
+    unsigned long *pulSrc, *pulDest;
+
+    //
+    // Copy the data segment initializers from flash to SRAM.
+    //
+    pulSrc = &_etext;
+    for(pulDest = &_data; pulDest < &_edata; )
+    {
+        *pulDest++ = *pulSrc++;
+    }
+	
+	
+#if !defined (__USE_LPCOPEN)
+// LPCOpen init code deals with FP and VTOR initialisation
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+    /*
+     * Code to enable the Cortex-M4 FPU only included
+     * if appropriate build options have been selected.
+     * Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+     */
+    // CPACR is located at address 0xE000ED88
+    asm("LDR.W R0, =0xE000ED88");
+    // Read CPACR
+    asm("LDR R1, [R0]");
+    // Set bits 20-23 to enable CP10 and CP11 coprocessors
+    asm(" ORR R1, R1, #(0xF << 20)");
+    // Write back the modified value to the CPACR
+    asm("STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+    // ******************************
+    // Check to see if we are running the code from a non-zero
+    // address (eg RAM, external flash), in which case we need
+    // to modify the VTOR register to tell the CPU that the
+    // vector table is located at a non-0x0 address.
+
+    // Note that we do not use the CMSIS register access mechanism,
+    // as there is no guarantee that the project has been configured
+    // to use CMSIS.
+    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+    if ((unsigned int *) g_pfnVectors != (unsigned int *) 0x00000000) {
+        // CMSIS : SCB->VTOR = <address of vector table>
+        *pSCB_VTOR = (unsigned int) g_pfnVectors;
+    }
+#endif
+	
+    //
+    // Zero fill the bss segment.
+    //
+    __asm("    ldr     r0, =_bss\n"
+          "    ldr     r1, =_ebss\n"
+          "    mov     r2, #0\n"
+          "    .thumb_func\n"
+          "zero_loop:\n"
+          "        cmp     r0, r1\n"
+          "        it      lt\n"
+          "        strlt   r2, [r0], #4\n"
+          "        blt     zero_loop");
+
+    // call system init.	
+	SystemInit();
+
+    //
+    // Call the application's entry point.
+    //
+    main();
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt.  This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void Default_Handler(void)
+{
+    //
+    // Go into an infinite loop.
+    //
+    while(1)
+    {
+    }
+}

bsp/lpc5410x/Libraries/Device/startup/iar_startup_lpc5410x-m0.s

@@ -0,0 +1,304 @@
+;/*****************************************************************************
+; * @file:    startup_LPC5410x-m0.s
+; * @purpose: CMSIS Cortex-M4/M0+ Core Device Startup File
+; *           for the NXP LPC5410x Device Series (manually edited)
+; * @version: V1.00
+; * @date:    19. October 2009
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+__vector_table_0x1c
+        DCD     0							; Checksum of the first 7 words
+        DCD     0
+        DCD     0							; Enhanced image marker, set to 0x0 for legacy boot
+        DCD     0							; Pointer to enhanced boot block, set to 0x0 for legacy boot
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     WDT_IRQHandler              ; Watchdog
+        DCD     BOD_IRQHandler              ; Brown Out Detect
+        DCD     Reserved_IRQHandler         ; Reserved
+        DCD     DMA_IRQHandler              ; DMA Controller
+        DCD     GINT0_IRQHandler            ; GPIO Group0 Interrupt
+        DCD     PIN_INT0_IRQHandler         ; PIO INT0
+        DCD     PIN_INT1_IRQHandler         ; PIO INT1
+        DCD     PIN_INT2_IRQHandler         ; PIO INT2
+        DCD     PIN_INT3_IRQHandler         ; PIO INT3
+        DCD     UTICK_IRQHandler            ; UTICK timer  				
+        DCD     MRT_IRQHandler              ; Multi-Rate Timer
+        DCD     CT32B0_IRQHandler           ; CT32B0
+        DCD     CT32B1_IRQHandler           ; CT32B1
+        DCD     CT32B2_IRQHandler           ; CT32B2
+        DCD     CT32B3_IRQHandler           ; CT32B3
+        DCD     CT32B4_IRQHandler           ; CT32B4
+        DCD     SCT0_IRQHandler             ; Smart Counter Timer 
+        DCD     UART0_IRQHandler            ; UART0             
+        DCD     UART1_IRQHandler            ; UART1            
+        DCD     UART2_IRQHandler            ; UART2
+        DCD     UART3_IRQHandler            ; UART3
+        DCD     I2C0_IRQHandler             ; I2C0 controller  
+        DCD     I2C1_IRQHandler             ; I2C1 controller  
+        DCD     I2C2_IRQHandler             ; I2C2 controller  
+        DCD     SPI0_IRQHandler             ; SPI0 controller				
+        DCD     SPI1_IRQHandler             ; SPI1 controller
+        DCD     ADC_SEQA_IRQHandler         ; ADC0 A sequence (A/D Converter) interrupt
+        DCD     ADC_SEQB_IRQHandler         ; ADC0 B sequence (A/D Converter) interrupt
+        DCD     ADC_THCMP_IRQHandler        ; ADC THCMP and OVERRUN ORed
+        DCD     RTC_IRQHandler              ; RTC Timer
+        DCD     Reserved_IRQHandler         ; Reserved
+        DCD     MAILBOX_IRQHandler          ; Mailbox 
+
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+
+#if !defined(SLAVEBOOT)
+        DATA
+cpu_id	 		EQU		0xE000ED00
+cpu_ctrl 		EQU		0x40000300
+coproc_boot 	EQU		0x40000304
+coproc_stack	EQU		0x40000308
+rel_vals
+				DC32	cpu_id, cpu_ctrl, coproc_boot, coproc_stack
+				DC16	0xFFF, 0xC24
+#endif
+
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler - shared for both cores
+Reset_Handler
+
+#if !defined(SLAVEBOOT)
+; Both the M0+ and M4 core come via this shared startup code,
+				; but the M0+ and M4 core have different vector tables.
+				; Determine if the core executing this code is the master or
+				; the slave and handle each core state individually.
+shared_boot_entry
+				LDR		r6, =rel_vals
+				MOVS	r4, #0							; Flag for slave core (0)
+				MOVS	r5, #1
+
+				; Determine which core (M0+ or M4) this code is running on
+				; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
+get_current_core_id
+				LDR		r0, [r6, #0]
+				LDR		r1, [r0]						; r1 = CPU ID status
+				LSRS	r1, r1, #4						; Right justify 12 CPU ID bits
+				LDRH	r2, [r6, #16]					; Mask for CPU ID bits
+				ANDS	r2, r1, r2						; r2 = ARM COrtex CPU ID
+				LDRH	r3, [r6, #18]					; Mask for CPU ID bits
+				CMP		r3, r2							; Core ID matches M4 identifier
+				BNE		get_master_status
+				MOV		r4, r5							; Set flag for master core (1)
+
+				; Determine if M4 core is the master or slave
+				; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
+get_master_status
+				LDR		r0, [r6, #4]
+				LDR		r3, [r0]			            ; r3 = SYSCON co-processor CPU control status
+				ANDS	r3, r3, r5						; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
+
+				; Select boot based on selected master core and core ID
+select_boot
+				EORS 	r3, r3, r4						; r4 = (Bit 0: 0 = master, 1 = slave)
+				BNE		slave_boot
+				B		normal_boot
+
+				; Slave boot
+slave_boot
+				LDR		r0, [r6, #8]
+				LDR		r2, [r0]						; r1 = SYSCON co-processor boot address
+				CMP		r2, #0							; Slave boot address = 0 (not set up)?
+				BEQ		cpu_sleep
+				LDR		r0, [r6, #12]
+				LDR		r1, [r0]						; r5 = SYSCON co-processor stack address
+				MOV		sp, r1							; Update slave CPU stack pointer
+				; Be sure to update VTOR for the slave MCU to point to the
+				; slave vector table in boot memory
+				BX		r2								; Jump to slave boot address
+
+				; Slave isn't yet setup for system boot from the master
+				; so sleep until the master sets it up and then reboots it
+cpu_sleep
+				MOV		sp, r5							; Will force exception if something happens
+cpu_sleep_wfi
+				WFI										; Sleep forever until master reboots
+				B		cpu_sleep_wfi
+#endif ; defined(SLAVEBOOT)
+
+				; Normal boot for master/slave
+normal_boot
+				LDR		r0, =SystemInit
+				BLX		r0
+				LDR		r0, =__iar_program_start
+				BX		r0
+
+; For cores with SystemInit() or __iar_program_start(), the code will sleep the MCU
+        PUBWEAK SystemInit
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SystemInit
+        BX		LR
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+	PUBWEAK Reserved_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Reserved_IRQHandler
+        B .
+
+		PUBWEAK WDT_IRQHandler              ; Watchdog
+		PUBWEAK BOD_IRQHandler              ; Brown Out Detect
+		PUBWEAK DMA_IRQHandler              ; DMA Controller
+		PUBWEAK GINT0_IRQHandler            ; GPIO Group0 Interrupt
+		PUBWEAK PIN_INT0_IRQHandler         ; PIO INT0
+		PUBWEAK PIN_INT1_IRQHandler         ; PIO INT1
+		PUBWEAK PIN_INT2_IRQHandler         ; PIO INT2
+		PUBWEAK PIN_INT3_IRQHandler         ; PIO INT3
+		PUBWEAK UTICK_IRQHandler            ; UTICK timer  				
+		PUBWEAK MRT_IRQHandler              ; Multi-Rate Timer
+		PUBWEAK CT32B0_IRQHandler           ; CT32B0
+		PUBWEAK CT32B1_IRQHandler           ; CT32B1
+		PUBWEAK CT32B2_IRQHandler           ; CT32B2
+		PUBWEAK CT32B3_IRQHandler           ; CT32B3
+		PUBWEAK CT32B4_IRQHandler           ; CT32B4
+		PUBWEAK UART0_IRQHandler            ; UART0             
+		PUBWEAK SCT0_IRQHandler             ; Smart Counter Timer 
+		PUBWEAK UART1_IRQHandler            ; UART1            
+		PUBWEAK UART2_IRQHandler            ; UART2
+		PUBWEAK UART3_IRQHandler            ; UART3
+		PUBWEAK I2C0_IRQHandler             ; I2C0 controller  
+		PUBWEAK I2C1_IRQHandler             ; I2C1 controller  
+		PUBWEAK I2C2_IRQHandler             ; I2C2 controller  
+		PUBWEAK SPI0_IRQHandler             ; SPI0 controller				
+		PUBWEAK SPI1_IRQHandler             ; SPI1 controller
+		PUBWEAK ADC_SEQA_IRQHandler         ; ADC0 A sequence (A/D Converter) interrupt
+		PUBWEAK ADC_SEQB_IRQHandler         ; ADC0 B sequence (A/D Converter) interrupt
+		PUBWEAK ADC_THCMP_IRQHandler        ; ADC THCMP and OVERRUN ORed
+		PUBWEAK RTC_IRQHandler              ; RTC Timer
+		PUBWEAK MAILBOX_IRQHandler          ; Mailbox 
+
+WDT_IRQHandler              ; Watchdog
+BOD_IRQHandler              ; Brown Out Detect
+DMA_IRQHandler              ; DMA Controller
+GINT0_IRQHandler            ; GPIO Group0 Interrupt
+PIN_INT0_IRQHandler         ; PIO INT0
+PIN_INT1_IRQHandler         ; PIO INT1
+PIN_INT2_IRQHandler         ; PIO INT2
+PIN_INT3_IRQHandler         ; PIO INT3
+UTICK_IRQHandler            ; UTICK timer  				
+MRT_IRQHandler              ; Multi-Rate Timer
+CT32B0_IRQHandler           ; CT32B0
+CT32B1_IRQHandler           ; CT32B1
+CT32B2_IRQHandler           ; CT32B2
+CT32B3_IRQHandler           ; CT32B3
+CT32B4_IRQHandler           ; CT32B4
+UART0_IRQHandler            ; UART0             
+SCT0_IRQHandler             ; Smart Counter Timer 
+UART1_IRQHandler            ; UART1            
+UART2_IRQHandler            ; UART2
+UART3_IRQHandler            ; UART3
+I2C0_IRQHandler             ; I2C0 controller  
+I2C1_IRQHandler             ; I2C1 controller  
+I2C2_IRQHandler             ; I2C2 controller  
+SPI0_IRQHandler             ; SPI0 controller				
+SPI1_IRQHandler             ; SPI1 controller
+ADC_SEQA_IRQHandler         ; ADC0 A sequence (A/D Converter) interrupt
+ADC_SEQB_IRQHandler         ; ADC0 B sequence (A/D Converter) interrupt
+ADC_THCMP_IRQHandler        ; ADC THCMP and OVERRUN ORed
+RTC_IRQHandler              ; RTC Timer
+MAILBOX_IRQHandler          ; Mailbox 
+
+Default_Handler:
+        B .
+
+        END

bsp/lpc5410x/Libraries/Device/startup/iar_startup_lpc5410x.s

@@ -0,0 +1,356 @@
+;/*****************************************************************************
+; * @file:    startup_LPC5410x.s
+; * @purpose: CMSIS Cortex-M4/M0+ Core Device Startup File
+; *           for the NXP LPC5410x Device Series (manually edited)
+; * @version: V1.00
+; * @date:    19. October 2009
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (C) 2009 ARM Limited. All rights reserved.
+; *
+; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+__vector_table_0x1c
+        DCD     0							; Checksum of the first 7 words
+        DCD     0
+        DCD     0							; Enhanced image marker, set to 0x0 for legacy boot
+        DCD     0							; Pointer to enhanced boot block, set to 0x0 for legacy boot
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     WDT_IRQHandler              ; Watchdog
+        DCD     BOD_IRQHandler              ; Brown Out Detect
+        DCD     Reserved_IRQHandler         ; Reserved
+        DCD     DMA_IRQHandler              ; DMA Controller
+        DCD     GINT0_IRQHandler            ; GPIO Group0 Interrupt
+        DCD     PIN_INT0_IRQHandler         ; PIO INT0
+        DCD     PIN_INT1_IRQHandler         ; PIO INT1
+        DCD     PIN_INT2_IRQHandler         ; PIO INT2
+        DCD     PIN_INT3_IRQHandler         ; PIO INT3
+        DCD     UTICK_IRQHandler            ; UTICK timer  				
+        DCD     MRT_IRQHandler              ; Multi-Rate Timer
+        DCD     CT32B0_IRQHandler           ; CT32B0
+        DCD     CT32B1_IRQHandler           ; CT32B1
+        DCD     CT32B2_IRQHandler           ; CT32B2
+        DCD     CT32B3_IRQHandler           ; CT32B3
+        DCD     CT32B4_IRQHandler           ; CT32B4
+        DCD     SCT0_IRQHandler             ; Smart Counter Timer 
+        DCD     UART0_IRQHandler            ; UART0             
+        DCD     UART1_IRQHandler            ; UART1            
+        DCD     UART2_IRQHandler            ; UART2
+        DCD     UART3_IRQHandler            ; UART3
+        DCD     I2C0_IRQHandler             ; I2C0 controller  
+        DCD     I2C1_IRQHandler             ; I2C1 controller  
+        DCD     I2C2_IRQHandler             ; I2C2 controller  
+        DCD     SPI0_IRQHandler             ; SPI0 controller				
+        DCD     SPI1_IRQHandler             ; SPI1 controller
+        DCD     ADC_SEQA_IRQHandler         ; ADC0 A sequence (A/D Converter) interrupt
+        DCD     ADC_SEQB_IRQHandler         ; ADC0 B sequence (A/D Converter) interrupt
+        DCD     ADC_THCMP_IRQHandler        ; ADC THCMP and OVERRUN ORed
+        DCD     RTC_IRQHandler              ; RTC Timer
+        DCD     Reserved_IRQHandler         ; Reserved
+        DCD     MAILBOX_IRQHandler          ; Mailbox 
+        DCD     GINT1_IRQHandler            ; GPIO Group1 Interrupt
+        DCD     PIN_INT4_IRQHandler         ; PIO INT4
+        DCD     PIN_INT5_IRQHandler         ; PIO INT5
+        DCD     PIN_INT6_IRQHandler         ; PIO INT6
+        DCD     PIN_INT7_IRQHandler         ; PIO INT7
+        DCD     Reserved_IRQHandler         ; Reserved				
+        DCD     Reserved_IRQHandler         ; Reserved				
+        DCD     Reserved_IRQHandler         ; Reserved
+        DCD     RIT_IRQHandler              ; RITimer
+        DCD     Reserved41_IRQHandler       ; Reserved                         
+        DCD     Reserved42_IRQHandler       ; Reserved                         
+        DCD     Reserved43_IRQHandler       ; Reserved                         
+        DCD     Reserved44_IRQHandler       ; Reserved                         
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+
+#if !defined(SLAVEBOOT)
+        DATA
+cpu_id	 		EQU		0xE000ED00
+cpu_ctrl 		EQU		0x40000300
+coproc_boot 	EQU		0x40000304
+coproc_stack	EQU		0x40000308
+rel_vals
+				DC32	cpu_id, cpu_ctrl, coproc_boot, coproc_stack
+				DC16	0xFFF, 0xC24
+#endif
+
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+; Reset Handler - shared for both cores
+Reset_Handler
+
+#if !defined(SLAVEBOOT)
+; Both the M0+ and M4 core come via this shared startup code,
+				; but the M0+ and M4 core have different vector tables.
+				; Determine if the core executing this code is the master or
+				; the slave and handle each core state individually.
+shared_boot_entry
+				LDR		r6, =rel_vals
+				MOVS	r4, #0							; Flag for slave core (0)
+				MOVS	r5, #1
+
+				; Determine which core (M0+ or M4) this code is running on
+				; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
+get_current_core_id
+				LDR		r0, [r6, #0]
+				LDR		r1, [r0]						; r1 = CPU ID status
+				LSRS	r1, r1, #4						; Right justify 12 CPU ID bits
+				LDRH	r2, [r6, #16]					; Mask for CPU ID bits
+				ANDS	r2, r1, r2						; r2 = ARM COrtex CPU ID
+				LDRH	r3, [r6, #18]					; Mask for CPU ID bits
+				CMP		r3, r2							; Core ID matches M4 identifier
+				BNE		get_master_status
+				MOV		r4, r5							; Set flag for master core (1)
+
+				; Determine if M4 core is the master or slave
+				; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
+get_master_status
+				LDR		r0, [r6, #4]
+				LDR		r3, [r0]			            ; r3 = SYSCON co-processor CPU control status
+				ANDS	r3, r3, r5						; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
+
+				; Select boot based on selected master core and core ID
+select_boot
+				EORS 	r3, r3, r4						; r4 = (Bit 0: 0 = master, 1 = slave)
+				BNE		slave_boot
+				B		normal_boot
+
+				; Slave boot
+slave_boot
+				LDR		r0, [r6, #8]
+				LDR		r2, [r0]						; r1 = SYSCON co-processor boot address
+				CMP		r2, #0							; Slave boot address = 0 (not set up)?
+				BEQ		cpu_sleep
+				LDR		r0, [r6, #12]
+				LDR		r1, [r0]						; r5 = SYSCON co-processor stack address
+				MOV		sp, r1							; Update slave CPU stack pointer
+				; Be sure to update VTOR for the slave MCU to point to the
+				; slave vector table in boot memory
+				BX		r2								; Jump to slave boot address
+
+				; Slave isn't yet setup for system boot from the master
+				; so sleep until the master sets it up and then reboots it
+cpu_sleep
+				MOV		sp, r5							; Will force exception if something happens
+cpu_sleep_wfi
+				WFI										; Sleep forever until master reboots
+				B		cpu_sleep_wfi
+#endif ; defined(SLAVEBOOT)
+
+				; Normal boot for master/slave
+normal_boot
+				LDR		r0, =SystemInit
+				BLX		r0
+				LDR		r0, =__iar_program_start
+				BX		r0
+
+; For cores with SystemInit() or __iar_program_start(), the code will sleep the MCU
+        PUBWEAK SystemInit
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SystemInit
+        BX		LR
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+	PUBWEAK Reserved_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+Reserved_IRQHandler
+        B .
+
+		PUBWEAK WDT_IRQHandler              ; Watchdog
+		PUBWEAK BOD_IRQHandler              ; Brown Out Detect
+		PUBWEAK DMA_IRQHandler              ; DMA Controller
+		PUBWEAK GINT0_IRQHandler            ; GPIO Group0 Interrupt
+		PUBWEAK PIN_INT0_IRQHandler         ; PIO INT0
+		PUBWEAK PIN_INT1_IRQHandler         ; PIO INT1
+		PUBWEAK PIN_INT2_IRQHandler         ; PIO INT2
+		PUBWEAK PIN_INT3_IRQHandler         ; PIO INT3
+		PUBWEAK UTICK_IRQHandler            ; UTICK timer  				
+		PUBWEAK MRT_IRQHandler              ; Multi-Rate Timer
+		PUBWEAK CT32B0_IRQHandler           ; CT32B0
+		PUBWEAK CT32B1_IRQHandler           ; CT32B1
+		PUBWEAK CT32B2_IRQHandler           ; CT32B2
+		PUBWEAK CT32B3_IRQHandler           ; CT32B3
+		PUBWEAK CT32B4_IRQHandler           ; CT32B4
+		PUBWEAK UART0_IRQHandler            ; UART0             
+		PUBWEAK SCT0_IRQHandler             ; Smart Counter Timer 
+		PUBWEAK UART1_IRQHandler            ; UART1            
+		PUBWEAK UART2_IRQHandler            ; UART2
+		PUBWEAK UART3_IRQHandler            ; UART3
+		PUBWEAK I2C0_IRQHandler             ; I2C0 controller  
+		PUBWEAK I2C1_IRQHandler             ; I2C1 controller  
+		PUBWEAK I2C2_IRQHandler             ; I2C2 controller  
+		PUBWEAK SPI0_IRQHandler             ; SPI0 controller				
+		PUBWEAK SPI1_IRQHandler             ; SPI1 controller
+		PUBWEAK ADC_SEQA_IRQHandler         ; ADC0 A sequence (A/D Converter) interrupt
+		PUBWEAK ADC_SEQB_IRQHandler         ; ADC0 B sequence (A/D Converter) interrupt
+		PUBWEAK ADC_THCMP_IRQHandler        ; ADC THCMP and OVERRUN ORed
+		PUBWEAK RTC_IRQHandler              ; RTC Timer
+		PUBWEAK MAILBOX_IRQHandler          ; Mailbox 
+		PUBWEAK GINT1_IRQHandler            ; GPIO Group1 Interrupt
+		PUBWEAK PIN_INT4_IRQHandler         ; PIO INT4
+		PUBWEAK PIN_INT5_IRQHandler         ; PIO INT5
+		PUBWEAK PIN_INT6_IRQHandler         ; PIO INT6
+		PUBWEAK PIN_INT7_IRQHandler         ; PIO INT7
+		PUBWEAK RIT_IRQHandler              ; RITimer
+		PUBWEAK Reserved41_IRQHandler       ; Reserved                         
+		PUBWEAK Reserved42_IRQHandler       ; Reserved       
+		PUBWEAK Reserved43_IRQHandler       ; Reserved                         
+		PUBWEAK Reserved44_IRQHandler       ; Reserved  
+
+WDT_IRQHandler              ; Watchdog
+BOD_IRQHandler              ; Brown Out Detect
+DMA_IRQHandler              ; DMA Controller
+GINT0_IRQHandler            ; GPIO Group0 Interrupt
+PIN_INT0_IRQHandler         ; PIO INT0
+PIN_INT1_IRQHandler         ; PIO INT1
+PIN_INT2_IRQHandler         ; PIO INT2
+PIN_INT3_IRQHandler         ; PIO INT3
+UTICK_IRQHandler            ; UTICK timer  				
+MRT_IRQHandler              ; Multi-Rate Timer
+CT32B0_IRQHandler           ; CT32B0
+CT32B1_IRQHandler           ; CT32B1
+CT32B2_IRQHandler           ; CT32B2
+CT32B3_IRQHandler           ; CT32B3
+CT32B4_IRQHandler           ; CT32B4
+UART0_IRQHandler            ; UART0             
+SCT0_IRQHandler             ; Smart Counter Timer 
+UART1_IRQHandler            ; UART1            
+UART2_IRQHandler            ; UART2
+UART3_IRQHandler            ; UART3
+I2C0_IRQHandler             ; I2C0 controller  
+I2C1_IRQHandler             ; I2C1 controller  
+I2C2_IRQHandler             ; I2C2 controller  
+SPI0_IRQHandler             ; SPI0 controller				
+SPI1_IRQHandler             ; SPI1 controller
+ADC_SEQA_IRQHandler         ; ADC0 A sequence (A/D Converter) interrupt
+ADC_SEQB_IRQHandler         ; ADC0 B sequence (A/D Converter) interrupt
+ADC_THCMP_IRQHandler        ; ADC THCMP and OVERRUN ORed
+RTC_IRQHandler              ; RTC Timer
+MAILBOX_IRQHandler          ; Mailbox 
+GINT1_IRQHandler            ; GPIO Group1 Interrupt
+PIN_INT4_IRQHandler         ; PIO INT4
+PIN_INT5_IRQHandler         ; PIO INT5
+PIN_INT6_IRQHandler         ; PIO INT6
+PIN_INT7_IRQHandler         ; PIO INT7
+RIT_IRQHandler              ; RITimer
+Reserved41_IRQHandler       ; Reserved                         
+Reserved42_IRQHandler       ; Reserved       
+Reserved43_IRQHandler       ; Reserved                         
+Reserved44_IRQHandler       ; Reserved  
+
+Default_Handler:
+        B .
+
+        END

bsp/lpc5410x/Libraries/Device/startup/keil_startup_lpc5410x-m0.s

@@ -0,0 +1,338 @@
+;/*
+; * @brief LPC5410x M0 core startup code for Keil
+; *
+; * @note
+; * Copyright(C) NXP Semiconductors, 2014
+; * All rights reserved.
+; *
+; * @par
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * LPC products.  This software is supplied "AS IS" without any warranties of
+; * any kind, and NXP Semiconductors and its licensor disclaim any and
+; * all warranties, express or implied, including all implied warranties of
+; * merchantability, fitness for a particular purpose and non-infringement of
+; * intellectual property rights.  NXP Semiconductors assumes no responsibility
+; * or liability for the use of the software, conveys no license or rights under any
+; * patent, copyright, mask work right, or any other intellectual property rights in
+; * or to any products. NXP Semiconductors reserves the right to make changes
+; * in the software without notification. NXP Semiconductors also makes no
+; * representation or warranty that such application will be suitable for the
+; * specified use without further testing or modification.
+; *
+; * @par
+; * Permission to use, copy, modify, and distribute this software and its
+; * documentation is hereby granted, under NXP Semiconductors' and its
+; * licensor's relevant copyrights in the software, without fee, provided that it
+; * is used in conjunction with NXP Semiconductors microcontrollers.  This
+; * copyright, permission, and disclaimer notice must appear in all copies of
+; * this code.
+; */
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0
+                DCD     0
+                DCD     0
+__vector_table_0x1c
+                DCD     0                         ; Checksum of the first 7 words
+                DCD     0
+                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
+                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0
+                DCD     0
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+        ; External Interrupts
+                DCD     WDT_IRQHandler            ; Watchdog
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     DMA_IRQHandler            ; DMA Controller
+                DCD     GINT0_IRQHandler          ; GPIO Group0 Interrupt
+                DCD     PIN_INT0_IRQHandler       ; PIO INT0
+                DCD     PIN_INT1_IRQHandler       ; PIO INT1
+                DCD     PIN_INT2_IRQHandler       ; PIO INT2
+                DCD     PIN_INT3_IRQHandler       ; PIO INT3
+                DCD     UTICK_IRQHandler          ; UTICK timer  				
+                DCD     MRT_IRQHandler            ; Multi-Rate Timer
+                DCD     CT32B0_IRQHandler         ; CT32B0
+                DCD     CT32B1_IRQHandler         ; CT32B1
+                DCD     CT32B2_IRQHandler         ; CT32B2
+                DCD     CT32B3_IRQHandler         ; CT32B3
+                DCD     CT32B4_IRQHandler         ; CT32B4
+                DCD     SCT0_IRQHandler           ; Smart Counter Timer 
+                DCD     UART0_IRQHandler          ; UART0             
+                DCD     UART1_IRQHandler          ; UART1            
+                DCD     UART2_IRQHandler          ; UART2
+                DCD     UART3_IRQHandler          ; UART3
+                DCD     I2C0_IRQHandler           ; I2C0 controller  
+                DCD     I2C1_IRQHandler           ; I2C1 controller  
+                DCD     I2C2_IRQHandler           ; I2C2 controller  
+                DCD     SPI0_IRQHandler           ; SPI0 controller				
+                DCD     SPI1_IRQHandler           ; SPI1 controller
+                DCD     ADC_SEQA_IRQHandler       ; ADC0 A sequence (A/D Converter) interrupt
+                DCD     ADC_SEQB_IRQHandler       ; ADC0 B sequence (A/D Converter) interrupt
+                DCD     ADC_THCMP_IRQHandler      ; ADC THCMP and OVERRUN ORed
+                DCD     RTC_IRQHandler            ; RTC Timer
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     MAILBOX_IRQHandler        ; Mailbox 
+
+;//   <h> Code Read Protection level (CRP)
+;//     <o>    CRP_Level:
+;//                     <0xFFFFFFFF=> Disabled
+;//                     <0x4E697370=> NO_ISP
+;//                     <0x12345678=> CRP1
+;//                     <0x87654321=> CRP2
+;//                     <0x43218765=> CRP3 (Are you sure?)
+;//   </h>
+CRP_Level		EQU		0xFFFFFFFF
+
+				IF		:LNOT::DEF:NO_CRP
+				AREA	|.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key			DCD		0xFFFFFFFF
+				ENDIF
+
+				AREA	|.text|, CODE, READONLY
+
+cpu_id	 		EQU		0xE000ED00
+cpu_ctrl 		EQU		0x40000300
+coproc_boot 	EQU		0x40000304
+coproc_stack	EQU		0x40000308
+
+rel_vals
+				DCD		cpu_id, cpu_ctrl, coproc_boot, coproc_stack
+				DCW		0xFFF, 0xC24
+
+; Reset Handler - shared for both cores
+Reset_Handler   PROC
+                EXPORT	Reset_Handler				[WEAK]
+                EXPORT	SystemInit					[WEAK]
+                IMPORT	__main
+
+				IF		:LNOT::DEF:SLAVEBOOT
+				; Both the M0+ and M4 core come via this shared startup code,
+				; but the M0+ and M4 core have different vector tables.
+				; Determine if the core executing this code is the master or
+				; the slave and handle each core state individually.
+shared_boot_entry
+				LDR		r6, =rel_vals
+				MOVS	r4, #0							; Flag for slave core (0)
+				MOVS	r5, #1
+
+				; Determine which core (M0+ or M4) this code is running on
+				; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
+get_current_core_id
+				LDR		r0, [r6, #0]
+				LDR		r1, [r0]						; r1 = CPU ID status
+				LSRS	r1, r1, #4						; Right justify 12 CPU ID bits
+				LDRH	r2, [r6, #16]					; Mask for CPU ID bits
+				ANDS	r2, r1, r2						; r2 = ARM COrtex CPU ID
+				LDRH	r3, [r6, #18]					; Mask for CPU ID bits
+				CMP		r3, r2							; Core ID matches M4 identifier
+				BNE		get_master_status
+				MOV		r4, r5							; Set flag for master core (1)
+
+				; Determine if M4 core is the master or slave
+				; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
+get_master_status
+				LDR		r0, [r6, #4]
+				LDR		r3, [r0]			            ; r3 = SYSCON co-processor CPU control status
+				ANDS	r3, r3, r5						; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
+
+				; Select boot based on selected master core and core ID
+select_boot
+				EORS 	r3, r3, r4						; r4 = (Bit 0: 0 = master, 1 = slave)
+				BNE		slave_boot
+				B		normal_boot
+
+				; Slave boot
+slave_boot
+				LDR		r0, [r6, #8]
+				LDR		r2, [r0]						; r1 = SYSCON co-processor boot address
+				CMP		r2, #0							; Slave boot address = 0 (not set up)?
+				BEQ		cpu_sleep
+				LDR		r0, [r6, #12]
+				LDR		r1, [r0]						; r5 = SYSCON co-processor stack address
+				MOV		sp, r1							; Update slave CPU stack pointer
+				; Be sure to update VTOR for the slave MCU to point to the
+				; slave vector table in boot memory
+				BX		r2								; Jump to slave boot address
+
+				; Slave isn't yet setup for system boot from the master
+				; so sleep until the master sets it up and then reboots it
+cpu_sleep
+				MOV		sp, r5							; Will force exception if something happens
+cpu_sleep_wfi
+				WFI										; Sleep forever until master reboots
+				B		cpu_sleep_wfi
+				ENDIF
+
+				; Normal boot for master/slave
+normal_boot
+				LDR		r0, =SystemInit
+				BLX		r0
+				LDR		r0, =__main
+				BX		r0
+				ENDP
+
+; For cores with SystemInit() or __main(), the code will sleep the MCU
+SystemInit		PROC
+                EXPORT  SystemInit					[WEAK]
+				BX		lr
+				ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+               EXPORT WDT_IRQHandler              [WEAK] ; Watchdog
+               EXPORT BOD_IRQHandler              [WEAK] ; Brown Out Detect
+               EXPORT DMA_IRQHandler              [WEAK] ; DMA Controller
+               EXPORT GINT0_IRQHandler            [WEAK] ; GPIO Group0 Interrupt
+               EXPORT PIN_INT0_IRQHandler         [WEAK] ; PIO INT0
+               EXPORT PIN_INT1_IRQHandler         [WEAK] ; PIO INT1
+               EXPORT PIN_INT2_IRQHandler         [WEAK] ; PIO INT2
+               EXPORT PIN_INT3_IRQHandler         [WEAK] ; PIO INT3
+               EXPORT UTICK_IRQHandler            [WEAK] ; UTICK timer  				
+               EXPORT MRT_IRQHandler              [WEAK] ; Multi-Rate Timer
+               EXPORT CT32B0_IRQHandler           [WEAK] ; CT32B0
+               EXPORT CT32B1_IRQHandler           [WEAK] ; CT32B1
+               EXPORT CT32B2_IRQHandler           [WEAK] ; CT32B2
+               EXPORT CT32B3_IRQHandler           [WEAK] ; CT32B3
+               EXPORT CT32B4_IRQHandler           [WEAK] ; CT32B4
+               EXPORT UART0_IRQHandler            [WEAK] ; UART0             
+               EXPORT SCT0_IRQHandler             [WEAK] ; Smart Counter Timer 
+               EXPORT UART1_IRQHandler            [WEAK] ; UART1            
+               EXPORT UART2_IRQHandler            [WEAK] ; UART2
+               EXPORT UART3_IRQHandler            [WEAK] ; UART3
+               EXPORT I2C0_IRQHandler             [WEAK] ; I2C0 controller  
+               EXPORT I2C1_IRQHandler             [WEAK] ; I2C1 controller  
+               EXPORT I2C2_IRQHandler             [WEAK] ; I2C2 controller  
+               EXPORT SPI0_IRQHandler             [WEAK] ; SPI0 controller				
+               EXPORT SPI1_IRQHandler             [WEAK] ; SPI1 controller
+               EXPORT ADC_SEQA_IRQHandler         [WEAK] ; ADC0 A sequence (A/D Converter) interrupt
+               EXPORT ADC_SEQB_IRQHandler         [WEAK] ; ADC0 B sequence (A/D Converter) interrupt
+               EXPORT ADC_THCMP_IRQHandler        [WEAK] ; ADC THCMP and OVERRUN ORed
+               EXPORT RTC_IRQHandler              [WEAK] ; RTC Timer
+               EXPORT MAILBOX_IRQHandler          [WEAK] ; Mailbox 
+               EXPORT Reserved_IRQHandler         [WEAK] ; Reserved  
+
+WDT_IRQHandler              ; Watchdog
+BOD_IRQHandler              ; Brown Out Detect
+DMA_IRQHandler              ; DMA Controller
+GINT0_IRQHandler            ; GPIO Group0 Interrupt
+PIN_INT0_IRQHandler         ; PIO INT0
+PIN_INT1_IRQHandler         ; PIO INT1
+PIN_INT2_IRQHandler         ; PIO INT2
+PIN_INT3_IRQHandler         ; PIO INT3
+UTICK_IRQHandler            ; UTICK timer  				
+MRT_IRQHandler              ; Multi-Rate Timer
+CT32B0_IRQHandler           ; CT32B0
+CT32B1_IRQHandler           ; CT32B1
+CT32B2_IRQHandler           ; CT32B2
+CT32B3_IRQHandler           ; CT32B3
+CT32B4_IRQHandler           ; CT32B4
+UART0_IRQHandler            ; UART0             
+SCT0_IRQHandler             ; Smart Counter Timer 
+UART1_IRQHandler            ; UART1            
+UART2_IRQHandler            ; UART2
+UART3_IRQHandler            ; UART3
+I2C0_IRQHandler             ; I2C0 controller  
+I2C1_IRQHandler             ; I2C1 controller  
+I2C2_IRQHandler             ; I2C2 controller  
+SPI0_IRQHandler             ; SPI0 controller				
+SPI1_IRQHandler             ; SPI1 controller
+ADC_SEQA_IRQHandler         ; ADC0 A sequence (A/D Converter) interrupt
+ADC_SEQB_IRQHandler         ; ADC0 B sequence (A/D Converter) interrupt
+ADC_THCMP_IRQHandler        ; ADC THCMP and OVERRUN ORed
+RTC_IRQHandler              ; RTC Timer
+MAILBOX_IRQHandler          ; Mailbox 
+Reserved_IRQHandler         ; Reserved  
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

bsp/lpc5410x/Libraries/Device/startup/keil_startup_lpc5410x.s

@@ -0,0 +1,388 @@
+;/*
+; * @brief LPC5410x startup code for Keil
+; *
+; * @note
+; * Copyright(C) NXP Semiconductors, 2014
+; * All rights reserved.
+; *
+; * @par
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * LPC products.  This software is supplied "AS IS" without any warranties of
+; * any kind, and NXP Semiconductors and its licensor disclaim any and
+; * all warranties, express or implied, including all implied warranties of
+; * merchantability, fitness for a particular purpose and non-infringement of
+; * intellectual property rights.  NXP Semiconductors assumes no responsibility
+; * or liability for the use of the software, conveys no license or rights under any
+; * patent, copyright, mask work right, or any other intellectual property rights in
+; * or to any products. NXP Semiconductors reserves the right to make changes
+; * in the software without notification. NXP Semiconductors also makes no
+; * representation or warranty that such application will be suitable for the
+; * specified use without further testing or modification.
+; *
+; * @par
+; * Permission to use, copy, modify, and distribute this software and its
+; * documentation is hereby granted, under NXP Semiconductors' and its
+; * licensor's relevant copyrights in the software, without fee, provided that it
+; * is used in conjunction with NXP Semiconductors microcontrollers.  This
+; * copyright, permission, and disclaimer notice must appear in all copies of
+; * this code.
+; */
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000200
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000100
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+
+                DCD     NMI_Handler
+                DCD     HardFault_Handler
+                DCD     MemManage_Handler
+                DCD     BusFault_Handler
+                DCD     UsageFault_Handler
+__vector_table_0x1c
+                DCD     0                         ; Checksum of the first 7 words
+                DCD     0
+                DCD     0                         ; Enhanced image marker, set to 0x0 for legacy boot
+                DCD     0                         ; Pointer to enhanced boot block, set to 0x0 for legacy boot
+                DCD     SVC_Handler
+                DCD     DebugMon_Handler
+                DCD     0
+                DCD     PendSV_Handler
+                DCD     SysTick_Handler
+
+        ; External Interrupts
+                DCD     WDT_IRQHandler            ; Watchdog
+                DCD     BOD_IRQHandler            ; Brown Out Detect
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     DMA_IRQHandler            ; DMA Controller
+                DCD     GINT0_IRQHandler          ; GPIO Group0 Interrupt
+                DCD     PIN_INT0_IRQHandler       ; PIO INT0
+                DCD     PIN_INT1_IRQHandler       ; PIO INT1
+                DCD     PIN_INT2_IRQHandler       ; PIO INT2
+                DCD     PIN_INT3_IRQHandler       ; PIO INT3
+                DCD     UTICK_IRQHandler          ; UTICK timer  				
+                DCD     MRT_IRQHandler            ; Multi-Rate Timer
+                DCD     CT32B0_IRQHandler         ; CT32B0
+                DCD     CT32B1_IRQHandler         ; CT32B1
+                DCD     CT32B2_IRQHandler         ; CT32B2
+                DCD     CT32B3_IRQHandler         ; CT32B3
+                DCD     CT32B4_IRQHandler         ; CT32B4
+                DCD     SCT0_IRQHandler           ; Smart Counter Timer 
+                DCD     UART0_IRQHandler          ; UART0             
+                DCD     UART1_IRQHandler          ; UART1            
+                DCD     UART2_IRQHandler          ; UART2
+                DCD     UART3_IRQHandler          ; UART3
+                DCD     I2C0_IRQHandler           ; I2C0 controller  
+                DCD     I2C1_IRQHandler           ; I2C1 controller  
+                DCD     I2C2_IRQHandler           ; I2C2 controller  
+                DCD     SPI0_IRQHandler           ; SPI0 controller				
+                DCD     SPI1_IRQHandler           ; SPI1 controller
+                DCD     ADC_SEQA_IRQHandler       ; ADC0 A sequence (A/D Converter) interrupt
+                DCD     ADC_SEQB_IRQHandler       ; ADC0 B sequence (A/D Converter) interrupt
+                DCD     ADC_THCMP_IRQHandler      ; ADC THCMP and OVERRUN ORed
+                DCD     RTC_IRQHandler            ; RTC Timer
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     MAILBOX_IRQHandler        ; Mailbox 
+                DCD     GINT1_IRQHandler          ; GPIO Group1 Interrupt
+                DCD     PIN_INT4_IRQHandler       ; PIO INT4
+                DCD     PIN_INT5_IRQHandler       ; PIO INT5
+                DCD     PIN_INT6_IRQHandler       ; PIO INT6
+                DCD     PIN_INT7_IRQHandler       ; PIO INT7
+                DCD     Reserved_IRQHandler       ; Reserved				
+                DCD     Reserved_IRQHandler       ; Reserved				
+                DCD     Reserved_IRQHandler       ; Reserved
+                DCD     RIT_IRQHandler            ; RITimer
+                DCD     Reserved41_IRQHandler     ; Reserved                         
+                DCD     Reserved42_IRQHandler     ; Reserved                         
+                DCD     Reserved43_IRQHandler     ; Reserved                         
+                DCD     Reserved44_IRQHandler     ; Reserved      
+
+;//   <h> Code Read Protection level (CRP)
+;//     <o>    CRP_Level:
+;//                     <0xFFFFFFFF=> Disabled
+;//                     <0x4E697370=> NO_ISP
+;//                     <0x12345678=> CRP1
+;//                     <0x87654321=> CRP2
+;//                     <0x43218765=> CRP3 (Are you sure?)
+;//   </h>
+;CRP_Level		EQU		0xFFFFFFFF
+
+				;IF		:LNOT::DEF:NO_CRP
+				;AREA	|.ARM.__at_0x02FC|, CODE, READONLY
+;CRP_Key			DCD		0xFFFFFFFF
+				;ENDIF
+
+				AREA	|.text|, CODE, READONLY
+
+;cpu_id	 		EQU		0xE000ED00
+;cpu_ctrl 		EQU		0x40000300
+;coproc_boot 	EQU		0x40000304
+;coproc_stack	EQU		0x40000308
+
+;rel_vals
+				;DCD		cpu_id, cpu_ctrl, coproc_boot, coproc_stack
+				;DCW		0xFFF, 0xC24
+
+; Reset Handler - shared for both cores
+Reset_Handler   PROC
+                EXPORT	Reset_Handler				[WEAK]
+                EXPORT	SystemInit					[WEAK]
+                IMPORT	__main
+
+				;IF		:LNOT::DEF:SLAVEBOOT
+				 ;Both the M0+ and M4 core come via this shared startup code,
+				 ;but the M0+ and M4 core have different vector tables.
+				 ;Determine if the core executing this code is the master or
+				 ;the slave and handle each core state individually.
+;shared_boot_entry
+				;LDR		r6, =rel_vals
+				;MOVS	r4, #0							; Flag for slave core (0)
+				;MOVS	r5, #1
+
+				;; Determine which core (M0+ or M4) this code is running on
+				;; r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24)
+;get_current_core_id
+				;LDR		r0, [r6, #0]
+				;LDR		r1, [r0]						; r1 = CPU ID status
+				;LSRS	r1, r1, #4						; Right justify 12 CPU ID bits
+				;LDRH	r2, [r6, #16]					; Mask for CPU ID bits
+				;ANDS	r2, r1, r2						; r2 = ARM COrtex CPU ID
+				;LDRH	r3, [r6, #18]					; Mask for CPU ID bits
+				;CMP		r3, r2							; Core ID matches M4 identifier
+				;BNE		get_master_status
+				;MOV		r4, r5							; Set flag for master core (1)
+
+				;; Determine if M4 core is the master or slave
+				;; r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4)
+;get_master_status
+				;LDR		r0, [r6, #4]
+				;LDR		r3, [r0]			            ; r3 = SYSCON co-processor CPU control status
+				;ANDS	r3, r3, r5						; r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave)
+
+				;; Select boot based on selected master core and core ID
+;select_boot
+				;EORS 	r3, r3, r4						; r4 = (Bit 0: 0 = master, 1 = slave)
+				;BNE		slave_boot
+				;B		normal_boot
+
+				;; Slave boot
+;slave_boot
+				;LDR		r0, [r6, #8]
+				;LDR		r2, [r0]						; r1 = SYSCON co-processor boot address
+				;CMP		r2, #0							; Slave boot address = 0 (not set up)?
+				;BEQ		cpu_sleep
+				;LDR		r0, [r6, #12]
+				;LDR		r1, [r0]						; r5 = SYSCON co-processor stack address
+				;MOV		sp, r1							; Update slave CPU stack pointer
+				;; Be sure to update VTOR for the slave MCU to point to the
+				;; slave vector table in boot memory
+				;BX		r2								; Jump to slave boot address
+
+				;; Slave isn't yet setup for system boot from the master
+				;; so sleep until the master sets it up and then reboots it
+;cpu_sleep
+				;MOV		sp, r5							; Will force exception if something happens
+;cpu_sleep_wfi
+				;WFI										; Sleep forever until master reboots
+				;B		cpu_sleep_wfi
+				;ENDIF
+
+				; Normal boot for master/slave
+;normal_boot
+				LDR		r0, =SystemInit
+				BLX		r0
+				LDR		r0, =__main
+				BX		r0
+				ENDP
+
+; For cores with SystemInit() or __main(), the code will sleep the MCU
+SystemInit		PROC
+                EXPORT  SystemInit					[WEAK]
+				BX		lr
+				ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)                
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler     PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+               EXPORT WDT_IRQHandler              [WEAK] ; Watchdog
+               EXPORT BOD_IRQHandler              [WEAK] ; Brown Out Detect
+               EXPORT DMA_IRQHandler              [WEAK] ; DMA Controller
+               EXPORT GINT0_IRQHandler            [WEAK] ; GPIO Group0 Interrupt
+               EXPORT PIN_INT0_IRQHandler         [WEAK] ; PIO INT0
+               EXPORT PIN_INT1_IRQHandler         [WEAK] ; PIO INT1
+               EXPORT PIN_INT2_IRQHandler         [WEAK] ; PIO INT2
+               EXPORT PIN_INT3_IRQHandler         [WEAK] ; PIO INT3
+               EXPORT UTICK_IRQHandler            [WEAK] ; UTICK timer  				
+               EXPORT MRT_IRQHandler              [WEAK] ; Multi-Rate Timer
+               EXPORT CT32B0_IRQHandler           [WEAK] ; CT32B0
+               EXPORT CT32B1_IRQHandler           [WEAK] ; CT32B1
+               EXPORT CT32B2_IRQHandler           [WEAK] ; CT32B2
+               EXPORT CT32B3_IRQHandler           [WEAK] ; CT32B3
+               EXPORT CT32B4_IRQHandler           [WEAK] ; CT32B4
+               EXPORT UART0_IRQHandler            [WEAK] ; UART0             
+               EXPORT SCT0_IRQHandler             [WEAK] ; Smart Counter Timer 
+               EXPORT UART1_IRQHandler            [WEAK] ; UART1            
+               EXPORT UART2_IRQHandler            [WEAK] ; UART2
+               EXPORT UART3_IRQHandler            [WEAK] ; UART3
+               EXPORT I2C0_IRQHandler             [WEAK] ; I2C0 controller  
+               EXPORT I2C1_IRQHandler             [WEAK] ; I2C1 controller  
+               EXPORT I2C2_IRQHandler             [WEAK] ; I2C2 controller  
+               EXPORT SPI0_IRQHandler             [WEAK] ; SPI0 controller				
+               EXPORT SPI1_IRQHandler             [WEAK] ; SPI1 controller
+               EXPORT ADC_SEQA_IRQHandler         [WEAK] ; ADC0 A sequence (A/D Converter) interrupt
+               EXPORT ADC_SEQB_IRQHandler         [WEAK] ; ADC0 B sequence (A/D Converter) interrupt
+               EXPORT ADC_THCMP_IRQHandler        [WEAK] ; ADC THCMP and OVERRUN ORed
+               EXPORT RTC_IRQHandler              [WEAK] ; RTC Timer
+               EXPORT MAILBOX_IRQHandler          [WEAK] ; Mailbox 
+               EXPORT GINT1_IRQHandler            [WEAK] ; GPIO Group1 Interrupt
+               EXPORT PIN_INT4_IRQHandler         [WEAK] ; PIO INT4
+               EXPORT PIN_INT5_IRQHandler         [WEAK] ; PIO INT5
+               EXPORT PIN_INT6_IRQHandler         [WEAK] ; PIO INT6
+               EXPORT PIN_INT7_IRQHandler         [WEAK] ; PIO INT7
+               EXPORT RIT_IRQHandler              [WEAK] ; RITimer
+               EXPORT Reserved41_IRQHandler       [WEAK] ; Reserved                         
+               EXPORT Reserved42_IRQHandler       [WEAK] ; Reserved       
+               EXPORT Reserved43_IRQHandler       [WEAK] ; Reserved                         
+               EXPORT Reserved44_IRQHandler       [WEAK] ; Reserved  
+               EXPORT Reserved_IRQHandler         [WEAK] ; Reserved  
+
+WDT_IRQHandler              ; Watchdog
+BOD_IRQHandler              ; Brown Out Detect
+DMA_IRQHandler              ; DMA Controller
+GINT0_IRQHandler            ; GPIO Group0 Interrupt
+PIN_INT0_IRQHandler         ; PIO INT0
+PIN_INT1_IRQHandler         ; PIO INT1
+PIN_INT2_IRQHandler         ; PIO INT2
+PIN_INT3_IRQHandler         ; PIO INT3
+UTICK_IRQHandler            ; UTICK timer  				
+MRT_IRQHandler              ; Multi-Rate Timer
+CT32B0_IRQHandler           ; CT32B0
+CT32B1_IRQHandler           ; CT32B1
+CT32B2_IRQHandler           ; CT32B2
+CT32B3_IRQHandler           ; CT32B3
+CT32B4_IRQHandler           ; CT32B4
+UART0_IRQHandler            ; UART0             
+SCT0_IRQHandler             ; Smart Counter Timer 
+UART1_IRQHandler            ; UART1            
+UART2_IRQHandler            ; UART2
+UART3_IRQHandler            ; UART3
+I2C0_IRQHandler             ; I2C0 controller  
+I2C1_IRQHandler             ; I2C1 controller  
+I2C2_IRQHandler             ; I2C2 controller  
+SPI0_IRQHandler             ; SPI0 controller				
+SPI1_IRQHandler             ; SPI1 controller
+ADC_SEQA_IRQHandler         ; ADC0 A sequence (A/D Converter) interrupt
+ADC_SEQB_IRQHandler         ; ADC0 B sequence (A/D Converter) interrupt
+ADC_THCMP_IRQHandler        ; ADC THCMP and OVERRUN ORed
+RTC_IRQHandler              ; RTC Timer
+MAILBOX_IRQHandler          ; Mailbox 
+GINT1_IRQHandler            ; GPIO Group1 Interrupt
+PIN_INT4_IRQHandler         ; PIO INT4
+PIN_INT5_IRQHandler         ; PIO INT5
+PIN_INT6_IRQHandler         ; PIO INT6
+PIN_INT7_IRQHandler         ; PIO INT7
+RIT_IRQHandler              ; RITimer
+Reserved41_IRQHandler       ; Reserved                         
+Reserved42_IRQHandler       ; Reserved       
+Reserved43_IRQHandler       ; Reserved                         
+Reserved44_IRQHandler       ; Reserved  
+Reserved_IRQHandler         ; Reserved  
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

bsp/lpc5410x/Libraries/Device/startup/mtb.c

@@ -0,0 +1,86 @@
+//*****************************************************************************
+//   +--+       
+//   | ++----+   
+//   +-++    |  
+//     |     |  
+//   +-+--+  |   
+//   | +--+--+  
+//   +----+    Copyright (c) 2013 Code Red Technologies Ltd.
+//
+//  mtb.c 
+//
+// Optionally defines an array to be used as a buffer for Micro Trace
+// Buffer (MTB) instruction trace on Cortex-M0+ parts
+//
+// Version : 130502
+//
+// Software License Agreement
+// 
+// The software is owned by Code Red Technologies and/or its suppliers, and is 
+// protected under applicable copyright laws.  All rights are reserved.  Any 
+// use in violation of the foregoing restrictions may subject the user to criminal 
+// sanctions under applicable laws, as well as to civil liability for the breach
+// of the terms and conditions of this license.
+// 
+// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
+// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
+// CODE RED TECHNOLOGIES LTD. 
+//
+//*****************************************************************************
+
+/*******************************************************************
+ * Symbols controlling behavior of this code...
+ *
+ * __MTB_DISABLE
+ *     If this symbol is defined, then the buffer array for the MTB
+ *     will not be created.
+ *
+ * __MTB_BUFFER_SIZE
+ *     Symbol specifying the sizer of the buffer array for the MTB.
+ *     This must be a power of 2 in size, and fit into the available
+ *     RAM. The MTB buffer will also be aligned to its 'size' 
+ *     boundary and be placed at the start of a RAM bank (which 
+ *     should ensure minimal or zero padding due to alignment).
+ * 
+ * __MTB_RAM_BANK
+ *     Allows MTB Buffer to be placed into specific RAM bank. When 
+ *     this is not defined, the "default" (first if there are 
+ *     several) RAM bank is used.
+ *******************************************************************/
+
+// Ignore with none Code Red tools
+#if defined (__CODE_RED)
+
+// Allow MTB to be removed by setting a define (via command line)
+#if !defined (__MTB_DISABLE)
+
+  // Allow for MTB buffer size being set by define set via command line
+  // Otherwise provide small default buffer
+  #if !defined (__MTB_BUFFER_SIZE)
+    #define __MTB_BUFFER_SIZE 128
+  #endif
+
+  // Check that buffer size requested is >0 bytes in size
+  #if (__MTB_BUFFER_SIZE > 0)
+    // Pull in MTB related macros
+    #include <cr_mtb_buffer.h>
+
+    // Check if MYTB buffer is to be placed in specific RAM bank
+    #if defined(__MTB_RAM_BANK)
+	    // Place MTB buffer into explicit bank of RAM
+	    __CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK);
+    #else
+	    // Place MTB buffer into 'default' bank of RAM
+	    __CR_MTB_BUFFER(__MTB_BUFFER_SIZE);
+
+    #endif  // defined(__MTB_RAM_BANK)
+
+  #endif // (__MTB_BUFFER_SIZE > 0)
+
+#endif // !defined (__MTB_DISABLE)
+
+#endif // defined (__CODE_RED)
+

bsp/lpc5410x/Libraries/Device/startup/sysinit.c

@@ -0,0 +1,78 @@
+/*
+ * @brief Common SystemInit function for LPC54xxx chips
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+
+
+ #include "chip.h"
+
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+/* Clock rate on the CLKIN pin */
+const uint32_t ExtClockIn = 0;
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+
+/* Set up and initialize hardware prior to call to main */
+void SystemInit(void)
+{
+#if defined(__CODE_RED)
+	extern void(*const g_pfnVectors[]) (void);
+	SCB->VTOR = (uint32_t) &g_pfnVectors;
+#else
+	//extern void *__Vectors;
+	//SCB->VTOR = (uint32_t) &isr_vector;
+	SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
+#endif
+
+#if defined(CORE_M4)
+#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
+	fpuInit();
+#endif
+#endif
+
+#if !defined(__MULTICORE_M0SLAVE) && !defined(__MULTICORE_M4SLAVE)
+	/* Chip specific SystemInit */
+	Chip_SystemInit();
+#endif
+}

bsp/lpc5410x/Libraries/SConscript

@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/lpc5410x/Libraries/lpc_chip/SConscript

@@ -0,0 +1,75 @@
+# RT-Thread building script for component
+
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+
+
+src = Split('''
+chip_common/fpu_init.c
+chip_common/iap.c
+chip_common/ring_buffer.c
+chip_common/rtc_ut.c
+
+chip_5410x/chip_5410x.c
+chip_5410x/clock_5410x.c
+chip_5410x/crc_5410x.c
+chip_5410x/fifo_5410x.c
+chip_5410x/gpiogroup_5410x.c
+chip_5410x/gpio_5410x.c
+chip_5410x/hw_adc.c
+chip_5410x/hw_dmaaltd.c
+chip_5410x/hw_dmaaltd_rom_api.c
+chip_5410x/hw_i2cmd.c
+chip_5410x/hw_i2cmd_rom_api.c
+chip_5410x/hw_i2cmond.c
+chip_5410x/hw_i2cmond_rom_api.c
+chip_5410x/hw_i2csd.c
+chip_5410x/hw_i2csd_rom_api.c
+chip_5410x/hw_spimd.c
+chip_5410x/hw_spimd_rom_api.c
+chip_5410x/hw_spisd.c
+chip_5410x/hw_spisd_rom_api.c
+chip_5410x/hw_uart.c
+chip_5410x/iocon_5410x.c
+chip_5410x/pinint_5410x.c
+chip_5410x/pll_5410x.c
+chip_5410x/ritimer_5410x.c
+chip_5410x/romapi_adc.c
+chip_5410x/romapi_dma.c
+chip_5410x/romapi_i2cm.c
+chip_5410x/romapi_i2cmon.c
+chip_5410x/romapi_i2cs.c
+chip_5410x/romapi_spim.c
+chip_5410x/romapi_spis.c
+chip_5410x/romapi_uart.c
+chip_5410x/rtc_5410x.c
+chip_5410x/sct_5410x.c
+chip_5410x/sct_pwm_5410x.c
+chip_5410x/stopwatch_5410x.c
+chip_5410x/syscon_5410x.c
+chip_5410x/sysinit_5410x.c
+chip_5410x/timer_5410x.c
+chip_5410x/utick_5410x.c
+chip_5410x/wwdt_5410x.c
+''')
+
+
+#LIBS = [cwd + '/chip_5410x/power_lib/keil/lib_power']
+
+#lpc_chip\chip_5410x\power_lib\lpcxpresso
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+	LIBPATH = [cwd + '/chip_5410x/power_lib/lpcxpresso']
+	LIBS = ['libpower']
+elif rtconfig.CROSS_TOOL == 'keil':
+	LIBPATH = [cwd + '/chip_5410x/power_lib/keil']
+	LIBS = ['lib_power']
+
+CPPPATH = [cwd + '/chip_common',cwd + '/chip_5410x',cwd + '/chip_5410x/config']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH,LIBS = LIBS,LIBPATH=LIBPATH)
+
+Return('group')

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/chip.h

@@ -0,0 +1,240 @@
+/*
+ * @brief LPC5410x basic chip inclusion file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_H_
+#define __CHIP_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef CORE_M4
+#ifndef CORE_M0PLUS
+#error "CORE_M4 or CORE_M0PLUS is not defined for the LPC5410x architecture"
+#error "CORE_M4 or CORE_M0PLUS should be defined as part of your compiler define list"
+#endif
+#endif
+
+#ifndef CHIP_LPC5410X
+#error "The LPC5410X Chip include path is used for this build, but"
+#error "CHIP_LPC5410X is not defined!"
+#endif
+
+/** @defgroup PERIPH_5410X_BASE CHIP: LPC5410x Peripheral addresses and register set declarations
+ * @ingroup CHIP_5410X_DRIVERS
+ * @{
+ */
+
+/* Main memory addresses */
+#define LPC_FLASHMEM_BASE          0x00000000UL
+#define LPC_SRAM0_BASE             0x02000000UL
+#define LPC_SRAM1_BASE             0x02010000UL
+#define LPC_ROM_BASE               0x03000000UL
+#define LPC_SRAM2_BASE             0x03400000UL
+#define LPC_GPIO_PORT_BASE         0x1C000000UL
+#define LPC_DMA_BASE               0x1C004000UL
+#define LPC_CRC_BASE               0x1C010000UL
+#define LPC_SCT_BASE               0x1C018000UL
+#define LPC_MBOX_BASE              0x1C02C000UL
+#define LPC_ADC_BASE               0x1C034000UL
+#define LPC_FIFO_BASE              0x1C038000UL
+
+/* APB0 peripheral group addresses */
+#define LPC_SYSCON_BASE            0x40000000UL
+#define LPC_TIMER2_BASE            0x40004000UL
+#define LPC_TIMER3_BASE            0x40008000UL
+#define LPC_TIMER4_BASE            0x4000C000UL
+#define LPC_GPIO_GROUPINT0_BASE    0x40010000UL
+#define LPC_GPIO_GROUPINT1_BASE    0x40014000UL
+#define LPC_PIN_INT_BASE           0x40018000UL
+#define LPC_IOCON_BASE             0x4001C000UL
+#define LPC_UTICK_BASE             0x40020000UL
+#define LPC_FMC_BASE               0x40024000UL
+#define LPC_PMU_BASE               0x4002C000UL
+#define LPC_WWDT_BASE              0x40038000UL
+#define LPC_RTC_BASE               0x4003C000UL
+
+/* APB1 peripheral group addresses */
+#define LPC_ASYNC_SYSCON_BASE      0x40080000UL
+#define LPC_USART0_BASE            0x40084000UL
+#define LPC_USART1_BASE            0x40088000UL
+#define LPC_USART2_BASE            0x4008C000UL
+#define LPC_USART3_BASE            0x40090000UL
+#define LPC_I2C0_BASE              0x40094000UL
+#define LPC_I2C1_BASE              0x40098000UL
+#define LPC_I2C2_BASE              0x4009C000UL
+#define LPC_SPI0_BASE              0x400A4000UL
+#define LPC_SPI1_BASE              0x400A8000UL
+#define LPC_TIMER0_BASE            0x400B4000UL
+#define LPC_TIMER1_BASE            0x400B8000UL
+#define LPC_INMUX_BASE             0x40050000UL
+#define LPC_RITIMER_BASE           0x40070000UL
+#define LPC_MRT_BASE               0x40074000UL
+
+/* Main memory register access */
+#define LPC_GPIO           ((LPC_GPIO_T            *) LPC_GPIO_PORT_BASE)
+#define LPC_DMA            ((LPC_DMA_T             *) LPC_DMA_BASE)
+#define LPC_CRC            ((LPC_CRC_T             *) LPC_CRC_BASE)
+#define LPC_SCT            ((LPC_SCT_T             *) LPC_SCT_BASE)
+#define LPC_MBOX           ((LPC_MBOX_T            *) LPC_MBOX_BASE)
+#define LPC_ADC            ((LPC_ADC_T             *) LPC_ADC_BASE)
+#define LPC_FIFO           ((LPC_FIFO_T            *) LPC_FIFO_BASE)
+
+/* APB0 peripheral group register access */
+#define LPC_SYSCON         ((LPC_SYSCON_T          *) LPC_SYSCON_BASE)
+#define LPC_TIMER2         ((LPC_TIMER_T           *) LPC_TIMER2_BASE)
+#define LPC_TIMER3         ((LPC_TIMER_T           *) LPC_TIMER3_BASE)
+#define LPC_TIMER4         ((LPC_TIMER_T           *) LPC_TIMER4_BASE)
+#define LPC_GINT           ((LPC_GPIOGROUPINT_T    *) LPC_GPIO_GROUPINT0_BASE)
+#define LPC_PININT         ((LPC_PIN_INT_T         *) LPC_PIN_INT_BASE)
+#define LPC_IOCON          ((LPC_IOCON_T           *) LPC_IOCON_BASE)
+#define LPC_UTICK          ((LPC_UTICK_T           *) LPC_UTICK_BASE)
+#define LPC_WWDT           ((LPC_WWDT_T            *) LPC_WWDT_BASE)
+#define LPC_RTC            ((LPC_RTC_T             *) LPC_RTC_BASE)
+
+/* APB1 peripheral group register access */
+#define LPC_ASYNC_SYSCON   ((LPC_ASYNC_SYSCON_T    *) LPC_ASYNC_SYSCON_BASE)
+#define LPC_USART0         ((LPC_USART_T           *) LPC_USART0_BASE)
+#define LPC_USART1         ((LPC_USART_T           *) LPC_USART1_BASE)
+#define LPC_USART2         ((LPC_USART_T           *) LPC_USART2_BASE)
+#define LPC_USART3         ((LPC_USART_T           *) LPC_USART3_BASE)
+#define LPC_I2C0           ((LPC_I2C_T             *) LPC_I2C0_BASE)
+#define LPC_I2C1           ((LPC_I2C_T             *) LPC_I2C1_BASE)
+#define LPC_I2C2           ((LPC_I2C_T             *) LPC_I2C2_BASE)
+#define LPC_SCT0           LPC_SCT
+#define LPC_SPI0           ((LPC_SPI_T             *) LPC_SPI0_BASE)
+#define LPC_SPI1           ((LPC_SPI_T             *) LPC_SPI1_BASE)
+#define LPC_TIMER0         ((LPC_TIMER_T           *) LPC_TIMER0_BASE)
+#define LPC_TIMER1         ((LPC_TIMER_T           *) LPC_TIMER1_BASE)
+#define LPC_INMUX          ((LPC_INMUX_T           *) LPC_INMUX_BASE)
+#define LPC_RITIMER        ((LPC_RITIMER_T         *) LPC_RITIMER_BASE)
+#define LPC_MRT            ((LPC_MRT_T             *) LPC_MRT_BASE)
+#define LPC_PMU            ((LPC_PMU_T             *) LPC_PMU_BASE)
+
+/**
+ * @}
+ */
+
+/** @ingroup CHIP_5410X_DRIVER_OPTIONS
+ * @{
+ */
+
+/**
+ * @brief	Clock rate on the CLKIN pin
+ * This value is defined externally to the chip layer and contains
+ * the value in Hz for the CLKIN pin for the board. If this pin isn't used,
+ * this rate can be 0.
+ */
+extern const uint32_t ExtClockIn;
+
+/**
+ * @}
+ */
+
+/* 如果不用莫个文件，去掉相应的文件，可以 */
+
+/* Include order is important! */
+#include "romapi_5410x.h"
+#include "syscon_5410x.h"
+#include "cpuctrl_5410x.h"
+#include "clock_5410x.h"
+#include "pmu_5410x.h"
+#include "iocon_5410x.h"
+#include "pinint_5410x.h"
+#include "inmux_5410x.h"
+#include "crc_5410x.h"
+#include "gpio_5410x.h"
+#include "fifo_5410x.h"
+#include "mrt_5410x.h"
+#include "wwdt_5410x.h"
+#include "sct_5410x.h"
+#include "sct_pwm_5410x.h"
+#include "rtc_5410x.h"
+#include "timer_5410x.h"
+#include "ritimer_5410x.h"
+#include "utick_5410x.h"
+#include "gpiogroup_5410x.h"
+#include "mailbox_5410x.h"
+#include "fpu_init.h"
+#include "power_lib_5410x.h"
+
+/** @defgroup SUPPORT_5410X_FUNC CHIP: LPC5410x support functions
+ * @ingroup CHIP_5410X_DRIVERS
+ * @{
+ */
+
+/**
+ * @brief	Current system clock rate, mainly used for peripherals in SYSCON
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief	Update system core and ASYNC syscon clock rate, should be called if the
+ *			system has a clock rate change
+ * @return	None
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief	Set up and initialize hardware prior to call to main()
+ * @return	None
+ * @note	Chip_SystemInit() is called prior to the application and sets up
+ * system clocking prior to the application starting.
+ */
+void Chip_SystemInit(void);
+
+/**
+ * @brief	Clock and PLL initialization based on the internal oscillator
+ * @param	iFreq	: Rate (in Hz) to set the main system clock to
+ * @return	None
+ */
+void Chip_SetupIrcClocking(uint32_t iFreq);
+
+/**
+ * @brief	Clock and PLL initialization based on the external clock input
+ * @param	iFreq	: Rate (in Hz) to set the main system clock to
+ * @return	None
+ */
+void Chip_SetupExtInClocking(uint32_t iFreq);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/chip_5410x.c

@@ -0,0 +1,59 @@
+/*
+ * @brief LPC5410X Miscellaneous chip specific functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/* System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock;
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Update system core clock rate, should be called if the system has
+   a clock rate change */
+void SystemCoreClockUpdate(void)
+{
+	/* CPU core speed (main clock speed adjusted by system clock divider) */
+	SystemCoreClock = Chip_Clock_GetSystemClockRate();
+}

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/clock_5410x.c

@@ -0,0 +1,393 @@
+/*
+ * @brief LPC5410X clock driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/* Return asynchronous APB clock rate (no regard for divider) */
+static uint32_t Chip_Clock_GetAsyncSyscon_ClockRate_NoDiv(void)
+{
+	CHIP_ASYNC_SYSCON_SRC_T src;
+	uint32_t clkRate;
+
+	src = Chip_Clock_GetAsyncSysconClockSource();
+	switch (src) {
+	case SYSCON_ASYNC_IRC:
+		clkRate = Chip_Clock_GetIntOscRate();
+		break;
+
+	case SYSCON_ASYNC_WDTOSC:
+		clkRate = Chip_Clock_GetWDTOSCRate();
+		break;
+
+	case SYSCON_ASYNC_MAINCLK:
+		clkRate = Chip_Clock_GetMainClockRate();
+		break;
+
+	case SYSCON_ASYNC_CLKIN:
+		clkRate = Chip_Clock_GetSystemPLLInClockRate();
+		break;
+
+	case SYSCON_ASYNC_SYSPLLOUT:
+		clkRate = Chip_Clock_GetSystemPLLOutClockRate(false);
+		break;
+
+	default:
+		clkRate = 0;
+		break;
+	}
+
+	return clkRate;
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Return main A clock rate */
+uint32_t Chip_Clock_GetMain_A_ClockRate(void)
+{
+	uint32_t clkRate = 0;
+
+	switch (Chip_Clock_GetMain_A_ClockSource()) {
+	case SYSCON_MAIN_A_CLKSRC_IRC:
+		clkRate = Chip_Clock_GetIntOscRate();
+		break;
+
+	case SYSCON_MAIN_A_CLKSRCA_CLKIN:
+		clkRate = Chip_Clock_GetExtClockInRate();
+		break;
+
+	case SYSCON_MAIN_A_CLKSRCA_WDTOSC:
+		clkRate = Chip_Clock_GetWDTOSCRate();
+		break;
+
+	default:
+		clkRate = 0;
+		break;
+	}
+
+	return clkRate;
+}
+
+/* Return main B clock rate */
+uint32_t Chip_Clock_GetMain_B_ClockRate(void)
+{
+	uint32_t clkRate = 0;
+
+	switch (Chip_Clock_GetMain_B_ClockSource()) {
+	case SYSCON_MAIN_B_CLKSRC_MAINCLKSELA:
+		clkRate = Chip_Clock_GetMain_A_ClockRate();
+		break;
+
+	case SYSCON_MAIN_B_CLKSRC_SYSPLLIN:
+		clkRate = Chip_Clock_GetSystemPLLInClockRate();
+		break;
+
+	case SYSCON_MAIN_B_CLKSRC_SYSPLLOUT:
+		clkRate = Chip_Clock_GetSystemPLLOutClockRate(false);
+		break;
+
+	case SYSCON_MAIN_B_CLKSRC_RTC:
+		clkRate = Chip_Clock_GetRTCOscRate();
+		break;
+	}
+
+	return clkRate;
+}
+
+/* Set CLKOUT clock source and divider */
+void Chip_Clock_SetCLKOUTSource(CHIP_SYSCON_CLKOUTSRC_T src, uint32_t div)
+{
+	uint32_t srcClk = (uint32_t) src;
+
+	/* Use a clock A source? */
+	if (src >= SYSCON_CLKOUTSRCA_OUTPUT) {
+		/* Not using a CLKOUT A source */
+		LPC_SYSCON->CLKOUTSELB = srcClk - SYSCON_CLKOUTSRCA_OUTPUT;
+	}
+	else {
+		/* Using a clock A source, select A and then switch B to A */
+		LPC_SYSCON->CLKOUTSELA = srcClk;
+		LPC_SYSCON->CLKOUTSELB = 0;
+	}
+
+	LPC_SYSCON->CLKOUTDIV = div;
+}
+
+/* Enable a system or peripheral clock */
+void Chip_Clock_EnablePeriphClock(CHIP_SYSCON_CLOCK_T clk)
+{
+	uint32_t clkEnab = (uint32_t) clk;
+
+	if (clkEnab >= 128) {
+		clkEnab = clkEnab - 128;
+
+		LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1 << clkEnab);
+	}
+	else if (clkEnab >= 32) {
+		LPC_SYSCON->AHBCLKCTRLSET[1] = (1 << (clkEnab - 32));
+	}
+	else {
+		LPC_SYSCON->AHBCLKCTRLSET[0] = (1 << clkEnab);
+	}
+}
+
+/* Disable a system or peripheral clock */
+void Chip_Clock_DisablePeriphClock(CHIP_SYSCON_CLOCK_T clk)
+{
+	uint32_t clkEnab = (uint32_t) clk;
+
+	if (clkEnab >= 128) {
+		clkEnab = clkEnab - 128;
+
+		LPC_ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1 << clkEnab);
+	}
+	else if (clkEnab >= 32) {
+		LPC_SYSCON->AHBCLKCTRLCLR[1] = (1 << (clkEnab - 32));
+	}
+	else {
+		LPC_SYSCON->AHBCLKCTRLCLR[0] = (1 << clkEnab);
+	}
+}
+
+/* Returns the system tick rate as used with the system tick divider */
+uint32_t Chip_Clock_GetSysTickClockRate(void)
+{
+	uint32_t sysRate, div;
+
+	div = LPC_SYSCON->SYSTICKCLKDIV;
+
+	/* If divider is 0, the system tick clock is disabled */
+	if (div == 0) {
+		sysRate = 0;
+	}
+	else {
+		sysRate = Chip_Clock_GetSystemClockRate() / LPC_SYSCON->SYSTICKCLKDIV;
+	}
+
+	return sysRate;
+}
+
+/* Return ADC clock rate */
+uint32_t Chip_Clock_GetADCClockRate(void)
+{
+	uint32_t div, clkRate = 0;
+
+	div = Chip_Clock_GetADCClockDiv();
+
+	/* ADC clock only enabled if div>0 */
+	if (div > 0) {
+		switch (Chip_Clock_GetADCClockSource()) {
+		case SYSCON_ADCCLKSELSRC_MAINCLK:
+			clkRate = Chip_Clock_GetMainClockRate();
+			break;
+
+		case SYSCON_ADCCLKSELSRC_SYSPLLOUT:
+			clkRate = Chip_Clock_GetSystemPLLOutClockRate(false);
+			break;
+
+		case SYSCON_ADCCLKSELSRC_IRC:
+			clkRate = Chip_Clock_GetIntOscRate();
+			break;
+		}
+
+		clkRate = clkRate / div;
+	}
+
+	return clkRate;
+}
+
+/* Set asynchronous APB clock source */
+void Chip_Clock_SetAsyncSysconClockSource(CHIP_ASYNC_SYSCON_SRC_T src)
+{
+	uint32_t clkSrc = (uint32_t) src;
+
+	if (src >= SYSCON_ASYNC_MAINCLK) {
+		LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB = (clkSrc - 4);
+	}
+	else {
+		LPC_ASYNC_SYSCON->ASYNCAPBCLKSELA = clkSrc;
+		LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB = 3;
+	}
+}
+
+/* Get asynchronous APB clock source */
+CHIP_ASYNC_SYSCON_SRC_T Chip_Clock_GetAsyncSysconClockSource(void)
+{
+	uint32_t clkSrc;
+
+	if (LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB == 3) {
+		clkSrc = LPC_ASYNC_SYSCON->ASYNCAPBCLKSELA;
+	}
+	else {
+		clkSrc = 4 + LPC_ASYNC_SYSCON->ASYNCAPBCLKSELB;
+	}
+
+	return (CHIP_ASYNC_SYSCON_SRC_T) clkSrc;
+}
+
+/* Return asynchronous APB clock rate */
+uint32_t Chip_Clock_GetAsyncSyscon_ClockRate(void)
+{
+	uint32_t clkRate, div;
+
+	clkRate = Chip_Clock_GetAsyncSyscon_ClockRate_NoDiv();
+	div = LPC_ASYNC_SYSCON->ASYNCCLKDIV;
+	if (div == 0) {
+		/* Clock is disabled */
+		return 0;
+	}
+
+	return clkRate / div;
+}
+
+/* Set main system clock source */
+void Chip_Clock_SetMainClockSource(CHIP_SYSCON_MAINCLKSRC_T src)
+{
+	uint32_t clkSrc = (uint32_t) src;
+
+	if (clkSrc >= 4) {
+		/* Main B source only, not using main A */
+		Chip_Clock_SetMain_B_ClockSource((CHIP_SYSCON_MAIN_B_CLKSRC_T) (clkSrc - 4));
+	}
+	else {
+		/* Select main A clock source and set main B source to use main A */
+		Chip_Clock_SetMain_A_ClockSource((CHIP_SYSCON_MAIN_A_CLKSRC_T) clkSrc);
+		Chip_Clock_SetMain_B_ClockSource(SYSCON_MAIN_B_CLKSRC_MAINCLKSELA);
+	}
+}
+
+/* Returns the main clock source */
+CHIP_SYSCON_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
+{
+	CHIP_SYSCON_MAIN_B_CLKSRC_T srcB;
+	uint32_t clkSrc;
+
+	/* Get main B clock source */
+	srcB = Chip_Clock_GetMain_B_ClockSource();
+	if (srcB == SYSCON_MAIN_B_CLKSRC_MAINCLKSELA) {
+		/* Using source A, so return source A */
+		clkSrc = (uint32_t) Chip_Clock_GetMain_A_ClockSource();
+	}
+	else {
+		/* Using source B */
+		clkSrc = 4 + (uint32_t) srcB;
+	}
+
+	return (CHIP_SYSCON_MAINCLKSRC_T) clkSrc;
+}
+
+/* Return main clock rate */
+uint32_t Chip_Clock_GetMainClockRate(void)
+{
+	uint32_t clkRate;
+
+	if (Chip_Clock_GetMain_B_ClockSource() == SYSCON_MAIN_B_CLKSRC_MAINCLKSELA) {
+		/* Return main A clock rate */
+		clkRate = Chip_Clock_GetMain_A_ClockRate();
+	}
+	else {
+		/* Return main B clock rate */
+		clkRate = Chip_Clock_GetMain_B_ClockRate();
+	}
+
+	return clkRate;
+}
+
+/* Return system clock rate */
+uint32_t Chip_Clock_GetSystemClockRate(void)
+{
+	/* No point in checking for divide by 0 */
+	return Chip_Clock_GetMainClockRate() / LPC_SYSCON->AHBCLKDIV;
+}
+
+/* Get UART base rate */
+uint32_t Chip_Clock_GetUARTBaseClockRate(void)
+{
+	uint64_t inclk;
+
+	/* Get clock rate into FRG */
+	inclk = (uint64_t) Chip_Clock_GetAsyncSyscon_ClockRate();
+
+	if (inclk != 0) {
+		uint32_t mult, divmult;
+
+		divmult = LPC_ASYNC_SYSCON->FRGCTRL & 0xFF;
+		if ((divmult & 0xFF) == 0xFF) {
+			/* Fractional part is enabled, get multiplier */
+			mult = (divmult >> 8) & 0xFF;
+
+			/* Get fractional error */
+			inclk = (inclk * 256) / (uint64_t) (256 + mult);
+		}
+	}
+
+	return (uint32_t) inclk;
+}
+
+/* Set UART base rate */
+uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate)
+{
+	uint32_t div, inclk, err;
+	uint64_t uart_fra_multiplier;
+
+	/* Input clock into FRG block is the main system cloock */
+	inclk = Chip_Clock_GetAsyncSyscon_ClockRate();
+
+	/* Get integer divider for coarse rate */
+	div = inclk / rate;
+	if (div == 0) {
+		div = 1;
+	}
+
+	/* Enable FRG clock */
+	Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_FRG);
+
+	err = inclk - (rate * div);
+	uart_fra_multiplier = (((uint64_t) err + (uint64_t) rate) * 256) / (uint64_t) (rate * div);
+
+	/* Enable fractional divider and set multiplier */
+	LPC_ASYNC_SYSCON->FRGCTRL = 0xFF | (uart_fra_multiplier << 8);
+
+	return Chip_Clock_GetUARTBaseClockRate();
+}

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/clock_5410x.h

@@ -0,0 +1,473 @@
+/*
+ * @brief LPC5410X clock driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CLOCK_5410X_H_
+#define __CLOCK_5410X_H_
+
+#include "pll_5410x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CLOCK_5410X CHIP: LPC5410X Clock Driver
+ * @ingroup CHIP_5410X_DRIVERS
+ * @{
+ */
+
+/* Internal oscillator frequency */
+#define SYSCON_IRC_FREQ     (12000000)
+#define SYSCON_WDTOSC_FREQ  (500000)
+#define SYSCON_RTC_FREQ     (32768)
+
+/**
+ * @brief	Returns the internal oscillator (IRC) clock rate
+ * @return	internal oscillator (IRC) clock rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
+{
+	return SYSCON_IRC_FREQ;
+}
+
+/**
+ * @brief	Returns the external clock input rate
+ * @return	External clock input rate
+ */
+STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void)
+{
+	return ExtClockIn;
+}
+
+/**
+ * @brief	Returns the RTC clock rate
+ * @return	RTC oscillator clock rate in Hz
+ */
+STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
+{
+	return SYSCON_RTC_FREQ;
+}
+
+/**
+ * @brief	Return estimated watchdog oscillator rate
+ * @return	Estimated watchdog oscillator rate
+ * @note	This rate is accurate to plus or minus 40%.
+ */
+STATIC INLINE uint32_t Chip_Clock_GetWDTOSCRate(void)
+{
+	return SYSCON_WDTOSC_FREQ;
+}
+
+/**
+ * Clock source selections for only the main A system clock. The main A system
+ * clock is used as an input into the main B system clock selector. Main clock A
+ * only needs to be setup if the main clock A input is used in the main clock
+ * system selector.
+ */
+typedef enum {
+	SYSCON_MAIN_A_CLKSRC_IRC = 0,		/*!< Internal oscillator */
+	SYSCON_MAIN_A_CLKSRCA_CLKIN,		/*!< Crystal (main) oscillator in */
+	SYSCON_MAIN_A_CLKSRCA_WDTOSC,		/*!< Watchdog oscillator rate */
+} CHIP_SYSCON_MAIN_A_CLKSRC_T;
+
+/**
+ * @brief	Set main A system clock source
+ * @param	src	: Clock source for main A
+ * @return	Nothing
+ * @note	This function only needs to be setup if main clock A will be
+ * selected in the Chip_Clock_GetMain_B_ClockRate() function.
+ */
+STATIC INLINE void Chip_Clock_SetMain_A_ClockSource(CHIP_SYSCON_MAIN_A_CLKSRC_T src)
+{
+	LPC_SYSCON->MAINCLKSELA = (uint32_t) src;
+}
+
+/**
+ * @brief   Returns the main A clock source
+ * @return	Returns which clock is used for the main A
+ */
+STATIC INLINE CHIP_SYSCON_MAIN_A_CLKSRC_T Chip_Clock_GetMain_A_ClockSource(void)
+{
+	return (CHIP_SYSCON_MAIN_A_CLKSRC_T) (LPC_SYSCON->MAINCLKSELA);
+}
+
+/**
+ * @brief	Return main A clock rate
+ * @return	main A clock rate in Hz
+ */
+uint32_t Chip_Clock_GetMain_A_ClockRate(void);
+
+/**
+ * Clock sources for only main B system clock
+ */
+typedef enum {
+	SYSCON_MAIN_B_CLKSRC_MAINCLKSELA = 0,	/*!< main clock A */
+	SYSCON_MAIN_B_CLKSRC_SYSPLLIN,			/*!< System PLL input */
+	SYSCON_MAIN_B_CLKSRC_SYSPLLOUT,			/*!< System PLL output */
+	SYSCON_MAIN_B_CLKSRC_RTC,				/*!< RTC oscillator 32KHz output */
+} CHIP_SYSCON_MAIN_B_CLKSRC_T;
+
+/**
+ * @brief	Set main B system clock source
+ * @param	src	: Clock source for main B
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_SetMain_B_ClockSource(CHIP_SYSCON_MAIN_B_CLKSRC_T src)
+{
+	LPC_SYSCON->MAINCLKSELB = (uint32_t) src;
+}
+
+/**
+ * @brief   Returns the main B clock source
+ * @return	Returns which clock is used for the main B
+ */
+STATIC INLINE CHIP_SYSCON_MAIN_B_CLKSRC_T Chip_Clock_GetMain_B_ClockSource(void)
+{
+	return (CHIP_SYSCON_MAIN_B_CLKSRC_T) (LPC_SYSCON->MAINCLKSELB);
+}
+
+/**
+ * @brief	Return main B clock rate
+ * @return	main B clock rate
+ */
+uint32_t Chip_Clock_GetMain_B_ClockRate(void);
+
+/**
+ * Clock sources for CLKOUT
+ */
+typedef enum {
+	SYSCON_CLKOUTSRC_MAINCLK = 0,		/*!< Main system clock for CLKOUT */
+	SYSCON_CLKOUTSRC_CLKIN,				/*!< CLKIN for CLKOUT */
+	SYSCON_CLKOUTSRC_WDTOSC,			/*!< Watchdog oscillator for CLKOUT */
+	SYSCON_CLKOUTSRC_IRC,				/*!< Internal oscillator for CLKOUT */
+	SYSCON_CLKOUTSRCA_OUTPUT,			/*!< clkoutA output route to input of clkoutB */
+	SYSCON_CLKOUTSRC_RTC = 7			/*!< RTC oscillator 32KHz for CLKOUT */
+} CHIP_SYSCON_CLKOUTSRC_T;
+
+/**
+ * @brief	Set CLKOUT clock source and divider
+ * @param	src	: Clock source for CLKOUT
+ * @param	div	: divider for CLKOUT clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
+ * rate is the clock source divided by the divider. This function will
+ * also toggle the clock source update register to update the clock
+ * source.
+ */
+void Chip_Clock_SetCLKOUTSource(CHIP_SYSCON_CLKOUTSRC_T src, uint32_t div);
+
+/**
+ * System and peripheral clocks enum
+ */
+typedef enum CHIP_SYSCON_CLOCK {
+	/* Peripheral clock enables for SYSAHBCLKCTRL0 */
+	SYSCON_CLOCK_ROM = 1,				/*!< ROM clock */
+	SYSCON_CLOCK_SRAM1 = 3,				/*!< SRAM1 clock */
+	SYSCON_CLOCK_SRAM2,					/*!< SRAM2 clock */
+	SYSCON_CLOCK_FLASH = 7,				/*!< FLASH controller clock */
+	SYSCON_CLOCK_FMC,					/*!< FMC clock */
+	SYSCON_CLOCK_INPUTMUX = 11,			/*!< Input mux clock */
+	SYSCON_CLOCK_IOCON = 13,			/*!< IOCON clock */
+	SYSCON_CLOCK_GPIO0,					/*!< GPIO0 clock */
+	SYSCON_CLOCK_GPIO1,					/*!< GPIO1 clock */
+	SYSCON_CLOCK_PINT = 18,				/*!< PININT clock */
+	SYSCON_CLOCK_GINT,					/*!< grouped pin interrupt block clock */
+	SYSCON_CLOCK_DMA,					/*!< DMA clock */
+	SYSCON_CLOCK_CRC,					/*!< CRC clock */
+	SYSCON_CLOCK_WWDT,					/*!< WDT clock */
+	SYSCON_CLOCK_RTC,					/*!< RTC clock */
+	SYSCON_CLOCK_MAILBOX = 26,			/*!< Mailbox clock */
+	SYSCON_CLOCK_ADC0,					/*!< ADC0 clock */
+
+	/* Peripheral clock enables for SYSAHBCLKCTRL1 */
+	SYSCON_CLOCK_MRT = 32,				/*!< multi-rate timer clock */
+	SYSCON_CLOCK_RIT,					/*!< Repetitive interval timer clock */
+	SYSCON_CLOCK_SCT0,					/*!< SCT0 clock */
+	SYSCON_CLOCK_FIFO = 32 + 9,			/*!< System FIFO clock */
+	SYSCON_CLOCK_UTICK,					/*!< UTICK clock */
+	SYSCON_CLOCK_TIMER2 = 32 + 22,		/*!< TIMER2 clock */
+	SYSCON_CLOCK_TIMER3 = 32 + 26,		/*!< TIMER3 clock */
+	SYSCON_CLOCK_TIMER4,				/*!< TIMER4 clock */
+
+	/* Peripheral clock enables for ASYNCAPBCLKCTRLCLR */
+	SYSCON_CLOCK_USART0 = 128 + 1,		/*!< USART0 clock */
+	SYSCON_CLOCK_USART1,				/*!< USART1 clock */
+	SYSCON_CLOCK_USART2,				/*!< USART2 clock */
+	SYSCON_CLOCK_USART3,				/*!< USART3 clock */
+	SYSCON_CLOCK_I2C0,					/*!< I2C0  clock */
+	SYSCON_CLOCK_I2C1,					/*!< I2C1  clock */
+	SYSCON_CLOCK_I2C2,					/*!< I2C2  clock */
+	SYSCON_CLOCK_SPI0 = 128 + 9,		/*!< SPI0  clock */
+	SYSCON_CLOCK_SPI1,					/*!< SPI1  clock */
+	SYSCON_CLOCK_TIMER0 = 128 + 13,		/*!< TIMER0 clock */
+	SYSCON_CLOCK_TIMER1,				/*!< TIMER1 clock */
+	SYSCON_CLOCK_FRG					/*!< FRG clock */
+} CHIP_SYSCON_CLOCK_T;
+
+/**
+ * @brief	Enable a system or peripheral clock
+ * @param	clk	: Clock to enable
+ * @return	Nothing
+ */
+void Chip_Clock_EnablePeriphClock(CHIP_SYSCON_CLOCK_T clk);
+
+/**
+ * @brief	Disable a system or peripheral clock
+ * @param	clk	: Clock to disable
+ * @return	Nothing
+ */
+void Chip_Clock_DisablePeriphClock(CHIP_SYSCON_CLOCK_T clk);
+
+/**
+ * @brief	Set system tick clock divider (external CLKIN as SYSTICK reference only)
+ * @param	div	: divider for system clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The system tick
+ * rate is the external CLKIN rate divided by this value. The extern CLKIN pin
+ * signal, divided by the SYSTICKCLKDIV divider, is selected by clearing
+ * CLKSOURCE bit 2 in the System Tick CSR register. The core clock must be at least
+ * 2.5 times faster than the reference system tick clock otherwise the count
+ * values are unpredictable.
+ */
+STATIC INLINE void Chip_Clock_SetSysTickClockDiv(uint32_t div)
+{
+	LPC_SYSCON->SYSTICKCLKDIV = div;
+}
+
+/**
+ * @brief	Returns system tick clock divider
+ * @return	system tick clock divider
+ */
+STATIC INLINE uint32_t Chip_Clock_GetSysTickClockDiv(void)
+{
+	return LPC_SYSCON->SYSTICKCLKDIV;
+}
+
+/**
+ * @brief	Returns the system tick rate as used with the system tick divider
+ * @return	the system tick rate
+ */
+uint32_t Chip_Clock_GetSysTickClockRate(void);
+
+/**
+ * @brief	Set system clock divider
+ * @param	div	: divider for system clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The system clock
+ * rate is the main system clock divided by this value.
+ */
+STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
+{
+	LPC_SYSCON->AHBCLKDIV = div;
+}
+
+/**
+ * @brief	Set system tick clock divider
+ * @param	div	: divider for system clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The system tick
+ * rate is the main system clock divided by this value. Use caution when using
+ * the CMSIS SysTick_Config() functions as they typically use SystemCoreClock
+ * for setup.
+ */
+STATIC INLINE void Chip_Clock_SetADCClockDiv(uint32_t div)
+{
+	LPC_SYSCON->ADCCLKDIV = div;
+}
+
+/**
+ * @brief	Returns ADC clock divider
+ * @return	ADC clock divider, 0 = disabled
+ */
+STATIC INLINE uint32_t Chip_Clock_GetADCClockDiv(void)
+{
+	return LPC_SYSCON->ADCCLKDIV;
+}
+
+/**
+ * Clock sources for ADC clock source select
+ */
+typedef enum {
+	SYSCON_ADCCLKSELSRC_MAINCLK = 0,		/*!< Main clock */
+	SYSCON_ADCCLKSELSRC_SYSPLLOUT,			/*!< PLL output */
+	SYSCON_ADCCLKSELSRC_IRC					/*!< Internal oscillator */
+} CHIP_SYSCON_ADCCLKSELSRC_T;
+
+/**
+ * @brief	Set the ADC clock source
+ * @param	src	: ADC clock source
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_SetADCClockSource(CHIP_SYSCON_ADCCLKSELSRC_T src)
+{
+	LPC_SYSCON->ADCCLKSEL = (uint32_t) src;
+}
+
+/**
+ * @brief   Returns the ADC clock source
+ * @return	Returns which clock is used for the ADC clock source
+ */
+STATIC INLINE CHIP_SYSCON_ADCCLKSELSRC_T Chip_Clock_GetADCClockSource(void)
+{
+	return (CHIP_SYSCON_ADCCLKSELSRC_T) (LPC_SYSCON->ADCCLKSEL);
+}
+
+/**
+ * @brief	Return ADC clock rate
+ * @return	ADC clock rate
+ */
+uint32_t Chip_Clock_GetADCClockRate(void);
+
+/**
+ * @brief	Enable the RTC 32KHz output
+ * @return	Nothing
+ * @note	This clock can be used for the main clock directly, but
+ *			do not use this clock with the system PLL.
+ */
+STATIC INLINE void Chip_Clock_EnableRTCOsc(void)
+{
+	LPC_SYSCON->RTCOSCCTRL  = 1;
+}
+
+/**
+ * @brief	Disable the RTC 32KHz output
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_Clock_DisableRTCOsc(void)
+{
+	LPC_SYSCON->RTCOSCCTRL  = 0;
+}
+
+/**
+ * Clock source selections for the asynchronous APB clock
+ */
+typedef enum {
+	SYSCON_ASYNC_IRC = 0,			/*!< IRC input */
+	SYSCON_ASYNC_WDTOSC,			/*!< Watchdog oscillator */
+	SYSCON_ASYNC_MAINCLK = 4,		/*!< Main clock */
+	SYSCON_ASYNC_CLKIN,				/*!< external CLK input */
+	SYSCON_ASYNC_SYSPLLOUT			/*!< System PLL output */
+} CHIP_ASYNC_SYSCON_SRC_T;
+
+/**
+ * @brief	Set asynchronous APB clock source
+ * @param	src	: Clock source for asynchronous APB clock
+ * @return	Nothing
+ */
+void Chip_Clock_SetAsyncSysconClockSource(CHIP_ASYNC_SYSCON_SRC_T src);
+
+/**
+ * @brief	Get asynchronous APB clock source
+ * @return	Clock source for asynchronous APB clock
+ */
+CHIP_ASYNC_SYSCON_SRC_T Chip_Clock_GetAsyncSysconClockSource(void);
+
+/**
+ * @brief	Return asynchronous APB clock rate
+ * @return	Asynchronous APB clock rate
+ * @note	Includes adjustments by Async clock divider (ASYNCCLKDIV).
+ */
+uint32_t Chip_Clock_GetAsyncSyscon_ClockRate(void);
+
+/**
+ * @brief	Set UART divider clock
+ * @param	div	: divider for UART clock
+ * @return	Nothing
+ * @note	Use 0 to disable, or a divider value of 1 to 255. The UART clock
+ * rate is the main system clock divided by this value.
+ */
+STATIC INLINE void Chip_Clock_SetAsyncSysconClockDiv(uint32_t div)
+{
+	LPC_ASYNC_SYSCON->ASYNCCLKDIV = div;
+}
+
+/**
+ * Clock sources for main system clock. This is a mix of both main clock A
+ * and B selections.
+ */
+typedef enum {
+	SYSCON_MAINCLKSRC_IRC = 0,				/*!< Internal oscillator */
+	SYSCON_MAINCLKSRC_CLKIN,				/*!< Crystal (main) oscillator in */
+	SYSCON_MAINCLKSRC_WDTOSC,				/*!< Watchdog oscillator rate */
+	SYSCON_MAINCLKSRC_PLLIN = 5,			/*!< System PLL input */
+	SYSCON_MAINCLKSRC_PLLOUT,				/*!< System PLL output */
+	SYSCON_MAINCLKSRC_RTC					/*!< RTC oscillator 32KHz output */
+} CHIP_SYSCON_MAINCLKSRC_T;
+
+/**
+ * @brief	Set main system clock source
+ * @param	src	: Clock source for main system
+ * @return	Nothing
+ */
+void Chip_Clock_SetMainClockSource(CHIP_SYSCON_MAINCLKSRC_T src);
+
+/**
+ * @brief	Get main system clock source
+ * @return	Clock source for main system
+ * @note
+ */
+CHIP_SYSCON_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void);
+
+/**
+ * @brief	Return main clock rate
+ * @return	main clock rate
+ */
+uint32_t Chip_Clock_GetMainClockRate(void);
+
+/**
+ * @brief	Return system clock rate
+ * @return	system clock rate
+ * @note	This is the main clock rate divided by AHBCLKDIV.
+ */
+uint32_t Chip_Clock_GetSystemClockRate(void);
+
+/**
+ * @brief	Get UART base clock rate
+ * @return	UART base clock rate
+ */
+uint32_t Chip_Clock_GetUARTBaseClockRate(void);
+
+/**
+ * @brief	Get UART base clock rate using FRG
+ * @return	Actual UART base clock rate
+ * @note	It's recommended to set a base rate at least 16x the
+ * expected maximum UART transfer bit rate.
+ */
+uint32_t Chip_Clock_SetUARTBaseClockRate(uint32_t rate);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CLOCK_5410X_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/cmd.bat

@@ -0,0 +1 @@
+dir *.c >C:\Users\Administrator\Desktop\c.txt

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/cmsis.h

@@ -0,0 +1,56 @@
+/*
+ * @brief LPC5410x selective CMSIS inclusion file
+ *
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_H_
+#define __CMSIS_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Select correct CMSIS include file based on CORE_* definition */
+#if defined(CORE_M4)
+#include "cmsis_5410x.h"
+typedef LPC5410X_IRQn_Type IRQn_Type;
+#include "core_cm4.h"					/*!< Cortex-M4 processor and core peripherals      */
+#elif defined(CORE_M0PLUS)
+#include "cmsis_5410x_m0.h"
+typedef LPC5410X_M0_IRQn_Type IRQn_Type;
+#include "core_cm0plus.h"				/*!< Cortex-M0 Plus processor and core peripherals  */
+#else
+#error "No CORE_* definition is defined"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/config.xml

@@ -0,0 +1,48 @@
+<LPCOpenCfg>
+	<symbol options="default" name="varChipConfigDir" value="${varChipLibSrcDir}/config"/>
+	<symbol options="default" name="varCPUCore" value="m4"/>
+	<symbol options="default" name="varPMULibName_m4" value="power"/>
+	<symbol options="default" name="varPMULibName_m0plus" value="power_m0"/>
+	<symbol name="varExampleName"     value="${prjCurrClassName}_${prjCurrExampleName}"/> <!-- FIXME: Need to append class name -->
+	<symbol name="varSysinitDir" value="${prjDestToRoot}/${prjExampleBaseDir}/startup"/>
+
+	<module name="core_${varCPUCore}"/>
+	<template section="filelist" name="${varChipLibName}" tool="xpresso">
+		<import src="${varChipConfigDir}" dest="inc">
+			<include>*.h</include>
+		</import>
+	</template>
+	<template section="import" name="${varChipLibName}_inc1" tool="xpresso">
+		<copy>../chip_common/error.h</copy>
+		<copy>../chip_common/iap.h</copy>
+		<copy>../chip_common/packing.h</copy>
+		<copy>../chip_common/rtc_ut.h</copy>
+		<copy>../chip_common/stopwatch.h</copy>
+	</template>
+	<template section="import" name="${varChipLibName}_src1" tool="xpresso">
+		<copy>../chip_common/iap.c</copy>
+		<copy>../chip_common/rtc_ut.c</copy>
+	</template>
+	<template section="filelist" name="${varChipLibName}" tool="xpresso">
+		<import src="${varChipLibSrcDir}/power_lib/lpcxpresso" dest="libs">
+			<copy>lib${varPMULibName_${varCPUCore}}.a</copy>
+		</import>
+	</template>
+	<template section="import" name="${varExampleEnable}_startup" tool="xpresso">
+		<copy>crp.c</copy>
+	</template>
+	<template section="cfglist" tool="xpresso" name="${varExampleEnable}">
+		<setting id="linker.crp">
+			<value>true</value>
+		</setting>
+	</template>
+	<template tool="xpresso" section="cfglist" name="${varExampleEnable}">
+		<setting id="linker.paths">
+			<value>${workspace_loc:/${varChipLibName}/libs}</value>
+		</setting>
+		<!-- FIXME: These must be single -->
+		<setting id="linker.libs">
+			<value>${varPMULibName_${varCPUCore}}</value>
+		</setting>
+	</template>
+</LPCOpenCfg>

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/config/cmsis_5410x.h

@@ -0,0 +1,172 @@
+/*
+ * @brief Basic CMSIS include file for LPC5410x M4 core
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_5410X_H_
+#define __CMSIS_5410X_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CMSIS_5410X_M4 CHIP: LPC5410X M4 core CMSIS include file
+ * @ingroup CHIP_5410X_CMSIS_DRIVERS
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+// Kill warning "#pragma push with no matching #pragma pop"
+  #pragma diag_suppress 2525
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+//  #pragma push // FIXME not usable for IAR
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+#if !defined(CORE_M4)
+#error "CORE_M4 is not defined"
+#endif
+
+/** @defgroup CMSIS_5410X_M4_IRQ CHIP_5410X: LPC5410X M4 core peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
+	Reset_IRQn                    = -15,	/*!< 1  Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn           = -14,	/*!< 2  Non maskable Interrupt, cannot be stopped or preempted */
+	HardFault_IRQn                = -13,	/*!< 3  Hard Fault, all classes of Fault */
+	MemoryManagement_IRQn         = -12,	/*!< 4  Memory Management, MPU mismatch, including Access Violation and No Match */
+	BusFault_IRQn                 = -11,	/*!< 5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+	UsageFault_IRQn               = -10,	/*!< 6  Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+	SVCall_IRQn                   =  -5,	/*!< 11  System Service Call via SVC instruction */
+	DebugMonitor_IRQn             =  -4,	/*!< 12  Debug Monitor                    */
+	PendSV_IRQn                   =  -2,	/*!< 14  Pendable request for system service */
+	SysTick_IRQn                  =  -1,	/*!< 15  System Tick Timer                */
+
+	/******  LPC5410X Specific Interrupt Numbers ********************************************************/
+	WDT_IRQn                      = 0,		/*!< WWDT                                             */
+	BOD_IRQn                      = 1,		/*!< BOD                                              */
+	Reserved2_IRQn                = 2,		/*!< Reserved Interrupt                               */
+	DMA_IRQn                      = 3,		/*!< DMA                                              */
+	GINT0_IRQn                    = 4,		/*!< GINT0                                            */
+	PIN_INT0_IRQn                 = 5,		/*!< PININT0                                          */
+	PIN_INT1_IRQn                 = 6,		/*!< PININT1                                          */
+	PIN_INT2_IRQn                 = 7,		/*!< PININT2                                          */
+	PIN_INT3_IRQn                 = 8,		/*!< PININT3                                          */
+	UTICK_IRQn                    = 9,		/*!< Micro-tick Timer interrupt                       */
+	MRT_IRQn                      = 10,		/*!< Multi-rate timer interrupt                       */
+	CT32B0_IRQn                   = 11,		/*!< CTMR0                                            */
+	CT32B1_IRQn                   = 12,		/*!< CTMR1                                            */
+	CT32B2_IRQn                   = 13,		/*!< CTMR2                                            */
+	CT32B3_IRQn                   = 14,		/*!< CTMR3                                            */
+	CT32B4_IRQn                   = 15,		/*!< CTMR4                                            */
+	SCT0_IRQn                     = 16,		/*!< SCT                                              */
+	UART0_IRQn                    = 17,		/*!< UART0                                            */
+	UART1_IRQn                    = 18,		/*!< UART1                                            */
+	UART2_IRQn                    = 19,		/*!< UART2                                            */
+	UART3_IRQn                    = 20,		/*!< UART3                                            */
+	I2C0_IRQn                     = 21,		/*!< I2C0                                             */
+	I2C1_IRQn                     = 22,		/*!< I2C1                                             */
+	I2C2_IRQn                     = 23,		/*!< I2C2                                             */
+	SPI0_IRQn                     = 24,		/*!< SPI0                                             */
+	SPI1_IRQn                     = 25,		/*!< SPI1                                             */
+	ADC_SEQA_IRQn                 = 26,		/*!< ADC0 sequence A completion                       */
+	ADC_SEQB_IRQn                 = 27,		/*!< ADC0 sequence B completion                       */
+	ADC_THCMP_IRQn                = 28,		/*!< ADC0 threshold compare and error                 */
+	RTC_IRQn                      = 29,		/*!< RTC alarm and wake-up interrupts                 */
+	Reserved30_IRQn               = 30,		/*!< Reserved Interrupt                               */
+	MAILBOX_IRQn                  = 31,		/*!< Mailbox                                          */
+	GINT1_IRQn                    = 32,		/*!< GINT1                                            */
+	PIN_INT4_IRQn                 = 33,		/*!< External Interrupt 4                             */
+	PIN_INT5_IRQn                 = 34,		/*!< External Interrupt 5                             */
+	PIN_INT6_IRQn                 = 35,		/*!< External Interrupt 6                             */
+	PIN_INT7_IRQn                 = 36,		/*!< External Interrupt 7                             */
+	Reserved37_IRQn               = 37,		/*!< Reserved Interrupt                               */
+	Reserved38_IRQn               = 38,		/*!< Reserved Interrupt                               */
+	Reserved39_IRQn               = 39,		/*!< Reserved Interrupt                               */
+	RIT_IRQn                      = 40,		/*!< Repetitive Interrupt Timer                       */
+	Reserved41_IRQn               = 41,		/*!< Reserved Interrupt                               */
+	Reserved42_IRQn               = 42,		/*!< Reserved Interrupt                               */
+	Reserved43_IRQn               = 43,		/*!< Reserved Interrupt                               */
+	Reserved44_IRQn               = 44,		/*!< Reserved Interrupt                               */
+} LPC5410X_IRQn_Type;
+
+/**
+ * @}
+ */
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/** @defgroup CMSIS_5410X_M4_COMMON CHIP: LPC5410X M4 core Cortex CMSIS definitions
+ * @{
+ */
+
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV                 0x0001	/*!< Cortex-M4 Core Revision                          */
+#define __MPU_PRESENT             1			/*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          3			/*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used     */
+#define __FPU_PRESENT             1
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_5410X_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/config/cmsis_5410x_m0.h

@@ -0,0 +1,155 @@
+/*
+ * @brief Basic CMSIS include file for LPC5410x M0+ core
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CMSIS_5410X_M0_H_
+#define __CMSIS_5410X_M0_H_
+
+#include "lpc_types.h"
+#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CMSIS_5410X_M0 CHIP: LPC5410X M0 core CMSIS include file
+ * @ingroup CHIP_5410X_CMSIS_DRIVERS
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+// Kill warning "#pragma push with no matching #pragma pop"
+  #pragma diag_suppress 2525
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+/* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+//  #pragma push // FIXME not usable for IAR
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+#if !defined(CORE_M0PLUS)
+#error "CORE_M0PLUS is not defined"
+#endif
+
+/** @defgroup CMSIS_5410X_M0_IRQ CHIP_5410X: LPC5410X M0 core peripheral interrupt numbers
+ * @{
+ */
+
+typedef enum {
+	/******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
+	Reset_IRQn                    = -15,	/*!< 1 Reset Vector, invoked on Power up and warm reset */
+	NonMaskableInt_IRQn           = -14,	/*!< 2 Non Maskable Interrupt                           */
+	HardFault_IRQn                = -13,	/*!< 3 Cortex-M0 Hard Fault Interrupt                   */
+	SVCall_IRQn                   = -5,		/*!< 11 Cortex-M0 SV Call Interrupt                     */
+	PendSV_IRQn                   = -2,		/*!< 14 Cortex-M0 Pend SV Interrupt                     */
+	SysTick_IRQn                  = -1,		/*!< 15 Cortex-M0 System Tick Interrupt                 */
+
+	/******  LPC5410X Specific Interrupt Numbers ********************************************************/
+	WDT_IRQn                      = 0,		/*!< WWDT                                             */
+	BOD_IRQn                      = 1,		/*!< BOD                                              */
+	Reserved2_IRQn                = 2,		/*!< Reserved Interrupt                               */
+	DMA_IRQn                      = 3,		/*!< DMA                                              */
+	GINT0_IRQn                    = 4,		/*!< GINT0                                            */
+	PIN_INT0_IRQn                 = 5,		/*!< PININT0                                          */
+	PIN_INT1_IRQn                 = 6,		/*!< PININT1                                          */
+	PIN_INT2_IRQn                 = 7,		/*!< PININT2                                          */
+	PIN_INT3_IRQn                 = 8,		/*!< PININT3                                          */
+	UTICK_IRQn                    = 9,		/*!< Micro-tick Timer interrupt                       */
+	MRT_IRQn                      = 10,		/*!< Multi-rate timer interrupt                       */
+	CT32B0_IRQn                   = 11,		/*!< CTMR0                                            */
+	CT32B1_IRQn                   = 12,		/*!< CTMR1                                            */
+	CT32B2_IRQn                   = 13,		/*!< CTMR2                                            */
+	CT32B3_IRQn                   = 14,		/*!< CTMR3                                            */
+	CT32B4_IRQn                   = 15,		/*!< CTMR4                                            */
+	SCT0_IRQn                     = 16,		/*!< SCT                                              */
+	UART0_IRQn                    = 17,		/*!< UART0                                            */
+	UART1_IRQn                    = 18,		/*!< UART1                                            */
+	UART2_IRQn                    = 19,		/*!< UART2                                            */
+	UART3_IRQn                    = 20,		/*!< UART3                                            */
+	I2C0_IRQn                     = 21,		/*!< I2C0                                             */
+	I2C1_IRQn                     = 22,		/*!< I2C1                                             */
+	I2C2_IRQn                     = 23,		/*!< I2C2                                             */
+	SPI0_IRQn                     = 24,		/*!< SPI0                                             */
+	SPI1_IRQn                     = 25,		/*!< SPI1                                             */
+	ADC_SEQA_IRQn                 = 26,		/*!< ADC0 sequence A completion                       */
+	ADC_SEQB_IRQn                 = 27,		/*!< ADC0 sequence B completion                       */
+	ADC_THCMP_IRQn                = 28,		/*!< ADC0 threshold compare and error                 */
+	RTC_IRQn                      = 29,		/*!< RTC alarm and wake-up interrupts                 */
+	Reserved30_IRQn               = 30,		/*!< Reserved Interrupt                               */
+	MAILBOX_IRQn                  = 31,		/*!< Mailbox                                          */
+} LPC5410X_M0_IRQn_Type;
+
+/**
+ * @}
+ */
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/** @defgroup CMSIS_5410X_M0_COMMON CHIP: LPC5410X M0 core Cortex CMSIS definitions
+ * @{
+ */
+
+/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
+#define __CM0PLUS_REV             0x0001	/*!< Cortex-M0PLUS Core Revision                      */
+#define __MPU_PRESENT             0			/*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          2			/*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0			/*!< Set to 1 if different SysTick Config is used     */
+#define __VTOR_PRESENT            1
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CMSIS_5410X_M0_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/config/sys_config.h

@@ -0,0 +1,43 @@
+/*
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __SYS_CONFIG_H_
+#define __SYS_CONFIG_H_
+
+/* Build for LPC5410X chip family */
+#define CHIP_LPC5410X
+
+/* Define ROMDRIVERSV2_PRESENT to enable v2 driver support in ROM. For LPC54xxx
+     devices with boot ROM version 17.2 and later, this should be defined.
+     For earlier versions, this should not be defined. If the definitions is
+     not defined, the same v2 drivers will be used, but will use a version that
+     is located in FLASH instead. */
+// #define ROMDRIVERSV2_PRESENT
+
+#endif /* __SYS_CONFIG_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/cpuctrl_5410x.h

@@ -0,0 +1,98 @@
+/*
+ * @brief LPC5410X CPU multi-core support driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CPUCTRL_5410X_H_
+#define __CPUCTRL_5410X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CPUCTRL_5410X CHIP: LPC5410X CPU multi-core support driver
+ * @ingroup CHIP_5410X_DRIVERS
+ * This driver helps with determine which MCU core the software is running,
+ * whether the MCU core is in master or slave mode, and provides functions
+ * for master and slave core control.<br>
+ *
+ * The functions for the driver are provided as part of the
+ * @ref POWER_LIBRARY_5410X library. For more information on using the
+ * LPC5410x LPCopen package with multi-core, see @ref CHIP_5410X_MULTICORE<br>.
+ * @{
+ */
+
+/**
+ * @brief	Determine which MCU this code is running on
+ * @return  true if executing on the CM4, or false if executing on the CM0+
+ */
+STATIC INLINE bool Chip_CPU_IsM4Core(void) {
+	/* M4 core is designated by values 0xC24 on bits 15..4 */
+	if (((SCB->CPUID >> 4) & 0xFFF) == 0xC24) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * @brief	Determine if this core is a slave or master
+ * @return  true if this MCU is operating as the master, or false if operating as a slave
+ */
+bool Chip_CPU_IsMasterCore(void);
+
+/**
+ * @brief	Setup M0+ boot and reset M0+ core
+ * @param	coentry		: Pointer to boot entry point for M0+ core
+ * @param	costackptr	: Pointer to where stack should be located for M0+ core
+ * @return  Nothing
+ * @note	Will setup boot stack and entry point, enable M0+ clock and then
+ * reset M0+ core.
+ */
+void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr);
+
+/**
+ * @brief	Setup M4 boot and reset M4 core
+ * @param	coentry		: Pointer to boot entry point for M4 core
+ * @param	costackptr	: Pointer to where stack should be located for M4 core
+ * @return  Nothing
+ * @note	Will setup boot stack and entry point, enable M4 clock and then
+ * reset M0+ core.
+ */
+void Chip_CPU_CM4Boot(uint32_t *coentry, uint32_t *costackptr);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CPUCTRL_5410X_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/crc_5410x.c

@@ -0,0 +1,118 @@
+/*
+ * @brief LPC5410X Cyclic Redundancy Check (CRC) Engine driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initialize CRC engine */
+void Chip_CRC_Init(void)
+{
+	Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_CRC);
+	Chip_SYSCON_PeriphReset(RESET_CRC);
+}
+
+/* De-initialize CRC engine */
+void Chip_CRC_Deinit(void)
+{
+	Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_CRC);
+}
+
+/* Sets up the CRC engine with defaults based on the polynomial to be used */
+void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly)
+{
+	switch (poly) {
+	case CRC_POLY_CRC16:
+		Chip_CRC_UseCRC16();
+		break;
+
+	case CRC_POLY_CRC32:
+		Chip_CRC_UseCRC32();
+		break;
+
+	case CRC_POLY_CCITT:
+	default:
+		Chip_CRC_UseCCITT();
+		break;
+	}
+}
+
+/* configure CRC engine and compute CCITT checksum from 8-bit data */
+uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes)
+{
+	Chip_CRC_UseCCITT();
+	while (bytes > 0) {
+		Chip_CRC_Write8(*data);
+		data++;
+		bytes--;
+	}
+
+	return Chip_CRC_Sum();
+}
+
+/* Convenience function for computing a standard CRC16 checksum from 16-bit data block */
+uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords)
+{
+	Chip_CRC_UseCRC16();
+	while (hwords > 0) {
+		Chip_CRC_Write16(*data);
+		data++;
+		hwords--;
+	}
+
+	return Chip_CRC_Sum();
+}
+
+/* Convenience function for computing a standard CRC32 checksum from 32-bit data block */
+uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words)
+{
+	Chip_CRC_UseCRC32();
+	while (words > 0) {
+		Chip_CRC_Write32(*data);
+		data++;
+		words--;
+	}
+
+	return Chip_CRC_Sum();
+}

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/crc_5410x.h

@@ -0,0 +1,262 @@
+/*
+ * @brief LPC5410X Cyclic Redundancy Check (CRC) Engine driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CRC_5410X_H_
+#define __CRC_5410X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup CRC_5410X CHIP: LPC5410X Cyclic Redundancy Check Engine driver
+ * @ingroup CHIP_5410X_DRIVERS
+ * @{
+ */
+
+/**
+ * @brief CRC register block structure
+ */
+typedef struct {					/*!< CRC Structure */
+	__IO    uint32_t    MODE;		/*!< CRC Mode Register */
+	__IO    uint32_t    SEED;		/*!< CRC SEED Register */
+	union {
+		__I     uint32_t    SUM;	/*!< CRC Checksum Register. */
+		__O     uint32_t    WRDATA32;	/*!< CRC Data Register: write size 32-bit*/
+		__O     uint16_t    WRDATA16;	/*!< CRC Data Register: write size 16-bit*/
+		__O     uint8_t     WRDATA8;	/*!< CRC Data Register: write size 8-bit*/
+	};
+
+} LPC_CRC_T;
+
+/*
+ * @brief CRC MODE register description
+ */
+#define CRC_MODE_POLY_BITMASK   ((0x03))	/** CRC polynomial Bit mask */
+#define CRC_MODE_POLY_CCITT     (0x00)		/** Select CRC-CCITT polynomial */
+#define CRC_MODE_POLY_CRC16     (0x01)		/** Select CRC-16 polynomial */
+#define CRC_MODE_POLY_CRC32     (0x02)		/** Select CRC-32 polynomial */
+#define CRC_MODE_WRDATA_BITMASK (0x03 << 2)	/** CRC WR_Data Config Bit mask */
+#define CRC_MODE_WRDATA_BIT_RVS (1 << 2)	/** Select Bit order reverse for WR_DATA (per byte) */
+#define CRC_MODE_WRDATA_CMPL    (1 << 3)	/** Select One's complement for WR_DATA */
+#define CRC_MODE_SUM_BITMASK    (0x03 << 4)	/** CRC Sum Config Bit mask */
+#define CRC_MODE_SUM_BIT_RVS    (1 << 4)	/** Select Bit order reverse for CRC_SUM */
+#define CRC_MODE_SUM_CMPL       (1 << 5)	/** Select One's complement for CRC_SUM */
+
+#define MODE_CFG_CCITT          (0x00)	/** Pre-defined mode word for default CCITT setup */
+#define MODE_CFG_CRC16          (0x15)	/** Pre-defined mode word for default CRC16 setup */
+#define MODE_CFG_CRC32          (0x36)	/** Pre-defined mode word for default CRC32 setup */
+
+#define CRC_SEED_CCITT          (0x0000FFFF)/** Initial seed value for CCITT mode */
+#define CRC_SEED_CRC16          (0x00000000)/** Initial seed value for CRC16 mode */
+#define CRC_SEED_CRC32          (0xFFFFFFFF)/** Initial seed value for CRC32 mode */
+
+/**
+ * @brief CRC polynomial
+ */
+typedef enum IP_CRC_001_POLY {
+	CRC_POLY_CCITT = CRC_MODE_POLY_CCITT,	/**< CRC-CCIT polynomial */
+	CRC_POLY_CRC16 = CRC_MODE_POLY_CRC16,	/**< CRC-16 polynomial */
+	CRC_POLY_CRC32 = CRC_MODE_POLY_CRC32,	/**< CRC-32 polynomial */
+	CRC_POLY_LAST,
+} CRC_POLY_T;
+
+/**
+ * @brief	Initializes the CRC Engine
+ * @return	Nothing
+ */
+void Chip_CRC_Init(void);
+
+/**
+ * @brief	Deinitializes the CRC Engine
+ * @return	Nothing
+ */
+void Chip_CRC_Deinit(void);
+
+/**
+ * @brief	Set the polynomial used for the CRC calculation
+ * @param	poly	: The enumerated polynomial to be used
+ * @param	flags	: An Or'ed value of flags that setup the mode
+ * @return	Nothing
+ * @note	Flags for setting up the mode word include CRC_MODE_WRDATA_BIT_RVS,
+ * CRC_MODE_WRDATA_CMPL, CRC_MODE_SUM_BIT_RVS, and CRC_MODE_SUM_CMPL.
+ */
+STATIC INLINE void Chip_CRC_SetPoly(CRC_POLY_T poly, uint32_t flags)
+{
+	LPC_CRC->MODE = (uint32_t) poly | flags;
+}
+
+/**
+ * @brief	Sets up the CRC engine for CRC16 mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_UseCRC16(void)
+{
+	LPC_CRC->MODE = MODE_CFG_CRC16;
+	LPC_CRC->SEED = CRC_SEED_CRC16;
+}
+
+/**
+ * @brief	Sets up the CRC engine for CRC32 mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_UseCRC32(void)
+{
+	LPC_CRC->MODE = MODE_CFG_CRC32;
+	LPC_CRC->SEED = CRC_SEED_CRC32;
+}
+
+/**
+ * @brief	Sets up the CRC engine for CCITT mode
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_UseCCITT(void)
+{
+	LPC_CRC->MODE = MODE_CFG_CCITT;
+	LPC_CRC->SEED = CRC_SEED_CCITT;
+}
+
+/**
+ * @brief	Engage the CRC engine with defaults based on the polynomial to be used
+ * @param	poly	: The enumerated polynomial to be used
+ * @return	Nothing
+ */
+void Chip_CRC_UseDefaultConfig(CRC_POLY_T poly);
+
+/**
+ * @brief	Set the CRC Mode bits
+ * @param	mode	: Mode value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_SetMode(uint32_t mode)
+{
+	LPC_CRC->MODE = mode;
+}
+
+/**
+ * @brief	Get the CRC Mode bits
+ * @return	The current value of the CRC Mode bits
+ */
+STATIC INLINE uint32_t Chip_CRC_GetMode(void)
+{
+	return LPC_CRC->MODE;
+}
+
+/**
+ * @brief	Set the seed bits used by the CRC_SUM register
+ * @param	seed	: Seed value
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_SetSeed(uint32_t seed)
+{
+	LPC_CRC->SEED = seed;
+}
+
+/**
+ * @brief	Get the CRC seed value
+ * @return	Seed value
+ */
+STATIC INLINE uint32_t Chip_CRC_GetSeed(void)
+{
+	return LPC_CRC->SEED;
+}
+
+/**
+ * @brief	Convenience function for writing 8-bit data to the CRC engine
+ * @param	data	: 8-bit data to write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_Write8(uint8_t data)
+{
+	LPC_CRC->WRDATA8 = data;
+}
+
+/**
+ * @brief	Convenience function for writing 16-bit data to the CRC engine
+ * @param	data	: 16-bit data to write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_Write16(uint16_t data)
+{
+	LPC_CRC->WRDATA16 = data;
+}
+
+/**
+ * @brief	Convenience function for writing 32-bit data to the CRC engine
+ * @param	data	: 32-bit data to write
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_CRC_Write32(uint32_t data)
+{
+	LPC_CRC->WRDATA32 = data;
+}
+
+/**
+ * @brief	Gets the CRC Sum based on the Mode and Seed as previously configured
+ * @return	CRC Checksum value
+ */
+STATIC INLINE uint32_t Chip_CRC_Sum(void)
+{
+	return LPC_CRC->SUM;
+}
+
+/**
+ * @brief	Convenience function for computing a standard CCITT checksum from an 8-bit data block
+ * @param	data	: Pointer to the block of 8-bit data
+ * @param   bytes	: The number of bytes pointed to by data
+ * @return	Check sum value
+ */
+uint32_t Chip_CRC_CRC8(const uint8_t *data, uint32_t bytes);
+
+/**
+ * @brief	Convenience function for computing a standard CRC16 checksum from 16-bit data block
+ * @param	data	: Pointer to the block of 16-bit data
+ * @param   hwords	: The number of 16 byte entries pointed to by data
+ * @return	Check sum value
+ */
+uint32_t Chip_CRC_CRC16(const uint16_t *data, uint32_t hwords);
+
+/**
+ * @brief	Convenience function for computing a standard CRC32 checksum from 32-bit data block
+ * @param	data	: Pointer to the block of 32-bit data
+ * @param   words	: The number of 32-bit entries pointed to by data
+ * @return	Check sum value
+ */
+uint32_t Chip_CRC_CRC32(const uint32_t *data, uint32_t words);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CRC_5410X_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/fifo_5410x.c

@@ -0,0 +1,306 @@
+/*
+ * @brief LPC5410X System FIFO chip driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/** SPI FIFO read FIFO statuses */
+#define LPC_SPIRXFIFO_STAT_SSEL0N       (1 << 16)		/*!< Slave select for receive on SSEL0 (active low) */
+#define LPC_SPIRXFIFO_STAT_SSEL1N       (1 << 17)		/*!< Slave select for receive on SSEL1 (active low) */
+#define LPC_SPIRXFIFO_STAT_SSEL2N       (1 << 18)		/*!< Slave select for receive on SSEL2 (active low) */
+#define LPC_SPIRXFIFO_STAT_SSEL3N       (1 << 19)		/*!< Slave select for receive on SSEL3 (active low) */
+#define LPC_SPIRXFIFO_STAT_SOT          (1 << 20)		/*!< This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted */
+
+/** SPI FIFO write FIFO control */
+#define LPC_SPITXFIFO_CTRL_SSEL0N       (1 << 16)		/*!< Master assert for receive on SSEL0 (active low) */
+#define LPC_SPITXFIFO_CTRL_SSEL1N       (1 << 17)		/*!< Master assert for receive on SSEL1 (active low) */
+#define LPC_SPITXFIFO_CTRL_SSEL2N       (1 << 18)		/*!< Master assert for receive on SSEL2 (active low) */
+#define LPC_SPITXFIFO_CTRL_SSEL3N       (1 << 19)		/*!< Master assert for receive on SSEL3 (active low) */
+#define LPC_SPITXFIFO_CTRL_EOT          (1 << 20)		/*!< End of Transfer. The asserted SSEL will be deasserted at the end of a transfer */
+#define LPC_SPITXFIFO_CTRL_EOF          (1 << 21)		/*!< End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register */
+#define LPC_SPITXFIFO_CTRL_RXIGNORE     (1 << 22)		/*!< Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver */
+#define LPC_SPITXFIFO_CTRL_LEN(n)       ((n) << 24)		/*!< Data Length. Specifies the data length from 1 to 16 bits ((n-1) encoded) */
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Initializes the system FIFO */
+void Chip_FIFO_Init(LPC_FIFO_T *pFIFO)
+{
+	Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_FIFO);
+	Chip_SYSCON_PeriphReset(RESET_FIFO);
+}
+
+/* Deinitializes the system FIFO */
+void Chip_FIFO_Deinit(LPC_FIFO_T *pFIFO)
+{
+	Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_FIFO);
+}
+
+/* Get the FIFO space available for the USART/SPI direction */
+uint32_t Chip_FIFO_GetFifoSpace(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir)
+{
+	uint32_t pcfg;
+
+	if (periphId == FIFO_USART) {
+		pcfg = pFIFO->common.FIFOCTLUSART;
+	}
+	else {
+		pcfg = pFIFO->common.FIFOCTLSPI;
+	}
+
+	if (dir == FIFO_RX) {
+		pcfg = pcfg >> 16;
+	}
+	else {
+		pcfg = pcfg >> 24;
+	}
+
+	return pcfg & 0xFF;
+}
+
+/* Pause a peripheral FIFO */
+void Chip_FIFO_PauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir)
+{
+	if (periphId == FIFO_USART) {
+		if (dir == FIFO_RX) {
+			pFIFO->common.FIFOCTLUSART |= (1 << 0);
+		}
+		else {
+			pFIFO->common.FIFOCTLUSART |= (1 << 8);
+		}
+	}
+	else {
+		if (dir == FIFO_RX) {
+			pFIFO->common.FIFOCTLSPI |= (1 << 0);
+		}
+		else {
+			pFIFO->common.FIFOCTLSPI |= (1 << 8);
+		}
+	}
+}
+
+/* Unpause a peripheral FIFO */
+void Chip_FIFO_UnpauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir)
+{
+	if (periphId == FIFO_USART) {
+		if (dir == FIFO_RX) {
+			pFIFO->common.FIFOCTLUSART &= ~(1 << 0);
+		}
+		else {
+			pFIFO->common.FIFOCTLUSART &= ~(1 << 8);
+		}
+	}
+	else {
+		if (dir == FIFO_RX) {
+			pFIFO->common.FIFOCTLSPI &= ~(1 << 0);
+		}
+		else {
+			pFIFO->common.FIFOCTLSPI &= ~(1 << 8);
+		}
+	}
+}
+
+/* Configure a peripheral's FIFO sizes */
+void Chip_FIFO_ConfigFifoSize(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_CFGSIZE_T *pSizes)
+{
+	int maxP, i;
+	uint32_t upDateMask;
+	volatile uint32_t *updateReg, *pFifoSizes, *pFifoPause;
+
+	/* Pause FIFOs */
+	Chip_FIFO_PauseFifo(LPC_FIFO, periphId, FIFO_RX);
+	Chip_FIFO_PauseFifo(LPC_FIFO, periphId, FIFO_TX);
+
+	/* Maximum peripheral FIFOs supported */
+	if (periphId == FIFO_USART) {
+		maxP = LPC_FIFO_USART_MAX;
+		updateReg = &pFIFO->common.FIFOUPDATEUSART;
+		upDateMask = 0xF | (0xF << 16);
+		pFifoSizes = &pFIFO->common.FIFOCFGUSART[0];
+		pFifoPause = &pFIFO->common.FIFOCTLUSART;
+	}
+	else {
+		maxP = LPC_FIFO_SPI_MAX;
+		updateReg = &pFIFO->common.FIFOUPDATESPI;
+		upDateMask = 0x3 | (0x3 << 16);
+		pFifoSizes = &pFIFO->common.FIFOCFGSPI[0];
+		pFifoPause = &pFIFO->common.FIFOCTLSPI;
+	}
+
+	/* Wait for FIFO pause */
+	while ((*pFifoPause & ((1 << 0) | (1 << 8))) != ((1 << 0) | (1 << 8))) {}
+
+	/* Update FIFO sizes */
+	for (i = 0; i < maxP; i++) {
+		pFifoSizes[i] = ((uint32_t) (pSizes->fifoRXSize[i]) << 0) |
+						((uint32_t) (pSizes->fifoTXSize[i]) << 8);
+	}
+
+	/* Update all peripheral FIFO sizes */
+	*updateReg = upDateMask;
+}
+
+/* Configure the USART system FIFO */
+void Chip_FIFOUSART_Configure(LPC_FIFO_T *pFIFO, int usartIndex, LPC_FIFO_CFG_T *pUSARTCfg)
+{
+	pFIFO->usart[usartIndex].CFG =
+		(pUSARTCfg->noTimeoutContWrite << 4) |
+		(pUSARTCfg->noTimeoutContEmpty << 5) |
+		(pUSARTCfg->timeoutBase << 8) |
+		(pUSARTCfg->timeoutValue << 12) |
+		(pUSARTCfg->rxThreshold << 16) |
+		(pUSARTCfg->txThreshold << 24);
+}
+
+/* Write data to a system FIFO (non-blocking) */
+int Chip_FIFOUSART_WriteTX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData)
+{
+	int datumWritten, sz16;
+	uint8_t *p8 = (uint8_t *) buff;
+	uint16_t *p16 = (uint16_t *) buff;
+
+	/* Get configured FIFO size to determine write size, limit to buffer size */
+	sz16 = (pFIFO->usart[usartIndex].STAT >> 24) & 0xFF;
+	if (sz16 > numData) {
+		sz16 = numData;
+	}
+	datumWritten = sz16;
+
+	/* Write from buffer */
+	while (sz16 > 0) {
+		if (sz8) {
+			pFIFO->usart[usartIndex].TXDAT = (uint32_t) *p8;
+			p8++;
+		}
+		else {
+			pFIFO->usart[usartIndex].TXDAT = (uint32_t) *p16;
+			p16++;
+		}
+
+		sz16--;
+	}
+
+	return datumWritten;
+}
+
+/* Read data from a system FIFO (non-blocking) */
+int Chip_FIFOUSART_ReadRX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData)
+{
+	int datumRead, sz16;
+	uint8_t *p8 = (uint8_t *) buff;
+	uint16_t *p16 = (uint16_t *) buff;
+
+	/* Get configured FIFO size to determine read size, limit to buffer size */
+	sz16 = (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF;
+	if (sz16 > numData) {
+		sz16 = numData;
+	}
+	datumRead = sz16;
+
+	/* Read into buffer */
+	while (sz16 > 0) {
+		if (sz8) {
+			*p8 = (uint8_t) (pFIFO->usart[usartIndex].RXDAT & 0xFF);
+			p8++;
+		}
+		else {
+			*p16 = (uint16_t) (pFIFO->usart[usartIndex].RXDAT & 0x1FF);
+			p16++;
+		}
+
+		sz16--;
+	}
+
+	return datumRead;
+}
+
+/* Read data from a system FIFO with status (non-blocking) */
+int Chip_FIFOUSART_ReadRXStatus(LPC_FIFO_T *pFIFO, int usartIndex, uint16_t *buff, int numData)
+{
+	int datumRead, sz16;
+	uint16_t *p16 = (uint16_t *) buff;
+
+	/* Get configured FIFO size to determine read size, limit to buffer size */
+	sz16 = (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF;
+	if (sz16 > numData) {
+		sz16 = numData;
+	}
+	datumRead = sz16;
+
+	/* Read into buffer */
+	while (sz16 > 0) {
+		*p16 = (uint16_t) (pFIFO->usart[usartIndex].RXDATSTAT & 0xFFFF);
+		p16++;
+		sz16--;
+	}
+
+	return datumRead;
+}
+
+#if 0 /* Sorry, not yet support */
+/* Configure the USART system FIFO */
+void Chip_FIFOSPI_Configure(LPC_FIFO_T *pFIFO, int spiIndex, LPC_FIFO_CFG_T *pSPICfg)
+{
+	pFIFO->spi[spiIndex].CFG =
+		(pSPICfg->noTimeoutContWrite << 4) |
+		(pSPICfg->noTimeoutContEmpty << 5) |
+		(pSPICfg->timeoutBase << 6) |
+		(pSPICfg->timeoutValue << 12) |
+		(pSPICfg->rxThreshold << 16) |
+		(pSPICfg->txThreshold << 24);
+}
+
+/* Start a data transfer (non-blocking) */
+void Chip_FIFOSPI_StartTransfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData)
+{
+	pSetupData->start = 1;
+	Chip_FIFOSPI_Transfer(pFIFO, pSetupData);
+}
+
+
+/* Feed a SPI data transfer (non-blocking) */
+void Chip_FIFOSPI_Transfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData)
+{
+	// FIXME - not yet ready
+}
+#endif

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/gpio_5410x.c

@@ -0,0 +1,108 @@
+/*
+ * @brief LPC5410X GPIO driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* GPIO initilisation function */
+void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
+{
+	Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO0);
+	Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GPIO1);
+	Chip_SYSCON_PeriphReset(RESET_GPIO0);
+	Chip_SYSCON_PeriphReset(RESET_GPIO1);
+}
+
+/* GPIO deinitialisation function */
+void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
+{
+	Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GPIO0);
+	Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GPIO1);
+}
+
+/* Set GPIO direction for a single GPIO pin */
+void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting)
+{
+	if (setting) {
+		pGPIO->DIR[port] |= 1UL << pin;
+	}
+	else {
+		pGPIO->DIR[port] &= ~(1UL << pin);
+	}
+}
+
+/* Set GPIO direction for a single GPIO pin */
+void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
+{
+	if (output) {
+		Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
+	}
+	else {
+		Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
+	}
+}
+
+/* Set Direction for a GPIO port */
+void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
+{
+	if (out) {
+		pGPIO->DIR[portNum] |= bitValue;
+	}
+	else {
+		pGPIO->DIR[portNum] &= ~bitValue;
+	}
+}
+
+/* Set GPIO direction for a all selected GPIO pins to an input or output */
+void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet)
+{
+	if (outSet) {
+		Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
+	}
+	else {
+		Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
+	}
+}

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/gpio_5410x.h

@@ -0,0 +1,471 @@
+/*
+ * @brief LPC5410X GPIO driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIO_5410X_H_
+#define __GPIO_5410X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPIO_5410X CHIP: LPC5410X GPIO driver
+ * @ingroup CHIP_5410X_DRIVERS
+ * @{
+ */
+
+/**
+ * @brief  GPIO port register block structure
+ */
+typedef struct {				/*!< GPIO_PORT Structure */
+	__IO uint8_t B[128][32];	/*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
+	__IO uint32_t W[32][32];	/*!< Offset 0x1000: Word pin registers port 0 to n */
+	__IO uint32_t DIR[32];		/*!< Offset 0x2000: Direction registers port n */
+	__IO uint32_t MASK[32];		/*!< Offset 0x2080: Mask register port n */
+	__IO uint32_t PIN[32];		/*!< Offset 0x2100: Portpin register port n */
+	__IO uint32_t MPIN[32];		/*!< Offset 0x2180: Masked port register port n */
+	__IO uint32_t SET[32];		/*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */
+	__O  uint32_t CLR[32];		/*!< Offset 0x2280: Clear port n */
+	__O  uint32_t NOT[32];		/*!< Offset 0x2300: Toggle port n */
+} LPC_GPIO_T;
+
+/**
+ * @brief	Initialize GPIO block
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_GPIO_Init(LPC_GPIO_T *pGPIO);
+
+/**
+ * @brief	De-Initialize GPIO block
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @return	Nothing
+ */
+void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO);
+
+/**
+ * @brief	Set a GPIO port/pin state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	pin		: GPIO pin to set
+ * @param	setting	: true for high, false for low
+ * @return	Nothing
+ * @note	It is recommended to use the Chip_GPIO_SetPinState() function instead.
+ */
+STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting)
+{
+	pGPIO->B[port][pin] = setting;
+}
+
+/**
+ * @brief	Set a GPIO pin state via the GPIO byte register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	pin		: GPIO pin to set
+ * @param	setting	: true for high, false for low
+ * @return	Nothing
+ * @note	This function replaces Chip_GPIO_WritePortBit()
+ */
+STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting)
+{
+	pGPIO->B[port][pin] = setting;
+}
+
+/**
+ * @brief	Read a GPIO pin state via the GPIO byte register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	pin		: GPIO pin to read
+ * @return	true if the GPIO pin is high, false if low
+ * @note	It is recommended to use the Chip_GPIO_GetPinState() function instead.
+ */
+STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin)
+{
+	return (bool) pGPIO->B[port][pin];
+}
+
+/**
+ * @brief	Get a GPIO pin state via the GPIO byte register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	pin		: GPIO pin to get state for
+ * @return	true if the GPIO is high, false if low
+ * @note	This function replaces Chip_GPIO_ReadPortBit()
+ */
+STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	return (bool) pGPIO->B[port][pin];
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	pin		: GPIO pin to set
+ * @param	setting	: true for output, false for input
+ * @return	Nothing
+ * @note	It is recommended to use the Chip_GPIO_SetPinDIROutput(),
+ * Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead
+ * of this function.
+ */
+void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting);
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin to an output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	pin		: GPIO pin to set direction on as output
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->DIR[port] |= 1UL << pin;
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin to an input
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	pin		: GPIO pin to set direction on as input
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->DIR[port] &= ~(1UL << pin);
+}
+
+/**
+ * @brief	Set GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to set
+ * @param	pin		: GPIO pin to set direction for
+ * @param	output	: true for output, false for input
+ * @return	Nothing
+ */
+void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output);
+
+/**
+ * @brief	Read a GPIO direction (out or in)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read
+ * @param	bit		: GPIO bit direction to read
+ * @return	true if the GPIO is an output, false if input
+ * @note	It is recommended to use the Chip_GPIO_GetPinDIR() function instead.
+ */
+STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
+{
+	return (bool) (((pGPIO->DIR[port]) >> bit) & 1);
+}
+
+/**
+ * @brief	Get GPIO direction for a single GPIO pin
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: GPIO port to read (supports port 0 only)
+ * @param	pin		: GPIO pin to get direction for
+ * @return	true if the GPIO is an output, false if input
+ */
+STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	return Chip_GPIO_ReadDirBit(pGPIO, port, pin);
+}
+
+/**
+ * @brief	Set Direction for a GPIO port
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port Number
+ * @param	bitValue	: GPIO bit to set
+ * @param	out			: Direction value, 0 = input, !0 = output
+ * @return	None
+ * @note	Bits set to '0' are not altered. It is recommended to use the
+ * Chip_GPIO_SetPortDIR() function instead.
+ */
+void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out);
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number
+ * @param	pinMask	: GPIO pin mask to set direction on as output (bits 0..b for pins 0..n)
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the output direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
+{
+	pGPIO->DIR[port] |= pinMask;
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an input
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number
+ * @param	pinMask	: GPIO pin mask to set direction on as input (bits 0..b for pins 0..n)
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the input direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an input.
+ */
+STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask)
+{
+	pGPIO->DIR[port] &= ~pinMask;
+}
+
+/**
+ * @brief	Set GPIO direction for a all selected GPIO pins to an input or output
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number
+ * @param	pinMask	: GPIO pin mask to set direction on (bits 0..b for pins 0..n)
+ * @param	outSet	: Direction value, false = set as inputs, true = set as outputs
+ * @return	Nothing
+ * @note	Sets multiple GPIO pins to the input direction, each bit's position that is
+ * high sets the corresponding pin number for that bit to an input.
+ */
+void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet);
+
+/**
+ * @brief	Get GPIO direction for a all GPIO pins
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number
+ * @return	a bitfield containing the input and output states for each pin
+ * @note	For pins 0..n, a high state in a bit corresponds to an output state for the
+ * same pin, while a low  state corresponds to an input state.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO->DIR[port];
+}
+
+/**
+ * @brief	Set GPIO port mask value for GPIO masked read and write
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	mask	: Mask value for read and write
+ * @return	Nothing
+ * @note	Controls which bits corresponding to PIO0_n are active in the P0MPORT
+ * register (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17).
+ */
+STATIC INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t mask)
+{
+	pGPIO->MASK[port] = mask;
+}
+
+/**
+ * @brief	Get GPIO port mask value used for GPIO masked read and write
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @return	Returns value set with the Chip_GPIO_SetPortMask() function.
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO->MASK[port];
+}
+
+/**
+ * @brief	Set all GPIO raw pin states (regardless of masking)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	value	: Value to set all GPIO pin states (0..n) to
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
+{
+	pGPIO->PIN[port] = value;
+}
+
+/**
+ * @brief	Get all GPIO raw pin states (regardless of masking)
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @return	Current (raw) state of all GPIO pins
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO->PIN[port];
+}
+
+/**
+ * @brief	Set all GPIO pin states, but mask via the MASKP0 register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	value	: Value to set all GPIO pin states (0..n) to
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
+{
+	pGPIO->MPIN[port] = value;
+}
+
+/**
+ * @brief	Get all GPIO pin statesm but mask via the MASKP0 register
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @return	Current (masked) state of all GPIO pins
+ */
+STATIC INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
+{
+	return pGPIO->MPIN[port];
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the high state
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port number (supports port 0 only)
+ * @param	bitValue	: bit(s) in the port to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output. It is recommended to use the
+ * Chip_GPIO_SetPortOutHigh() function instead.
+ */
+STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
+{
+	pGPIO->SET[portNum] = bitValue;
+}
+
+/**
+ * @brief	Set selected GPIO output pins to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	pins	: pins (0..n) to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO->SET[port] = pins;
+}
+
+/**
+ * @brief	Set an individual GPIO output pin to the high state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	pin		: pin number (0..n) to set high
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->SET[port] = (1 << pin);
+}
+
+/**
+ * @brief	Set a GPIO port/bit to the low state
+ * @param	pGPIO		: The base of GPIO peripheral on the chip
+ * @param	portNum		: port number (support port 0 only)
+ * @param	bitValue	: bit(s) in the port to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output. It is recommended to use the
+ * Chip_GPIO_SetPortOutLow() function instead.
+ */
+STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
+{
+	pGPIO->CLR[portNum] = bitValue;
+}
+
+/**
+ * @brief	Set selected GPIO output pins to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	pins	: pins (0..n) to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO->CLR[port] = pins;
+}
+
+/**
+ * @brief	Set an individual GPIO output pin to the low state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	pin		: pin number (0..n) to set low
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->CLR[port] = (1 << pin);
+}
+
+/**
+ * @brief	Toggle selected GPIO output pins to the opposite state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	pins	: pins (0..n) to toggle
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
+{
+	pGPIO->NOT[port] = pins;
+}
+
+/**
+ * @brief	Toggle an individual GPIO output pin to the opposite state
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	port	: port Number (supports port 0 only)
+ * @param	pin		: pin number (0..n) to toggle
+ * @return	None
+ * @note	Any bit set as a '0' will not have it's state changed. This only
+ * applies to ports configured as an output.
+ */
+STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
+{
+	pGPIO->NOT[port] = (1 << pin);
+}
+
+/**
+ * @brief	Read current bit states for the selected port
+ * @param	pGPIO	: The base of GPIO peripheral on the chip
+ * @param	portNum	: port number to read (supports port 0 only)
+ * @return	Current value of GPIO port
+ * @note	The current states of the bits for the port are read, regardless of
+ * whether the GPIO port bits are input or output. It is recommended to use the
+ * Chip_GPIO_GetPortValue() function instead.
+ */
+STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)
+{
+	return pGPIO->PIN[portNum];
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_5410X_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/gpiogroup_5410x.c

@@ -0,0 +1,48 @@
+/*
+ * @brief LPC5410x GPIO group driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "chip.h"
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/gpiogroup_5410x.h

@@ -0,0 +1,223 @@
+/*
+ * @brief LPC5410x GPIO group driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __GPIOGROUP_5410X_H_
+#define __GPIOGROUP_5410X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup GPIOGP_5410X CHIP: LPC5410x GPIO group driver
+ * @ingroup CHIP_5410X_DRIVERS
+ * @{
+ */
+
+/**
+ * @brief GPIO grouped interrupt register block structure
+ */
+typedef struct {					/*!< GPIO_GROUP_INTn Structure */
+	__IO uint32_t  CTRL;			/*!< GPIO grouped interrupt control register */
+	__I  uint32_t  RESERVED0[7];
+	__IO uint32_t  PORT_POL[8];		/*!< GPIO grouped interrupt port polarity register */
+	__IO uint32_t  PORT_ENA[8];		/*!< GPIO grouped interrupt port m enable register */
+	uint32_t       RESERVED1[4072];
+} LPC_GPIOGROUPINT_T;
+
+/**
+ * LPC5410x GPIO group bit definitions
+ */
+#define GPIOGR_INT       (1 << 0)	/*!< GPIO interrupt pending/clear bit */
+#define GPIOGR_COMB      (1 << 1)	/*!< GPIO interrupt OR(0)/AND(1) mode bit */
+#define GPIOGR_TRIG      (1 << 2)	/*!< GPIO interrupt edge(0)/level(1) mode bit */
+
+/**
+ * @brief	Initialize GPIO group interrupt block
+ * @param	pGPIOGPINT	: The base of GPIO group peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIOGP_Init(LPC_GPIOGROUPINT_T *pGPIOGPINT)
+{
+	Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_GINT);
+	Chip_SYSCON_PeriphReset(RESET_GINT);
+}
+
+/**
+ * @brief	De-Initialize GPIO group interrupt block
+ * @param	pGPIOGPINT	: The base of GPIO group peripheral on the chip
+ * @return	Nothing
+ */
+STATIC INLINE void Chip_GPIOGP_DeInit(LPC_GPIOGROUPINT_T *pGPIOGPINT)
+{
+	Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_GINT);
+}
+
+/**
+ * @brief	Clear interrupt pending status for the selected group
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL |= GPIOGR_INT;
+}
+
+/**
+ * @brief	Returns current GPIO group inetrrupt pending status
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	true if the group interrupt is pending, otherwise false.
+ */
+STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0);
+}
+
+/**
+ * @brief	Selected GPIO group functionality for trigger on any pin in group (OR mode)
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL &= ~(GPIOGR_COMB | GPIOGR_INT);
+}
+
+/**
+ * @brief	Selected GPIO group functionality for trigger on all matching pins in group (AND mode)
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectAndMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL = (pGPIOGPINT[group].CTRL & ~GPIOGR_INT) | GPIOGR_COMB;
+}
+
+/**
+ * @brief	Selected GPIO group functionality edge trigger mode
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectEdgeMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL &= ~(GPIOGR_TRIG | GPIOGR_INT);
+}
+
+/**
+ * @brief	Selected GPIO group functionality level trigger mode
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectLevelMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
+{
+	pGPIOGPINT[group].CTRL = (pGPIOGPINT[group].CTRL & ~GPIOGR_INT) | GPIOGR_TRIG;
+}
+
+/**
+ * @brief	Set selected pins for the group and port to low level trigger
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @param	port		: GPIO port number
+ * @param	pinMask		: Or'ed value of pins to select for low level (bit 0 = pin 0, 1 = pin1, etc.)
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectLowLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
+											  uint8_t group,
+											  uint8_t port,
+											  uint32_t pinMask)
+{
+	pGPIOGPINT[group].PORT_POL[port] &= ~pinMask;
+}
+
+/**
+ * @brief	Set selected pins for the group and port to high level trigger
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @param	port		: GPIO port number
+ * @param	pinMask		: Or'ed value of pins to select for high level (bit 0 = pin 0, 1 = pin1, etc.)
+ * @return	None
+ */
+STATIC INLINE void Chip_GPIOGP_SelectHighLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
+											   uint8_t group,
+											   uint8_t port,
+											   uint32_t pinMask)
+{
+	pGPIOGPINT[group].PORT_POL[port] |= pinMask;
+}
+
+/**
+ * @brief	Disabled selected pins for the group interrupt
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @param	port		: GPIO port number
+ * @param	pinMask		: Or'ed value of pins to disable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
+ * @return	None
+ * @note	Disabled pins do not contribute to the group interrupt.
+ */
+STATIC INLINE void Chip_GPIOGP_DisableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
+												uint8_t group,
+												uint8_t port,
+												uint32_t pinMask)
+{
+	pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask;
+}
+
+/**
+ * @brief	Enable selected pins for the group interrupt
+ * @param	pGPIOGPINT	: Pointer to GPIO group register block
+ * @param	group		: GPIO group number
+ * @param	port		: GPIO port number
+ * @param	pinMask		: Or'ed value of pins to enable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
+ * @return	None
+ * @note	Enabled pins contribute to the group interrupt.
+ */
+STATIC INLINE void Chip_GPIOGP_EnableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
+											   uint8_t group,
+											   uint8_t port,
+											   uint32_t pinMask)
+{
+	pGPIOGPINT[group].PORT_ENA[port] |= pinMask;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIOGROUP_5410X_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc.h

@@ -0,0 +1,243 @@
+/*
+ * @brief ADC ROM API declarations and functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef  _HW_ADC_H
+#define  _HW_ADC_H
+
+/*******************
+ * INCLUDE FILES    *
+ ********************/
+#include <stdint.h>
+
+#if defined( __CC_ARM   )
+  #pragma anon_unions
+#endif
+
+/*******************
+ * EXPORTED MACROS  *
+ ********************/
+
+/*********************
+ * EXPORTED TYPEDEFS  *
+ **********************/
+// ------------------------------------------------------------------------------------------------
+// -----                                          ADC                                         -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3  (ADC)
+ */
+
+typedef struct {						/*!< (@ 0x40000000) ADC Structure          */
+	volatile uint32_t CTRL;						/*!< (@ 0x40000000) A/D Control Register */
+	volatile uint32_t INPUTSEL;					/*!< (@ 0x40000004) A/D Input Control Register */
+	union {
+		volatile uint32_t SEQ_CTRL[2];
+		struct {
+			volatile uint32_t SEQA_CTRL;			/*!< (@ 0x40000008) A/D SEQA Ctrl Register */
+			volatile uint32_t SEQB_CTRL;			/*!< (@ 0x4000000C) A/D SEQB Ctrl Register */
+		};
+
+	};
+
+	union {
+		const volatile uint32_t SEQ_GDAT[2];
+		struct {
+			const volatile uint32_t SEQA_GDAT;					/*!< (@ 0x40000010) A/D SEQA Global Data Register */
+			const volatile uint32_t SEQB_GDAT;					/*!< (@ 0x40000014) A/D SEQB Global Data Register */
+		};
+
+	};
+
+	uint32_t Reserved[2];
+	union {
+		const volatile uint32_t DAT[12];				/*!< (@ 0x40000020) A/D Channel Data Register*/
+		struct {
+			const volatile uint32_t DAT0;					/*!< (@ 0x40000020) A/D Channel Data Register 0*/
+			const volatile uint32_t DAT1;					/*!< (@ 0x40000024) A/D Channel Data Register 1*/
+			const volatile uint32_t DAT2;					/*!< (@ 0x40000028) A/D Channel Data Register 2*/
+			const volatile uint32_t DAT3;					/*!< (@ 0x4000002C) A/D Channel Data Register 3*/
+			const volatile uint32_t DAT4;					/*!< (@ 0x40000030) A/D Channel Data Register 4*/
+			const volatile uint32_t DAT5;					/*!< (@ 0x40000034) A/D Channel Data Register 5*/
+			const volatile uint32_t DAT6;					/*!< (@ 0x40000038) A/D Channel Data Register 6*/
+			const volatile uint32_t DAT7;					/*!< (@ 0x4000003C) A/D Channel Data Register 7*/
+			const volatile uint32_t DAT8;					/*!< (@ 0x40000040) A/D Channel Data Register 8*/
+			const volatile uint32_t DAT9;					/*!< (@ 0x40000044) A/D Channel Data Register 9*/
+			const volatile uint32_t DAT10;					/*!< (@ 0x40000048) A/D Channel Data Register 10*/
+			const volatile uint32_t DAT11;					/*!< (@ 0x4000004C) A/D Channel Data Register 11*/
+		};
+
+	};
+
+	union {
+		volatile uint32_t THR_LOW[2];
+		struct {
+			volatile uint32_t THR0_LOW;				/*!< (@ 0x40000050) A/D Low Threhold Register 0. */
+			volatile uint32_t THR1_LOW;				/*!< (@ 0x40000054) A/D Low Threhold Register 1. */
+		};
+
+	};
+
+	union {
+		volatile uint32_t THR_HIGH[2];
+		struct {
+			volatile uint32_t THR0_HIGH;			/*!< (@ 0x40000058) A/D High Threhold Register 0. */
+			volatile uint32_t THR1_HIGH;			/*!< (@ 0x4000005C) A/D High Threhold Register 1. */
+		};
+
+	};
+
+	volatile uint32_t CHAN_THRSEL;				/*!< (@ 0x40000060) A/D Channel Threhold Select Register. */
+	volatile uint32_t INTEN;					/*!< (@ 0x40000064) A/D Interrupt Enable Register. */
+	volatile uint32_t FLAGS;					/*!< (@ 0x40000068) A/D Interrupt Request Flags Register. */
+	volatile uint32_t STARTUP;					/*!< (@ 0x4000006C) A/D Startup Register. */
+	volatile uint32_t CALIBR;					/*!< (@ 0x40000070) A/D Calibration Register. */
+} ADC_REGS_T;
+
+/** Maximum sample rate in Hz (12-bit conversions) */
+#define ADC_MAX_CHANNEL_NUM         12
+
+/**
+ * @brief ADC register support bitfields and mask
+ */
+/** ADC Control register bit fields */
+#define ADC_CR_CLKDIV_MASK      (0xFF << 0)				/*!< Mask for Clock divider value */
+#define ADC_CR_CLKDIV_BITPOS    (0)							/*!< Bit position for Clock divider value */
+#define ADC_CR_ASYNC_MODE       (1 << 8)
+#define ADC_CR_RESOL_MASK       (0x3 << 9)				/*!< Two-bit mask for resolution */
+#define ADC_CR_RESOL(n)         ((n) << 9)				/*!< 2-bits, 6(0x0),8(0x1),10(0x2),12(0x3)-bit mode enable bit */
+#define ADC_CR_RESOL_BITPOS     (9)
+#define ADC_CR_BYPASS           (1 << 11)					/*!< Bypass mode */
+#define ADC_CR_TSAMP_MASK       (0x7 << 12)				/*!< Three-bit mask for Sample time */
+
+/**
+ * @brief ADC resolution bits 9 and 10
+ */
+typedef enum _ADC_RESOL_T {
+	ADC_RESOL_6BIT = 0,
+	ADC_RESOL_8BIT,
+	ADC_RESOL_10BIT,
+	ADC_RESOL_12BIT,
+} ADC_RESOL_T;
+
+/* ADC input Select register */
+#define ADC_INPUTSEL_PIN            (0x0 << 0)
+#define ADC_INPUTSEL_CORE_VOL       (0x1 << 0)
+#define ADC_INPUTSEL_INTERNAL_VOL   (0x2 << 0)
+#define ADC_INPUTSEL_TEMP_VOL       (0x3 << 0)
+
+/** ADC Sequence Control register bit fields */
+#define ADC_SEQ_CTRL_CHANSEL(n)             (1 << (n))		/*!< Channel select macro */
+#define ADC_SEQ_CTRL_CHANSEL_BITPOS(n)      ((n) << 0)				/*!< Channel select macro */
+#define ADC_SEQ_CTRL_CHANSEL_MASK           (0xFFF)				/*!< Channel select mask */
+
+/** SEQ_CTRL register bit fields */
+#define ADC_SEQ_CTRL_TRIGGER(n)          ((n) << 12)
+#define ADC_SEQ_CTRL_TRIGGER_MASK        (0x1F << 12)
+#define ADC_SEQ_CTRL_HWTRIG_POLPOS       (1 << 18)		/*!< HW trigger polarity - positive edge */
+#define ADC_SEQ_CTRL_HWTRIG_SYNCBYPASS   (1 << 19)		/*!< HW trigger bypass synchronisation */
+#define ADC_SEQ_CTRL_START               (1 << 26)		/*!< Start conversion enable bit */
+#define ADC_SEQ_CTRL_BURST               (1 << 27)		/*!< Repeated conversion enable bit */
+#define ADC_SEQ_CTRL_SINGLESTEP          (1 << 28)		/*!< Single step enable bit */
+#define ADC_SEQ_CTRL_LOWPRIO             (1 << 29)		/*!< High priority enable bit (regardless of name) */
+#define ADC_SEQ_CTRL_MODE_EOS            (1 << 30)		/*!< Mode End of sequence enable bit */
+#define ADC_SEQ_CTRL_SEQ_ENA             (1UL << 31)	/*!< Sequence enable bit */
+
+/** ADC global data register bit fields */
+#define ADC_SEQ_GDAT_RESULT_MASK         (0xFFF << 4)	/*!< Result value mask */
+#define ADC_SEQ_GDAT_RESULT_BITPOS       (4)			/*!< Result start bit position */
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK     (0x3 << 16)	/*!< Comparion range mask */
+#define ADC_SEQ_GDAT_THCMPRANGE_BITPOS   (16)			/*!< Comparison range bit position */
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK     (0x3 << 18)	/*!< Comparion cross mask */
+#define ADC_SEQ_GDAT_THCMPCROSS_BITPOS   (18)			/*!< Comparison cross bit position */
+#define ADC_SEQ_GDAT_CHAN_MASK           (0xF << 26)	/*!< Channel number mask */
+#define ADC_SEQ_GDAT_CHAN_BITPOS         (26)			/*!< Channel number bit position */
+#define ADC_SEQ_GDAT_OVERRUN             (1 << 30)		/*!< Overrun bit */
+#define ADC_SEQ_GDAT_DATAVALID           (1UL << 31)	/*!< Data valid bit */
+
+/** ADC Data register bit fields */
+#define ADC_DR_RESULT(n)           ((((n) >> 4) & 0xFFF))	/*!< Macro for getting the ADC data value */
+#define ADC_DRTHR_RESULT(n)        ((((n) >> 4) & 0xFFFF))	/*!< Macro for getting the ADC data value along with Threshold */
+#define ADC_DR_THCMPRANGE_MASK     (0x3 << 16)			/*!< Comparion range mask */
+#define ADC_DR_THCMPRANGE_BITPOS   (16)					/*!< Comparison range bit position */
+#define ADC_DR_THCMPRANGE(n)       (((n) >> ADC_DR_THCMPRANGE_BITPOS) & 0x3)
+#define ADC_DR_THCMPCROSS_MASK     (0x3 << 18)			/*!< Comparion cross mask */
+#define ADC_DR_THCMPCROSS_BITPOS   (18)					/*!< Comparison cross bit position */
+#define ADC_DR_THCMPCROSS(n)       (((n) >> ADC_DR_THCMPCROSS_BITPOS) & 0x3)
+#define ADC_DR_CHAN_MASK           (0xF << 26)			/*!< Channel number mask */
+#define ADC_DR_CHAN_BITPOS         (26)					/*!< Channel number bit position */
+#define ADC_DR_CHANNEL(n)          (((n) >> ADC_DR_CHAN_BITPOS) & 0xF)	/*!< Channel number bit position */
+#define ADC_DR_OVERRUN             (1 << 30)			/*!< Overrun bit */
+#define ADC_DR_DATAVALID           (1UL << 31)			/*!< Data valid bit */
+#define ADC_DR_DONE(n)             (((n) >> 31))
+
+/** ADC low/high Threshold register bit fields */
+#define ADC_THR_VAL_MASK            (0xFFF << 4)		/*!< Threshold value bit mask */
+#define ADC_THR_VAL_POS             (4)					/*!< Threshold value bit position */
+
+/** ADC Threshold select register bit fields */
+#define ADC_THRSEL_CHAN_SEL_THR1(n) (1 << (n))			/*!< Select THR1 register for channel n */
+
+/** ADC Interrupt Enable register bit fields */
+#define ADC_INTEN_SEQA_ENABLE       (1 << 0)			/*!< Sequence A Interrupt enable bit */
+#define ADC_INTEN_SEQB_ENABLE       (1 << 1)			/*!< Sequence B Interrupt enable bit */
+#define ADC_INTEN_SEQN_ENABLE(seq)  (1 << (seq))		/*!< Sequence A/B Interrupt enable bit */
+#define ADC_INTEN_OVRRUN_ENABLE     (1 << 2)			/*!< Overrun Interrupt enable bit */
+#define ADC_INTEN_CMP_DISBALE       (0)					/*!< Disable comparison interrupt value */
+#define ADC_INTEN_CMP_OUTSIDETH     (1)					/*!< Outside threshold interrupt value */
+#define ADC_INTEN_CMP_CROSSTH       (2)					/*!< Crossing threshold interrupt value */
+#define ADC_INTEN_CMP_MASK          (3)					/*!< Comparison interrupt value mask */
+#define ADC_INTEN_CMP_ENABLE(isel, ch) (((isel) & ADC_INTEN_CMP_MASK) << ((2 * (ch)) + 3))	/*!< Interrupt selection for channel */
+
+/** ADC Flags register bit fields */
+#define ADC_FLAGS_THCMP_MASK(ch)    (1 << (ch))		/*!< Threshold comparison status for channel */
+#define ADC_FLAGS_OVRRUN_MASK(ch)   (1 << (12 + (ch)))	/*!< Overrun status for channel */
+#define ADC_FLAGS_SEQA_OVRRUN_MASK  (1 << 24)			/*!< Seq A Overrun status */
+#define ADC_FLAGS_SEQB_OVRRUN_MASK  (1 << 25)			/*!< Seq B Overrun status */
+#define ADC_FLAGS_SEQN_OVRRUN_MASK(seq) (1 << (24 + (seq)))	/*!< Seq A/B Overrun status */
+#define ADC_FLAGS_SEQA_INT_MASK     (1 << 28)			/*!< Seq A Interrupt status */
+#define ADC_FLAGS_SEQB_INT_MASK     (1 << 29)			/*!< Seq B Interrupt status */
+#define ADC_FLAGS_SEQN_INT_MASK(seq) (1 << (28 + (seq)))/*!< Seq A/B Interrupt status */
+#define ADC_FLAGS_THCMP_INT_MASK    (1 << 30)			/*!< Threshold comparison Interrupt status */
+#define ADC_FLAGS_OVRRUN_INT_MASK   (1UL << 31)			/*!< Overrun Interrupt status */
+
+/** ADC Startup register bit fields */
+#define ADC_STARTUP_ENABLE       (0x1 << 0)
+#define ADC_STARTUP_INIT         (0x1 << 1)
+
+/* ADC Calibration register definition */
+#define ADC_CALIB                       (0x1 << 0)
+#define ADC_CALREQD                     (0x1 << 1)
+
+/* Depending on the mode you are running: the slowest case is using interrupt and end of conversion while BURST mode is enabled.
+   For interrupt and end of sequence, the clock can be set faster. */
+
+#endif /* _HW_ADCD_H      Do not add any thing below this line */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_adc_rom_api.h

@@ -0,0 +1,216 @@
+/*
+ * @brief ADC ROM API declarations and functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __HW_ADC_ROM_API_H
+#define __HW_ADC_ROM_API_H
+
+#include <stdint.h>
+#include <string.h>
+#include "error.h"
+#include "packing.h"
+#include "hw_adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup ROMAPI_ADC ADC (12-Bit) ROM driver functions and definitions
+ * @ingroup ROMAPI_ADC_WRAPPER
+ * @{
+ */
+
+/** @brief ADC Handler type */
+typedef void *ADC_HANDLE_T;
+
+/** @brief	ADC SEQ Options */
+#define TRIG_SOFT      (0UL << 12)		/*!< Software Trigger */
+#define TRIG_PININT0   (0UL << 12)		/*!< Hardware Trigger on PININT0 */
+#define TRIG_PININT1   (1UL << 12)		/*!< Hardware Trigger on PININT1 */
+#define TRIG_ARMTXEV   (5UL << 12)		/*!< Hardware Trigger on ARM_TXEV */
+#define TRIG_POL_NEG   0				/*!< Trigger polarity is negative */
+#define TRIG_POL_POS   (1UL << 18)		/*!< Trigger polarity is positive */
+#define BYPASS_SYNC    (1UL << 19)		/*!< Bypass Synchronization Filp-Flop */
+#define MODE_BURST     (1UL << 27)		/*!< Enable Burst mode */
+#define MODE_SINGLE    (1UL << 28)		/*!< Enable Single mode */
+#define SEQA_PIRO_HIGH (1UL << 29)		/*!< Set SEQA as HIGH Priority */
+#define MODE_EOC       (0UL << 30)		/*!< Event after end of Conversion */
+#define MODE_EOS       (1UL << 30)		/*!< Event after end of sequence */
+#define ENABLE_CH(ch)  (1UL << (ch))	/*!< Enable the channel number */
+
+/* Gets the ADC trigger from configuration */
+#define ADC_TRIGGER(cfg) (((cfg) & 0x3F000) >> 12)
+
+/** @brief	ADC DMA source address offsets */
+#define ADC_DMA_SRC_SEQA    4			/*!< DMA Source offset for SEQ_A */
+#define ADC_DMA_SRC_SEQB    5			/*!< DMA Source offset for SEQ_B */
+#define ADC_DMA_SRC_CH0     8			/*!< DMA Source offset for CH0 */
+#define ADC_DMA_SRC_CH1     9			/*!< DMA Source offset for CH1 */
+#define ADC_DMA_SRC_CH2     10			/*!< DMA Source offset for CH2 */
+#define ADC_DMA_SRC_CH3     11			/*!< DMA Source offset for CH3 */
+#define ADC_DMA_SRC_CH4     12			/*!< DMA Source offset for CH4 */
+#define ADC_DMA_SRC_CH5     13			/*!< DMA Source offset for CH5 */
+#define ADC_DMA_SRC_CH6     14			/*!< DMA Source offset for CH6 */
+#define ADC_DMA_SRC_CH7     15			/*!< DMA Source offset for CH7 */
+#define ADC_DMA_SRC_CH8     16			/*!< DMA Source offset for CH8 */
+#define ADC_DMA_SRC_CH9     17			/*!< DMA Source offset for CH9 */
+#define ADC_DMA_SRC_CH10    18			/*!< DMA Source offset for CH10 */
+#define ADC_DMA_SRC_CH11    19			/*!< DMA Source offset for CH11 */
+
+/** @brief	ADC DMA Source address calculator */
+#define ADC_DMA_ADDR(ptr, src) ((*(uint32_t *) (ptr)) + ((src) << 2))
+
+/** @brief	ADC CTRL Options */
+#define MODE_SYNC      (0UL << 8)		/*!< Set ADC to synchoronous mode */
+#define MODE_ASYNC     (1UL << 8)		/*!< Set ADC to asynchoronous mode */
+#define RESOL_6BIT     (0UL << 9)		/*!< Set ADC Resolution to 6 bits */
+#define RESOL_8BIT     (1UL << 9)		/*!< Set ADC Resolution to 8 bits */
+#define RESOL_10BIT    (2UL << 9)		/*!< Set ADC Resolution to 10 bits */
+#define RESOL_12BIT    (3UL << 9)		/*!< Set ADC Resolution to 12 bits */
+#define BYPASS_CALIB   (1UL << 11)		/*!< Bypass calibration data */
+#define SAMPLE_TIME(x) (((x) & 7) << 12)	/*!< Set the Sample Time to @a x */
+#define ENABLE_OVR     (1UL << 24)		/*!< Enable Overflow interrupt */
+
+/** @brief User context conversion macro
+ * Macro used to extract the user defined data pointer from a ADC ROM
+ * driver handle.<br>
+ * To get a user context, simply use the macro on the driver's handle:
+ * void *pUserData = ROM_ADC_HANDLE_TOUDATA(hADC);
+ */
+#define ROM_ADC_HANDLE_TOUDATA(p)          (void *) (*(uint32_t *) p)
+
+/** @brief	ADC Threshold select */
+#define SEL_THRES1(ch) (1UL << (ch))	/*!< Select THRESHOLD-1 register */
+#define EN_THRES(ch)   (1UL << (16 + (ch)))	/*!< Enable Threshold compare */
+
+/** @brief	Convert DMA data to channel data */
+#define ADC_DATA_CH(data) (((data) >> 4) & 0xFFFF)
+
+/**@brief	Threshold ranges */
+#define ADC_THRES_ABOVE      2		/*!< Threshold is above THRES_HI */
+#define ADC_THRES_BELOW      1		/*!< Threshold is below THRES_LO */
+#define ADC_THRES_INSIDE     0		/*!< Threshold is inside the range */
+#define ADC_THRES_RANGE(data) (((data) >> 12) & 0x3)	/*!< Get Threshold range data */
+
+/**@brief	Threshold crossings */
+#define ADC_THRES_UP         3		/*!< Threshold crossing UP */
+#define ADC_THRES_DOWN       2		/*!< Threshold crossing DOWN */
+#define ADC_THRES_NONE       0		/*!< No threshold crossing */
+#define ADC_THRES_CORSS(data)   (((data) >> 14) & 0x3)	/*!< Get threshold crossing data */
+
+/* @brief	ADC Configuration data structure */
+typedef PRE_PACK struct POST_PACK {
+	uint32_t flagSeqA;	/*!< Options for SEQ_A, like triggers, burst/single mode etc; */
+	uint32_t flagSeqB;	/*!< Options for SEQ_B, like triggers, burst/single mode etc; */
+	uint32_t flagCfg;	/*!< ADC Configuration flags, like SYNC/ASYNC mode select resolution select etc; see #MODE_SYNC, #RESOL_6BIT, #BYPASS_CALIB and #SAMPLE_TIME */
+	uint32_t clkDiv;	/*!< Clock divider value to be used in SYNC mode; not valid #MODE_ASYNC is present in #flagCfg */
+} ADC_CFG_T;
+
+/** @brief	Event handler, event types */
+typedef enum {
+	ADC_EV_SEQ_A_POLL,		/*!< SEQ_A Polling */
+	ADC_EV_SEQ_B_POLL,		/*!< SEQ_B Polling */
+	ADC_EV_SEQ_A_INT,		/*!< SEQ_A Interrupt */
+	ADC_EV_SEQ_B_INT,		/*!< SEQ_B Interrupt */
+	ADC_EV_SEQ_A_DMA,		/*!< SEQ_A DMA Event */
+	ADC_EV_SEQ_B_DMA,		/*!< SEQ_B DMA Event */
+	ADC_EV_OVR_INT,			/*!< Overflow interrupt */
+	ADC_EV_THRES_INT,		/*!< Threshold interrupt */
+} ADC_HEVENT_T;
+
+/** @brief	Channel configuration options */
+#define ADC_CH_THRES_SEL1           0x01	/*!< Use THRES1 for threshold compare */
+#define ADC_CH_THRES_CALLBACK       0x02	/*!< Enable threshold callback event */
+#define ADC_CH_THRES_OUTSIDE        0x04	/*!< Enable threshold outside event */
+#define ADC_CH_THRES_CROSSING       0x08	/*!< Enable threshold crossing event */
+#define ADC_CH_DATA_CALLBACK        0x10	/*!< Enable callback for data available */
+#define ADC_CH_THRES_DATA           0x20	/*!< Add threshold value to DATA */
+
+/** @brief	Macros to extract information from call-back flags */
+#define ADC_OVR_SEQ_A(flag)         (((flag) >> 12) & 1)	/*!< Overflow in SEQ_A */
+#define ADC_OVR_SEQ_B(flag)         (((flag) >> 13) & 1)	/*!< Overflow in SEQ_B */
+
+/** @brief	Index to call-back functions */
+typedef enum {
+	ADC_START_SEQ,							/*!< Start SEQ event */
+	ADC_START_SEQ_A = ADC_START_SEQ,		/*!< Start SEQ_A event */
+	ADC_START_SEQ_B,						/*!< Start SEQ_B event */
+	ADC_STOP_SEQ,							/*!< Stop SEQ event */
+	ADC_STOP_SEQ_A = ADC_STOP_SEQ,			/*!< Stop SEQ_A event */
+	ADC_STOP_SEQ_B,							/*!< Stop SEQ_B event */
+	ADC_BUFFER_DONE,						/*!< ADC Buffer full event */
+	ADC_BUFFER_DONE_A = ADC_BUFFER_DONE,	/*!< ADC Buffer full event for SEQ_A */
+	ADC_BUFFER_DONE_B,						/*!< ADC Buffer full event for SEQ_B */
+	ADC_CHDATA,								/*!< Data for Channel available */
+	ADC_OVERFLOW,							/*!< Over flow event */
+	ADC_THRESHOLD,							/*!< Threshold event */
+	ADC_CBIDX_RESERVED,						/*!< Reserved value (should not be used) */
+} ADC_CBINDEX_T;
+
+/** @brief	ADC Sequence index */
+typedef enum {
+	ADC_SEQ_A,								/*!< Index for Sequence A */
+	ADC_SEQ_B,								/*!< Index for Sequence B */
+} ADC_SEQ_INDEX_T;
+
+/**
+ * @brief	Structure that has the API pointers in ROM Table
+ */
+typedef PRE_PACK struct POST_PACK {
+	/* Index of All the 12-Bit ADC driver APIs */
+	uint32_t (*GetMemSize)(void);	/*!< Returns needed memory size required for run-time context of ADC driver */
+	ADC_HANDLE_T (*Init)(void *pMem, uint32_t baseAddr, void *pUserData);	/*!< Initializes the ADC driver and peripheral */
+	ErrorCode_t (*Configure)(ADC_HANDLE_T hADC, const ADC_CFG_T *pCfg);	/*!< Configure the ADC to given parameters like resolution etc. */
+	ErrorCode_t (*ConfigureCh)(ADC_HANDLE_T hADC, uint32_t chanNum, uint32_t chanOpts);	/*!< Configure channel specific options */
+	void (*SetThreshold)(ADC_HANDLE_T hADC, uint32_t valThr0, uint32_t valThr1);/*!< Set the threshold values for THRES0 (HIGH & LOW) and THRES1 (HIGH & LOW) */
+	ErrorCode_t (*RegisterCB)(ADC_HANDLE_T hADC, ADC_CBINDEX_T cbIndex,
+							  void (*pCbFunc)(ADC_HANDLE_T, ADC_CBINDEX_T, void *));											/*!< Registers an ADC callback function */
+	ErrorCode_t (*Calibrate)(ADC_HANDLE_T hADC, uint32_t sysclk_freq);	/*!< Calibrate the ADC peripheral */
+	ErrorCode_t (*Handler)(ADC_HANDLE_T hADC, ADC_HEVENT_T event);	/*!< ADC Event handler, should be called from the ISR */
+	ErrorCode_t (*StartConversion)(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex, void *buffer, size_t bufCount);	/*!< Start sampling of ADC inputs */
+	ErrorCode_t (*StopConversion)(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex);	/*!< Stop sampling of ADC inputs */
+	ErrorCode_t (*SwTrigger)(ADC_HANDLE_T hADC, ADC_SEQ_INDEX_T seqIndex);	/*!< Generate a software trigger */
+	uint32_t (*GetDriverVersion)(void);	/*!< Get the version of the Driver Firmware in ROM */
+} ROM_ADC_API_T;
+
+/* Extern declaration so that application can access
+ * pointer to the function table
+ */
+extern const ROM_ADC_API_T  adcrom_api;
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HW_ADCD_ROM_API_H */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd.h

@@ -0,0 +1,80 @@
+/*
+ * @brief DMA master ROM API declarations and functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __HW_DMAALTD_H
+#define __HW_DMAALTD_H
+
+#include "error.h"
+#include "hw_dmaaltd_rom_api.h"
+
+// *** DMA controller functions called by Application Program ***
+uint32_t dmaalt_get_mem_size(void);
+
+ROM_DMA_HANDLE_T dmaalt_init(void *mem, const ROM_DMA_INIT_T *pInit);
+
+ErrorCode_t dmaalt_setup_channel(ROM_DMA_HANDLE_T pHandle, ROM_DMA_CHAN_CFG_T *pCfg, uint8_t dmaCh);
+
+ErrorCode_t dmaalt_init_queue(ROM_DMA_HANDLE_T pHandle, uint8_t dmaCh, ROM_DMA_QUEUE_T *pQueue);
+
+void dmaalt_register_queue_callback(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, uint32_t cbIndex, void *pCB);
+
+ErrorCode_t dmaalt_build_descriptor_chain(ROM_DMA_HANDLE_T pHandle,
+										  ROM_DMA_XFERDESC_CFG_T *pXferCfg,
+										  ROM_DMA_DESC_T *pDesc,
+										  ROM_DMA_DESC_T *pDescPrev);
+
+uint32_t dmaalt_get_transfer_count(ROM_DMA_HANDLE_T pHandle, ROM_DMA_DESC_T *pDesc);
+
+void dmaalt_unstall_descriptor_chain(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
+
+void dmaalt_queue_descriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue, ROM_DMA_DESC_T *pDescChainHead);
+
+ROM_DMA_DESC_STS_T dmaalt_get_queue_pop_descriptor_status(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
+
+ROM_DMA_DESC_T *dmaalt_unqueue_descriptor(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
+
+ErrorCode_t dmaalt_start_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
+
+ErrorCode_t dmaalt_stop_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
+
+void dmaalt_flush_queue(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
+
+uint8_t dmaalt_get_queue_state(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
+
+void dmaalt_force_trigger(ROM_DMA_HANDLE_T pHandle, ROM_DMA_QUEUE_T *pQueue);
+
+void dmaalt_handler(ROM_DMA_HANDLE_T pHandle);
+
+uint32_t dmaalt_get_driver_version(void);
+
+// ***
+
+#endif /* __HW_DMAALTD_H */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_regs.h

@@ -0,0 +1,147 @@
+/*
+ * @brief DMA master ROM API declarations and functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __HW_DMA_REGS_H_
+#define __HW_DMA_REGS_H_
+
+/**
+ * @brief DMA Controller shared registers structure
+ */
+typedef struct {					/*!< DMA shared registers structure */
+	volatile uint32_t  ENABLESET;		/*!< DMA Channel Enable read and Set for all DMA channels */
+	volatile  uint32_t  RESERVED0;
+	volatile  uint32_t  ENABLECLR;		/*!< DMA Channel Enable Clear for all DMA channels */
+	volatile  uint32_t  RESERVED1;
+	volatile  uint32_t  ACTIVE;			/*!< DMA Channel Active status for all DMA channels */
+	volatile  uint32_t  RESERVED2;
+	volatile  uint32_t  BUSY;			/*!< DMA Channel Busy status for all DMA channels */
+	volatile  uint32_t  RESERVED3;
+	volatile  uint32_t  ERRINT;			/*!< DMA Error Interrupt status for all DMA channels */
+	volatile  uint32_t  RESERVED4;
+	volatile  uint32_t  INTENSET;		/*!< DMA Interrupt Enable read and Set for all DMA channels */
+	volatile  uint32_t  RESERVED5;
+	volatile  uint32_t  INTENCLR;		/*!< DMA Interrupt Enable Clear for all DMA channels */
+	volatile  uint32_t  RESERVED6;
+	volatile  uint32_t  INTA;			/*!< DMA Interrupt A status for all DMA channels */
+	volatile  uint32_t  RESERVED7;
+	volatile  uint32_t  INTB;			/*!< DMA Interrupt B status for all DMA channels */
+	volatile  uint32_t  RESERVED8;
+	volatile  uint32_t  SETVALID;		/*!< DMA Set ValidPending control bits for all DMA channels */
+	volatile  uint32_t  RESERVED9;
+	volatile  uint32_t  SETTRIG;			/*!< DMA Set Trigger control bits for all DMA channels */
+	volatile  uint32_t  RESERVED10;
+	volatile  uint32_t  ABORT;			/*!< DMA Channel Abort control for all DMA channels */
+} LPC_DMA_COMMON_T;
+
+/**
+ * @brief DMA Controller shared registers structure
+ */
+typedef struct {					/*!< DMA channel register structure */
+	volatile  uint32_t  CFG;				/*!< DMA Configuration register */
+	volatile  uint32_t  CTLSTAT;			/*!< DMA Control and status register */
+	volatile  uint32_t  XFERCFG;			/*!< DMA Transfer configuration register */
+	volatile  uint32_t  RESERVED;
+} LPC_DMA_CHANNEL_T;
+
+/* On LPC540XX, Max DMA channel is 22 */
+#define MAX_DMA_CHANNEL         (22)
+
+/**
+ * @brief DMA Controller register block structure
+ */
+typedef struct {					/*!< DMA Structure */
+	volatile  uint32_t  CTRL;			/*!< DMA control register */
+	volatile  uint32_t  INTSTAT;			/*!< DMA Interrupt status register */
+	volatile  uint32_t  SRAMBASE;		/*!< DMA SRAM address of the channel configuration table */
+	volatile  uint32_t  RESERVED2[5];
+	LPC_DMA_COMMON_T DMACOMMON[1];	/*!< DMA shared channel (common) registers */
+	volatile  uint32_t  RESERVED0[225];
+	LPC_DMA_CHANNEL_T DMACH[MAX_DMA_CHANNEL];	/*!< DMA channel registers */
+} LPC_DMA_T;
+
+/* DMA interrupt status bits (common) */
+#define DMA_INTSTAT_ACTIVEINT       0x2		/*!< Summarizes whether any enabled interrupts are pending */
+#define DMA_INTSTAT_ACTIVEERRINT    0x4		/*!< Summarizes whether any error interrupts are pending */
+
+/* Support macro for DMA_CHDESC_T */
+#define DMA_ADDR(addr)      ((uint32_t) (addr))
+
+/* Support definitions for setting the configuration of a DMA channel. You
+   will need to get more information on these options from the User manual. */
+#define DMA_CFG_PERIPHREQEN     (1 << 0)	/*!< Enables Peripheral DMA requests */
+#define DMA_CFG_HWTRIGEN        (1 << 1)	/*!< Use hardware triggering via imput mux */
+#define DMA_CFG_TRIGPOL_LOW     (0 << 4)	/*!< Hardware trigger is active low or falling edge */
+#define DMA_CFG_TRIGPOL_HIGH    (1 << 4)	/*!< Hardware trigger is active high or rising edge */
+#define DMA_CFG_TRIGTYPE_EDGE   (0 << 5)	/*!< Hardware trigger is edge triggered */
+#define DMA_CFG_TRIGTYPE_LEVEL  (1 << 5)	/*!< Hardware trigger is level triggered */
+#define DMA_CFG_TRIGBURST_SNGL  (0 << 6)	/*!< Single transfer. Hardware trigger causes a single transfer */
+#define DMA_CFG_TRIGBURST_BURST (1 << 6)	/*!< Burst transfer (see UM) */
+#define DMA_CFG_BURSTPOWER_1    (0 << 8)	/*!< Set DMA burst size to 1 transfer */
+#define DMA_CFG_BURSTPOWER_2    (1 << 8)	/*!< Set DMA burst size to 2 transfers */
+#define DMA_CFG_BURSTPOWER_4    (2 << 8)	/*!< Set DMA burst size to 4 transfers */
+#define DMA_CFG_BURSTPOWER_8    (3 << 8)	/*!< Set DMA burst size to 8 transfers */
+#define DMA_CFG_BURSTPOWER_16   (4 << 8)	/*!< Set DMA burst size to 16 transfers */
+#define DMA_CFG_BURSTPOWER_32   (5 << 8)	/*!< Set DMA burst size to 32 transfers */
+#define DMA_CFG_BURSTPOWER_64   (6 << 8)	/*!< Set DMA burst size to 64 transfers */
+#define DMA_CFG_BURSTPOWER_128  (7 << 8)	/*!< Set DMA burst size to 128 transfers */
+#define DMA_CFG_BURSTPOWER_256  (8 << 8)	/*!< Set DMA burst size to 256 transfers */
+#define DMA_CFG_BURSTPOWER_512  (9 << 8)	/*!< Set DMA burst size to 512 transfers */
+#define DMA_CFG_BURSTPOWER_1024 (10 << 8)	/*!< Set DMA burst size to 1024 transfers */
+#define DMA_CFG_BURSTPOWER(n)   ((n) << 8)	/*!< Set DMA burst size to 2^n transfers, max n=10 */
+#define DMA_CFG_SRCBURSTWRAP    (1 << 14)	/*!< Source burst wrapping is enabled for this DMA channel */
+#define DMA_CFG_DSTBURSTWRAP    (1 << 15)	/*!< Destination burst wrapping is enabled for this DMA channel */
+#define DMA_CFG_CHPRIORITY(p)   ((p) << 16)	/*!< Sets DMA channel priority, min 0 (highest), max 3 (lowest) */
+
+/* DMA channel control and status register definitions */
+#define DMA_CTLSTAT_VALIDPENDING    (1 << 0)	/*!< Valid pending flag for this channel */
+#define DMA_CTLSTAT_TRIG            (1 << 2)	/*!< Trigger flag. Indicates that the trigger for this channel is currently set */
+
+/* DMA channel transfer configuration registers definitions */
+#define DMA_XFERCFG_CFGVALID        (1 << 0)	/*!< Configuration Valid flag */
+#define DMA_XFERCFG_RELOAD          (1 << 1)	/*!< Indicates whether the channels control structure will be reloaded when the current descriptor is exhausted */
+#define DMA_XFERCFG_SWTRIG          (1 << 2)	/*!< Software Trigger */
+#define DMA_XFERCFG_CLRTRIG         (1 << 3)	/*!< Clear Trigger */
+#define DMA_XFERCFG_SETINTA         (1 << 4)	/*!< Set Interrupt flag A for this channel to fire when descriptor is complete */
+#define DMA_XFERCFG_SETINTB         (1 << 5)	/*!< Set Interrupt flag B for this channel to fire when descriptor is complete */
+#define DMA_XFERCFG_WIDTH_8         (0 << 8)	/*!< 8-bit transfers are performed */
+#define DMA_XFERCFG_WIDTH_16        (1 << 8)	/*!< 16-bit transfers are performed */
+#define DMA_XFERCFG_WIDTH_32        (2 << 8)	/*!< 32-bit transfers are performed */
+#define DMA_XFERCFG_SRCINC_0        (0 << 12)	/*!< DMA source address is not incremented after a transfer */
+#define DMA_XFERCFG_SRCINC_1        (1 << 12)	/*!< DMA source address is incremented by 1 (width) after a transfer */
+#define DMA_XFERCFG_SRCINC_2        (2 << 12)	/*!< DMA source address is incremented by 2 (width) after a transfer */
+#define DMA_XFERCFG_SRCINC_4        (3 << 12)	/*!< DMA source address is incremented by 4 (width) after a transfer */
+#define DMA_XFERCFG_DSTINC_0        (0 << 14)	/*!< DMA destination address is not incremented after a transfer */
+#define DMA_XFERCFG_DSTINC_1        (1 << 14)	/*!< DMA destination address is incremented by 1 (width) after a transfer */
+#define DMA_XFERCFG_DSTINC_2        (2 << 14)	/*!< DMA destination address is incremented by 2 (width) after a transfer */
+#define DMA_XFERCFG_DSTINC_4        (3 << 14)	/*!< DMA destination address is incremented by 4 (width) after a transfer */
+#define DMA_XFERCFG_XFERCOUNT(n)    ((n - 1) << 16)	/*!< DMA transfer count in 'transfers', between (0)1 and (1023)1024 */
+
+#endif /* __HW_DMA_REGS_H_ */

bsp/lpc5410x/Libraries/lpc_chip/chip_5410x/hw_dmaaltd_rom_api.c

@@ -0,0 +1,53 @@
+/*
+ * @brief DMA controller ROM API declarations and functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2014
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#include "hw_dmaaltd.h"
+
+const ROM_DMAALTD_API_T  dmaalt_api = {
+	&dmaalt_get_mem_size,
+	&dmaalt_init,
+	&dmaalt_setup_channel,
+	&dmaalt_init_queue,
+	&dmaalt_register_queue_callback,
+	&dmaalt_build_descriptor_chain,
+	&dmaalt_get_transfer_count,
+	&dmaalt_unstall_descriptor_chain,
+	&dmaalt_queue_descriptor,
+	&dmaalt_get_queue_pop_descriptor_status,
+	&dmaalt_unqueue_descriptor,
+	&dmaalt_start_queue,
+	&dmaalt_stop_queue,
+	&dmaalt_flush_queue,
+	&dmaalt_get_queue_state,
+	&dmaalt_force_trigger,
+	&dmaalt_handler,
+	&dmaalt_get_driver_version
+};		// end of table ************************************