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添加 imxrt1060-evk BSP (#5657)
* 添加 imxrt1060-evk BSP * add LVGL * add README.md * Delete irrelevant files * Modify the optimization level to O1 * Organize documents * Source code formatting
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# files format check exclude path, please follow the instructions below to modify;
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dir_path:
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- board/board.c
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- board/MCUX_Config
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- xip
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mainmenu "RT-Thread Configuration"
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "../libraries/Kconfig"
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source "board/Kconfig"
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# BSP README 模板
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## 简介
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本文档为 MIMXRT1060-EVK 开发板的 BSP (板级支持包) 说明。
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主要内容如下：
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- 开发板资源介绍
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- BSP 快速上手
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- 进阶使用方法
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通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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## 开发板介绍
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开发板外观如下图所示：
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该开发板常用 **板载资源** 如下：
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- MCU：MIMXRT1062DVL6A，主频 600MHz，4096KB FLASH ，1024KB RAM
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- 外部 RAM：型号IS42S16160J-6BLI，32MB
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- 外部 FLASH：型号S26KS512SDPBHI02，64MB
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- 常用外设
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- LED：1个，D18（绿色）
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- 按键：1个
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- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口等
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- 调试接口，标准 JTAG/SWD
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开发板更多详细信息请参考【NXP】 [MIMXRT1060-EVK开发板介绍](https://www.nxp.com.cn/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1060-evaluation-kit:MIMXRT1060-EVK)。
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## 外设支持
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本 BSP 目前对外设的支持情况如下：
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| **板载外设** | **支持情况** | **备注** |
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| :----------------- | :----------: | :------------------------------------- |
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| USB 转串口 | 支持 | |
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| SPI Flash | 支持 | |
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| 以太网 | 支持 | |
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
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| UART | 支持 | UART1 |
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| SPI | 暂不支持 | 即将支持 |
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| I2C | 暂不支持 | 即将支持 |
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| SDIO | 暂不支持 | 即将支持 |
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| RTC | 暂不支持 | 即将支持 |
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| PWM | 暂不支持 | 即将支持 |
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| USB Device | 暂不支持 | 即将支持 |
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| USB Host | 暂不支持 | 即将支持 |
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| IWG | 暂不支持 | 即将支持 |
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| **扩展模块** | **支持情况** | **备注** |
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| LVGL | 支持 | |
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## 使用说明
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使用说明分为如下两个章节：
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- 快速上手
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本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
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- 进阶使用
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本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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### 快速上手
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本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，以及GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
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#### 硬件连接
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使用数据线连接开发板到 PC，打开电源开关。
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#### 编译下载
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双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
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> 工程默认配置使用 CMSIS-DAP 仿真器下载程序，在通过 USB 连接开发板的基础上，点击下载按钮即可下载程序到开发板
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#### 运行结果
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下载程序成功之后，系统会自动运行，LED会以1Hz的频率闪烁。
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连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
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```bash
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\ | /
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- RT - Thread Operating System
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/ | \ 4.1.0 build Mar 10 2022 18:07:41
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2006 - 2022 Copyright by RT-Thread team
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msh >
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```
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### 进阶使用
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此 BSP 默认只开启了 GPIO 和 串口1 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置(暂时还不支持，等待第二阶段)，步骤如下：
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1. 在 bsp 下打开 env 工具。
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2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
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3. 输入`pkgs --update`命令更新软件包。
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4. 输入`scons --target=mdk/iar` 命令重新生成工程。
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本章节更多详细的介绍请参考 [IMXRT 系列 BSP 外设驱动使用教程](../docs/IMXRT系列BSP外设驱动使用教程.md)。
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@@ -0,0 +1,14 @@
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# for module compiling
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -0,0 +1,73 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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DefaultEnvironment(tools=[])
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if rtconfig.PLATFORM == 'armcc':
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
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# overwrite cflags, because cflags has '--C99'
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CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES')
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else:
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
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CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
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CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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if rtconfig.PLATFORM == 'iar':
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env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
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env.Replace(ARFLAGS = [''])
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env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(SDK_ROOT + '/libraries'):
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libraries_path_prefix = SDK_ROOT + '/libraries'
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else:
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libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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imxrt_library = 'MIMXRT1060'
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rtconfig.BSP_LIBRARY_TYPE = imxrt_library
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# include libraries
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objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SConscript')))
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# include drivers
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
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# include peripherals
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript')))
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# make a building
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DoBuilding(TARGET, objs)
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import rtconfig
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd]
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# add for startup script
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if rtconfig.CROSS_TOOL == 'gcc':
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CPPDEFINES = ['__START=entry']
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else:
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CPPDEFINES = []
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
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list = os.listdir(cwd)
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for item in list:
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if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
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group = group + SConscript(os.path.join(item, 'SConscript'))
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Return('group')
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import os
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from building import *
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cwd = GetCurrentDir()
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group = []
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src = Glob('*.c')
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CPPPATH = [cwd]
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CPPDEFINES = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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group = group + SConscript(os.path.join(d, 'SConscript'))
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group = group + DefineGroup('LVGL-port', src, depend = ['BSP_USING_LVGL'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
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Return('group')
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@@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-18 Meco Man First version
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*/
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#ifndef LV_CONF_H
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#define LV_CONF_H
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#define LV_USE_PERF_MONITOR 1
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#define LV_COLOR_DEPTH 16
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#define LV_USE_NXP_SOC 1
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//#define LV_USE_GPU_NXP_PXP 1
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//#define LV_USE_GPU_NXP_VG_LITE 0
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//#define LV_USE_GPU_NXP_PXP_AUTO_INIT 1
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#define LV_ATTRIBUTE_MEM_ALIGN_SIZE 64
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/* music player demo */
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#define LV_HOR_RES_MAX 480
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#define LV_VER_RES_MAX 272
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#define LV_USE_DEMO_RTT_MUSIC 1
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#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1
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#define LV_FONT_MONTSERRAT_12 1
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#define LV_FONT_MONTSERRAT_16 1
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#endif
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@@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-17 Meco Man First version
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*/
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#include <rtthread.h>
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#include <lvgl.h>
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#include <lv_port_indev.h>
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#define DBG_TAG "LVGL.demo"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#ifndef LV_THREAD_STACK_SIZE
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#define LV_THREAD_STACK_SIZE 4096
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#endif
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#ifndef LV_THREAD_PRIO
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#define LV_THREAD_PRIO (RT_THREAD_PRIORITY_MAX * 2 / 8)
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#endif
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static struct rt_thread lvgl_thread;
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static rt_uint8_t lvgl_thread_stack[LV_THREAD_STACK_SIZE];
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static void lvgl_entry(void *parameter)
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{
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extern void lv_demo_music(void);
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lv_demo_music();
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while(1)
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{
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lv_task_handler();
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rt_thread_mdelay(5);
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}
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}
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static int lvgl_demo_init(void)
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{
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rt_thread_t tid;
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rt_thread_init(&lvgl_thread,
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"LVGL",
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lvgl_entry,
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RT_NULL,
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&lvgl_thread_stack[0],
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sizeof(lvgl_thread_stack),
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LV_THREAD_PRIO,
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10);
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rt_thread_startup(&lvgl_thread);
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return 0;
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}
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INIT_APP_EXPORT(lvgl_demo_init);
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@@ -0,0 +1,242 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
|
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*
|
||||
* SPDX-License-Identifier: Apache-2.0
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*
|
||||
* Change Logs:
|
||||
* Date Author Notes
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* 2021-10-18 Meco Man The first version
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* 2021-12-24 Rb Refresh using dma2d
|
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*/
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#include <lvgl.h>
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//#define DRV_DEBUG
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#define LOG_TAG "LVGL.port.disp"
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#include <drv_log.h>
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#if LV_USE_NXP_SOC
|
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#include "fsl_gpio.h"
|
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#include "fsl_elcdif.h"
|
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#include "fsl_cache.h"
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#endif
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|
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/*A static or global variable to store the buffers*/
|
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static lv_disp_draw_buf_t disp_buf;
|
||||
|
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static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/
|
||||
|
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/* Macros for panel. */
|
||||
#define LCD_WIDTH 480
|
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#define LCD_HEIGHT 272
|
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#define LCD_FB_BYTE_PER_PIXEL 2
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#define LCD_HSW 41
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#define LCD_HFP 4
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#define LCD_HBP 8
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#define LCD_VSW 10
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#define LCD_VFP 4
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#define LCD_VBP 2
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#define LCD_POL_FLAGS \
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(kELCDIF_DataEnableActiveHigh | kELCDIF_VsyncActiveLow | kELCDIF_HsyncActiveLow | kELCDIF_DriveDataOnRisingClkEdge)
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#define LCD_LCDIF_DATA_BUS kELCDIF_DataBus16Bit
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|
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/* Back light. */
|
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#define LCD_BL_GPIO GPIO2
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#define LCD_BL_GPIO_PIN 31
|
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|
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#define DEMO_FB_ALIGN LV_ATTRIBUTE_MEM_ALIGN_SIZE
|
||||
#define DISP_BUF_SIZE (((LCD_WIDTH * LCD_HEIGHT * LCD_FB_BYTE_PER_PIXEL) + DEMO_FB_ALIGN - 1) & ~(DEMO_FB_ALIGN - 1))
|
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|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
static volatile bool s_framePending;
|
||||
|
||||
static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/
|
||||
|
||||
SDK_ALIGN(static uint8_t s_frameBuffer[2][DISP_BUF_SIZE], DEMO_FB_ALIGN);
|
||||
|
||||
static rt_sem_t s_frameSema = RT_NULL;
|
||||
|
||||
static void lcd_fb_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
|
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{
|
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rt_sem_take(s_frameSema, RT_WAITING_FOREVER);
|
||||
|
||||
DCACHE_CleanInvalidateByRange((uint32_t)color_p, DISP_BUF_SIZE);
|
||||
|
||||
ELCDIF_SetNextBufferAddr(LCDIF, (uint32_t)color_p);
|
||||
|
||||
s_framePending = true;
|
||||
}
|
||||
|
||||
static void DEMO_InitLcdClock(void)
|
||||
{
|
||||
/*
|
||||
* The desired output frame rate is 60Hz. So the pixel clock frequency is:
|
||||
* (480 + 41 + 4 + 18) * (272 + 10 + 4 + 2) * 60 = 9.2M.
|
||||
* Here set the LCDIF pixel clock to 9.3M.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Initialize the Video PLL.
|
||||
* Video PLL output clock is OSC24M * (loopDivider + (denominator / numerator)) / postDivider = 93MHz.
|
||||
*/
|
||||
clock_video_pll_config_t config =
|
||||
{
|
||||
.loopDivider = 31,
|
||||
.postDivider = 8,
|
||||
.numerator = 0,
|
||||
.denominator = 0,
|
||||
};
|
||||
|
||||
CLOCK_InitVideoPll(&config);
|
||||
|
||||
/*
|
||||
* 000 derive clock from PLL2
|
||||
* 001 derive clock from PLL3 PFD3
|
||||
* 010 derive clock from PLL5
|
||||
* 011 derive clock from PLL2 PFD0
|
||||
* 100 derive clock from PLL2 PFD1
|
||||
* 101 derive clock from PLL3 PFD1
|
||||
*/
|
||||
CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);
|
||||
|
||||
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 4);
|
||||
|
||||
CLOCK_SetDiv(kCLOCK_LcdifDiv, 1);
|
||||
}
|
||||
|
||||
static void DEMO_InitLcdBackLight(void)
|
||||
{
|
||||
const gpio_pin_config_t config =
|
||||
{
|
||||
kGPIO_DigitalOutput,
|
||||
1,
|
||||
kGPIO_NoIntmode,
|
||||
};
|
||||
|
||||
/* Backlight. */
|
||||
GPIO_PinInit(LCD_BL_GPIO, LCD_BL_GPIO_PIN, &config);
|
||||
}
|
||||
|
||||
#if LV_USE_GPU_NXP_PXP
|
||||
static void DEMO_CleanInvalidateCache(lv_disp_drv_t *disp_drv)
|
||||
{
|
||||
SCB_CleanInvalidateDCache();
|
||||
}
|
||||
#endif
|
||||
|
||||
static void DEMO_InitLcd(void)
|
||||
{
|
||||
/* Initialize the display. */
|
||||
const elcdif_rgb_mode_config_t config =
|
||||
{
|
||||
.panelWidth = LCD_WIDTH,
|
||||
.panelHeight = LCD_HEIGHT,
|
||||
.hsw = LCD_HSW,
|
||||
.hfp = LCD_HFP,
|
||||
.hbp = LCD_HBP,
|
||||
.vsw = LCD_VSW,
|
||||
.vfp = LCD_VFP,
|
||||
.vbp = LCD_VBP,
|
||||
.polarityFlags = LCD_POL_FLAGS,
|
||||
/* lvgl starts render in frame buffer 0, so show frame buffer 1 first. */
|
||||
.bufferAddr = (uint32_t)s_frameBuffer[1],
|
||||
.pixelFormat = kELCDIF_PixelFormatRGB565,
|
||||
.dataBus = LCD_LCDIF_DATA_BUS,
|
||||
};
|
||||
|
||||
/* Clear frame buffer. */
|
||||
rt_memset((void *)s_frameBuffer, 0, sizeof(s_frameBuffer));
|
||||
|
||||
s_frameSema = rt_sem_create("lvgl_sem", 1, RT_IPC_FLAG_PRIO);
|
||||
|
||||
if (RT_NULL == s_frameSema)
|
||||
{
|
||||
rt_kprintf("lvgl semaphore create failed\r\n");
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
|
||||
/* No frame pending. */
|
||||
s_framePending = false;
|
||||
|
||||
NVIC_SetPriority(LCDIF_IRQn, 3);
|
||||
|
||||
DEMO_InitLcdClock();
|
||||
|
||||
ELCDIF_RgbModeInit(LCDIF, &config);
|
||||
|
||||
ELCDIF_EnableInterrupts(LCDIF, kELCDIF_CurFrameDoneInterruptEnable);
|
||||
|
||||
NVIC_EnableIRQ(LCDIF_IRQn);
|
||||
|
||||
ELCDIF_RgbModeStart(LCDIF);
|
||||
|
||||
DEMO_InitLcdBackLight();
|
||||
}
|
||||
|
||||
void LCDIF_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
uint32_t intStatus = ELCDIF_GetInterruptStatus(LCDIF);
|
||||
|
||||
ELCDIF_ClearInterruptStatus(LCDIF, intStatus);
|
||||
|
||||
if (s_framePending)
|
||||
{
|
||||
if (intStatus & kELCDIF_CurFrameDone)
|
||||
{
|
||||
/* IMPORTANT!!!
|
||||
* Inform the graphics library that you are ready with the flushing*/
|
||||
lv_disp_flush_ready(&disp_drv);
|
||||
|
||||
s_framePending = false;
|
||||
|
||||
rt_sem_release(s_frameSema);
|
||||
}
|
||||
}
|
||||
|
||||
rt_interrupt_leave();
|
||||
|
||||
SDK_ISR_EXIT_BARRIER;
|
||||
}
|
||||
|
||||
void lv_port_disp_init(void)
|
||||
{
|
||||
static lv_disp_draw_buf_t disp_buf;
|
||||
|
||||
lv_disp_draw_buf_init(&disp_buf, s_frameBuffer[0], s_frameBuffer[1], LCD_WIDTH * LCD_HEIGHT);
|
||||
|
||||
/*-------------------------
|
||||
* Initialize your display
|
||||
* -----------------------*/
|
||||
DEMO_InitLcd();
|
||||
|
||||
/*-----------------------------------
|
||||
* Register the display in LittlevGL
|
||||
*----------------------------------*/
|
||||
|
||||
lv_disp_drv_init(&disp_drv); /*Basic initialization*/
|
||||
|
||||
/*Set up the functions to access to your display*/
|
||||
|
||||
/*Set the resolution of the display*/
|
||||
disp_drv.hor_res = LCD_WIDTH;
|
||||
disp_drv.ver_res = LCD_HEIGHT;
|
||||
|
||||
/*Used to copy the buffer's content to the display*/
|
||||
disp_drv.flush_cb = lcd_fb_flush;
|
||||
|
||||
#if LV_USE_GPU_NXP_PXP
|
||||
disp_drv.clean_dcache_cb = DEMO_CleanInvalidateCache;
|
||||
#endif
|
||||
|
||||
/*Set a display buffer*/
|
||||
disp_drv.draw_buf = &disp_buf;
|
||||
|
||||
/* Partial refresh */
|
||||
disp_drv.full_refresh = 1;
|
||||
|
||||
/*Finally register the driver*/
|
||||
lv_disp_drv_register(&disp_drv);
|
||||
}
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-10-18 Meco Man The first version
|
||||
*/
|
||||
#ifndef LV_PORT_DISP_H
|
||||
#define LV_PORT_DISP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void lv_port_disp_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /*extern "C"*/
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-10-18 Meco Man The first version
|
||||
*/
|
||||
#include <lvgl.h>
|
||||
#include <stdbool.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
static lv_indev_state_t last_state = LV_INDEV_STATE_REL;
|
||||
static rt_int16_t last_x = 0;
|
||||
static rt_int16_t last_y = 0;
|
||||
|
||||
static void input_read(lv_indev_drv_t *indev_drv, lv_indev_data_t *data)
|
||||
{
|
||||
data->point.x = last_x;
|
||||
data->point.y = last_y;
|
||||
data->state = last_state;
|
||||
}
|
||||
|
||||
void lv_port_indev_input(rt_int16_t x, rt_int16_t y, lv_indev_state_t state)
|
||||
{
|
||||
last_state = state;
|
||||
last_x = x;
|
||||
last_y = LV_HOR_RES_MAX - y;
|
||||
}
|
||||
|
||||
lv_indev_t * button_indev;
|
||||
|
||||
void lv_port_indev_init(void)
|
||||
{
|
||||
static lv_indev_drv_t indev_drv;
|
||||
|
||||
lv_indev_drv_init(&indev_drv); /*Basic initialization*/
|
||||
indev_drv.type = LV_INDEV_TYPE_POINTER;
|
||||
indev_drv.read_cb = input_read;
|
||||
|
||||
/*Register the driver in LVGL and save the created input device object*/
|
||||
button_indev = lv_indev_drv_register(&indev_drv);
|
||||
}
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-10-18 Meco Man The first version
|
||||
*/
|
||||
#ifndef LV_PORT_INDEV_H
|
||||
#define LV_PORT_INDEV_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <lv_hal_indev.h>
|
||||
|
||||
extern lv_indev_t * button_indev;
|
||||
|
||||
void lv_port_indev_init(void);
|
||||
void lv_port_indev_input(rt_int16_t x, rt_int16_t y, lv_indev_state_t state);
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /*extern "C"*/
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-04-29 tyustli first version
|
||||
*/
|
||||
|
||||
#include "MIMXRT1062.h"
|
||||
#include <rtdevice.h>
|
||||
#include "drv_gpio.h"
|
||||
#include "core_cm7.h"
|
||||
|
||||
/* defined the LED pin: GPIO1_IO9 */
|
||||
#define LED0_PIN GET_PIN(1, 9)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
#ifndef PHY_USING_KSZ8081
|
||||
/* set LED0 pin mode to output */
|
||||
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED0_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED0_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void reboot(void)
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
MSH_CMD_EXPORT(reboot, reset system)
|
||||
@@ -0,0 +1,127 @@
|
||||
menu "Hardware Drivers Config"
|
||||
|
||||
|
||||
config BSP_USING_HYPERFLASH
|
||||
bool
|
||||
default n
|
||||
|
||||
config BSP_USING_4MFLASH
|
||||
bool
|
||||
default n
|
||||
|
||||
config SOC_MIMXRT1062DVL6A
|
||||
bool
|
||||
select SOC_MIMXRT1062_SERIES
|
||||
select BSP_USING_4MFLASH
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_LPUART
|
||||
bool "Enable UART"
|
||||
select RT_USING_SERIAL
|
||||
default y
|
||||
if BSP_USING_LPUART
|
||||
config BSP_USING_LPUART1
|
||||
bool "Enable LPUART1"
|
||||
default y
|
||||
config BSP_USING_LPUART2
|
||||
bool "Enable LPUART2"
|
||||
default n
|
||||
config BSP_USING_LPUART3
|
||||
bool "Enable LPUART3"
|
||||
default n
|
||||
config BSP_USING_LPUART4
|
||||
bool "Enable LPUART4"
|
||||
default n
|
||||
config BSP_USING_LPUART5
|
||||
bool "Enable LPUART5"
|
||||
default n
|
||||
config BSP_USING_LPUART6
|
||||
bool "Enable LPUART6"
|
||||
default n
|
||||
config BSP_USING_LPUART7
|
||||
bool "Enable LPUART7"
|
||||
default n
|
||||
config BSP_USING_LPUART8
|
||||
bool "Enable LPUART8"
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_PXP
|
||||
bool "Enable PXP"
|
||||
default n
|
||||
|
||||
config BSP_USING_CACHE
|
||||
bool "Enable CACHE"
|
||||
default n
|
||||
|
||||
menuconfig BSP_USING_LCD
|
||||
bool "Enable LCD"
|
||||
default n
|
||||
if BSP_USING_LCD
|
||||
config LCD_WIDTH
|
||||
int "width"
|
||||
default 480
|
||||
|
||||
config LCD_HEIGHT
|
||||
int "height"
|
||||
default 272
|
||||
|
||||
config LCD_HFP
|
||||
int "HFP"
|
||||
default 4
|
||||
config LCD_VFP
|
||||
int "VFP"
|
||||
default 4
|
||||
config LCD_HBP
|
||||
int "HBP"
|
||||
default 8
|
||||
config LCD_VBP
|
||||
int "VBP"
|
||||
default 2
|
||||
config LCD_HSW
|
||||
int "HSW"
|
||||
default 40
|
||||
config LCD_VSW
|
||||
int "VSW"
|
||||
default 10
|
||||
config LCD_BL_PIN
|
||||
int "Backlight ctrl pin"
|
||||
default 63
|
||||
config LCD_RST_PIN
|
||||
int "Reset pin"
|
||||
default 2
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Onboard Peripheral Drivers"
|
||||
|
||||
config BSP_USING_SDRAM
|
||||
bool "Enable SDRAM"
|
||||
default n
|
||||
|
||||
config BSP_USING_LVGL
|
||||
bool "Enable LVGL for LCD"
|
||||
select BSP_USING_LCD
|
||||
select PKG_USING_LVGL
|
||||
select PKG_USING_LV_MUSIC_DEMO
|
||||
select BSP_USING_PXP
|
||||
select BSP_USING_CACHE
|
||||
default n
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Board extended module Drivers"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,399 @@
|
||||
<?xml version="1.0" encoding= "UTF-8" ?>
|
||||
<configuration name="MIMXRT1062xxxxA" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8 http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8.xsd" uuid="22c3ac06-9f09-4f14-9c74-93bdfd15fb8a" version="1.8" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_1.8" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<common>
|
||||
<processor>MIMXRT1062xxxxA</processor>
|
||||
<package>MIMXRT1062DVL6A</package>
|
||||
<board>MIMXRT1060-EVK</board>
|
||||
<mcu_data>ksdk2_0</mcu_data>
|
||||
<cores selected="core0">
|
||||
<core name="Cortex-M7F" id="core0" description="M7 core"/>
|
||||
</cores>
|
||||
<description></description>
|
||||
</common>
|
||||
<preferences>
|
||||
<validate_boot_init_only>true</validate_boot_init_only>
|
||||
<generate_extended_information>false</generate_extended_information>
|
||||
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
|
||||
</preferences>
|
||||
<tools>
|
||||
<pins name="Pins" version="8.0" enabled="true" update_project_code="true">
|
||||
<pins_profile>
|
||||
<processor_version>0.8.11</processor_version>
|
||||
<power_domains/>
|
||||
</pins_profile>
|
||||
<functions_list>
|
||||
<function name="BOARD_InitPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>true</callFromInitBoot>
|
||||
<coreID>core0</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="Peripheral" resourceId="ARM" description="Peripheral ARM is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="LPUART1" signal="RX" pin_num="L14" pin_signal="GPIO_AD_B0_13">
|
||||
<pin_features>
|
||||
<pin_feature name="software_input_on" value="Disable"/>
|
||||
<pin_feature name="hysteresis_enable" value="Disable"/>
|
||||
<pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
|
||||
<pin_feature name="pull_keeper_select" value="Keeper"/>
|
||||
<pin_feature name="pull_keeper_enable" value="Enable"/>
|
||||
<pin_feature name="open_drain" value="Disable"/>
|
||||
<pin_feature name="speed" value="MHZ_100"/>
|
||||
<pin_feature name="drive_strength" value="R0_6"/>
|
||||
<pin_feature name="slew_rate" value="Slow"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="LPUART1" signal="TX" pin_num="K14" pin_signal="GPIO_AD_B0_12">
|
||||
<pin_features>
|
||||
<pin_feature name="software_input_on" value="Disable"/>
|
||||
<pin_feature name="hysteresis_enable" value="Disable"/>
|
||||
<pin_feature name="pull_up_down_config" value="Pull_Down_100K_Ohm"/>
|
||||
<pin_feature name="pull_keeper_select" value="Keeper"/>
|
||||
<pin_feature name="pull_keeper_enable" value="Enable"/>
|
||||
<pin_feature name="open_drain" value="Disable"/>
|
||||
<pin_feature name="speed" value="MHZ_100"/>
|
||||
<pin_feature name="drive_strength" value="R0_6"/>
|
||||
<pin_feature name="slew_rate" value="Slow"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="ARM" signal="arm_trace_swo" pin_num="G13" pin_signal="GPIO_AD_B0_10">
|
||||
<pin_features>
|
||||
<pin_feature name="slew_rate" value="Fast"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
</pins>
|
||||
</function>
|
||||
</functions_list>
|
||||
</pins>
|
||||
<clocks name="Clocks" version="7.0" enabled="true" update_project_code="true">
|
||||
<clocks_profile>
|
||||
<processor_version>0.8.11</processor_version>
|
||||
</clocks_profile>
|
||||
<clock_configurations>
|
||||
<clock_configuration name="BOARD_BootClockRUN">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtali" description="'RTC_XTALI' (Pins tool id: XTALOSC24M.rtc_xtali, Clocks tool id: XTALOSC24M.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>INPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: XTALOSC24M.rtc_xtalo, Clocks tool id: XTALOSC24M.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>OUTPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtali" description="'XTALI' (Pins tool id: XTALOSC24M.xtali, Clocks tool id: XTALOSC24M.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>INPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PinSignal" resourceId="XTALOSC24M.xtalo" description="'XTALO' (Pins tool id: XTALOSC24M.xtalo, Clocks tool id: XTALOSC24M.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>OUTPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="core0">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources>
|
||||
<clock_source id="XTALOSC24M.RTC_OSC.outFreq" value="32.768 kHz" locked="false" enabled="true"/>
|
||||
</clock_sources>
|
||||
<clock_outputs>
|
||||
<clock_output id="AHB_CLK_ROOT.outFreq" value="600 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CAN_CLK_ROOT.outFreq" value="40 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CKIL_SYNC_CLK_ROOT.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CSI_CLK_ROOT.outFreq" value="12 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET1_TX_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET2_125M_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET2_TX_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_125M_CLK.outFreq" value="2.4 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_25M_REF_CLK.outFreq" value="1.2 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXSPI_CLK_ROOT.outFreq" value="1440/11 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="75 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="IPG_CLK_ROOT.outFreq" value="150 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LCDIF_CLK_ROOT.outFreq" value="67.5 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C_CLK_ROOT.outFreq" value="60 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI_CLK_ROOT.outFreq" value="105.6 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LVDS1_CLK.outFreq" value="1.2 GHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MQS_MCLK.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="PERCLK_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="PLL7_MAIN_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK2.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_CLK_ROOT.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_MCLK1.outFreq" value="1080/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_MCLK3.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SEMC_CLK_ROOT.outFreq" value="75 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SPDIF0_CLK_ROOT.outFreq" value="30 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="TRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="UART_CLK_ROOT.outFreq" value="80 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="CCM.AHB_PODF.scale" value="1" locked="true"/>
|
||||
<setting id="CCM.ARM_PODF.scale" value="2" locked="true"/>
|
||||
<setting id="CCM.FLEXSPI2_PODF.scale" value="2" locked="true"/>
|
||||
<setting id="CCM.FLEXSPI2_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
|
||||
<setting id="CCM.FLEXSPI_PODF.scale" value="2" locked="true"/>
|
||||
<setting id="CCM.FLEXSPI_SEL.sel" value="CCM_ANALOG.PLL3_PFD0_CLK" locked="false"/>
|
||||
<setting id="CCM.LPSPI_PODF.scale" value="5" locked="true"/>
|
||||
<setting id="CCM.PERCLK_PODF.scale" value="2" locked="true"/>
|
||||
<setting id="CCM.SEMC_PODF.scale" value="8" locked="false"/>
|
||||
<setting id="CCM.TRACE_CLK_SEL.sel" value="CCM_ANALOG.PLL2_MAIN_CLK" locked="false"/>
|
||||
<setting id="CCM.TRACE_PODF.scale" value="4" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL1_BYPASS.sel" value="CCM_ANALOG.PLL1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL1_PREDIV.scale" value="1" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL1_VDIV.scale" value="50" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2.denom" value="1" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2.num" value="0" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL2_BYPASS.sel" value="CCM_ANALOG.PLL2_OUT_CLK" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD0" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD2" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL2_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL2_PFD3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_BYPASS.sel" value="CCM_ANALOG.PLL3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD0" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_DIV.scale" value="33" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD0_MUL.scale" value="18" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD1_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD2_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD2" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL3_PFD3_BYPASS.sel" value="CCM_ANALOG.PLL3_PFD3" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL4.denom" value="50" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL4.div" value="47" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL5.denom" value="1" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL5.div" value="31" locked="true"/>
|
||||
<setting id="CCM_ANALOG.PLL5.num" value="0" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL5_BYPASS.sel" value="CCM_ANALOG.PLL5_POST_DIV" locked="false"/>
|
||||
<setting id="CCM_ANALOG.PLL5_POST_DIV.scale" value="2" locked="false"/>
|
||||
<setting id="CCM_ANALOG.VIDEO_DIV.scale" value="4" locked="false"/>
|
||||
<setting id="CCM_ANALOG_PLL_ENET_POWERDOWN_CFG" value="Yes" locked="false"/>
|
||||
<setting id="CCM_ANALOG_PLL_USB1_POWER_CFG" value="Yes" locked="false"/>
|
||||
<setting id="CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG" value="No" locked="false"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>true</called_from_default_init>
|
||||
</clock_configuration>
|
||||
</clock_configurations>
|
||||
</clocks>
|
||||
<dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
|
||||
<dcdx_profile>
|
||||
<processor_version>0.8.11</processor_version>
|
||||
<output_format>c_array</output_format>
|
||||
</dcdx_profile>
|
||||
<dcdx_configurations>
|
||||
<dcdx_configuration name="Device_configuration">
|
||||
<description></description>
|
||||
<options/>
|
||||
<command_groups>
|
||||
<command_group name="Imported Commands" enabled="true">
|
||||
<commands>
|
||||
<command type="write_value" address="CCM_CCGR0" value="0xFFFFFFFF" value_width="4"/>
|
||||
<command type="write_value" address="CCM_CCGR1" value="0xFFFFFFFF" value_width="4"/>
|
||||
<command type="write_value" address="CCM_CCGR2" value="0xFFFFFFFF" value_width="4"/>
|
||||
<command type="write_value" address="CCM_CCGR3" value="0xFFFFFFFF" value_width="4"/>
|
||||
<command type="write_value" address="CCM_CCGR4" value="0xFFFFFFFF" value_width="4"/>
|
||||
<command type="write_value" address="CCM_CCGR5" value="0xFFFFFFFF" value_width="4"/>
|
||||
<command type="write_value" address="CCM_CCGR6" value="0xFFFFFFFF" value_width="4"/>
|
||||
<command type="write_value" address="CCM_ANALOG_PLL_SYS" value="0x2001" value_width="4"/>
|
||||
<command type="write_value" address="CCM_ANALOG_PFD_528" value="0x1D0000" value_width="4"/>
|
||||
<command type="write_value" address="CCM_CBCDR" value="0x10D40" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39" value="0x10" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39" value="0x110F9" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_MCR" value="0x10000004" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BMCR0" value="0x81" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BMCR1" value="0x81" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR0" value="0x8000001B" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR1" value="0x8200001B" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR2" value="0x8400001B" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR3" value="0x8600001B" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR4" value="0x90000021" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR5" value="0xA0000019" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR6" value="0xA8000017" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR7" value="0xA900001B" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR8" value="0x21" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IOCR" value="0x79A8" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR0" value="0xF31" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR1" value="0x652922" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR2" value="0x10920" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR3" value="0x50210A08" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_DBICR0" value="0x21" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_DBICR1" value="0x888888" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR1" value="0x02" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR2" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR0" value="0x80000000" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCMD" value="0xA55A000F" value_width="4"/>
|
||||
<command type="check_any_bit_set" address="SEMC_INTR" value="0x01" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR0" value="0x80000000" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/>
|
||||
<command type="check_any_bit_set" address="SEMC_INTR" value="0x01" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR0" value="0x80000000" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/>
|
||||
<command type="check_any_bit_set" address="SEMC_INTR" value="0x01" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPTXDAT" value="0x33" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR0" value="0x80000000" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCMD" value="0xA55A000A" value_width="4"/>
|
||||
<command type="check_any_bit_set" address="SEMC_INTR" value="0x01" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR3" value="0x50210A09" value_width="4"/>
|
||||
</commands>
|
||||
</command_group>
|
||||
</command_groups>
|
||||
</dcdx_configuration>
|
||||
</dcdx_configurations>
|
||||
</dcdx>
|
||||
<periphs name="Peripherals" version="7.0" enabled="false" update_project_code="true">
|
||||
<peripherals_profile>
|
||||
<processor_version>N/A</processor_version>
|
||||
</peripherals_profile>
|
||||
<functional_groups/>
|
||||
<components/>
|
||||
</periphs>
|
||||
<tee name="TEE" version="2.0" enabled="false" update_project_code="true">
|
||||
<tee_profile>
|
||||
<processor_version>N/A</processor_version>
|
||||
</tee_profile>
|
||||
<global_options/>
|
||||
<user_memory_regions/>
|
||||
</tee>
|
||||
</tools>
|
||||
</configuration>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,119 @@
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
|
||||
|
||||
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
|
||||
/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
@@ -0,0 +1,315 @@
|
||||
/*
|
||||
* Copyright 2020-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#include "dcd.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.dcd_data"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.dcd_data"
|
||||
#endif
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: DCDx V2.0
|
||||
processor: MIMXRT1062xxxxA
|
||||
package_id: MIMXRT1062DVL6A
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.0.0
|
||||
board: MIMXRT1060-EVKB
|
||||
output_format: c_array
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
|
||||
const uint8_t dcd_data[] = {
|
||||
/* HEADER */
|
||||
/* Tag */
|
||||
0xD2,
|
||||
/* Image Length */
|
||||
0x04, 0x10,
|
||||
/* Version */
|
||||
0x41,
|
||||
|
||||
/* COMMANDS */
|
||||
|
||||
/* group: 'Imported Commands' */
|
||||
/* #1.1-113, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x03, 0x8C, 0x04,
|
||||
/* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||
/* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
|
||||
0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
|
||||
/* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */
|
||||
0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B,
|
||||
/* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */
|
||||
0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40,
|
||||
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */
|
||||
0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10,
|
||||
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */
|
||||
0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9,
|
||||
/* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04,
|
||||
/* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
|
||||
/* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
|
||||
/* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
|
||||
/* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
|
||||
/* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
|
||||
/* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B,
|
||||
/* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21,
|
||||
/* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19,
|
||||
/* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17,
|
||||
/* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B,
|
||||
/* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21,
|
||||
/* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8,
|
||||
/* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31,
|
||||
/* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
|
||||
/* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
|
||||
/* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
|
||||
/* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
|
||||
/* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
|
||||
/* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
|
||||
/* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
|
||||
/* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
|
||||
/* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #3.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #5.1-2, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x14, 0x04,
|
||||
/* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
|
||||
/* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #7.1-3, command header bytes for merged 'Write - value' command */
|
||||
0xCC, 0x00, 0x1C, 0x04,
|
||||
/* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
|
||||
/* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
|
||||
/* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
|
||||
0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
|
||||
/* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
|
||||
0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
|
||||
/* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
|
||||
0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
|
||||
};
|
||||
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
|
||||
|
||||
#else
|
||||
const uint8_t dcd_data[] = {0x00};
|
||||
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef __DCD__
|
||||
#define __DCD__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.1. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/*************************************
|
||||
* DCD Data
|
||||
*************************************/
|
||||
#define DCD_TAG_HEADER (0xD2)
|
||||
#define DCD_VERSION (0x41)
|
||||
#define DCD_TAG_HEADER_SHIFT (24)
|
||||
#define DCD_ARRAY_SIZE 1
|
||||
|
||||
#endif /* __DCD__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Definitions
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*! @brief Direction type */
|
||||
typedef enum _pin_mux_direction
|
||||
{
|
||||
kPIN_MUX_DirectionInput = 0U, /* Input direction */
|
||||
kPIN_MUX_DirectionOutput = 1U, /* Output direction */
|
||||
kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
|
||||
} pin_mux_direction_t;
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitSemcPins(void);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitI2C1Pins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@@ -0,0 +1,24 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers.
|
||||
src = Split("""
|
||||
board.c
|
||||
MCUX_Config/clock_config.c
|
||||
MCUX_Config/pin_mux.c
|
||||
MCUX_Config/dcd.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
|
||||
|
||||
CPPDEFINES = ['CPU_MIMXRT1062DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', 'FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1', 'DATA_SECTION_IS_CACHEABLE=1']
|
||||
|
||||
if rtconfig.CROSS_TOOL == 'keil':
|
||||
CPPDEFINES.append('__FPU_PRESENT=1')
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-09-22 Bernard add board.h to this bsp
|
||||
*/
|
||||
|
||||
// <<< Use Configuration Wizard in Context Menu >>>
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RTT_HEAP$$ZI$$Base;
|
||||
extern int Image$$RTT_HEAP$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base)
|
||||
#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit)
|
||||
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
extern void __RTT_HEAP_END;
|
||||
#define HEAP_END (&__RTT_HEAP_END)
|
||||
|
||||
#else
|
||||
extern int heap_start;
|
||||
extern int heap_end;
|
||||
#define HEAP_BEGIN (&heap_start)
|
||||
#define HEAP_END (&heap_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN)
|
||||
|
||||
#define SDRAM_BEGIN (0x80000000u)
|
||||
#define SDRAM_END (0x81E00000u)
|
||||
|
||||
|
||||
/*! @brief The board flash size */
|
||||
#define BOARD_FLASH_SIZE (0x400000U)
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#ifdef BSP_USING_ETH
|
||||
void imxrt_enet_pins_init(void);
|
||||
void imxrt_enet_phy_reset_by_gpio(void);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVJ5B
|
||||
** MIMXRT1052CVL5B
|
||||
** MIMXRT1052DVJ6B
|
||||
** MIMXRT1052DVL6B
|
||||
**
|
||||
** Compiler: IAR ANSI C/C++ Compiler for ARM
|
||||
** Reference manual: IMXRT1050RM Rev.1, 03/2018
|
||||
** Version: rev. 1.0, 2018-09-21
|
||||
** Build: b180921
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2018 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
define symbol m_interrupts_start = 0x70002000;
|
||||
define symbol m_interrupts_end = 0x700023FF;
|
||||
|
||||
define symbol m_text_start = 0x70002400;
|
||||
define symbol m_text_end = 0x73FFFFFF;
|
||||
|
||||
define symbol m_data_start = 0x20000000;
|
||||
define symbol m_data_end = 0x2001FFFF;
|
||||
|
||||
define symbol m_data2_start = 0x20200000;
|
||||
define symbol m_data2_end = 0x2023FFFF;
|
||||
|
||||
define exported symbol m_boot_hdr_conf_start = 0x70000000;
|
||||
define symbol m_boot_hdr_ivt_start = 0x70001000;
|
||||
define symbol m_boot_hdr_boot_data_start = 0x70001020;
|
||||
define symbol m_boot_hdr_dcd_data_start = 0x70001030;
|
||||
|
||||
/* Sizes */
|
||||
if (isdefinedsymbol(__stack_size__)) {
|
||||
define symbol __size_cstack__ = __stack_size__;
|
||||
} else {
|
||||
define symbol __size_cstack__ = 0x0400;
|
||||
}
|
||||
|
||||
if (isdefinedsymbol(__heap_size__)) {
|
||||
define symbol __size_heap__ = __heap_size__;
|
||||
} else {
|
||||
define symbol __size_heap__ = 0x0400;
|
||||
}
|
||||
|
||||
define exported symbol __VECTOR_TABLE = m_interrupts_start;
|
||||
define exported symbol __VECTOR_RAM = m_interrupts_start;
|
||||
define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
|
||||
define exported symbol __RTT_HEAP_END = m_data2_end;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
|
||||
| mem:[from m_text_start to m_text_end];
|
||||
|
||||
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
|
||||
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
|
||||
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block RW { readwrite };
|
||||
define block ZI { zi };
|
||||
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
|
||||
|
||||
initialize by copy { readwrite, section .textrw };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem: m_interrupts_start { readonly section .intvec };
|
||||
|
||||
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
|
||||
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
|
||||
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
|
||||
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
|
||||
|
||||
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
|
||||
|
||||
place in TEXT_region { readonly };
|
||||
place in DATA_region { block RW };
|
||||
place in DATA_region { block ZI };
|
||||
place in DATA_region { last block HEAP };
|
||||
place in DATA_region { block NCACHE_VAR };
|
||||
place in CSTACK_region { block CSTACK };
|
||||
|
||||
@@ -0,0 +1,283 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1052CVL5A
|
||||
** MIMXRT1052DVL6A
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Reference manual: IMXRT1050RM Rev.C, 08/2017
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b170927
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2017 NXP
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** 1. Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** 2. Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** 3. Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_boot_data (RX) : ORIGIN = 0x70000000, LENGTH = 0x00001000
|
||||
m_image_vertor_table (RX) : ORIGIN = 0x70001000, LENGTH = 0x00001000
|
||||
|
||||
m_interrupts (RX) : ORIGIN = 0x70002000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = 0x70002400, LENGTH = 0x003FDC00
|
||||
|
||||
m_itcm (RW) : ORIGIN = 0x00000000, LENGTH = 0x00020000
|
||||
m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
|
||||
m_ocram (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000
|
||||
|
||||
m_sdram (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000
|
||||
m_nocache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
.boot_data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__FLASH_BASE = .;
|
||||
KEEP(* (.boot_hdr.conf)) /* flash config section */
|
||||
. = ALIGN(4);
|
||||
} > m_boot_data
|
||||
|
||||
ivt_begin= ORIGIN(m_boot_data) + LENGTH(m_boot_data);
|
||||
|
||||
.image_vertor_table : AT(ivt_begin)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.boot_hdr.ivt))
|
||||
KEEP(*(.boot_hdr.boot_data))
|
||||
KEEP(*(.boot_hdr.dcd_data))
|
||||
. = ALIGN(4);
|
||||
} > m_image_vertor_table
|
||||
|
||||
/* The startup code goes first into internal RAM */
|
||||
.interrupts :
|
||||
{
|
||||
__VECTOR_TABLE = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
__VECTOR_RAM = __VECTOR_TABLE;
|
||||
__RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
|
||||
|
||||
/* The program code and other data goes into internal RAM */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
/* __CTOR_LIST__ = .; */
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
/* __CTOR_END__ = .; */
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
/* __DTOR_LIST__ = .; */
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
/* __DTOR_END__ = .; */
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(m_usb_dma_init_data)
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_dtcm
|
||||
|
||||
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
.ncache.init : AT(__NDATA_ROM)
|
||||
{
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||
} > m_nocache
|
||||
. = __noncachedata_init_end__;
|
||||
.ncache :
|
||||
{
|
||||
*(NonCacheable)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
} > m_nocache
|
||||
|
||||
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(m_usb_dma_noninit_data)
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_dtcm
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
stack_start = .;
|
||||
. += STACK_SIZE;
|
||||
stack_end = .;
|
||||
__StackTop = .;
|
||||
} > m_dtcm
|
||||
|
||||
.RTT_HEAP :
|
||||
{
|
||||
heap_start = .;
|
||||
. = ALIGN(8);
|
||||
} > m_dtcm
|
||||
|
||||
PROVIDE(heap_end = ORIGIN(m_dtcm) + LENGTH(m_dtcm));
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,121 @@
|
||||
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MIMXRT1062CVJ5A
|
||||
** MIMXRT1062CVL5A
|
||||
** MIMXRT1062DVJ6A
|
||||
** MIMXRT1062DVL6A
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
|
||||
** Version: rev. 0.1, 2017-01-10
|
||||
** Build: b210709
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2021 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#if (defined(__ram_vector_table__))
|
||||
#define __ram_vector_table_size__ 0x00000400
|
||||
#else
|
||||
#define __ram_vector_table_size__ 0x00000000
|
||||
#endif
|
||||
|
||||
#define m_flash_config_start 0x60000000
|
||||
#define m_flash_config_size 0x00001000
|
||||
|
||||
#define m_ivt_start 0x60001000
|
||||
#define m_ivt_size 0x00001000
|
||||
|
||||
#define m_interrupts_start 0x60002000
|
||||
#define m_interrupts_size 0x00000400
|
||||
|
||||
#define m_text_start 0x60002400
|
||||
#define m_text_size 0x007FDC00
|
||||
|
||||
#define m_qacode_start 0x00000000
|
||||
#define m_qacode_size 0x00020000
|
||||
|
||||
#define m_interrupts_ram_start 0x80000000
|
||||
#define m_interrupts_ram_size __ram_vector_table_size__
|
||||
|
||||
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
|
||||
#define m_data_size (0x01E00000 - m_interrupts_ram_size)
|
||||
|
||||
#define m_data2_start 0x20200000
|
||||
#define m_data2_size 0x00020000
|
||||
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
|
||||
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
|
||||
* (.boot_hdr.conf, +FIRST)
|
||||
}
|
||||
|
||||
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
|
||||
* (.boot_hdr.ivt, +FIRST)
|
||||
* (.boot_hdr.boot_data)
|
||||
* (.boot_hdr.dcd_data)
|
||||
}
|
||||
#else
|
||||
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
|
||||
#endif
|
||||
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
#if (defined(__ram_vector_table__))
|
||||
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
|
||||
}
|
||||
#else
|
||||
VECTOR_RAM m_interrupts_start EMPTY 0 {
|
||||
}
|
||||
#endif
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
* (RamFunction)
|
||||
* (NonCacheable.init)
|
||||
* (*NonCacheable)
|
||||
* (DataQuickAccess)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
|
||||
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
|
||||
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
|
||||
|
||||
RW_m_ram_text m_qacode_start m_qacode_size { ;
|
||||
* (CodeQuickAccess)
|
||||
}
|
||||
RW_m_ncache m_data2_start EMPTY 0 {
|
||||
}
|
||||
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-05 zylx The first version for STM32F4xx
|
||||
* 2019-4-25 misonyo port to IMXRT
|
||||
*/
|
||||
|
||||
#ifndef SDRAM_PORT_H__
|
||||
#define SDRAM_PORT_H__
|
||||
|
||||
/* parameters for sdram peripheral */
|
||||
|
||||
#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U)
|
||||
/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */
|
||||
#define SDRAM_REGION kSEMC_SDRAM_CS0
|
||||
/* CS pin: kSEMC_MUXCSX0/1/2/3 */
|
||||
#define SDRAM_CS_PIN kSEMC_MUXCSX0
|
||||
/* size(kbyte):32MB = 32*1024*1KBytes */
|
||||
#define SDRAM_SIZE ((uint32_t)0x8000)
|
||||
/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
|
||||
#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit
|
||||
/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
|
||||
#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit
|
||||
/* cas latency clock number: kSEMC_LatencyOne/Two/Three */
|
||||
#define SDRAM_CAS_LATENCY kSEMC_LatencyThree
|
||||
|
||||
/* Timing configuration for W9825G6KH */
|
||||
/* TRP:precharge to active command time (ns) */
|
||||
#define SDRAM_TRP 18
|
||||
/* TRCD:active to read/write command delay time (ns) */
|
||||
#define SDRAM_TRCD 18
|
||||
/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */
|
||||
#define SDRAM_REFRESH_RECOVERY 67
|
||||
/* TWR:write recovery time (ns). */
|
||||
#define SDRAM_TWR 12
|
||||
/* TRAS:active to precharge command time (ns). */
|
||||
#define SDRAM_TRAS 42
|
||||
/* TRC time (ns). */
|
||||
#define SDRAM_TRC 60
|
||||
/* active to active time (ns). */
|
||||
#define SDRAM_ACT2ACT 60
|
||||
/* refresh time (ns). 64ms */
|
||||
#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192
|
||||
|
||||
#endif /* SDRAM_PORT_H__ */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 128 KiB |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,202 @@
|
||||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_HOOK_USING_FUNC_PTR
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_MEMHEAP
|
||||
#define RT_MEMHEAP_FAST_MODE
|
||||
#define RT_USING_MEMHEAP_AS_HEAP
|
||||
#define RT_USING_MEMHEAP_AUTO_BINDING
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40100
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define RT_USING_MSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_CPUTIME
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_LIBC_DEFAULT_TIMEZONE 8
|
||||
|
||||
/* POSIX (Portable Operating System Interface) layer */
|
||||
|
||||
|
||||
/* Interprocess Communication (IPC) */
|
||||
|
||||
|
||||
/* Socket is in the 'Network' category */
|
||||
|
||||
/* Network */
|
||||
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
|
||||
/* security packages */
|
||||
|
||||
|
||||
/* language packages */
|
||||
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* LVGL: powerful and easy-to-use embedded GUI library */
|
||||
|
||||
|
||||
/* u8g2: a monochrome graphic library */
|
||||
|
||||
|
||||
/* PainterEngine: A cross-platform graphics application framework written in C language */
|
||||
|
||||
|
||||
/* tools packages */
|
||||
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* enhanced kernel services */
|
||||
|
||||
|
||||
/* POSIX extension functions */
|
||||
|
||||
|
||||
/* acceleration: Assembly language or algorithmic acceleration packages */
|
||||
|
||||
|
||||
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
|
||||
|
||||
|
||||
/* Micrium: Micrium software products porting for RT-Thread */
|
||||
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
|
||||
/* AI packages */
|
||||
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* project laboratory */
|
||||
|
||||
/* samples: kernel and components samples */
|
||||
|
||||
|
||||
/* entertainment: terminal games and other interesting software packages */
|
||||
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define BSP_USING_4MFLASH
|
||||
#define SOC_MIMXRT1062DVL6A
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_LPUART
|
||||
#define BSP_USING_LPUART1
|
||||
#define BSP_USING_PXP
|
||||
#define BSP_USING_CACHE
|
||||
|
||||
/* Onboard Peripheral Drivers */
|
||||
|
||||
|
||||
/* Board extended module Drivers */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,165 @@
|
||||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m7'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'C:\Users\XXYYZZ'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
# EXEC_PATH = r'C:/Keil_v5'
|
||||
EXEC_PATH = r'D:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
#BUILD = 'debug'
|
||||
BUILD = 'release'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry'
|
||||
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds -Xlinker -print-memory-usage'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
AFLAGS += ' -D__STARTUP_INITIALIZE_NONCACHEDATA'
|
||||
AFLAGS += ' -D__STARTUP_CLEAR_BSS'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g'
|
||||
AFLAGS += ' -g'
|
||||
CFLAGS += ' -O0'
|
||||
else:
|
||||
CFLAGS += ' -O2 -Os'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
# POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread-gcc.hex\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
|
||||
M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
|
||||
M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
|
||||
M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
|
||||
' -shared -fPIC -nostartfiles -static-libgcc'
|
||||
M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu ' + CPU + '.fp.sp'
|
||||
CFLAGS = DEVICE + ' --apcs=interwork'
|
||||
AFLAGS = DEVICE
|
||||
LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"'
|
||||
|
||||
CFLAGS += ' --diag_suppress=66,1296,186'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
|
||||
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
|
||||
|
||||
EXEC_PATH += '/arm/bin40/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' --c99'
|
||||
|
||||
# POST_ACTION = 'fromelf -z $TARGET'
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
# POST_ACTION = 'fromelf --i32combined $TARGET --output="rtthread-mdk.hex" \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = ' -D__FPU_PRESENT'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=' + CPU
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=None'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' -Ol'
|
||||
CFLAGS += ' --use_c++_inline'
|
||||
|
||||
AFLAGS = ''
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu ' + CPU
|
||||
AFLAGS += ' --fpu None'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --redirect _Printf=_PrintfTiny'
|
||||
LFLAGS += ' --redirect _Scanf=_ScanfSmall'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
@@ -0,0 +1,184 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc; *.md</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>rtthread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>8</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile>..\libraries\MIMXRT1060\MIMXRT1060\arm\evkbmimxrt1060_flexspi_nor_sdram.ini</tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC8000 -FD20000000 -FF0MIMXRT106x_QSPI_4KB_SEC -FL0800000 -FS060000000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"CMSIS-DAP" -U0229000009b0778f0000000000000000 -O974 -S8 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC.FLM -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
<DebugDescription>
|
||||
<Enable>1</Enable>
|
||||
<EnableFlashSeq>1</EnableFlashSeq>
|
||||
<EnableLog>0</EnableLog>
|
||||
<Protocol>2</Protocol>
|
||||
<DbgClock>10000000</DbgClock>
|
||||
</DebugDescription>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
</ProjectOpt>
|
||||
@@ -0,0 +1,392 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>rtthread</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
|
||||
<uAC6>1</uAC6>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>MIMXRT1062DVL6A</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<PackID>NXP.MIMXRT1062_DFP.14.0.0</PackID>
|
||||
<PackURL>https://mcuxpresso.nxp.com/cmsis_pack/repo/</PackURL>
|
||||
<Cpu>IRAM(0x20000000,0x020000) IRAM2(0x00000000,0x020000) IROM(0x00200000,0x020000) XRAM(0x20280000,0x040000) XRAM2(0x20200000,0x080000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1062DVL6A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM))</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:MIMXRT1062DVL6A$fsl_device_registers.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:MIMXRT1062DVL6A$MIMXRT1062.xml</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\keil\Obj\</OutputDirectory>
|
||||
<OutputName>rtthread</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\keil\List\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -REMAP -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM7</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4099</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>0</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M7"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>1</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>3</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<RvdsCdeCp>0</RvdsCdeCp>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>1</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>4</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>1</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>0</Im1Chk>
|
||||
<Im2Chk>1</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x200000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x20280000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x60000000</StartAddress>
|
||||
<Size>0x4000000</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x200000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20200000</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x80000000</StartAddress>
|
||||
<Size>0x2000000</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>2</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>1</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>3</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>3</v6Lang>
|
||||
<v6LangP>3</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls>-fno-common -fdata-sections -ffreestanding -fno-builtin -mthumb</MiscControls>
|
||||
<Define>XIP_EXTERNAL_FLASH=1, XIP_BOOT_HEADER_ENABLE=1, DEBUG, CPU_MIMXRT1062DVL6A, PRINTF_FLOAT_ENABLE=0, SCANF_FLOAT_ENABLE=0, PRINTF_ADVANCED_ENABLE=0, SCANF_ADVANCED_ENABLE=0, MCUXPRESSO_SDK</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<ClangAsOpt>1</ClangAsOpt>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>DEBUG, __STARTUP_INITIALIZE_NONCACHEDATA</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>--keep=*(.boot_hdr.ivt)--keep=*(.boot_hdr.boot_data)--keep=*(.boot_hdr.dcd_data)--keep=*(.boot_hdr.conf) --remove --entry=Reset_Handler --predefine="-DXIP_BOOT_HEADER_ENABLE=1"
|
||||
--remove</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,25 @@
|
||||
Import('RTT_ROOT')
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
if GetDepend('BSP_USING_4MFLASH'):
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if rtconfig.CROSS_TOOL == 'keil':
|
||||
LINKFLAGS = '--keep=*(.boot_hdr.ivt)'
|
||||
LINKFLAGS += '--keep=*(.boot_hdr.boot_data)'
|
||||
LINKFLAGS += '--keep=*(.boot_hdr.dcd_data)'
|
||||
LINKFLAGS += '--keep=*(.boot_hdr.conf)'
|
||||
LINKFLAGS += '--entry=Reset_Handler '
|
||||
LINKFLAGS += '--predefine="-DXIP_BOOT_HEADER_ENABLE=1"'
|
||||
else:
|
||||
LINKFLAGS = ''
|
||||
|
||||
group = DefineGroup('xip', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS)
|
||||
Return('group')
|
||||
|
||||
if GetDepend('BSP_USING_QSPIFLASH'):
|
||||
group = []
|
||||
Return('group')
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "evkbmimxrt1060_flexspi_nor_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_100MHz,
|
||||
.sflashA1Size = 8u * 1024u * 1024u,
|
||||
.lookupTable =
|
||||
{
|
||||
// Read LUTs
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.blockSize = 64u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
@@ -0,0 +1,268 @@
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.1. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related defintions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_120MHz = 7,
|
||||
kFlexSpiSerialClk_133MHz = 8,
|
||||
kFlexSpiSerialClk_166MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
//!@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
//!@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
//!@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
//!@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
//! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
//! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
//! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
//! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
//! details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
//! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
//! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t reserve2[11]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright 2017-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_flexspi_nor_boot.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_device"
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.ivt"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.ivt"
|
||||
#endif
|
||||
/*************************************
|
||||
* IVT Data
|
||||
*************************************/
|
||||
const ivt image_vector_table = {
|
||||
IVT_HEADER, /* IVT Header */
|
||||
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
|
||||
IVT_RSVD, /* Reserved = 0 */
|
||||
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
|
||||
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
|
||||
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
|
||||
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
|
||||
IVT_RSVD /* Reserved = 0 */
|
||||
};
|
||||
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.boot_data"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.boot_data"
|
||||
#endif
|
||||
/*************************************
|
||||
* Boot Data
|
||||
*************************************/
|
||||
const BOOT_DATA_T g_boot_data = {
|
||||
FLASH_BASE, /* boot start location */
|
||||
FLASH_SIZE, /* size */
|
||||
PLUGIN_FLAG, /* Plugin flag*/
|
||||
0xFFFFFFFFU /* empty - extra data word */
|
||||
};
|
||||
#endif
|
||||
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
* Copyright 2017-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __FLEXSPI_NOR_BOOT_H__
|
||||
#define __FLEXSPI_NOR_BOOT_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include "board.h"
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_DEVICE driver version 2.0.2. */
|
||||
#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
|
||||
/*@}*/
|
||||
|
||||
/*************************************
|
||||
* IVT Data
|
||||
*************************************/
|
||||
typedef struct _ivt_
|
||||
{
|
||||
/** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields
|
||||
* (see @ref data)
|
||||
*/
|
||||
uint32_t hdr;
|
||||
/** Absolute address of the first instruction to execute from the
|
||||
* image
|
||||
*/
|
||||
uint32_t entry;
|
||||
/** Reserved in this version of HAB: should be NULL. */
|
||||
uint32_t reserved1;
|
||||
/** Absolute address of the image DCD: may be NULL. */
|
||||
uint32_t dcd;
|
||||
/** Absolute address of the Boot Data: may be NULL, but not interpreted
|
||||
* any further by HAB
|
||||
*/
|
||||
uint32_t boot_data;
|
||||
/** Absolute address of the IVT.*/
|
||||
uint32_t self;
|
||||
/** Absolute address of the image CSF.*/
|
||||
uint32_t csf;
|
||||
/** Reserved in this version of HAB: should be zero. */
|
||||
uint32_t reserved2;
|
||||
} ivt;
|
||||
|
||||
#define IVT_MAJOR_VERSION 0x4
|
||||
#define IVT_MAJOR_VERSION_SHIFT 0x4
|
||||
#define IVT_MAJOR_VERSION_MASK 0xF
|
||||
#define IVT_MINOR_VERSION 0x1
|
||||
#define IVT_MINOR_VERSION_SHIFT 0x0
|
||||
#define IVT_MINOR_VERSION_MASK 0xF
|
||||
|
||||
#define IVT_VERSION(major, minor) \
|
||||
((((major)&IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \
|
||||
(((minor)&IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT))
|
||||
|
||||
/* IVT header */
|
||||
#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */
|
||||
#define IVT_SIZE 0x2000
|
||||
#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION)
|
||||
#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24))
|
||||
|
||||
/* Set resume entry */
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
|
||||
extern uint32_t __Vectors[];
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)
|
||||
#elif defined(__MCUXPRESSO)
|
||||
extern uint32_t __Vectors[];
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors)
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE)
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
|
||||
#define DCD_ADDRESS dcd_data
|
||||
#else
|
||||
#define DCD_ADDRESS 0
|
||||
#endif
|
||||
|
||||
#define BOOT_DATA_ADDRESS &g_boot_data
|
||||
#define CSF_ADDRESS 0
|
||||
#define IVT_RSVD (uint32_t)(0x00000000)
|
||||
|
||||
/*************************************
|
||||
* Boot Data
|
||||
*************************************/
|
||||
typedef struct _boot_data_
|
||||
{
|
||||
uint32_t start; /* boot start location */
|
||||
uint32_t size; /* size */
|
||||
uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */
|
||||
uint32_t placeholder; /* placehoder to make even 0x10 size */
|
||||
} BOOT_DATA_T;
|
||||
|
||||
#define FLASH_BASE FlexSPI_AMBA_BASE
|
||||
#if defined(BOARD_FLASH_SIZE)
|
||||
#define FLASH_SIZE BOARD_FLASH_SIZE
|
||||
#else
|
||||
#error "Please define macro BOARD_FLASH_SIZE"
|
||||
#endif
|
||||
#define PLUGIN_FLAG (uint32_t)0
|
||||
|
||||
/* External Variables */
|
||||
extern const BOOT_DATA_T g_boot_data;
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE)
|
||||
extern const uint8_t dcd_data[];
|
||||
#endif
|
||||
|
||||
#endif /* __FLEXSPI_NOR_BOOT_H__ */
|
||||
@@ -0,0 +1,4 @@
|
||||
# files format check exclude path, please follow the instructions below to modify;
|
||||
|
||||
dir_path:
|
||||
- MIMXRT1060
|
||||
@@ -0,0 +1,321 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_CAN.h"
|
||||
|
||||
#define ARM_CAN_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) // CAN driver version
|
||||
|
||||
// Driver Version
|
||||
static const ARM_DRIVER_VERSION can_driver_version = { ARM_CAN_API_VERSION, ARM_CAN_DRV_VERSION };
|
||||
|
||||
// Driver Capabilities
|
||||
static const ARM_CAN_CAPABILITIES can_driver_capabilities = {
|
||||
32U, // Number of CAN Objects available
|
||||
1U, // Supports reentrant calls to ARM_CAN_MessageSend, ARM_CAN_MessageRead, ARM_CAN_ObjectConfigure and abort message sending used by ARM_CAN_Control.
|
||||
0U, // Does not support CAN with Flexible Data-rate mode (CAN_FD)
|
||||
0U, // Does not support restricted operation mode
|
||||
1U, // Supports bus monitoring mode
|
||||
1U, // Supports internal loopback mode
|
||||
1U, // Supports external loopback mode
|
||||
};
|
||||
|
||||
// Object Capabilities
|
||||
static const ARM_CAN_OBJ_CAPABILITIES can_object_capabilities = {
|
||||
1U, // Object supports transmission
|
||||
1U, // Object supports reception
|
||||
0U, // Object does not support RTR reception and automatic Data transmission
|
||||
0U, // Object does not support RTR transmission and automatic Data reception
|
||||
1U, // Object allows assignment of multiple filters to it
|
||||
1U, // Object supports exact identifier filtering
|
||||
0U, // Object does not support range identifier filtering
|
||||
1U, // Object supports mask identifier filtering
|
||||
3U // Object can buffer 3 messages
|
||||
};
|
||||
|
||||
static uint8_t can_driver_powered = 0U;
|
||||
static uint8_t can_driver_initialized = 0U;
|
||||
static ARM_CAN_SignalUnitEvent_t CAN_SignalUnitEvent = NULL;
|
||||
static ARM_CAN_SignalObjectEvent_t CAN_SignalObjectEvent = NULL;
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
static ARM_DRIVER_VERSION CAN_GetVersion (void) {
|
||||
// Return driver version
|
||||
return can_driver_version;
|
||||
}
|
||||
|
||||
static ARM_CAN_CAPABILITIES CAN_GetCapabilities (void) {
|
||||
// Return driver capabilities
|
||||
return can_driver_capabilities;
|
||||
}
|
||||
|
||||
static int32_t CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event,
|
||||
ARM_CAN_SignalObjectEvent_t cb_object_event) {
|
||||
|
||||
if (can_driver_initialized != 0U) { return ARM_DRIVER_OK; }
|
||||
|
||||
CAN_SignalUnitEvent = cb_unit_event;
|
||||
CAN_SignalObjectEvent = cb_object_event;
|
||||
|
||||
// Add code for pin, memory, RTX objects initialization
|
||||
// ..
|
||||
|
||||
can_driver_initialized = 1U;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_Uninitialize (void) {
|
||||
|
||||
// Add code for pin, memory, RTX objects de-initialization
|
||||
// ..
|
||||
|
||||
can_driver_initialized = 0U;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_PowerControl (ARM_POWER_STATE state) {
|
||||
switch (state) {
|
||||
case ARM_POWER_OFF:
|
||||
can_driver_powered = 0U;
|
||||
// Add code to disable interrupts and put peripheral into reset mode,
|
||||
// and if possible disable clock
|
||||
// ..
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
if (can_driver_initialized == 0U) { return ARM_DRIVER_ERROR; }
|
||||
if (can_driver_powered != 0U) { return ARM_DRIVER_OK; }
|
||||
|
||||
// Add code to enable clocks, reset variables enable interrupts
|
||||
// and put peripheral into operational
|
||||
// ..
|
||||
|
||||
can_driver_powered = 1U;
|
||||
break;
|
||||
|
||||
default:
|
||||
// Other states are not supported
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
uint32_t CAN_GetClock (void) {
|
||||
|
||||
// Add code to return peripheral clock frequency
|
||||
// ..
|
||||
}
|
||||
|
||||
static int32_t CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
// Add code to setup peripheral parameters to generate specified bitrate
|
||||
// with specified bit segments
|
||||
// ..
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_SetMode (ARM_CAN_MODE mode) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
switch (mode) {
|
||||
case ARM_CAN_MODE_INITIALIZATION:
|
||||
// Add code to put peripheral into initialization mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_NORMAL:
|
||||
// Add code to put peripheral into normal operation mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_RESTRICTED:
|
||||
// Add code to put peripheral into restricted operation mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_MONITOR:
|
||||
// Add code to put peripheral into bus monitoring mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_LOOPBACK_INTERNAL:
|
||||
// Add code to put peripheral into internal loopback mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_MODE_LOOPBACK_EXTERNAL:
|
||||
// Add code to put peripheral into external loopback mode
|
||||
// ..
|
||||
break;
|
||||
default:
|
||||
// Handle unknown mode code
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
ARM_CAN_OBJ_CAPABILITIES CAN_ObjectGetCapabilities (uint32_t obj_idx) {
|
||||
// Return object capabilities
|
||||
return can_object_capabilities;
|
||||
}
|
||||
|
||||
static int32_t CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
switch (operation) {
|
||||
case ARM_CAN_FILTER_ID_EXACT_ADD:
|
||||
// Add code to setup peripheral to receive messages with specified exact ID
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_MASKABLE_ADD:
|
||||
// Add code to setup peripheral to receive messages with specified maskable ID
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_RANGE_ADD:
|
||||
// Add code to setup peripheral to receive messages within specified range of IDs
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_EXACT_REMOVE:
|
||||
// Add code to remove specified exact ID from being received by peripheral
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_MASKABLE_REMOVE:
|
||||
// Add code to remove specified maskable ID from being received by peripheral
|
||||
break;
|
||||
case ARM_CAN_FILTER_ID_RANGE_REMOVE:
|
||||
// Add code to remove specified range of IDs from being received by peripheral
|
||||
break;
|
||||
default:
|
||||
// Handle unknown operation code
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
switch (obj_cfg) {
|
||||
case ARM_CAN_OBJ_INACTIVE:
|
||||
// Deactivate object
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_OBJ_RX_RTR_TX_DATA:
|
||||
// Setup object to automatically return data when RTR with it's ID is received
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_OBJ_TX_RTR_RX_DATA:
|
||||
// Setup object to send RTR and receive data response
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_OBJ_TX:
|
||||
// Setup object to be used for sending messages
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_OBJ_RX:
|
||||
// Setup object to be used for receiving messages
|
||||
// ..
|
||||
break;
|
||||
default:
|
||||
// Handle unknown object configuration code
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static int32_t CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
// Add code to send requested message
|
||||
// ..
|
||||
|
||||
return ((int32_t)size);
|
||||
}
|
||||
|
||||
static int32_t CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
// Add code to read previously received message
|
||||
// (reception was started when object was configured for reception)
|
||||
// ..
|
||||
|
||||
return ((int32_t)size);
|
||||
}
|
||||
|
||||
static int32_t CAN_Control (uint32_t control, uint32_t arg) {
|
||||
|
||||
if (can_driver_powered == 0U) { return ARM_DRIVER_ERROR; }
|
||||
|
||||
switch (control & ARM_CAN_CONTROL_Msk) {
|
||||
case ARM_CAN_ABORT_MESSAGE_SEND:
|
||||
// Add code to abort message pending to be sent
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_SET_FD_MODE:
|
||||
// Add code to enable Flexible Data-rate mode
|
||||
// ..
|
||||
break;
|
||||
case ARM_CAN_SET_TRANSCEIVER_DELAY:
|
||||
// Add code to set transceiver delay
|
||||
// ..
|
||||
break;
|
||||
default:
|
||||
// Handle unknown control code
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
static ARM_CAN_STATUS CAN_GetStatus (void) {
|
||||
|
||||
// Add code to return device bus and error status
|
||||
// ..
|
||||
}
|
||||
|
||||
|
||||
// IRQ handlers
|
||||
// Add interrupt routines to handle transmission, reception, error and status interrupts
|
||||
// ..
|
||||
|
||||
// CAN driver functions structure
|
||||
|
||||
ARM_DRIVER_CAN Driver_CAN = {
|
||||
CAN_GetVersion,
|
||||
CAN_GetCapabilities,
|
||||
CAN_Initialize,
|
||||
CAN_Uninitialize,
|
||||
CAN_PowerControl,
|
||||
CAN_GetClock,
|
||||
CAN_SetBitrate,
|
||||
CAN_SetMode,
|
||||
CAN_ObjectGetCapabilities,
|
||||
CAN_ObjectSetFilter,
|
||||
CAN_ObjectConfigure,
|
||||
CAN_MessageSend,
|
||||
CAN_MessageRead,
|
||||
CAN_Control,
|
||||
CAN_GetStatus
|
||||
};
|
||||
|
||||
@@ -0,0 +1,228 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_ETH_MAC.h"
|
||||
|
||||
#define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_ETH_MAC_API_VERSION,
|
||||
ARM_ETH_MAC_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_ETH_MAC_CAPABILITIES DriverCapabilities = {
|
||||
0, /* 1 = IPv4 header checksum verified on receive */
|
||||
0, /* 1 = IPv6 checksum verification supported on receive */
|
||||
0, /* 1 = UDP payload checksum verified on receive */
|
||||
0, /* 1 = TCP payload checksum verified on receive */
|
||||
0, /* 1 = ICMP payload checksum verified on receive */
|
||||
0, /* 1 = IPv4 header checksum generated on transmit */
|
||||
0, /* 1 = IPv6 checksum generation supported on transmit */
|
||||
0, /* 1 = UDP payload checksum generated on transmit */
|
||||
0, /* 1 = TCP payload checksum generated on transmit */
|
||||
0, /* 1 = ICMP payload checksum generated on transmit */
|
||||
0, /* Ethernet Media Interface type */
|
||||
0, /* 1 = driver provides initial valid MAC address */
|
||||
0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated */
|
||||
0, /* 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated */
|
||||
0, /* 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated */
|
||||
0 /* 1 = Precision Timer supported */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_SendFrame(const uint8_t *frame, uint32_t len, uint32_t flags)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_ReadFrame(uint8_t *frame, uint32_t len)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_ETH_MAC_GetRxFrameSize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_GetRxFrameTime(ARM_ETH_MAC_TIME *time)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_GetTxFrameTime(ARM_ETH_MAC_TIME *time)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
switch (control)
|
||||
{
|
||||
case ARM_ETH_MAC_CONFIGURE:
|
||||
|
||||
switch (arg & ARM_ETH_MAC_SPEED_Msk)
|
||||
{
|
||||
case ARM_ETH_MAC_SPEED_10M:
|
||||
break;
|
||||
case ARM_ETH_SPEED_100M:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
switch (arg & ARM_ETH_MAC_DUPLEX_Msk)
|
||||
{
|
||||
case ARM_ETH_MAC_DUPLEX_FULL:
|
||||
break;
|
||||
}
|
||||
|
||||
if (arg & ARM_ETH_MAC_LOOPBACK)
|
||||
{
|
||||
}
|
||||
|
||||
if ((arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX) ||
|
||||
(arg & ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
if (!(arg & ARM_ETH_MAC_ADDRESS_BROADCAST))
|
||||
{
|
||||
}
|
||||
|
||||
if (arg & ARM_ETH_MAC_ADDRESS_MULTICAST)
|
||||
{
|
||||
}
|
||||
|
||||
if (arg & ARM_ETH_MAC_ADDRESS_ALL)
|
||||
{
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_CONTROL_TX:
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_CONTROL_RX:
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_FLUSH:
|
||||
if (arg & ARM_ETH_MAC_FLUSH_RX)
|
||||
{
|
||||
}
|
||||
if (arg & ARM_ETH_MAC_FLUSH_TX)
|
||||
{
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_SLEEP:
|
||||
break;
|
||||
|
||||
case ARM_ETH_MAC_VLAN_FILTER:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_PHY_Read(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_MAC_PHY_Write(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_ETH_MAC_SignalEvent(uint32_t event)
|
||||
{
|
||||
}
|
||||
|
||||
// End ETH MAC Interface
|
||||
|
||||
ARM_DRIVER_ETH_MAC Driver_ETH_MAC =
|
||||
{
|
||||
ARM_ETH_MAC_GetVersion,
|
||||
ARM_ETH_MAC_GetCapabilities,
|
||||
ARM_ETH_MAC_Initialize,
|
||||
ARM_ETH_MAC_Uninitialize,
|
||||
ARM_ETH_MAC_PowerControl,
|
||||
ARM_ETH_MAC_GetMacAddress,
|
||||
ARM_ETH_MAC_SetMacAddress,
|
||||
ARM_ETH_MAC_SetAddressFilter,
|
||||
ARM_ETH_MAC_SendFrame,
|
||||
ARM_ETH_MAC_ReadFrame,
|
||||
ARM_ETH_MAC_GetRxFrameSize,
|
||||
ARM_ETH_MAC_GetRxFrameTime,
|
||||
ARM_ETH_MAC_GetTxFrameTime,
|
||||
ARM_ETH_MAC_ControlTimer,
|
||||
ARM_ETH_MAC_Control,
|
||||
ARM_ETH_MAC_PHY_Read,
|
||||
ARM_ETH_MAC_PHY_Write
|
||||
};
|
||||
@@ -0,0 +1,127 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_ETH_PHY.h"
|
||||
|
||||
#define ARM_ETH_PHY_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_ETH_PHY_API_VERSION,
|
||||
ARM_ETH_PHY_DRV_VERSION
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_Initialize(ARM_ETH_PHY_Read_t fn_read, ARM_ETH_PHY_Write_t fn_write)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_SetInterface(uint32_t interface)
|
||||
{
|
||||
switch (interface)
|
||||
{
|
||||
case ARM_ETH_INTERFACE_MII:
|
||||
break;
|
||||
case ARM_ETH_INTERFACE_RMII:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_ETH_PHY_SetMode(uint32_t mode)
|
||||
{
|
||||
switch (mode & ARM_ETH_PHY_SPEED_Msk)
|
||||
{
|
||||
case ARM_ETH_PHY_SPEED_10M:
|
||||
break;
|
||||
case ARM_ETH_PHY_SPEED_100M:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
switch (mode & ARM_ETH_PHY_DUPLEX_Msk)
|
||||
{
|
||||
case ARM_ETH_PHY_DUPLEX_HALF:
|
||||
break;
|
||||
case ARM_ETH_PHY_DUPLEX_FULL:
|
||||
break;
|
||||
}
|
||||
|
||||
if (mode & ARM_ETH_PHY_AUTO_NEGOTIATE)
|
||||
{
|
||||
}
|
||||
|
||||
if (mode & ARM_ETH_PHY_LOOPBACK)
|
||||
{
|
||||
}
|
||||
|
||||
if (mode & ARM_ETH_PHY_ISOLATE)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_DRIVER_ETH_PHY ARM_Driver_ETH_PHY_(ETH_PHY_NUM) =
|
||||
{
|
||||
ARM_ETH_PHY_GetVersion,
|
||||
ARM_ETH_PHY_Initialize,
|
||||
ARM_ETH_PHY_Uninitialize,
|
||||
ARM_ETH_PHY_PowerControl,
|
||||
ARM_ETH_PHY_SetInterface,
|
||||
ARM_ETH_PHY_SetMode,
|
||||
ARM_ETH_PHY_GetLinkState,
|
||||
ARM_ETH_PHY_GetLinkInfo,
|
||||
};
|
||||
@@ -0,0 +1,137 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_Flash.h"
|
||||
|
||||
#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
|
||||
|
||||
/* Sector Information */
|
||||
#ifdef FLASH_SECTORS
|
||||
static ARM_FLASH_SECTOR FLASH_SECTOR_INFO[FLASH_SECTOR_COUNT] = {
|
||||
FLASH_SECTORS
|
||||
};
|
||||
#else
|
||||
#define FLASH_SECTOR_INFO NULL
|
||||
#endif
|
||||
|
||||
/* Flash Information */
|
||||
static ARM_FLASH_INFO FlashInfo = {
|
||||
0, /* FLASH_SECTOR_INFO */
|
||||
0, /* FLASH_SECTOR_COUNT */
|
||||
0, /* FLASH_SECTOR_SIZE */
|
||||
0, /* FLASH_PAGE_SIZE */
|
||||
0, /* FLASH_PROGRAM_UNIT */
|
||||
0 /* FLASH_ERASED_VALUE */
|
||||
};
|
||||
|
||||
/* Flash Status */
|
||||
static ARM_FLASH_STATUS FlashStatus;
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_FLASH_API_VERSION,
|
||||
ARM_FLASH_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
|
||||
0, /* event_ready */
|
||||
0, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
|
||||
0 /* erase_chip */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data, uint32_t cnt)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_EraseSector(uint32_t addr)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_Flash_EraseChip(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_FLASH_INFO * ARM_Flash_GetInfo(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_Flash_SignalEvent(uint32_t event)
|
||||
{
|
||||
}
|
||||
// End Flash Interface
|
||||
|
||||
ARM_DRIVER_FLASH Driver_FLASH = {
|
||||
ARM_Flash_GetVersion,
|
||||
ARM_Flash_GetCapabilities,
|
||||
ARM_Flash_Initialize,
|
||||
ARM_Flash_Uninitialize,
|
||||
ARM_Flash_PowerControl,
|
||||
ARM_Flash_ReadData,
|
||||
ARM_Flash_ProgramData,
|
||||
ARM_Flash_EraseSector,
|
||||
ARM_Flash_EraseChip,
|
||||
ARM_Flash_GetStatus,
|
||||
ARM_Flash_GetInfo
|
||||
};
|
||||
@@ -0,0 +1,148 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_I2C.h"
|
||||
|
||||
#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_I2C_API_VERSION,
|
||||
ARM_I2C_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_I2C_CAPABILITIES DriverCapabilities = {
|
||||
0 /* supports 10-bit addressing */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_I2C_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_Initialize(ARM_I2C_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_MasterTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_MasterReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_SlaveTransmit(const uint8_t *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_SlaveReceive(uint8_t *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_GetDataCount(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_I2C_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
switch (control)
|
||||
{
|
||||
case ARM_I2C_OWN_ADDRESS:
|
||||
break;
|
||||
|
||||
case ARM_I2C_BUS_SPEED:
|
||||
switch (arg)
|
||||
{
|
||||
case ARM_I2C_BUS_SPEED_STANDARD:
|
||||
break;
|
||||
case ARM_I2C_BUS_SPEED_FAST:
|
||||
break;
|
||||
case ARM_I2C_BUS_SPEED_FAST_PLUS:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_I2C_BUS_CLEAR:
|
||||
break;
|
||||
|
||||
case ARM_I2C_ABORT_TRANSFER:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
ARM_I2C_STATUS ARM_I2C_GetStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_I2C_SignalEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End I2C Interface
|
||||
|
||||
ARM_DRIVER_I2C Driver_I2C = {
|
||||
ARM_I2C_GetVersion,
|
||||
ARM_I2C_GetCapabilities,
|
||||
ARM_I2C_Initialize,
|
||||
ARM_I2C_Uninitialize,
|
||||
ARM_I2C_PowerControl,
|
||||
ARM_I2C_MasterTransmit,
|
||||
ARM_I2C_MasterReceive,
|
||||
ARM_I2C_SlaveTransmit,
|
||||
ARM_I2C_SlaveReceive,
|
||||
ARM_I2C_GetDataCount,
|
||||
ARM_I2C_Control,
|
||||
ARM_I2C_GetStatus
|
||||
};
|
||||
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_MCI.h"
|
||||
|
||||
#define ARM_MCI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_MCI_API_VERSION,
|
||||
ARM_MCI_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_MCI_CAPABILITIES DriverCapabilities = {
|
||||
0, /* cd_state */
|
||||
0, /* cd_event */
|
||||
0, /* vdd */
|
||||
0, /* vdd_1v8 */
|
||||
0, /* vccq */
|
||||
0, /* vccq_1v8 */
|
||||
0, /* vccq_1v2 */
|
||||
1, /* data_width_4 */
|
||||
1, /* data_width_8 */
|
||||
0, /* data_width_4_ddr */
|
||||
0, /* data_width_8_ddr */
|
||||
0, /* high_speed */
|
||||
0, /* uhs_signaling */
|
||||
0, /* uhs_tuning */
|
||||
0, /* uhs_sdr50 */
|
||||
0, /* uhs_sdr104 */
|
||||
0, /* uhs_ddr50 */
|
||||
0, /* uhs_driver_type_a */
|
||||
0, /* uhs_driver_type_c */
|
||||
0, /* uhs_driver_type_d */
|
||||
1, /* sdio_interrupt */
|
||||
1, /* read_wait */
|
||||
0, /* suspend_resume */
|
||||
0, /* mmc_interrupt */
|
||||
0, /* mmc_boot */
|
||||
0, /* ccs */
|
||||
0 /* ccs_timeout */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_MCI_GetVersion(void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_Initialize(ARM_MCI_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_Uninitialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_CardPower(uint32_t voltage)
|
||||
{
|
||||
switch (voltage & ARM_MCI_POWER_VDD_Msk)
|
||||
{
|
||||
case ARM_MCI_POWER_VDD_OFF:
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
case ARM_MCI_POWER_VDD_3V3:
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_ReadCD(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_ReadWP(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_SendCommand(uint32_t cmd, uint32_t arg, uint32_t flags, uint32_t *response)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_SetupTransfer(uint8_t *data, uint32_t block_count, uint32_t block_size, uint32_t mode)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_AbortTransfer(void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_MCI_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
switch (control)
|
||||
{
|
||||
case ARM_MCI_BUS_SPEED:
|
||||
break;
|
||||
|
||||
case ARM_MCI_BUS_SPEED_MODE:
|
||||
break;
|
||||
|
||||
case ARM_MCI_BUS_CMD_MODE:
|
||||
/* Implement external pull-up control to support MMC cards in open-drain mode */
|
||||
/* Default mode is push-pull and is configured in Driver_MCI0.Initialize() */
|
||||
if (arg == ARM_MCI_BUS_CMD_PUSH_PULL)
|
||||
{
|
||||
/* Configure external circuit to work in push-pull mode */
|
||||
}
|
||||
else if (arg == ARM_MCI_BUS_CMD_OPEN_DRAIN)
|
||||
{
|
||||
/* Configure external circuit to work in open-drain mode */
|
||||
}
|
||||
else
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_MCI_BUS_DATA_WIDTH:
|
||||
switch (arg)
|
||||
{
|
||||
case ARM_MCI_BUS_DATA_WIDTH_1:
|
||||
break;
|
||||
case ARM_MCI_BUS_DATA_WIDTH_4:
|
||||
break;
|
||||
case ARM_MCI_BUS_DATA_WIDTH_8:
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_MCI_CONTROL_RESET:
|
||||
break;
|
||||
|
||||
case ARM_MCI_CONTROL_CLOCK_IDLE:
|
||||
break;
|
||||
|
||||
case ARM_MCI_DATA_TIMEOUT:
|
||||
break;
|
||||
|
||||
case ARM_MCI_MONITOR_SDIO_INTERRUPT:
|
||||
break;
|
||||
|
||||
case ARM_MCI_CONTROL_READ_WAIT:
|
||||
break;
|
||||
|
||||
case ARM_MCI_DRIVER_STRENGTH:
|
||||
default: return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
ARM_MCI_STATUS ARM_MCI_GetStatus(void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_MCI_SignalEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End MCI Interface
|
||||
|
||||
ARM_DRIVER_MCI Driver_MCI = {
|
||||
ARM_MCI_GetVersion,
|
||||
ARM_MCI_GetCapabilities,
|
||||
ARM_MCI_Initialize,
|
||||
ARM_MCI_Uninitialize,
|
||||
ARM_MCI_PowerControl,
|
||||
ARM_MCI_CardPower,
|
||||
ARM_MCI_ReadCD,
|
||||
ARM_MCI_ReadWP,
|
||||
ARM_MCI_SendCommand,
|
||||
ARM_MCI_SetupTransfer,
|
||||
ARM_MCI_AbortTransfer,
|
||||
ARM_MCI_Control,
|
||||
ARM_MCI_GetStatus
|
||||
};
|
||||
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "Driver_SAI.h"
|
||||
|
||||
#define ARM_SAI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_SAI_API_VERSION,
|
||||
ARM_SAI_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_SAI_CAPABILITIES DriverCapabilities = {
|
||||
1, /* supports asynchronous Transmit/Receive */
|
||||
0, /* supports synchronous Transmit/Receive */
|
||||
0, /* supports user defined Protocol */
|
||||
1, /* supports I2S Protocol */
|
||||
0, /* supports MSB/LSB justified Protocol */
|
||||
0, /* supports PCM short/long frame Protocol */
|
||||
0, /* supports AC'97 Protocol */
|
||||
0, /* supports Mono mode */
|
||||
0, /* supports Companding */
|
||||
0, /* supports MCLK (Master Clock) pin */
|
||||
0 /* supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR */
|
||||
};
|
||||
|
||||
//
|
||||
// Functions
|
||||
//
|
||||
|
||||
ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Uninitialize (void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Send (const void *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Receive (void *data, uint32_t num)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_SAI_GetTxCount (void)
|
||||
{
|
||||
}
|
||||
|
||||
uint32_t ARM_SAI_GetRxCount (void)
|
||||
{
|
||||
}
|
||||
|
||||
int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
|
||||
{
|
||||
}
|
||||
|
||||
ARM_SAI_STATUS ARM_SAI_GetStatus (void)
|
||||
{
|
||||
}
|
||||
|
||||
void ARM_SAI_SignalEvent(uint32_t event)
|
||||
{
|
||||
// function body
|
||||
}
|
||||
|
||||
// End SAI Interface
|
||||
|
||||
ARM_DRIVER_SAI Driver_SAI = {
|
||||
ARM_SAI_GetVersion,
|
||||
ARM_SAI_GetCapabilities,
|
||||
ARM_SAI_Initialize,
|
||||
ARM_SAI_Uninitialize,
|
||||
ARM_SAI_PowerControl,
|
||||
ARM_SAI_Send,
|
||||
ARM_SAI_Receive,
|
||||
ARM_SAI_GetTxCount,
|
||||
ARM_SAI_GetRxCount,
|
||||
ARM_SAI_Control,
|
||||
ARM_SAI_GetStatus
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user