mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-10-02 14:23:19 +08:00
[arm][cortex-m4] Add hardware stack guard support
Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only available on Cortex-M7 and Cortex-M33. Core porting (libcpu/arm/cortex-m4/): - Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only difference is the default memory type attribute: Cortex-M4 has no L1 cache, so the cacheability bits are reduced to three cases. - Add rt_hw_stack_guard_init() to cpuport.c. - Add missing #include <rtconfig.h> to context_gcc.S and invoke rt_hw_mpu_table_switch() in the PendSV context switch path. - Update SConscript to exclude mpu.c when memory protection is disabled. BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/): - board.h: include rtthread.h and define NUM_STATIC_REGIONS. - board.c: define static_regions[] marking the Flash region read-only, guarded by RT_USING_MEM_PROTECTION so it is not enabled by default.
This commit is contained in:
hanzhijian
Rbb666
@@ -11,50 +11,61 @@
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#include <board.h>
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#include <drv_common.h>
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#ifdef RT_USING_MEM_PROTECTION
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#include "mprotect.h"
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rt_mem_region_t static_regions[NUM_STATIC_REGIONS] = {
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/* Flash region, read only */
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{
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.start = (void *)STM32_FLASH_START_ADRESS,
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.size = (rt_size_t)STM32_FLASH_SIZE,
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.attr = RT_MEM_REGION_P_RX_U_RX,
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},
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};
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#endif
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
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RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 };
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/**Configure the main internal regulator output voltage
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*/
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
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|RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 4;
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RCC_OscInitStruct.PLL.PLLN = 168;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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/**Configure the main internal regulator output voltage
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*/
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 4;
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RCC_OscInitStruct.PLL.PLLN = 168;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/**Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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Error_Handler();
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}
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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}
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@@ -11,31 +11,36 @@
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtthread.h>
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#include <stm32f4xx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define STM32_SRAM_SIZE (128)
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#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
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#define STM32_SRAM_SIZE (128)
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#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
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#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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#define STM32_FLASH_SIZE (1024 * 1024)
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#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
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#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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#define STM32_FLASH_SIZE (1024 * 1024)
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#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
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#if defined(__ARMCC_VERSION)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#pragma section = "CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END STM32_SRAM_END
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#define HEAP_END STM32_SRAM_END
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#ifdef RT_USING_MEM_PROTECTION
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#define NUM_STATIC_REGIONS 1
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#endif
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void SystemClock_Config(void);
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@@ -21,6 +21,19 @@ if rtconfig.PLATFORM in ['gcc', 'llvm-arm']:
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if rtconfig.PLATFORM in ['iccarm']:
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src += Glob('*_iar.S')
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using_mpu = (
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GetDepend('RT_USING_MEM_PROTECTION') or
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GetDepend('RT_USING_HW_STACK_GUARD')
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)
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if using_mpu:
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if rtconfig.PLATFORM not in ['gcc', 'llvm-arm']:
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raise RuntimeError(
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'Cortex-M4 memory protection currently supports GCC only'
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)
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else:
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SrcRemove(src, 'mpu.c')
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group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@@ -18,6 +18,8 @@
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*/
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/*@{*/
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#include <rtconfig.h>
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.cpu cortex-m4
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.syntax unified
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.thumb
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@@ -155,6 +157,13 @@ switch_to_thread:
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BICNE lr, lr, #0x10 /* lr &= ~(1 << 4), set FPCA. */
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#endif
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#if defined (RT_USING_MEM_PROTECTION)
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PUSH {r0-r3, r12, lr}
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BL rt_thread_self
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BL rt_hw_mpu_table_switch
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POP {r0-r3, r12, lr}
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#endif
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pendsv_exit:
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/* restore interrupt */
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MSR PRIMASK, r2
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,102 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-09-25 tangzz98 the first version
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* 2026-08-23 RT-Thread add cortex-m4 support
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*/
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#ifndef __MPU_H__
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#define __MPU_H__
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#ifdef RT_USING_MEM_PROTECTION
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#include <board.h>
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#define MPU_MIN_REGION_SIZE 32U
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/* MPU attributes for configuring data region permission.
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* These are identical to Cortex-M7 because both cores implement the
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* ARMv7-M MPU with the same AP/XN bit layout in the RASR register. */
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/* Privileged No Access, Unprivileged No Access */
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#define P_NA_U_NA ((0x0 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk)
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/* Privileged Read Write, Unprivileged No Access */
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#define P_RW_U_NA ((0x1 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk)
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/* Privileged Read Write, Unprivileged Read Only */
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#define P_RW_U_RO ((0x2 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk)
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/* Privileged Read Write, Unprivileged Read Write */
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#define P_RW_U_RW ((0x3 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk)
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/* Privileged Read Only, Unprivileged No Access */
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#define P_RO_U_NA ((0x5 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk)
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/* Privileged Read Only, Unprivileged Read Only */
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#define P_RO_U_RO ((0x6 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk | MPU_RASR_XN_Msk)
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/* MPU attributes for configuring code region permission */
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/* Privileged Read Write Execute, Unprivileged Read Write Execute */
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#define P_RWX_U_RWX ((0x3 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
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/* Privileged Read Write Execute, Unprivileged Read Execute */
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#define P_RWX_U_RX ((0x2 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
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/* Privileged Read Write Execute, Unprivileged No Access */
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#define P_RWX_U_NA ((0x1 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
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/* Privileged Read Execute, Unprivileged Read Execute */
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#define P_RX_U_RX ((0x6 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
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/* Privileged Read Execute, Unprivileged No Access */
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#define P_RX_U_NA ((0x5 << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)
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/* MPU attributes for configuring memory type, cacheability and shareability.
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*
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* Unlike Cortex-M7, Cortex-M4 has no L1 cache, so the cacheability bits in
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* RASR only control memory ordering (strongly-ordered / device / normal)
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* rather than an actual cache. The full write-through / write-back taxonomy
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* used on M7 is therefore not needed here and is reduced to three types. */
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#define STRONGLY_ORDERED_SHAREABLE MPU_RASR_S_Msk
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#define STRONGLY_ORDERED_NON_SHAREABLE 0U
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#define DEVICE_SHAREABLE (MPU_RASR_B_Msk | MPU_RASR_S_Msk)
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#define DEVICE_NON_SHAREABLE MPU_RASR_B_Msk
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#define NORMAL_NON_CACHEABLE_SHAREABLE (MPU_RASR_C_Msk | MPU_RASR_S_Msk)
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#define NORMAL_NON_CACHEABLE MPU_RASR_C_Msk
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/* Sentinel marking an attribute that only carries the permission bits and
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* therefore needs the default memory type filled in later. */
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#define RESERVED ((2 << MPU_RASR_TEX_Pos) | MPU_RASR_B_Msk)
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typedef struct
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{
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rt_thread_t thread; /* Thread that triggered exception */
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void *addr; /* Address of faulting memory access */
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rt_mem_region_t region; /* Configurations of the memory region containing the address */
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rt_uint8_t mmfsr; /* Content of MemManage Status Register */
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} rt_mem_exception_info_t;
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typedef void (*rt_hw_mpu_exception_hook_t)(rt_mem_exception_info_t *);
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#define RT_ARM_MEM_ATTR(perm, type) ((rt_mem_attr_t){ (perm) | (type) })
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/* Convenient macros for configuring data region attributes with default memory type */
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#define RT_MEM_REGION_P_NA_U_NA RT_ARM_MEM_ATTR(P_NA_U_NA, RESERVED)
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#define RT_MEM_REGION_P_RW_U_RW RT_ARM_MEM_ATTR(P_RW_U_RW, RESERVED)
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#define RT_MEM_REGION_P_RW_U_RO RT_ARM_MEM_ATTR(P_RW_U_RO, RESERVED)
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#define RT_MEM_REGION_P_RW_U_NA RT_ARM_MEM_ATTR(P_RW_U_NA, RESERVED)
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#define RT_MEM_REGION_P_RO_U_RO RT_ARM_MEM_ATTR(P_RO_U_RO, RESERVED)
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#define RT_MEM_REGION_P_RO_U_NA RT_ARM_MEM_ATTR(P_RO_U_NA, RESERVED)
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/* Convenient macros for configuring code region attributes with default memory type */
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#define RT_MEM_REGION_P_RWX_U_RWX RT_ARM_MEM_ATTR(P_RWX_U_RWX, RESERVED)
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#define RT_MEM_REGION_P_RWX_U_RX RT_ARM_MEM_ATTR(P_RWX_U_RX, RESERVED)
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#define RT_MEM_REGION_P_RWX_U_NA RT_ARM_MEM_ATTR(P_RWX_U_NA, RESERVED)
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#define RT_MEM_REGION_P_RX_U_RX RT_ARM_MEM_ATTR(P_RX_U_RX, RESERVED)
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#define RT_MEM_REGION_P_RX_U_NA RT_ARM_MEM_ATTR(P_RX_U_NA, RESERVED)
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rt_bool_t rt_hw_mpu_region_valid(rt_mem_region_t *region);
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rt_err_t rt_hw_mpu_init(void);
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rt_err_t rt_hw_mpu_add_region(rt_thread_t thread, rt_mem_region_t *region);
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rt_err_t rt_hw_mpu_delete_region(rt_thread_t thread, rt_mem_region_t *region);
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rt_err_t rt_hw_mpu_update_region(rt_thread_t thread, rt_mem_region_t *region);
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rt_err_t rt_hw_mpu_exception_set_hook(rt_hw_mpu_exception_hook_t hook);
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void rt_hw_mpu_table_switch(rt_thread_t thread);
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#endif /* RT_USING_MEM_PROTECTION */
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#endif /* __MPU_H__ */
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@@ -0,0 +1,33 @@
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/*
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* Copyright (c) 2006-2026, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-09-25 tangzz98 the first version
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* 2026-08-23 RT-Thread add cortex-m4 support
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*/
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#ifndef __MPUTYPE_H__
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#define __MPUTYPE_H__
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#ifdef RT_USING_MEM_PROTECTION
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#ifdef RT_USING_HW_STACK_GUARD
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#define NUM_DYNAMIC_REGIONS (2 + NUM_CONFIGURABLE_REGIONS)
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#else
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#define NUM_DYNAMIC_REGIONS (NUM_CONFIGURABLE_REGIONS)
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#endif
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/* Cortex-M4 follows ARMv7-M, whose MPU programs the full attribute set
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* (access permission + memory type) through the single RASR register,
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* just like Cortex-M7. */
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typedef struct
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{
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rt_uint32_t rasr;
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} rt_mem_attr_t;
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#endif /* RT_USING_MEM_PROTECTION */
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#endif /* __MPUTYPE_H__ */
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